diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
90 files changed, 1695 insertions, 11 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c index 6c6f7e16df..47d7a96aa1 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c @@ -16,6 +16,18 @@ atomic_fetch_sub_ACQUIRE () } int +atomic_fetch_add_negative_RELAXED () +{ + return __atomic_fetch_add (&v, -4096, __ATOMIC_RELAXED); +} + +int +atomic_fetch_sub_negative_ACQUIRE () +{ + return __atomic_fetch_sub (&v, -4096, __ATOMIC_ACQUIRE); +} + +int atomic_fetch_and_SEQ_CST () { return __atomic_fetch_and (&v, 4096, __ATOMIC_SEQ_CST); @@ -75,4 +87,4 @@ atomic_or_fetch_CONSUME () return __atomic_or_fetch (&v, 4096, __ATOMIC_CONSUME); } -/* { dg-final { scan-assembler-times "\tw\[0-9\]+, w\[0-9\]+, #*4096" 12 } } */ +/* { dg-final { scan-assembler-times "\tw\[0-9\]+, w\[0-9\]+, #*4096" 14 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fnmul-1.c b/gcc/testsuite/gcc.target/aarch64/fnmul-1.c new file mode 100644 index 0000000000..92945d402f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fnmul-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "fnmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "fnmul\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fnmul-2.c b/gcc/testsuite/gcc.target/aarch64/fnmul-2.c new file mode 100644 index 0000000000..2c80dc8fc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fnmul-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -frounding-math" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "fneg\\td\[0-9\]+, d\[0-9\]+" } } */ + /* { dg-final { scan-assembler "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "fneg\\ts\[0-9\]+, s\[0-9\]+" } } */ + /* { dg-final { scan-assembler "fmul\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fnmul-3.c b/gcc/testsuite/gcc.target/aarch64/fnmul-3.c new file mode 100644 index 0000000000..8b77eec6f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fnmul-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "fnmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "fnmul\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ + return -(a * b); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fnmul-4.c b/gcc/testsuite/gcc.target/aarch64/fnmul-4.c new file mode 100644 index 0000000000..3306210a63 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fnmul-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -frounding-math" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "fnmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "fnmul\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ + return -(a * b); +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr66912.c b/gcc/testsuite/gcc.target/aarch64/pr66912.c new file mode 100644 index 0000000000..b8aabcd3b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr66912.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic" } */ + +__attribute__((visibility("protected"))) +int n_common; + +__attribute__((weak, visibility("protected"))) +int n_weak_common; + +__attribute__((visibility("protected"))) +int n_init = -1; + +__attribute__((weak, visibility("protected"))) +int n_weak_init = -1; + +int +f1 () +{ + /* { dg-final { scan-assembler ":got(page_lo15)?:n_common" } } */ + return n_common; +} + +int +f2 () +{ + /* { dg-final { scan-assembler ":got(page_lo15)?:n_weak_common" } } */ + return n_weak_common; +} + +int +f3 () +{ + /* { dg-final { scan-assembler ":got(page_lo15)?:n_init" } } */ + return n_init; +} + +int +f4 () +{ + /* { dg-final { scan-assembler ":got(page_lo15)?:n_weak_init" } } */ + return n_weak_init; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr68102_1.c b/gcc/testsuite/gcc.target/aarch64/pr68102_1.c new file mode 100644 index 0000000000..3193b276aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68102_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef __Float64x1_t float64x1_t; + +typedef long int64_t; + +extern int64_t bar (float64x1_t f); + +int +foo (void) +{ + float64x1_t f = { 3.14159265358979311599796346854 }; + int64_t c = 0x400921FB54442D18; + int64_t r; + r = bar (f); + return r == c; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr68106.c b/gcc/testsuite/gcc.target/aarch64/pr68106.c new file mode 100644 index 0000000000..dc552ecce0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68106.c @@ -0,0 +1,50 @@ +/* { dg-do run { target aarch64*-*-* } } */ +/* { dg-options "-O" } */ + +typedef signed long long int S; +typedef unsigned long long int U; +typedef __int128 W; +__attribute__ ((noinline, noclone)) +U upseu (U x, S y, int *ovf) +{ + U res; + *ovf = __builtin_add_overflow (x, y, &res); + return res; +} +U +usueu (U x, U y, int *ovf) +{ + U res; + *ovf = __builtin_sub_overflow (x, y, &res); + return res; +} +U +usseu (U x, S y, int *ovf) +{ + U res; + *ovf = __builtin_sub_overflow (x, y, &res); + return res; +} +int +main () +{ + int i, j; + for (i = 0; i < ((unsigned char) ~0); i++) + for (j = 0; j < ((unsigned char) ~0); j++) + { + U u1 = ((W) i << ((8 - 1) * 8)); + S s2 = ((W) j << ((8 - 1) * 8)) + (-0x7fffffffffffffffLL - 1); + U u2 = ((W) j << ((8 - 1) * 8)); + W w; + int ovf; + w = ((W) u1) + ((W) s2); + if (upseu (u1, s2, &ovf) != (U) w || ovf != (w != (U) w)) + __builtin_abort (); + w = ((W) u1) - ((W) u2); + if (usueu (u1, u2, &ovf) != (U) w || ovf != (w != (U) w)) + __builtin_abort (); + w = ((W) u1) - ((W) s2); + if (usseu (u1, s2, &ovf) != (U) w || ovf != (w != (U) w)) + __builtin_abort (); + } +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr68363_1.c b/gcc/testsuite/gcc.target/aarch64/pr68363_1.c new file mode 100644 index 0000000000..bb294b50dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68363_1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-cortex-a53-835769" } */ + +int +foo (int i) +{ + switch (i) + { + case 0: + case 2: + case 5: + return 0; + case 7: + case 11: + case 13: + return 1; + } + return -1; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c new file mode 100644 index 0000000000..126b9978f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-ipa-icf" } */ + +#include "sync-comp-swap.x" + +/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.x b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.x new file mode 100644 index 0000000000..eda52e407f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.x @@ -0,0 +1,13 @@ +int v = 0; + +int +sync_bool_compare_swap (int a, int b) +{ + return __sync_bool_compare_and_swap (&v, &a, &b); +} + +int +sync_val_compare_swap (int a, int b) +{ + return __sync_val_compare_and_swap (&v, &a, &b); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c new file mode 100644 index 0000000000..2639f9f9d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "sync-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.x b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.x new file mode 100644 index 0000000000..4c4548c739 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.x @@ -0,0 +1,7 @@ +int v; + +int +sync_lock_test_and_set (int a) +{ + return __sync_lock_test_and_set (&v, a); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-full.c b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c new file mode 100644 index 0000000000..10fc8fc957 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "sync-op-full.x" + +/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 12 } } */ +/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 12 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 12 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-full.x b/gcc/testsuite/gcc.target/aarch64/sync-op-full.x new file mode 100644 index 0000000000..c24223d5ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-full.x @@ -0,0 +1,73 @@ +int v = 0; + +int +sync_fetch_and_add (int a) +{ + return __sync_fetch_and_add (&v, a); +} + +int +sync_fetch_and_sub (int a) +{ + return __sync_fetch_and_sub (&v, a); +} + +int +sync_fetch_and_and (int a) +{ + return __sync_fetch_and_and (&v, a); +} + +int +sync_fetch_and_nand (int a) +{ + return __sync_fetch_and_nand (&v, a); +} + +int +sync_fetch_and_xor (int a) +{ + return __sync_fetch_and_xor (&v, a); +} + +int +sync_fetch_and_or (int a) +{ + return __sync_fetch_and_or (&v, a); +} + +int +sync_add_and_fetch (int a) +{ + return __sync_add_and_fetch (&v, a); +} + +int +sync_sub_and_fetch (int a) +{ + return __sync_sub_and_fetch (&v, a); +} + +int +sync_and_and_fetch (int a) +{ + return __sync_and_and_fetch (&v, a); +} + +int +sync_nand_and_fetch (int a) +{ + return __sync_nand_and_fetch (&v, a); +} + +int +sync_xor_and_fetch (int a) +{ + return __sync_xor_and_fetch (&v, a); +} + +int +sync_or_and_fetch (int a) +{ + return __sync_or_and_fetch (&v, a); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-release.c b/gcc/testsuite/gcc.target/aarch64/sync-op-release.c new file mode 100644 index 0000000000..d25b46f2c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-release.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "sync-op-release.x" + +/* { dg-final { scan-assembler-times "stlr" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-release.x b/gcc/testsuite/gcc.target/aarch64/sync-op-release.x new file mode 100644 index 0000000000..704bcff2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sync-op-release.x @@ -0,0 +1,7 @@ +int v; + +void +sync_lock_release (void) +{ + __sync_lock_release (&v); +} diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c b/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c new file mode 100644 index 0000000000..0e95986d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-comp-swap.x" + +/* { dg-final { scan-assembler-times "ldrex" 2 } } */ +/* { dg-final { scan-assembler-times "stlex" 2 } } */ +/* { dg-final { scan-assembler-times "dmb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c new file mode 100644 index 0000000000..c448599813 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldrex" 1 } } */ +/* { dg-final { scan-assembler-times "strex" 1 } } */ +/* { dg-final { scan-assembler-times "dmb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c new file mode 100644 index 0000000000..cce9e00697 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-full.x" + +/* { dg-final { scan-assembler-times "ldrex" 12 } } */ +/* { dg-final { scan-assembler-times "stlex" 12 } } */ +/* { dg-final { scan-assembler-times "dmb" 12 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c new file mode 100644 index 0000000000..502a266010 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-release.x" + +/* { dg-final { scan-assembler-times "stl" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/macro_defs0.c b/gcc/testsuite/gcc.target/arm/macro_defs0.c index 962ff03db3..684d49ffaf 100644 --- a/gcc/testsuite/gcc.target/arm/macro_defs0.c +++ b/gcc/testsuite/gcc.target/arm/macro_defs0.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-m" } } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-options "-march=armv7-m -mcpu=cortex-m3 -mfloat-abi=soft -mthumb" } */ #ifdef __ARM_FP diff --git a/gcc/testsuite/gcc.target/arm/macro_defs1.c b/gcc/testsuite/gcc.target/arm/macro_defs1.c index d5423c7212..4cc9ae6045 100644 --- a/gcc/testsuite/gcc.target/arm/macro_defs1.c +++ b/gcc/testsuite/gcc.target/arm/macro_defs1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6-m" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-options "-march=armv6-m -mthumb" } */ #ifdef __ARM_NEON_FP diff --git a/gcc/testsuite/gcc.target/arm/pr63210.c b/gcc/testsuite/gcc.target/arm/pr63210.c index c3ae92801f..9b63a67d3f 100644 --- a/gcc/testsuite/gcc.target/arm/pr63210.c +++ b/gcc/testsuite/gcc.target/arm/pr63210.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-mthumb -Os " } */ /* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "do not test on armv4t" { *-*-* } { "-march=armv4t" } } */ +/* { dg-additional-options "-march=armv5t" {target arm_arch_v5t_ok} } */ int foo1 (int c); int foo2 (int c); diff --git a/gcc/testsuite/gcc.target/arm/pr66912.c b/gcc/testsuite/gcc.target/arm/pr66912.c new file mode 100644 index 0000000000..27e4c452bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr66912.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic" } */ + +__attribute__((visibility("protected"))) +int n_common; + +__attribute__((weak, visibility("protected"))) +int n_weak_common; + +__attribute__((visibility("protected"))) +int n_init = -1; + +__attribute__((weak, visibility("protected"))) +int n_weak_init = -1; + +int +f1 () +{ + /* { dg-final { scan-assembler "\\.word\\tn_common\\(GOT\\)" } } */ + return n_common; +} + +int +f2 () +{ + /* { dg-final { scan-assembler "\\.word\\tn_weak_common\\(GOT\\)" } } */ + return n_weak_common; +} + +int +f3 () +{ + /* { dg-final { scan-assembler "\\.word\\tn_init\\(GOT\\)" } } */ + return n_init; +} + +int +f4 () +{ + /* { dg-final { scan-assembler "\\.word\\tn_weak_init\\(GOT\\)" } } */ + return n_weak_init; +} diff --git a/gcc/testsuite/gcc.target/arm/pr67439_1.c b/gcc/testsuite/gcc.target/arm/pr67439_1.c new file mode 100644 index 0000000000..f7a6128758 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr67439_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O1 -mfp16-format=ieee -march=armv7-a -mfpu=neon -mthumb -mrestrict-it" } */ + +__fp16 h0 = -1.0; + +void +f (__fp16 *p) +{ + h0 = 1.0; +} diff --git a/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c b/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c index e36000b19a..3cb93dc6c8 100644 --- a/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c +++ b/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-mthumb -Os -fdump-rtl-ira " } */ /* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "do not test on armv4t" { *-*-* } { "-march=armv4t" } } */ +/* { dg-additional-options "-march=armv5t" {target arm_arch_v5t_ok} } */ int foo (char *, char *, int); int test (int d, char * out, char *in, int len) diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100644 index 0000000000..de14bb580b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2 -marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +struct backtrace_state +{ + int threaded; + int lock_alloc; +}; + +void foo (struct backtrace_state *state) +{ + if (state->threaded) + __sync_lock_release (&state->lock_alloc); +} + +/* { dg-final { scan-assembler "stlne" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c b/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c index ee39887d10..37630f1a1f 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c +++ b/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c @@ -10,6 +10,8 @@ struct foo unsigned b28 : 1; unsigned rest : 28; }; + +unsigned foo(a) struct foo a; { diff --git a/gcc/testsuite/gcc.target/arm/thumb-ltu.c b/gcc/testsuite/gcc.target/arm/thumb-ltu.c index d057ea34d2..ae4ad5bdef 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-ltu.c +++ b/gcc/testsuite/gcc.target/arm/thumb-ltu.c @@ -2,6 +2,9 @@ /* { dg-require-effective-target arm_thumb1_ok } */ /* { dg-options "-mcpu=arm1136jf-s -mthumb -O2" } */ +extern int foo (); +extern int bar (); + void f(unsigned a, unsigned b, unsigned c, unsigned d) { if (a <= b || c > d) diff --git a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c index c6878f8ef8..78fcafaaf7 100644 --- a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c +++ b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c @@ -5,7 +5,7 @@ /* { dg-options "-Os" } */ /* { dg-skip-if "" { ! { arm_thumb1 } } } */ -volatile register r4 asm("r4"); +volatile register int r4 asm ("r4"); void f3(int i) { #define GO(n) \ diff --git a/gcc/testsuite/gcc.target/arm/vnmul-1.c b/gcc/testsuite/gcc.target/arm/vnmul-1.c new file mode 100644 index 0000000000..af0bebed20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -fno-rounding-math -mfpu=vfp -mfloat-abi=hard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-2.c b/gcc/testsuite/gcc.target/arm/vnmul-2.c new file mode 100644 index 0000000000..909b2a44a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -frounding-math -mfpu=vfp -mfloat-abi=hard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler-not "vnmul\\.f64" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler-not "vnmul\\.f32" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-3.c b/gcc/testsuite/gcc.target/arm/vnmul-3.c new file mode 100644 index 0000000000..df028823ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -fno-rounding-math -mfpu=vfp -mfloat-abi=hard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -(a * b); +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-4.c b/gcc/testsuite/gcc.target/arm/vnmul-4.c new file mode 100644 index 0000000000..670ee40e0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -frounding-math -mfpu=vfp -mfloat-abi=hard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -(a * b); +} diff --git a/gcc/testsuite/gcc.target/i386/20060512-1.c b/gcc/testsuite/gcc.target/i386/20060512-1.c index 374d18aea5..ec163a9bc5 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-1.c +++ b/gcc/testsuite/gcc.target/i386/20060512-1.c @@ -1,5 +1,4 @@ /* { dg-do run } */ -/* { dg-require-effective-target ia32 } */ /* { dg-options "-std=gnu99 -msse2 -mpreferred-stack-boundary=4" } */ /* { dg-require-effective-target sse2 } */ @@ -7,6 +6,14 @@ #include <emmintrin.h> +#ifdef __x86_64__ +# define PUSH "pushq %rsi" +# define POP "popq %rsi" +#else +# define PUSH "pushl %esi" +# define POP "popl %esi" +#endif + __m128i __attribute__ ((__noinline__)) vector_using_function () { @@ -27,9 +34,9 @@ static void sse2_test (void) { int result; - asm ("pushl %esi"); /* Disalign runtime stack. */ + asm (PUSH); /* Misalign runtime stack. */ result = self_aligning_function (g_1, g_2); if (result != 42) abort (); - asm ("popl %esi"); + asm (POP); } diff --git a/gcc/testsuite/gcc.target/i386/20060512-2.c b/gcc/testsuite/gcc.target/i386/20060512-2.c index d3a779cb4e..8ce4bd7f8b 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-2.c +++ b/gcc/testsuite/gcc.target/i386/20060512-2.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ia32 } */ /* { dg-options "-std=gnu99 -mpreferred-stack-boundary=4" } */ int outer_function (int x, int y) diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c index 9fff611b6c..b0ba6e253d 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-madx -O2" } */ -/* { dg-final { scan-assembler-times "adcx" 2 } } */ +/* { dg-final { scan-assembler-times "adc\[xl\]" 2 } } */ /* { dg-final { scan-assembler-times "sbbl" 1 } } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c index 3608dea79b..cbe19856c6 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-madx -O2" } */ -/* { dg-final { scan-assembler-times "adcx" 2 } } */ +/* { dg-final { scan-assembler-times "adc\[xq\]" 2 } } */ /* { dg-final { scan-assembler-times "sbbq" 1 } } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h b/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h index 591ff0640e..97aca27722 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h @@ -25,7 +25,7 @@ main () __cpuid_count (7, 0, eax, ebx, ecx, edx); - if ((avx512f_os_support ()) && ((ebx & bit_AVX512VBMI) == bit_AVX512VBMI)) + if ((avx512f_os_support ()) && ((ecx & bit_AVX512VBMI) == bit_AVX512VBMI)) { do_test (); #ifdef DEBUG diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66048.cc b/gcc/testsuite/gcc.target/i386/mpx/pr66048.cc new file mode 100644 index 0000000000..b29cd03ed0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66048.cc @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcheck-pointer-bounds -mmpx -march=corei7-avx" } */ + +struct c1 +{ + c1 (const c1 &other) : p (other.p) { }; + int *p; +}; + +struct c2 : public c1 { }; + +c1 +test (c2 a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66134.c b/gcc/testsuite/gcc.target/i386/mpx/pr66134.c new file mode 100644 index 0000000000..3889674ed5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66134.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcheck-pointer-bounds -mmpx -fno-tree-ccp" } */ + +extern int vfork (void) __attribute__ ((__nothrow__ , __leaf__)); +void test1 (void); +void test2 (void); +void test3 (int *); + +void test (int *p) +{ + test1 (); + p++; + test2 (); + p++; + vfork (); + test3 (p); +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66566.c b/gcc/testsuite/gcc.target/i386/mpx/pr66566.c new file mode 100644 index 0000000000..a405c20ac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66566.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcheck-pointer-bounds -mmpx" } */ + +union jsval_layout +{ + void *asPtr; +}; +union jsval_layout a; +union jsval_layout b; +union jsval_layout __inline__ fn1() { return b; } + +void fn2() { a = fn1(); } diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66567.c b/gcc/testsuite/gcc.target/i386/mpx/pr66567.c new file mode 100644 index 0000000000..5a7e2f29e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66567.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ + +void (*b) (); + +void fn1 (const int *p1) +{ + static void *a = &&conv_1234_123C; + conv_1234_123C: + ; +} + +void fn2 () +{ + b = fn1; +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66568.c b/gcc/testsuite/gcc.target/i386/mpx/pr66568.c new file mode 100644 index 0000000000..2653ebc0fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66568.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fcheck-pointer-bounds -mmpx -O2 -fPIC" } */ + +extern void exit (int); +int a, b, c; +void *set_test () { + if (b) + a ? exit (0) : exit (1); + b = c; +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66569.c b/gcc/testsuite/gcc.target/i386/mpx/pr66569.c new file mode 100644 index 0000000000..ba2023c684 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66569.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ + +struct s1 { + int *p; + int i; +}; + +struct s2 { + struct s1 s; + int i; +}; + +int test (struct s2 s, ...) { } diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr66581.c b/gcc/testsuite/gcc.target/i386/mpx/pr66581.c new file mode 100644 index 0000000000..015faaeae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr66581.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ + +void *a; +int b; + +void +fn1 (void) +{ + void *c = &&l_nop; +l_nop: + for (; b;) + ; + int *d = c; + c = fn1; + *d = 1; + goto *a; +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr68337-1.c b/gcc/testsuite/gcc.target/i386/mpx/pr68337-1.c new file mode 100644 index 0000000000..3f8d79d428 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr68337-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ + +#include "mpx-check.h" + +#define N 2 + +extern void abort (); + +static int +mpx_test (int argc, const char **argv) +{ + char ** src = (char **)malloc (sizeof (char *) * N); + char ** dst = (char **)malloc (sizeof (char *) * N); + int i; + + for (i = 0; i < N; i++) + src[i] = __bnd_set_ptr_bounds (argv[0] + i, i + 1); + + __builtin_memcpy(dst, src, sizeof (char *) * N); + + for (i = 0; i < N; i++) + { + char *p = dst[i]; + if (p != argv[0] + i + || __bnd_get_ptr_lbound (p) != p + || __bnd_get_ptr_ubound (p) != p + i) + abort (); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr68337-2.c b/gcc/testsuite/gcc.target/i386/mpx/pr68337-2.c new file mode 100644 index 0000000000..8845cca79b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr68337-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ +/* { dg-final { scan-assembler-not "memcpy" } } */ + +void +test (void *dst, void *src) +{ + __builtin_memcpy (dst, src, sizeof (char *) / 2); +} diff --git a/gcc/testsuite/gcc.target/i386/mpx/pr68416.c b/gcc/testsuite/gcc.target/i386/mpx/pr68416.c new file mode 100644 index 0000000000..10587edf25 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mpx/pr68416.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmpx -fcheck-pointer-bounds" } */ +/* { dg-final { scan-assembler-not "bndmov" } } */ + +int +foo(int **arr, int i) +{ + return (*arr)[i]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr66424.c b/gcc/testsuite/gcc.target/i386/pr66424.c new file mode 100644 index 0000000000..f5f5e1e8b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66424.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ia32 } */ +int a, b, c, d, e[2], f, l, m, n, o; +long long g = 1, j; +static unsigned int h; +static int i, k; + +void +fn1 (long long p) +{ + int q = p; + f = 1 ^ e[f ^ (q & 1)]; +} + +static void +fn2 (long long p) +{ + f = 1 ^ e[(f ^ 1) & 1]; + fn1 (p >> 1 & 1); + fn1 (p >> 32 & 1); +} + +void +fn3 (int p) +{ + g |= j = p; +} + +int +main () +{ + e[0] = 1; + char p = l; + h = --g; + i = o = c; + m = d ? 1 / d : 0; + fn3 (l || 0); + b = a; + n = j++; + k--; + fn2 (g); + fn2 (h); + fn2 (i); + + if (k + f) + __builtin_abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/i386/pr66648.c b/gcc/testsuite/gcc.target/i386/pr66648.c new file mode 100644 index 0000000000..88c126fff8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66648.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mstringop-strategy=unrolled_loop -mtune=nocona" } */ + +#define PATTERN 0xdeadbeef +#define SIZE 32 + +struct S { int i; char str[SIZE]; int j; }; + +void __attribute__((noclone, noinline)) +my_memcpy (char *, const char *, unsigned int); + +void +my_memcpy (char *dst, const char *src, unsigned int len) +{ + if (len < 8) + __builtin_abort (); + + __builtin_memcpy (dst, src, len); +} + +int +main (void) +{ + const char str[SIZE]= "1234567890123456789012345678901"; + struct S *s = __builtin_malloc (sizeof (struct S)); + + s->j = PATTERN; + my_memcpy (s->str, str, SIZE); + if (s->j != PATTERN) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr66691.c b/gcc/testsuite/gcc.target/i386/pr66691.c new file mode 100644 index 0000000000..da78808acd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66691.c @@ -0,0 +1,64 @@ +/* PR debug/66691 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O3 -g -mtune=generic -march=i686" } */ + +unsigned int a; +int b[2], c, d, e, f, g, h, i, k[8], l, m, s, t, w; +static int j; + +void +fn1 (long long p) +{ + int t = p; + c = c ^ b[c ^ (t & 1)]; +} + +static void +fn2 (long long p) +{ + c = c ^ b[1 ^ (d & 1)]; + fn1 (p >> 1 & 1); + fn1 (p >> 2); +} + +static void +fn3 () +{ + unsigned char p; + f = g = 0; + for (h = 0; h < 6; h++) + { + for (s = 0; s < 7; s++) + if (k[s+1]) + g = 0; + else + for (j = 0; j < 2; j++) + ; + t = j > 2 ? 0 : 1 >> j; + } + if (l) + { + short q[2]; + q[0] = q[1] = 0; + if (m) + for (i = 0; i < 2; i++) + { + unsigned char r = q[i]; + p = f ? r % f : r; + e = ((p > 0) <= (q[i] ^ 1)) + a; + if (k[1]) + for (e = 0; e != 18; ++e) + k[0] = 0; + } + } +} + +int +main () +{ + fn3 (); + fn2 (w); + fn2 (j); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr66703.c b/gcc/testsuite/gcc.target/i386/pr66703.c new file mode 100644 index 0000000000..0fb05829de --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66703.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { ia32 } } } */ +/* { dg-options "-O0 -mtune=pentium" } */ + +#include "readeflags-1.c" diff --git a/gcc/testsuite/gcc.target/i386/pr66814.c b/gcc/testsuite/gcc.target/i386/pr66814.c new file mode 100644 index 0000000000..4ac9d234cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66814.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-march=i586 -mavx512f -O2" } */ + +#include "avx512f-klogic-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr66838.c b/gcc/testsuite/gcc.target/i386/pr66838.c new file mode 100644 index 0000000000..46effedad3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66838.c @@ -0,0 +1,36 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2" } */ + +void abort (void); + +char global; + +__attribute__((sysv_abi, noinline, noclone)) +void sysv_abi_func(char const *desc, void *local) +{ + register int esi asm ("esi"); + register int edi asm ("edi"); + + if (local != &global) + abort (); + + /* Clobber some of the extra SYSV ABI registers. */ + asm volatile ("movl\t%2, %0\n\tmovl\t%2, %1" + : "=r" (esi), "=r" (edi) + : "i" (0xdeadbeef)); +} + +__attribute__((ms_abi, noinline, noclone)) +void ms_abi_func () +{ + sysv_abi_func ("1st call", &global); + sysv_abi_func ("2nd call", &global); + sysv_abi_func ("3rd call", &global); +} + +int +main(void) +{ + ms_abi_func(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr66891.c b/gcc/testsuite/gcc.target/i386/pr66891.c new file mode 100644 index 0000000000..61a4570319 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66891.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2" } */ + +__attribute__((__stdcall__)) void fn1(); + +int a; + +static void fn2() { + for (;;) + ; +} + +void fn3() { + fn1(0); + fn2(a == 0); +} diff --git a/gcc/testsuite/gcc.target/i386/pr66922.c b/gcc/testsuite/gcc.target/i386/pr66922.c new file mode 100644 index 0000000000..46274b22ce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66922.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +struct S +{ + int:31; + int:2; + int f0:16; + int f1; + int f2; +}; + +static void +sse2_test (void) +{ + struct S a = { 1, 0, 0 }; + + if (a.f0 != 1) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/pr67265-2.c b/gcc/testsuite/gcc.target/i386/pr67265-2.c new file mode 100644 index 0000000000..a9f2eb460e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67265-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fstack-check" } */ + +void foo (int n) +{ + volatile char arr[64 * 1024]; + + arr[n] = 1; +} diff --git a/gcc/testsuite/gcc.target/i386/pr67265.c b/gcc/testsuite/gcc.target/i386/pr67265.c new file mode 100644 index 0000000000..7827685fe5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67265.c @@ -0,0 +1,12 @@ +/* PR target/67265 */ +/* Reduced testcase by Johannes Dewender <gnu@JonnyJD.net> */ + +/* { dg-do compile } */ +/* { dg-options "-O -fstack-check -fPIC" } */ + +int a, b, c, d, e; + +void foo (void) +{ + __asm__("" : "+r"(c), "+r"(e), "+r"(d), "+r"(a) : ""(b), "mg"(foo), "mm"(c)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr67317-1.c b/gcc/testsuite/gcc.target/i386/pr67317-1.c new file mode 100644 index 0000000000..7db4e5f31a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-1.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int u32; + +u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d) +{ + u32 result0, result1; + + __builtin_ia32_addcarryx_u32 + (__builtin_ia32_addcarryx_u32 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-2.c b/gcc/testsuite/gcc.target/i386/pr67317-2.c new file mode 100644 index 0000000000..97b2eff88d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-2.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d) +{ + u64 result0, result1; + + __builtin_ia32_addcarryx_u64 + (__builtin_ia32_addcarryx_u64 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-3.c b/gcc/testsuite/gcc.target/i386/pr67317-3.c new file mode 100644 index 0000000000..c141d09810 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-3.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int u32; + +u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d) +{ + u32 result0, result1; + + __builtin_ia32_sbb_u32 + (__builtin_ia32_sbb_u32 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-4.c b/gcc/testsuite/gcc.target/i386/pr67317-4.c new file mode 100644 index 0000000000..2f95dbc16f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-4.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d) +{ + u64 result0, result1; + + __builtin_ia32_sbb_u64 + (__builtin_ia32_sbb_u64 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67480.c b/gcc/testsuite/gcc.target/i386/pr67480.c new file mode 100644 index 0000000000..aa549682db --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67480.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bw -O2 -ftree-vectorize" } */ + +void +foo(const char *in, char *out, unsigned n) +{ + unsigned i; + for (i = 0; i < n; i++) + out[i] &= in[i]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr67609-2.c b/gcc/testsuite/gcc.target/i386/pr67609-2.c new file mode 100644 index 0000000000..7d3fcba3be --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67609-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +__m128d reg = { 2.0, 4.0 }; + +void +__attribute__((noinline)) +set_lower (double b) +{ + double v[2]; + _mm_store_pd(v, reg); + v[0] = b; + reg = _mm_load_pd(v); +} + +static void +sse2_test (void) +{ + set_lower (6.0); + + if (reg[1] != 4.0) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr67609.c b/gcc/testsuite/gcc.target/i386/pr67609.c new file mode 100644 index 0000000000..518071bdd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67609.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-final { scan-assembler "movdqa" } } */ + +#include <emmintrin.h> +__m128d reg; +void set_lower(double b) +{ + double v[2]; + _mm_store_pd(v, reg); + v[0] = b; + reg = _mm_load_pd(v); +} diff --git a/gcc/testsuite/gcc.target/i386/pr67770.c b/gcc/testsuite/gcc.target/i386/pr67770.c new file mode 100644 index 0000000000..3826aff45b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67770.c @@ -0,0 +1,40 @@ +/* PR target/67770 */ +/* { dg-do run { target ia32 } } */ +/* { dg-require-effective-target trampolines } */ +/* { dg-options "-O2" } */ + +#ifndef NO_TRAMPOLINES +__attribute__ ((noinline)) void +foo (int i, void (* __attribute__ ((regparm (3))) bar) (int)) +{ + bar (i); +} +#endif + +int +main () +{ +#ifndef NO_TRAMPOLINES + int p = 0; + + __attribute__ ((regparm (3), noinline)) void + bar (int i) + { + if (__builtin_expect (i, 0)) + ++p; + } + + foo (0, bar); + bar (0); + + if (p != 0) + __builtin_abort (); + + foo (1, bar); + bar (1); + + if (p != 2) + __builtin_abort (); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr68018.c b/gcc/testsuite/gcc.target/i386/pr68018.c new file mode 100644 index 0000000000..a0fa21e0b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr68018.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O -mabi=ms -mstackrealign" } */ + +typedef float V __attribute__ ((vector_size (16))); + +int fn1 (V * x) +{ + V a = *x; + return a[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr68483-1.c b/gcc/testsuite/gcc.target/i386/pr68483-1.c new file mode 100644 index 0000000000..29787e94bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr68483-1.c @@ -0,0 +1,22 @@ +/* PR target/68483 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -msse2 -mno-sse3" } */ + +void +test (int *input, int *out, unsigned x1, unsigned x2) +{ + unsigned i, j; + unsigned end = x1; + + for (i = j = 0; i < 1000; i++) + { + int sum = 0; + end += x2; + for (; j < end; j++) + sum += input[j]; + out[i] = sum; + } +} + +/* { dg-final { scan-assembler "psrldq\[^\n\r]*(8,|, 8)" { target ia32 } } } */ +/* { dg-final { scan-assembler "psrldq\[^\n\r]*(4,|, 4)" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr68483-2.c b/gcc/testsuite/gcc.target/i386/pr68483-2.c new file mode 100644 index 0000000000..394dc1bac7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr68483-2.c @@ -0,0 +1,15 @@ +/* PR target/68483 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mno-sse3" } */ + +typedef int V __attribute__((vector_size (16))); + +void +foo (V *a, V *b) +{ + V c = { 0, 0, 0, 0 }; + V d = { 1, 2, 3, 4 }; + *a = __builtin_shuffle (*b, c, d); +} + +/* { dg-final { scan-assembler "psrldq\[^\n\r]*(4,|, 4)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/readeflags-1.c b/gcc/testsuite/gcc.target/i386/readeflags-1.c index 6b2fa7e8d1..8b00d7d5d1 100644 --- a/gcc/testsuite/gcc.target/i386/readeflags-1.c +++ b/gcc/testsuite/gcc.target/i386/readeflags-1.c @@ -9,10 +9,11 @@ #define EFLAGS_TYPE unsigned int #endif -static EFLAGS_TYPE +__attribute__((noinline, noclone)) +EFLAGS_TYPE readeflags_test (unsigned int a, unsigned int b) { - unsigned x = (a == b); + volatile char x = (a == b); return __readeflags (); } diff --git a/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c new file mode 100644 index 0000000000..1b468e4775 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 400 +unsigned char yy[10000]; + +void +__attribute__ ((noinline)) foo (unsigned short s) +{ + unsigned short i; + for (i = 0; i < s; i++) + yy[i] = (unsigned char) i; +} + +void +avx512bw_test () +{ + unsigned short i; + foo (N); + + for (i = 0; i < N; i++) + if ( (unsigned char)i != yy [i] ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c new file mode 100644 index 0000000000..f3d899c113 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 400 +unsigned short yy[10000]; + +void +__attribute__ ((noinline)) foo (unsigned int s) +{ + unsigned int i; + for (i = 0; i < s; i++) + yy[i] = (unsigned short) i; +} + +void +avx512bw_test () +{ + unsigned int i; + foo (N); + for (i = 0; i < N; i++) + if ( (unsigned short)i != yy [i] ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpermi2w\[ \\t\]+\[^\n\]*%zmm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c b/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c new file mode 100644 index 0000000000..3de4dfabee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 400 +unsigned char yy[10000]; +unsigned char xx[10000]; + +void +__attribute__ ((noinline)) foo (unsigned short s) +{ + unsigned short i; + for (i = 0; i < s; i++) + yy[i] = xx [i*2 + 1]; +} + +void +avx512bw_test () +{ + unsigned short i; + unsigned char j = 0; + for (i = 0; i < 2 * N + 1; i++, j++) + xx [i] = j; + + foo (N); + + for (i = 0; i < N; i++) + if ( (unsigned char)(2*i+1) != yy [i] ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c b/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c new file mode 100644 index 0000000000..e32d40a1ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 400 + +typedef struct +{ + unsigned char real; + unsigned char imag; +} complex8_t; + +void +__attribute__ ((noinline)) foo (unsigned char *a, + complex8_t *x, unsigned len) +{ + unsigned i; + for (i = 0; i < len; i++) + a[i] = x[i].imag + x[i].real; +} + +void +avx512bw_test () +{ + unsigned short i; + unsigned char j = 0; + complex8_t x [N]; + unsigned char a [N]; + + for (i = 0; i < N; i++, j++) + { + x [i].real = j; + x [i].imag = j; + } + + foo (a, x, N); + + j = 0; + for (i = 0; i < N; i++, j++) + if ( a[i] != (unsigned char)(j+j) ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-unpack-1.c b/gcc/testsuite/gcc.target/i386/vect-unpack-1.c new file mode 100644 index 0000000000..84521e313e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-unpack-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 255 +unsigned int yy[10000]; + +void +__attribute__ ((noinline)) foo (unsigned char s) +{ + unsigned char i; + for (i = 0; i < s; i++) + yy[i] = (unsigned int) i; +} + +void +avx512bw_test () +{ + unsigned char i; + foo (N); + for (i = 0; i < N; i++) + if ( (unsigned int)i != yy [i] ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpmovzxbw\[ \\t\]+\[^\n\]*%zmm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-unpack-2.c b/gcc/testsuite/gcc.target/i386/vect-unpack-2.c new file mode 100644 index 0000000000..482524848b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-unpack-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" + +#define N 120 +signed int yy[10000]; + +void +__attribute__ ((noinline)) foo (signed char s) +{ + signed char i; + for (i = 0; i < s; i++) + yy[i] = (signed int) i; +} + +void +avx512bw_test () +{ + signed char i; + foo (N); + for (i = 0; i < N; i++) + if ( (signed int)i != yy [i] ) + abort (); +} + +/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\n\]*%zmm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c b/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c new file mode 100644 index 0000000000..691e517469 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_htm_ok } */ +/* { dg-options "-O2 -mhtm -ffixed-r3 -ffixed-r4 -ffixed-r5 -ffixed-r6 -ffixed-r7 -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12" } */ + +/* { dg-final { scan-assembler-not "tabort\\.\[ \t\]0" } } */ + +int +foo (void) +{ + return __builtin_tabort (10); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c new file mode 100644 index 0000000000..266fd97d66 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c @@ -0,0 +1,46 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O1 -mvsx -mlra -mcpu=power7" } */ + +/* PR 67808: LRA ICEs on simple double to long double conversion test case */ + +void +dfoo (long double *ldb1, double *db1) +{ + *ldb1 = *db1; +} + +long double +dfoo2 (double *db1) +{ + return *db1; +} + +long double +dfoo3 (double x) +{ + return x; +} + +void +ffoo (long double *ldb1, float *db1) +{ + *ldb1 = *db1; +} + +long double +ffoo2 (float *db1) +{ + return *db1; +} + +long double +ffoo3 (float x) +{ + return x; +} + +/* { dg-final { scan-assembler "xxlxor" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shr.c b/gcc/testsuite/gcc.target/powerpc/vec-shr.c new file mode 100644 index 0000000000..31a27c8832 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-shr.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fno-inline" } */ + +#include <stdlib.h> + +typedef struct { double r, i; } complex; +#define LEN 30 +complex c[LEN]; +double d[LEN]; + +void +foo (complex *c, double *d, int len1) +{ + int i; + for (i = 0; i < len1; i++) + { + c[i].r = d[i]; + c[i].i = 0.0; + } +} + +int +main (void) +{ + int i; + for (i = 0; i < LEN; i++) + d[i] = (double) i; + foo (c, d, LEN); + for (i=0;i<LEN;i++) + if ((c[i].r != (double) i) || (c[i].i != 0.0)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/s390/bswap-1.c b/gcc/testsuite/gcc.target/s390/bswap-1.c new file mode 100644 index 0000000000..e1f113a4cc --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bswap-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z900 -mzarch" } */ + +#include <stdint.h> + +uint64_t u64; +uint32_t u32; +uint16_t u16; + +uint64_t +foo64a (uint64_t a) +{ + return __builtin_bswap64 (a); +} +/* { dg-final { scan-assembler-times "lrvgr\t%r2,%r2" 1 { target lp64 } } } */ + +uint64_t +foo64b () +{ + return __builtin_bswap64 (u64); +} +/* { dg-final { scan-assembler-times "lrvg\t%r2,0\\(%r\[0-9\]*\\)" 1 { target lp64 } } } */ + +uint32_t +foo32 () +{ + return __builtin_bswap32 (u32); +} +/* { dg-final { scan-assembler-times "lrv\t%r2,0\\(%r\[0-9\]*\\)" 1 } } */ + +uint16_t +foo16 () +{ + return __builtin_bswap16 (u16); +} +/* { dg-final { scan-assembler-times "lrvh\t%r2,0\\(%r\[0-9\]*\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/pfpo.c b/gcc/testsuite/gcc.target/s390/pfpo.c new file mode 100644 index 0000000000..32725c991a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pfpo.c @@ -0,0 +1,21 @@ +/* The pfpo instruction generated by this code clobbers the r1 register while + it was still in use. */ + +/* { dg-do run } */ +/* { dg-options "-O0 -march=z10 -mzarch" } */ + +int foo(int x) +{ + return x; +} + +int bar(int i, float f) +{ + return i; +} + +int main() +{ + _Decimal32 d = 7; + return bar(foo(0x10203040), (float)d) == 0x10203040 ? 0 : 1; +} diff --git a/gcc/testsuite/gcc.target/s390/pr67443.c b/gcc/testsuite/gcc.target/s390/pr67443.c new file mode 100644 index 0000000000..e011a11882 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr67443.c @@ -0,0 +1,49 @@ +/* Test case for PR/67443. */ + +/* { dg-do run { target s390*-*-* } } */ +/* { dg-prune-output "call-clobbered register used for global register variable" } */ +/* { dg-options "-march=z900 -fPIC -fomit-frame-pointer -O3" } */ + +#include <assert.h> + +/* Block all registers except the first three argument registers. */ +register long r0 asm ("r0"); +register long r1 asm ("r1"); +register long r5 asm ("r5"); +register long r6 asm ("r6"); +register long r7 asm ("r7"); +register long r8 asm ("r8"); +register long r9 asm ("r9"); +register long r10 asm ("r10"); +register long r11 asm ("r11"); + +struct s_t +{ + unsigned f1 : 8; + unsigned f2 : 24; +}; + +__attribute__ ((noinline)) +void foo (struct s_t *ps, int c, int i) +{ + /* Uses r2 as address register. */ + ps->f1 = c; + /* The calculation of the value is so expensive that it's cheaper to spill ps + to the stack and reload it later (into a different register). + ==> Uses r4 as address register.*/ + ps->f2 = i + i % 3; + /* If dead store elimination fails to detect that the address in r2 during + the first assignment is an alias of the address in r4 during the second + assignment, it eliminates the first assignment and the f1 field is not + written (bug). */ +} + +int main (void) +{ + struct s_t s = { 0x01u, 0x020304u }; + + foo (&s, 0, 0); + assert (s.f1 == 0&& s.f2 == 0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/pr68015.c b/gcc/testsuite/gcc.target/s390/pr68015.c new file mode 100644 index 0000000000..b0d1f35ad1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr68015.c @@ -0,0 +1,24 @@ +/* { dg-compile } */ +/* { dg-options "-O2 -march=z196" } */ + +extern long useme (long, ...); + +void +foo (void) +{ + long secs = useme (41); + long utc_secs = useme (42); + long h, m; + + utc_secs = useme (42); + h = secs / 3600; + m = secs / 60; + if (utc_secs >= 86400) + { + m = 59; + h--; + if (h < 0) + h = 23; + } + useme (h, m); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c index dfe19f1913..ba9fd6ee1a 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c @@ -1,11 +1,13 @@ /* { dg-do run } */ /* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ /* { dg-require-effective-target vector } */ +/* { dg-require-effective-target int128 } */ typedef unsigned char uv16qi __attribute__((vector_size(16))); typedef unsigned short uv8hi __attribute__((vector_size(16))); typedef unsigned int uv4si __attribute__((vector_size(16))); typedef unsigned long long uv2di __attribute__((vector_size(16))); +typedef unsigned __int128 uv1ti __attribute__((vector_size(16))); uv2di __attribute__((noinline)) foo1 () @@ -45,6 +47,13 @@ foo4 () 0xff, 0, 0xff, 0, 0, 0xff, 0, 0xff }; } + +uv1ti __attribute__((noinline)) +foo5 () +{ + return (uv1ti){ 0xff00ff00ff00ff00ULL }; +} + /* { dg-final { scan-assembler-times "vgbm\t%v24,61605" 1 } } */ int @@ -64,6 +73,10 @@ main () if (foo4()[1] != 0xff) __builtin_abort (); + + if (foo5()[0] != 0xff00ff00ff00ff00ULL) + __builtin_abort (); + return 0; } diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c index e3ae34154c..46256e9253 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c @@ -1,10 +1,12 @@ /* { dg-do compile } */ /* { dg-options "-O3 -mzarch -march=z13" } */ +/* { dg-require-effective-target int128 } */ typedef unsigned char uv16qi __attribute__((vector_size(16))); typedef unsigned short uv8hi __attribute__((vector_size(16))); typedef unsigned int uv4si __attribute__((vector_size(16))); typedef unsigned long long uv2di __attribute__((vector_size(16))); +typedef unsigned __int128 uv1ti __attribute__((vector_size(16))); /* The elements differ. */ uv2di __attribute__((noinline)) @@ -43,4 +45,11 @@ foo4 () 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82 }; } + +/* We do not have vgmq. */ +uv1ti +foo5() +{ + return (uv1ti){ ((unsigned __int128)1 << 53) - 1 }; +} /* { dg-final { scan-assembler-not "vgm" } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c new file mode 100644 index 0000000000..9ebf6c7064 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O0 -mzarch -march=z13 -mzvector" } */ + +#include <vecintrin.h> + +signed char +foo64 (signed char *p) +{ + return vec_load_bndry (p, 64)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),0" 1 } } */ +} + +signed char +foo128 (signed char *p) +{ + return + vec_load_bndry (p, 128)[0] + + vec_load_bndry (p + 16, 128)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),1" 2 } } */ +} + +signed char +foo256 (signed char *p) +{ + return + vec_load_bndry (p, 256)[0] + + vec_load_bndry (p + 16, 256)[0] + + vec_load_bndry (p + 32, 256)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),2" 3 } } */ +} + +signed char +foo512 (signed char *p) +{ + return + vec_load_bndry (p, 512)[0] + + vec_load_bndry (p + 16, 512)[0] + + vec_load_bndry (p + 32, 512)[0] + + vec_load_bndry (p + 48, 512)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),3" 4 } } */ +} + +signed char +foo1024 (signed char *p) +{ + return + vec_load_bndry (p, 1024)[0] + + vec_load_bndry (p + 16, 1024)[0] + + vec_load_bndry (p + 32, 1024)[0] + + vec_load_bndry (p + 48, 1024)[0] + + vec_load_bndry (p + 64, 1024)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),4" 5 } } */ +} + +signed char +foo2048 (signed char *p) +{ + return + vec_load_bndry (p, 2048)[0] + + vec_load_bndry (p + 16, 2048)[0] + + vec_load_bndry (p + 32, 2048)[0] + + vec_load_bndry (p + 48, 2048)[0] + + vec_load_bndry (p + 64, 2048)[0] + + vec_load_bndry (p + 80, 2048)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),5" 6 } } */ +} + +signed char +foo4096 (signed char *p) +{ + return + vec_load_bndry (p, 4096)[0] + + vec_load_bndry (p + 16, 4096)[0] + + vec_load_bndry (p + 32, 4096)[0] + + vec_load_bndry (p + 48, 4096)[0] + + vec_load_bndry (p + 64, 4096)[0] + + vec_load_bndry (p + 80, 4096)[0] + + vec_load_bndry (p + 96, 4096)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),6" 7 } } */ +} diff --git a/gcc/testsuite/gcc.target/sparc/sparc-ret.c b/gcc/testsuite/gcc.target/sparc/sparc-ret-1.c index 808e8a98f0..808e8a98f0 100644 --- a/gcc/testsuite/gcc.target/sparc/sparc-ret.c +++ b/gcc/testsuite/gcc.target/sparc/sparc-ret-1.c diff --git a/gcc/testsuite/gcc.target/sparc/sparc-ret-2.c b/gcc/testsuite/gcc.target/sparc/sparc-ret-2.c new file mode 100644 index 0000000000..536b9b75a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/sparc-ret-2.c @@ -0,0 +1,13 @@ +/* PR target/57845 */ + +/* { dg-do compile } */ +/* { dg-options "-freg-struct-return" } */ + +struct S { short int i; }; + +struct S foo (short int i) +{ + struct S s; + s.i = i; + return s; +} |