diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
1997 files changed, 34329 insertions, 1549 deletions
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h index 7b7d0e24fa..06a92c3ec8 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h +++ b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h @@ -1,3 +1,4 @@ + #define IN_FRAMEWORK #ifdef VFP @@ -10,6 +11,13 @@ #define D6 48 #define D7 56 +#ifdef NEON +#define Q0 D0 +#define Q1 D2 +#define Q2 D4 +#define Q3 D6 +#endif + #define S0 64 #define S1 68 #define S2 72 @@ -27,23 +35,18 @@ #define S14 120 #define S15 124 -#define R0 128 -#define R1 132 -#define R2 136 -#define R3 140 - -#define STACK 144 - +#define CORE_REG_START 128 #else +#define CORE_REG_START 0 +#endif -#define R0 0 -#define R1 4 -#define R2 8 -#define R3 12 +#define R0 CORE_REG_START +#define R1 (R0 + 4) +#define R2 (R1 + 4) +#define R3 (R2 + 4) +#define STACK (R3 + 4) -#define STACK 16 -#endif extern void abort (void); diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h b/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h new file mode 100644 index 0000000000..08b75f7b1a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h @@ -0,0 +1,33 @@ + + +#include "arm_neon.h" + +const int32x4_t i32x4_constvec1 = { 1101, 1102, 1103, 1104}; +const int32x4_t i32x4_constvec2 = { 2101, 2102, 2103, 2104}; + +#define ELEM(INDEX) .val[INDEX] + +const int32x4x2_t i32x4x2_constvec1 = {ELEM(0) = {0xaddebccb,11,12,13}, + ELEM(1) = {14, 15, 16, 17} }; + +const int32x4x2_t i32x4x2_constvec2 = { ELEM(0) = {0xaadebcca,11,12,13}, + ELEM(1) = {140, 15, 16, 17}}; + +const int32x4x3_t i32x4x3_constvec1 = { ELEM(0) = {0xabbccdde,8, 9, 10}, + ELEM(1) = {0xabcccdde, 26, 27, 28}, + ELEM(2) = {0xaccccddf, 29, 30, 31}}; + +const int32x4x3_t i32x4x3_constvec2 = { ELEM(0) = {0xbccccdd0,8, 9, 10}, + ELEM(1) = {0xbdfe1000, 26, 27, 28}, + ELEM(2) = {0xaccccddf, 29, 30, 31}}; +const float32x4x2_t f32x4x2_constvec1 = + { ELEM(0) = { 7.101f, 0.201f, 0.301f, 0.401f} , + ELEM(1) = { 8.101f, 0.501f, 0.601f, 0.701f} }; + +const float32x4x2_t f32x4x2_constvec2 = + { ELEM(0) = { 11.99f , 11.21f, 1.27f, 8.74f}, + ELEM(1) = { 13.45f , 1.23f ,1.24f, 1.26f}}; + +const int32x2_t i32x2_constvec1 = { 1283, 1345 }; +const int32x2x2_t i32x2x2_constvec1 = { ELEM(0) = { 0xabcdefab, 32 }, + ELEM(1) = { 0xabcdefbc, 33 }}; diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c new file mode 100644 index 0000000000..47ae2f65fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect1.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c new file mode 100644 index 0000000000..f7b532a3be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c @@ -0,0 +1,23 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect2.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */ +ARG(float, 3.0f, S4) /* D2, Q1 occupied. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c new file mode 100644 index 0000000000..e5426b0ec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c @@ -0,0 +1,26 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect3.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(double, 11.0, STACK+sizeof(int32x4x2_t)) /* No backfill in D3. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c new file mode 100644 index 0000000000..96bd09c459 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect4.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(float, 5.0f, S5) /* Backfill in S5. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c new file mode 100644 index 0000000000..59e58c96c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c @@ -0,0 +1,28 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect5.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(float32x4x2_t, f32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */ +LAST_ARG(int, 3, R0) + +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c new file mode 100644 index 0000000000..fcb3998821 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c @@ -0,0 +1,24 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect6.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */ +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c new file mode 100644 index 0000000000..f8d1d07300 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect7.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(float, 24.3f, S0) /* S0 , D0, Q0 */ +ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */ +ARG(double, 25.6, D1) +ARG(float, 12.67f, S1) +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +ARG(double, 2.47, STACK+sizeof(int32x4x3_t)) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c new file mode 100644 index 0000000000..f2c295d84f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect8.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(float, 24.3f, S0) /* S0 , D0, Q0 */ +ARG(int32x2_t, i32x2_constvec1, D1) /* D1 */ +ARG(double, 25.6, D2) +ARG(float, 12.67f, S1) +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +ARG(double, 2.47, STACK+sizeof(int32x4x3_t)) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c index 380a3244dd..9fb926dbdf 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c index 58561aac9f..c3a1b39a94 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c index 2c143bafb0..a496a3ed5b 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c index 7b6b4cd54a..bbfa3df908 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c index ca0c5be7c3..a46361c090 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c index b5131d7fcf..43c19f2dd2 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c index d5a75b5b8f..c98ca38101 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c index 9815994ef8..956bc0ab5d 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c index d02160c860..9044ec221f 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c index a2db349e4a..bfe90675b2 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c index 807292b572..0e645d7110 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c index 8bb2a5678b..46dc4b98a7 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c index 0adc17fde1..216d98ea8e 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c index 6d8df0d62a..4d718da45d 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c index de4bdb4c42..3e57e45c7d 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c index 7865844ebb..e55006885c 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c index f9aa2960ca..c2be6bf4b7 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-eabi* } } */ +/* { dg-do run { target arm*-*-*eabi* } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/arm.exp b/gcc/testsuite/gcc.target/arm/arm.exp index 0838d37b3f..dc6c16ad52 100644 --- a/gcc/testsuite/gcc.target/arm/arm.exp +++ b/gcc/testsuite/gcc.target/arm/arm.exp @@ -30,6 +30,11 @@ if ![info exists DEFAULT_CFLAGS] then { set DEFAULT_CFLAGS " -ansi -pedantic-errors" } +# This variable should only apply to tests called in this exp file. +global dg_runtest_extra_prunes +set dg_runtest_extra_prunes "" +lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch" + # Initialize `dg'. dg-init @@ -39,3 +44,5 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ # All done. dg-finish + +set dg_runtest_extra_prunes "" diff --git a/gcc/testsuite/gcc.target/arm/cmp-1.c b/gcc/testsuite/gcc.target/arm/cmp-1.c new file mode 100644 index 0000000000..0d6b7c2661 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmp-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler-not "\tbl\t" } } */ +/* { dg-final { scan-assembler-not "__aeabi" } } */ +int x, y; + +#define TEST_EXPR(NAME, ARGS, EXPR) \ + int NAME##1 ARGS { return (EXPR); } \ + int NAME##2 ARGS { return !(EXPR); } \ + int NAME##3 ARGS { return (EXPR) ? x : y; } \ + void NAME##4 ARGS { if (EXPR) x++; } \ + void NAME##5 ARGS { if (!(EXPR)) x++; } + +#define TEST(NAME, TYPE, OPERATOR) \ + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \ + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \ + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \ + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \ + TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \ + TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1) + +#define TEST_OP(NAME, OPERATOR) \ + TEST (sc_##NAME, signed char, OPERATOR) \ + TEST (uc_##NAME, unsigned char, OPERATOR) \ + TEST (ss_##NAME, short, OPERATOR) \ + TEST (us_##NAME, unsigned short, OPERATOR) \ + TEST (si_##NAME, int, OPERATOR) \ + TEST (ui_##NAME, unsigned int, OPERATOR) \ + TEST (sll_##NAME, long long, OPERATOR) \ + TEST (ull_##NAME, unsigned long long, OPERATOR) + +TEST_OP (eq, ==) +TEST_OP (ne, !=) +TEST_OP (lt, <) +TEST_OP (gt, >) +TEST_OP (le, <=) +TEST_OP (ge, >=) diff --git a/gcc/testsuite/gcc.target/arm/cmp-2.c b/gcc/testsuite/gcc.target/arm/cmp-2.c new file mode 100644 index 0000000000..ed6b609ca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmp-2.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */ +/* { dg-final { scan-assembler-not "\tbl\t" } } */ +/* { dg-final { scan-assembler-not "__aeabi" } } */ +int x, y; + +#define EQ(X, Y) ((X) == (Y)) +#define NE(X, Y) ((X) != (Y)) +#define LT(X, Y) ((X) < (Y)) +#define GT(X, Y) ((X) > (Y)) +#define LE(X, Y) ((X) <= (Y)) +#define GE(X, Y) ((X) >= (Y)) + +#define TEST_EXPR(NAME, ARGS, EXPR) \ + int NAME##1 ARGS { return (EXPR); } \ + int NAME##2 ARGS { return !(EXPR); } \ + int NAME##3 ARGS { return (EXPR) ? x : y; } \ + void NAME##4 ARGS { if (EXPR) x++; } \ + void NAME##5 ARGS { if (!(EXPR)) x++; } + +#define TEST(NAME, TYPE, OPERATOR) \ + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \ + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \ + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \ + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \ + TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \ + TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1)) + +#define TEST_OP(NAME, OPERATOR) \ + TEST (f_##NAME, float, OPERATOR) \ + TEST (d_##NAME, double, OPERATOR) \ + TEST (ld_##NAME, long double, OPERATOR) + +TEST_OP (eq, EQ) +TEST_OP (ne, NE) +TEST_OP (lt, LT) +TEST_OP (gt, GT) +TEST_OP (le, LE) +TEST_OP (ge, GE) +TEST_OP (blt, __builtin_isless) +TEST_OP (bgt, __builtin_isgreater) +TEST_OP (ble, __builtin_islessequal) +TEST_OP (bge, __builtin_isgreaterequal) +/* This one should be expanded into separate ordered and equality + comparisons. */ +TEST_OP (blg, __builtin_islessgreater) +TEST_OP (bun, __builtin_isunordered) diff --git a/gcc/testsuite/gcc.target/arm/cold-lc.c b/gcc/testsuite/gcc.target/arm/cold-lc.c new file mode 100644 index 0000000000..295c29fe8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cold-lc.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-calls" } */ +/* { dg-final { scan-assembler-not "bl\[^\n\]*dump_stack" } } */ + +extern void dump_stack (void) __attribute__ ((__cold__)) __attribute__ ((noinline)); +struct thread_info { + struct task_struct *task; +}; +extern struct thread_info *current_thread_info (void); + +void dump_stack (void) +{ + unsigned long stack; + show_stack ((current_thread_info ()->task), &stack); +} + +void die (char *str, void *fp, int nr) +{ + dump_stack (); + while (1); +} + diff --git a/gcc/testsuite/gcc.target/arm/combine-movs.c b/gcc/testsuite/gcc.target/arm/combine-movs.c new file mode 100644 index 0000000000..e9fd6cb45d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/combine-movs.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { arm_thumb1 } } */ +/* { dg-options "-O" } */ + +void foo (unsigned long r[], unsigned int d) +{ + int i, n = d / 32; + for (i = 0; i < n; ++i) + r[i] = 0; +} + +/* { dg-final { scan-assembler "lsrs\tr\[0-9\]" { target arm_thumb2 } } } */ +/* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2 } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c new file mode 100644 index 0000000000..c2959165b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v5_ok } */ +/* { dg-options "-std=gnu99" } */ +/* { dg-add-options arm_arch_v5 } */ +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */ +/* { dg-message "file included" "In file included" { target *-*-* } 0 } */ + +#include "../../gcc.dg/di-longlong64-sync-1.c" + +/* On an old ARM we have no ldrexd or strexd so we have to use helpers. */ +/* { dg-final { scan-assembler-not "ldrexd" } } */ +/* { dg-final { scan-assembler-not "strexd" } } */ +/* { dg-final { scan-assembler "__sync_" } } */ diff --git a/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c new file mode 100644 index 0000000000..517c4a89d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-options "-marm -std=gnu99" } */ +/* { dg-require-effective-target arm_arch_v6k_ok } */ +/* { dg-add-options arm_arch_v6k } */ +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */ +/* { dg-message "file included" "In file included" { target *-*-* } 0 } */ + +#include "../../gcc.dg/di-longlong64-sync-1.c" + +/* We should be using ldrexd, strexd and no helpers or shorter ldrex. */ +/* { dg-final { scan-assembler-times "\tldrexd" 48 } } */ +/* { dg-final { scan-assembler-times "\tstrexd" 48 } } */ +/* { dg-final { scan-assembler-not "__sync_" } } */ +/* { dg-final { scan-assembler-not "ldrex\t" } } */ +/* { dg-final { scan-assembler-not "strex\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/fixed-point-exec.c b/gcc/testsuite/gcc.target/arm/fixed-point-exec.c new file mode 100644 index 0000000000..6bc3b07d6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/fixed-point-exec.c @@ -0,0 +1,301 @@ +/* { dg-do run { target { fixed_point } } } */ +/* { dg-options "-std=gnu99" } */ + +/* Check basic arithmetic ops for ARM fixed-point/saturating operation support. + Not target-independent since we make various assumptions about precision and + magnitudes of various types. */ + +#include <stdlib.h> +#include <stdio.h> +#include <math.h> +#include <stdfix.h> + +#define TEST(TYPE, OP, NAME, SUFFIX) \ + TYPE NAME##SUFFIX (TYPE A, TYPE B) \ + { \ + return A OP B; \ + } + +#define VARIANTS(TYPE, OP, NAME) \ + TEST (short TYPE, OP, NAME, _short); \ + TEST (TYPE, OP, NAME, _regular); \ + TEST (long TYPE, OP, NAME, _long); \ + TEST (_Sat short TYPE, OP, NAME, _sat_short); \ + TEST (_Sat TYPE, OP, NAME, _sat_regular); \ + TEST (_Sat long TYPE, OP, NAME, _sat_long); \ + TEST (unsigned short TYPE, OP, NAME, _uns_short); \ + TEST (unsigned TYPE, OP, NAME, _uns_regular); \ + TEST (unsigned long TYPE, OP, NAME, _uns_long); \ + TEST (unsigned _Sat short TYPE, OP, NAME, _uns_sat_short); \ + TEST (unsigned _Sat TYPE, OP, NAME, _uns_sat_regular); \ + TEST (unsigned _Sat long TYPE, OP, NAME, _uns_sat_long) + +VARIANTS (_Fract, +, plus_fract); +VARIANTS (_Accum, +, plus_accum); +VARIANTS (_Fract, -, minus_fract); +VARIANTS (_Accum, -, minus_accum); +VARIANTS (_Fract, *, mult_fract); +VARIANTS (_Accum, *, mult_accum); +VARIANTS (_Accum, /, div_accum); + +/* Inputs for signed add, multiply fractional tests. */ +short _Fract sf_a = 0.9hr; +short _Fract sf_b = -0.8hr; +_Fract f_a = 0.9r; +_Fract f_b = -0.8r; +long _Fract lf_a = 0.9lr; +long _Fract lf_b = -0.8lr; + +/* Inputs for signed subtract fractional tests. */ +short _Fract sf_c = 0.7hr; +short _Fract sf_d = 0.9hr; +_Fract f_c = 0.7r; +_Fract f_d = 0.9r; +long _Fract lf_c = 0.7lr; +long _Fract lf_d = 0.9lr; + +/* Inputs for unsigned add, subtract, multiply fractional tests. */ +unsigned short _Fract usf_a = 0.4uhr; +unsigned short _Fract usf_b = 0.3uhr; +unsigned _Fract uf_a = 0.4ur; +unsigned _Fract uf_b = 0.3ur; +unsigned long _Fract ulf_a = 0.4ulr; +unsigned long _Fract ulf_b = 0.3ulr; + +/* Inputs for saturating signed add tests. */ +short _Sat _Fract sf_e = 0.8hr; +short _Sat _Fract sf_f = 0.8hr; +_Sat _Fract f_e = 0.8r; +_Sat _Fract f_f = 0.8r; +long _Sat _Fract lf_e = 0.8r; +long _Sat _Fract lf_f = 0.8r; + +short _Sat _Fract sf_g = -0.8hr; +short _Sat _Fract sf_h = -0.8hr; +_Sat _Fract f_g = -0.8r; +_Sat _Fract f_h = -0.8r; +long _Sat _Fract lf_g = -0.8r; +long _Sat _Fract lf_h = -0.8r; + +/* Inputs for saturating unsigned subtract tests. */ +unsigned short _Sat _Fract usf_c = 0.3uhr; +unsigned short _Sat _Fract usf_d = 0.4uhr; +unsigned _Sat _Fract uf_c = 0.3ur; +unsigned _Sat _Fract uf_d = 0.4ur; +unsigned long _Sat _Fract ulf_c = 0.3ulr; +unsigned long _Sat _Fract ulf_d = 0.4ulr; + +/* Inputs for signed accumulator tests. */ + +short _Accum sa_a = 1.25hk; +short _Accum sa_b = -1.5hk; +_Accum a_a = 100.25k; +_Accum a_b = -100.5k; +long _Accum la_a = 1000.25lk; +long _Accum la_b = -1000.5lk; + +/* Inputs for unsigned accumulator tests. */ + +unsigned short _Accum usa_a = 2.5uhk; +unsigned short _Accum usa_b = 1.75uhk; +unsigned _Accum ua_a = 255.5uk; +unsigned _Accum ua_b = 170.25uk; +unsigned long _Accum ula_a = 1550.5ulk; +unsigned long _Accum ula_b = 999.5ulk; + +/* Inputs for signed saturating accumulator tests. */ + +short _Sat _Accum sa_c = 240.0hk; +short _Sat _Accum sa_d = 250.0hk; +short _Sat _Accum sa_e = -240.0hk; +short _Sat _Accum sa_f = -250.0hk; +short _Sat _Accum sa_g = 0.5hk; + +_Sat _Accum a_c = 65000.0k; +_Sat _Accum a_d = 20000.0k; +_Sat _Accum a_e = -65000.0k; +_Sat _Accum a_f = -20000.0k; +_Sat _Accum a_g = 0.5k; + +long _Sat _Accum la_c = 3472883712.0lk; +long _Sat _Accum la_d = 3456106496.0lk; +long _Sat _Accum la_e = -3472883712.0lk; +long _Sat _Accum la_f = -3456106496.0lk; +long _Sat _Accum la_g = 0.5lk; + +/* Inputs for unsigned saturating accumulator tests. */ + +unsigned short _Sat _Accum usa_c = 250.0uhk; +unsigned short _Sat _Accum usa_d = 240.0uhk; +unsigned short _Sat _Accum usa_e = 0.5uhk; + +unsigned _Sat _Accum ua_c = 65000.0uk; +unsigned _Sat _Accum ua_d = 20000.0uk; +unsigned _Sat _Accum ua_e = 0.5uk; + +unsigned long _Sat _Accum ula_c = 3472883712.0ulk; +unsigned long _Sat _Accum ula_d = 3456106496.0ulk; +unsigned long _Sat _Accum ula_e = 0.5ulk; + +#define CHECK(FN, EXP) do { \ + if (fabs ((float) (FN) - (EXP)) > 0.05) \ + { \ + fprintf (stderr, "result for " #FN " (as float): %f\n", (double) (FN));\ + abort (); \ + } \ + } while (0) + +#define CHECK_EXACT(FN, EXP) do { \ + if ((FN) != (EXP)) \ + { \ + fprintf (stderr, "result for " #FN " (as float): %f, should be %f\n", \ + (double) (FN), (double) (EXP)); \ + abort (); \ + } \ + } while (0) + +int +main (int argc, char *argv[]) +{ + /* Fract/fract operations, non-saturating. */ + + CHECK (plus_fract_short (sf_a, sf_b), 0.1); + CHECK (plus_fract_regular (f_a, f_b), 0.1); + CHECK (plus_fract_long (lf_a, lf_b), 0.1); + + CHECK (plus_fract_uns_short (usf_a, usf_b), 0.7); + CHECK (plus_fract_uns_regular (uf_a, uf_b), 0.7); + CHECK (plus_fract_uns_long (ulf_a, ulf_b), 0.7); + + CHECK (minus_fract_short (sf_c, sf_d), -0.2); + CHECK (minus_fract_regular (f_c, f_d), -0.2); + CHECK (minus_fract_long (lf_c, lf_d), -0.2); + + CHECK (minus_fract_uns_short (usf_a, usf_b), 0.1); + CHECK (minus_fract_uns_regular (uf_a, uf_b), 0.1); + CHECK (minus_fract_uns_long (ulf_a, ulf_b), 0.1); + + CHECK (mult_fract_short (sf_a, sf_b), -0.72); + CHECK (mult_fract_regular (f_a, f_b), -0.72); + CHECK (mult_fract_long (lf_a, lf_b), -0.72); + + CHECK (mult_fract_uns_short (usf_a, usf_b), 0.12); + CHECK (mult_fract_uns_regular (uf_a, uf_b), 0.12); + CHECK (mult_fract_uns_long (ulf_a, ulf_b), 0.12); + + /* Fract/fract operations, saturating. */ + + CHECK (plus_fract_sat_short (sf_e, sf_f), 1.0); + CHECK (plus_fract_sat_regular (f_e, f_f), 1.0); + CHECK (plus_fract_sat_long (lf_e, lf_f), 1.0); + + CHECK (plus_fract_sat_short (sf_g, sf_h), -1.0); + CHECK (plus_fract_sat_regular (f_g, f_h), -1.0); + CHECK (plus_fract_sat_long (lf_g, lf_h), -1.0); + + CHECK (plus_fract_uns_sat_short (sf_e, sf_f), 1.0); + CHECK (plus_fract_uns_sat_regular (f_e, f_f), 1.0); + CHECK (plus_fract_uns_sat_long (lf_e, lf_f), 1.0); + + CHECK (plus_fract_sat_short (sf_a, sf_b), 0.1); + CHECK (plus_fract_sat_regular (f_a, f_b), 0.1); + CHECK (plus_fract_sat_long (lf_a, lf_b), 0.1); + + CHECK (plus_fract_uns_sat_short (usf_a, usf_b), 0.7); + CHECK (plus_fract_uns_sat_regular (uf_a, uf_b), 0.7); + CHECK (plus_fract_uns_sat_long (ulf_a, ulf_b), 0.7); + + CHECK (minus_fract_uns_sat_short (usf_c, usf_d), 0.0); + CHECK (minus_fract_uns_sat_regular (uf_c, uf_d), 0.0); + CHECK (minus_fract_uns_sat_short (ulf_c, ulf_d), 0.0); + + CHECK (minus_fract_sat_short (sf_c, sf_d), -0.2); + CHECK (minus_fract_sat_regular (f_c, f_d), -0.2); + CHECK (minus_fract_sat_long (lf_c, lf_d), -0.2); + + /* Accum/accum operations, non-saturating. */ + + CHECK (plus_accum_short (sa_a, sa_b), -0.25); + CHECK (plus_accum_regular (a_a, a_b), -0.25); + CHECK (plus_accum_long (la_a, la_b), -0.25); + + CHECK (minus_accum_short (sa_a, sa_b), 2.75); + CHECK (minus_accum_regular (a_a, a_b), 200.75); + CHECK (minus_accum_long (la_a, la_b), 2000.75); + + CHECK (mult_accum_short (sa_a, sa_b), -1.875); + CHECK (mult_accum_regular (a_a, a_b), -10075.125); + CHECK (mult_accum_long (la_a, la_b), -1000750.125); + + CHECK (div_accum_short (sa_a, sa_b), -1.25/1.5); + CHECK (div_accum_regular (a_a, a_b), -100.25/100.5); + CHECK (div_accum_long (la_a, la_b), -1000.25/1000.5); + + /* Unsigned accum/accum operations, non-saturating. */ + + CHECK (plus_accum_uns_short (usa_a, usa_b), 4.25); + CHECK (plus_accum_uns_regular (ua_a, ua_b), 425.75); + CHECK (plus_accum_uns_long (ula_a, ula_b), 2550.0); + + CHECK (minus_accum_uns_short (usa_a, usa_b), 0.75); + CHECK (minus_accum_uns_regular (ua_a, ua_b), 85.25); + CHECK (minus_accum_uns_long (ula_a, ula_b), 551.0); + + CHECK (mult_accum_uns_short (usa_a, usa_b), 4.375); + CHECK (mult_accum_uns_regular (ua_a, ua_b), 43498.875); + CHECK (mult_accum_uns_long (ula_a, ula_b), 1549724.75); + + CHECK (div_accum_uns_short (usa_a, usa_b), 2.5/1.75); + CHECK (div_accum_uns_regular (ua_a, ua_b), 255.5/170.25); + CHECK (div_accum_uns_long (ula_a, ula_b), 1550.5/999.5); + + /* Signed accum/accum operations, saturating. */ + + CHECK_EXACT (plus_accum_sat_short (sa_c, sa_d), SACCUM_MAX); + CHECK_EXACT (plus_accum_sat_short (sa_e, sa_f), SACCUM_MIN); + CHECK_EXACT (plus_accum_sat_regular (a_c, a_d), ACCUM_MAX); + CHECK_EXACT (plus_accum_sat_regular (a_e, a_f), ACCUM_MIN); + CHECK_EXACT (plus_accum_sat_long (la_c, la_d), LACCUM_MAX); + CHECK_EXACT (plus_accum_sat_long (la_e, la_f), LACCUM_MIN); + + CHECK_EXACT (minus_accum_sat_short (sa_e, sa_d), SACCUM_MIN); + CHECK_EXACT (minus_accum_sat_short (sa_c, sa_f), SACCUM_MAX); + CHECK_EXACT (minus_accum_sat_regular (a_e, a_d), ACCUM_MIN); + CHECK_EXACT (minus_accum_sat_regular (a_c, a_f), ACCUM_MAX); + CHECK_EXACT (minus_accum_sat_long (la_e, la_d), LACCUM_MIN); + CHECK_EXACT (minus_accum_sat_long (la_c, la_f), LACCUM_MAX); + + CHECK_EXACT (mult_accum_sat_short (sa_c, sa_d), SACCUM_MAX); + CHECK_EXACT (mult_accum_sat_short (sa_c, sa_e), SACCUM_MIN); + CHECK_EXACT (mult_accum_sat_regular (a_c, a_d), ACCUM_MAX); + CHECK_EXACT (mult_accum_sat_regular (a_c, a_e), ACCUM_MIN); + CHECK_EXACT (mult_accum_sat_long (la_c, la_d), LACCUM_MAX); + CHECK_EXACT (mult_accum_sat_long (la_c, la_e), LACCUM_MIN); + + CHECK_EXACT (div_accum_sat_short (sa_d, sa_g), SACCUM_MAX); + CHECK_EXACT (div_accum_sat_short (sa_e, sa_g), SACCUM_MIN); + CHECK_EXACT (div_accum_sat_regular (a_c, a_g), ACCUM_MAX); + CHECK_EXACT (div_accum_sat_regular (a_e, a_g), ACCUM_MIN); + CHECK_EXACT (div_accum_sat_long (la_d, la_g), LACCUM_MAX); + CHECK_EXACT (div_accum_sat_long (la_e, la_g), LACCUM_MIN); + + /* Unsigned accum/accum operations, saturating. */ + + CHECK_EXACT (plus_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX); + CHECK_EXACT (plus_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX); + CHECK_EXACT (plus_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX); + + CHECK_EXACT (minus_accum_uns_sat_short (usa_d, usa_c), 0uhk); + CHECK_EXACT (minus_accum_uns_sat_regular (ua_d, ua_c), 0uk); + CHECK_EXACT (minus_accum_uns_sat_long (ula_d, ula_c), 0ulk); + + CHECK_EXACT (mult_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX); + CHECK_EXACT (mult_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX); + CHECK_EXACT (mult_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX); + + CHECK_EXACT (div_accum_uns_sat_short (usa_c, usa_e), USACCUM_MAX); + CHECK_EXACT (div_accum_uns_sat_regular (ua_c, ua_e), UACCUM_MAX); + CHECK_EXACT (div_accum_uns_sat_long (ula_c, ula_e), ULACCUM_MAX); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/g2.c b/gcc/testsuite/gcc.target/arm/g2.c index 031b93657d..85ba1906a9 100644 --- a/gcc/testsuite/gcc.target/arm/g2.c +++ b/gcc/testsuite/gcc.target/arm/g2.c @@ -2,6 +2,8 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=xscale -O2" } */ /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm32 } */ /* Brett Gaines' test case. */ diff --git a/gcc/testsuite/gcc.target/arm/handler-align.c b/gcc/testsuite/gcc.target/arm/handler-align.c new file mode 100644 index 0000000000..6c5187b202 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/handler-align.c @@ -0,0 +1,42 @@ +/* Test epilogue of a realigned interrupt handler. */ +/* { dg-do run } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-require-effective-target arm_cortex_m } */ +/* { dg-require-effective-target arm_eabi } */ + +extern __attribute__((noreturn)) void abort(void); +extern int snprintf(char *, int, const char *, ...); + +#define BUFF_LEN 256 +char buff[BUFF_LEN]; + +char *get_buffer(void) +{ + return buff; +} + +void __attribute__((interrupt)) foo(void) +{ + char *msg = get_buffer(); + snprintf(msg, BUFF_LEN, "%d %p", 1, buff+BUFF_LEN); +} + +volatile void * save_sp; +int main() +{ + register volatile void * sp asm("sp"); + /* Check stack pointer before/after calling the interrupt + * handler. Not equal means that handler doesn't restore + * stack correctly. */ + save_sp = sp; + foo(); + /* Abort here instead of return non-zero. Due to wrong sp, lr value, + * returning from main may not work. */ + if (save_sp != sp) + { + sp = save_sp; + abort(); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/headmerge-2.c b/gcc/testsuite/gcc.target/arm/headmerge-2.c index 36637a64eb..17d8e9365c 100644 --- a/gcc/testsuite/gcc.target/arm/headmerge-2.c +++ b/gcc/testsuite/gcc.target/arm/headmerge-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-times "120" 1 } } */ +/* { dg-final { scan-assembler-times "120\n" 1 } } */ extern void foo1 (int); extern void foo2 (int); diff --git a/gcc/testsuite/gcc.target/arm/ivopts-2.c b/gcc/testsuite/gcc.target/arm/ivopts-2.c new file mode 100644 index 0000000000..2cf6372301 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ivopts-2.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern void foo2 (short*); + +void +tr4 (short array[], int n) +{ + int x; + if (n > 0) + for (x = 0; x < n; x++) + foo2 (&array[x]); +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ +/* { dg-final { object-size text <= 26 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts-3.c b/gcc/testsuite/gcc.target/arm/ivopts-3.c new file mode 100644 index 0000000000..11d9aac80f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ivopts-3.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo2 (short*) __attribute__((pure)); + +unsigned int +tr3 (short array[], unsigned int n) +{ + int sum = 0; + unsigned int x; + for (x = 0; x < n; ++x) + sum += foo2 (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts-4.c b/gcc/testsuite/gcc.target/arm/ivopts-4.c new file mode 100644 index 0000000000..0c476b874f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ivopts-4.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo (int*) __attribute__((pure)); + +unsigned int +tr2 (int array[], int n) +{ + unsigned int sum = 0; + int x; + if (n > 0) + for (x = 0; x < n; x++) + sum += foo (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 36 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts-5.c b/gcc/testsuite/gcc.target/arm/ivopts-5.c new file mode 100644 index 0000000000..0f9023808e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ivopts-5.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo (int*) __attribute__((pure)); + +unsigned int +tr1 (int array[], unsigned int n) +{ + int sum = 0; + unsigned int x; + for (x = 0; x < n; ++x) + sum += foo (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c new file mode 100644 index 0000000000..8183d1d5f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +void +tr5 (short array[], int n) +{ + int x; + if (n > 0) + for (x = 0; x < n; x++) + array[x] = 0; +} + +/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ +/* { dg-final { object-size text <= 20 { target arm_thumb2 } } } */ +/* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ +/* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mla-1.c b/gcc/testsuite/gcc.target/arm/mla-1.c index 669647a55a..42101ef37c 100644 --- a/gcc/testsuite/gcc.target/arm/mla-1.c +++ b/gcc/testsuite/gcc.target/arm/mla-1.c @@ -19,4 +19,4 @@ foo (int *p, int *q) return accum; } -/* { dg-final { scan-assembler "mla" } } */ +/* { dg-final { scan-assembler "mla\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mla-2.c b/gcc/testsuite/gcc.target/arm/mla-2.c new file mode 100644 index 0000000000..1e3ca200b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mla-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long foolong (long long x, short *a, short *b) +{ + return x + *a * *b; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc/testsuite/gcc.target/arm/mmx-1.c index c2eca7f78f..d13c982845 100644 --- a/gcc/testsuite/gcc.target/arm/mmx-1.c +++ b/gcc/testsuite/gcc.target/arm/mmx-1.c @@ -4,6 +4,7 @@ /* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ /* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ /* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ /* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */ /* { dg-require-effective-target arm32 } */ /* { dg-require-effective-target arm_iwmmxt_ok } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c b/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c new file mode 100644 index 0000000000..ad6ba755e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -funsafe-math-optimizations" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +float32x2_t f_sub_abs_to_vabd_32() +{ + float32x2_t val1 = vdup_n_f32 (10); + float32x2_t val2 = vdup_n_f32 (30); + float32x2_t sres = vsub_f32(val1, val2); + float32x2_t res = vabs_f32 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.f32" } }*/ + +#include <arm_neon.h> +int8x8_t sub_abs_to_vabd_8() +{ + int8x8_t val1 = vdup_n_s8 (10); + int8x8_t val2 = vdup_n_s8 (30); + int8x8_t sres = vsub_s8(val1, val2); + int8x8_t res = vabs_s8 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s8" } }*/ + +int16x4_t sub_abs_to_vabd_16() +{ + int16x4_t val1 = vdup_n_s16 (10); + int16x4_t val2 = vdup_n_s16 (30); + int16x4_t sres = vsub_s16(val1, val2); + int16x4_t res = vabs_s16 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s16" } }*/ + +int32x2_t sub_abs_to_vabd_32() +{ + int32x2_t val1 = vdup_n_s32 (10); + int32x2_t val2 = vdup_n_s32 (30); + int32x2_t sres = vsub_s32(val1, val2); + int32x2_t res = vabs_s32 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s32" } }*/ diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-2.c b/gcc/testsuite/gcc.target/arm/neon-modes-2.c new file mode 100644 index 0000000000..40f1bba363 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-modes-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20) +#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1) +#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A) + +#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) + +void +bar (uint32_t *ptr, int y) +{ + uint32x2x3_t MANY (SETUP); + int *x = __builtin_alloca (y); + int z[0x1000]; + foo (x, z); + MANY (MODIFY); + foo (x, z); + MANY (STORE); +} diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-3.c b/gcc/testsuite/gcc.target/arm/neon-modes-3.c new file mode 100644 index 0000000000..fe8187570b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-modes-3.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n) +{ + float32x4x4_t a5, a6, a7, a8, a9; + int i; + + a5 = *src; + a6 = *src; + a7 = *src; + a8 = *src; + a9 = *src; + while (n--) + { + for (i = 0; i < 8; i++) + { + float32x4x4_t a0, a1, a2, a3, a4; + + a0 = *src; + a1 = *src; + a2 = *src; + a3 = *src; + a4 = *src; + *src = a0; + *dest = a0.val[0]; + *dest = a0.val[3]; + *src = a1; + *dest = a1.val[0]; + *dest = a1.val[3]; + *src = a2; + *dest = a2.val[0]; + *dest = a2.val[3]; + *src = a3; + *dest = a3.val[0]; + *dest = a3.val[3]; + *src = a4; + *dest = a4.val[0]; + *dest = a4.val[3]; + } + *src = a5; + *dest = a5.val[0]; + *dest = a5.val[3]; + *src = a6; + *dest = a6.val[0]; + *dest = a6.val[3]; + *src = a7; + *dest = a7.val[0]; + *dest = a7.val[3]; + *src = a8; + *dest = a8.val[0]; + *dest = a8.val[3]; + *src = a9; + *dest = a9.val[0]; + *dest = a9.val[3]; + } +} diff --git a/gcc/testsuite/gcc.target/arm/neon-reload-class.c b/gcc/testsuite/gcc.target/arm/neon-reload-class.c new file mode 100644 index 0000000000..c63aa04960 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-reload-class.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + + +void +_op_blend_p_caa_dp(unsigned *s, unsigned* e, unsigned *d, unsigned c) { + while (d < e) { + *d = ( (((((*s) >> 8) & 0x00ff00ff) * (c)) & 0xff00ff00) + (((((*s) & 0x00ff00ff) * (c)) >> 8) & 0x00ff00ff) ); + d++; + s++; + } +} + +/* These constants should be emitted as immediates rather than loaded from memory. */ + +/* { dg-final { scan-assembler-not "(\\.d?word|mov(w|t))" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c index 430a4d5717..9cf86dd05f 100644 --- a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c +++ b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-options "-O2 -mthumb -march=armv7-a" } */ /* { dg-add-options arm_neon } */ +/* { dg-prune-output "switch .* conflicts with" } */ #include <arm_neon.h> #include <stddef.h> diff --git a/gcc/testsuite/gcc.target/arm/neon-vld3-1.c b/gcc/testsuite/gcc.target/arm/neon-vld3-1.c new file mode 100644 index 0000000000..0cc5c8826d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vld3-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint32_t buffer[12]; + +void __attribute__((noinline)) +foo (uint32_t *a) +{ + uint32x4x3_t x; + + x = vld3q_u32 (a); + x.val[0] = vaddq_u32 (x.val[0], x.val[1]); + vst3q_u32 (a, x); +} + +int +main (void) +{ + buffer[0] = 1; + buffer[1] = 2; + foo (buffer); + return buffer[0] != 3; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c new file mode 100644 index 0000000000..e666371680 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, unsigned int x[], unsigned int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] >> 3; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c b/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c new file mode 100644 index 0000000000..6f2d20b6db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) +{ + int i; + for (i = 0; i < 9; i++) + c[i] = b[i] | (~a[i]); +} +void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) +{ + int i; + for (i = 0; i < 9; i++) + c[i] = b[i] & (~a[i]); +} + +/* { dg-final { scan-assembler "vorn\\t" } } */ +/* { dg-final { scan-assembler "vbic\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vrev.c b/gcc/testsuite/gcc.target/arm/neon-vrev.c new file mode 100644 index 0000000000..10f41bc32b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vrev.c @@ -0,0 +1,105 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x4_t +tst_vrev642_u16 (uint16x4_t __a) +{ + uint16x4_t __rv; + uint16x4_t __mask1 = { 3, 2, 1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x8_t +tst_vrev64q2_u16 (uint16x8_t __a) +{ + uint16x8_t __rv; + uint16x8_t __mask1 = {3, 2, 1, 0, 7, 6, 5, 4 }; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x8_t +tst_vrev642_u8 (uint8x8_t __a) +{ + uint8x8_t __rv; + uint8x8_t __mask1 = { 7, 6, 5, 4, 3, 2, 1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x16_t +tst_vrev64q2_u8 (uint8x16_t __a) +{ + uint8x16_t __rv; + uint8x16_t __mask1 = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}; + return __builtin_shuffle ( __a, __mask1) ; + +} + +uint32x2_t +tst_vrev642_u32 (uint32x2_t __a) +{ + uint32x2_t __rv; + uint32x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; + +} + +uint32x4_t +tst_vrev64q2_u32 (uint32x4_t __a) +{ + uint32x4_t __rv; + uint32x4_t __mask1 = {1, 0, 3, 2}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x4_t +tst_vrev322_u16 (uint16x4_t __a) +{ + uint16x4_t __mask1 = { 1, 0, 3, 2 }; + return __builtin_shuffle (__a, __mask1); +} + +uint16x8_t +tst_vrev32q2_u16 (uint16x8_t __a) +{ + uint16x8_t __mask1 = { 1, 0, 3, 2, 5, 4, 7, 6 }; + return __builtin_shuffle (__a, __mask1); +} + +uint8x8_t +tst_vrev322_u8 (uint8x8_t __a) +{ + uint8x8_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4}; + return __builtin_shuffle (__a, __mask1); +} + +uint8x16_t +tst_vrev32q2_u8 (uint8x16_t __a) +{ + uint8x16_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}; + return __builtin_shuffle (__a, __mask1); +} + +uint8x8_t +tst_vrev162_u8 (uint8x8_t __a) +{ + uint8x8_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6}; + return __builtin_shuffle (__a, __mask); +} + +uint8x16_t +tst_vrev16q2_u8 (uint8x16_t __a) +{ + uint8x16_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}; + return __builtin_shuffle (__a, __mask); +} + +/* { dg-final {scan-assembler-times "vrev32\.16\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev32\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev16\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.32\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.16\\t" 2} } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c b/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c index e87102edbe..51d38fd1df 100644 --- a/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c @@ -9,11 +9,14 @@ #include <stdlib.h> #include <string.h> -int8x8_t x = { 1, 2, 3, 4, 5, 6, 7, 8 }; -int8x8_t y = { 1, 2, 3, 16, 5, 6, 7, 8 }; +int8_t x_init[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; +int8_t y_init[8] = { 1, 2, 3, 16, 5, 6, 7, 8 }; int main (void) { + int8x8_t x = vld1_s8 (x_init); + int8x8_t y = vld1_s8 (y_init); + x = vset_lane_s8 (16, x, 3); if (memcmp (&x, &y, sizeof (x)) != 0) abort(); diff --git a/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c new file mode 100644 index 0000000000..913d5959be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] << 3; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c new file mode 100644 index 0000000000..82a3c5cfb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] >> 3; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vst3-1.c b/gcc/testsuite/gcc.target/arm/neon-vst3-1.c new file mode 100644 index 0000000000..a3bee6cb56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vst3-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint32_t buffer[64]; + +void __attribute__((noinline)) +foo (uint32_t *a) +{ + uint32x4x3_t x; + + x = vld3q_u32 (a); + a[35] = 1; + vst3q_lane_u32 (a + 32, x, 1); +} + +int +main (void) +{ + foo (buffer); + return buffer[35] != 1; +} diff --git a/gcc/testsuite/gcc.target/arm/neon/pr51534.c b/gcc/testsuite/gcc.target/arm/neon/pr51534.c new file mode 100644 index 0000000000..71cbb055f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/pr51534.c @@ -0,0 +1,84 @@ +/* Test the vector comparison intrinsics when comparing to immediate zero. + */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +#define GEN_TEST(T, D, C, R) \ + R test_##C##_##T (T a) { return C (a, D (0)); } + +#define GEN_DOUBLE_TESTS(S, T, C) \ + GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \ + GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) + +#define GEN_QUAD_TESTS(S, T, C) \ + GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \ + GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) + +#define GEN_COND_TESTS(C) \ + GEN_DOUBLE_TESTS (8, int8x8_t, C) \ + GEN_DOUBLE_TESTS (16, int16x4_t, C) \ + GEN_DOUBLE_TESTS (32, int32x2_t, C) \ + GEN_QUAD_TESTS (8, int8x16_t, C) \ + GEN_QUAD_TESTS (16, int16x8_t, C) \ + GEN_QUAD_TESTS (32, int32x4_t, C) + +GEN_COND_TESTS(vcgt) +GEN_COND_TESTS(vcge) +GEN_COND_TESTS(vclt) +GEN_COND_TESTS(vcle) +GEN_COND_TESTS(vceq) + +/* Scan for expected outputs. */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ + +/* And ensure we don't have unexpected output too. */ +/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */ + +/* Tidy up. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c b/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c new file mode 100644 index 0000000000..f31d9bfabf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c b/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c new file mode 100644 index 0000000000..f3f01c65e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c index 073d88f2b5..fa9cf20f55 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c @@ -15,5 +15,5 @@ void test_vld1Q_dupf32 (void) out_float32x4_t = vld1q_dup_f32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c index 1202e929a1..4e83038257 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c @@ -15,5 +15,5 @@ void test_vld1Q_dupp16 (void) out_poly16x8_t = vld1q_dup_p16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c index 27d7550972..70fb898850 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c @@ -15,5 +15,5 @@ void test_vld1Q_dupp8 (void) out_poly8x16_t = vld1q_dup_p8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c index df1e00880d..1fedcf94d2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c @@ -15,5 +15,5 @@ void test_vld1Q_dups16 (void) out_int16x8_t = vld1q_dup_s16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c index b371299bda..2abd4e4474 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c @@ -15,5 +15,5 @@ void test_vld1Q_dups32 (void) out_int32x4_t = vld1q_dup_s32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c index b4c3a8cc9f..912b93d1d6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c @@ -15,5 +15,5 @@ void test_vld1Q_dups64 (void) out_int64x2_t = vld1q_dup_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c index badeb3b804..e431a5cf10 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c @@ -15,5 +15,5 @@ void test_vld1Q_dups8 (void) out_int8x16_t = vld1q_dup_s8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c index d247fea562..6da756774f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c @@ -15,5 +15,5 @@ void test_vld1Q_dupu16 (void) out_uint16x8_t = vld1q_dup_u16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c index 1160f9820b..8e400bd25f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c @@ -15,5 +15,5 @@ void test_vld1Q_dupu32 (void) out_uint32x4_t = vld1q_dup_u32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c index 8cbc89c948..234db407b3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c @@ -15,5 +15,5 @@ void test_vld1Q_dupu64 (void) out_uint64x2_t = vld1q_dup_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c index c6d52a3d74..b1e540d702 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c @@ -15,5 +15,5 @@ void test_vld1Q_dupu8 (void) out_uint8x16_t = vld1q_dup_u8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c index bccdd26c20..8c7689edb0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c @@ -16,5 +16,5 @@ void test_vld1Q_lanef32 (void) out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c index f080107a66..163c2a7a95 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c @@ -16,5 +16,5 @@ void test_vld1Q_lanep16 (void) out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c index 4887ebcd0c..7f7a22eba4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c @@ -16,5 +16,5 @@ void test_vld1Q_lanep8 (void) out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c index aeb824c233..0d56492c25 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c @@ -16,5 +16,5 @@ void test_vld1Q_lanes16 (void) out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c index 90556ac9b2..3c5869fcdf 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c @@ -16,5 +16,5 @@ void test_vld1Q_lanes32 (void) out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c index db68bd0873..154583b677 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c @@ -16,5 +16,5 @@ void test_vld1Q_lanes64 (void) out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c index 3494c077dc..a6aa3f804b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c @@ -16,5 +16,5 @@ void test_vld1Q_lanes8 (void) out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c index eb791e7d39..1653dd31cb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c @@ -16,5 +16,5 @@ void test_vld1Q_laneu16 (void) out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c index 3841c9b96b..034e24d526 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c @@ -16,5 +16,5 @@ void test_vld1Q_laneu32 (void) out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c index 082e6a625b..ff92e91fcb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c @@ -16,5 +16,5 @@ void test_vld1Q_laneu64 (void) out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c index 194f749124..be338f1870 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c @@ -16,5 +16,5 @@ void test_vld1Q_laneu8 (void) out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c index 1c84b9127e..d792148d09 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c @@ -15,5 +15,5 @@ void test_vld1Qf32 (void) out_float32x4_t = vld1q_f32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c index f470da6bc6..84bceb557e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c @@ -15,5 +15,5 @@ void test_vld1Qp16 (void) out_poly16x8_t = vld1q_p16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c index a46d48bc2e..e756b1bc7f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c @@ -15,5 +15,5 @@ void test_vld1Qp8 (void) out_poly8x16_t = vld1q_p8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c index 39ab3fe55c..aaa29e982c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c @@ -15,5 +15,5 @@ void test_vld1Qs16 (void) out_int16x8_t = vld1q_s16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c index e12e8d97a4..14bc4221ea 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c @@ -15,5 +15,5 @@ void test_vld1Qs32 (void) out_int32x4_t = vld1q_s32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c index 1c6aca4a87..093aee61a3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c @@ -15,5 +15,5 @@ void test_vld1Qs64 (void) out_int64x2_t = vld1q_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c index 64e6b00644..d4fffd0a10 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c @@ -15,5 +15,5 @@ void test_vld1Qs8 (void) out_int8x16_t = vld1q_s8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c index 191deb0d76..267f7d15bc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c @@ -15,5 +15,5 @@ void test_vld1Qu16 (void) out_uint16x8_t = vld1q_u16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c index e3e01a6126..53ccab0c5b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c @@ -15,5 +15,5 @@ void test_vld1Qu32 (void) out_uint32x4_t = vld1q_u32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c index 24b55bab12..56b0dbd3e6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c @@ -15,5 +15,5 @@ void test_vld1Qu64 (void) out_uint64x2_t = vld1q_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c index 47e6ad07de..d68fc89eaa 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c @@ -15,5 +15,5 @@ void test_vld1Qu8 (void) out_uint8x16_t = vld1q_u8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c index 41eec0ef0a..6f8435b362 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c @@ -15,5 +15,5 @@ void test_vld1_dupf32 (void) out_float32x2_t = vld1_dup_f32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c index b38b29c725..1287b471b5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c @@ -15,5 +15,5 @@ void test_vld1_dupp16 (void) out_poly16x4_t = vld1_dup_p16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c index 69017c4ac5..8fde645535 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c @@ -15,5 +15,5 @@ void test_vld1_dupp8 (void) out_poly8x8_t = vld1_dup_p8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c index 61e0377fa4..084f89e064 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c @@ -15,5 +15,5 @@ void test_vld1_dups16 (void) out_int16x4_t = vld1_dup_s16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c index 0429ee513a..ba6697a4ce 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c @@ -15,5 +15,5 @@ void test_vld1_dups32 (void) out_int32x2_t = vld1_dup_s32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c index 90ee403d66..410ee6fcd5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c @@ -15,5 +15,5 @@ void test_vld1_dups64 (void) out_int64x1_t = vld1_dup_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c index aacac04bb1..18b21b527a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c @@ -15,5 +15,5 @@ void test_vld1_dups8 (void) out_int8x8_t = vld1_dup_s8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c index 64d736298b..1d893cd3b8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c @@ -15,5 +15,5 @@ void test_vld1_dupu16 (void) out_uint16x4_t = vld1_dup_u16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c index 6f3fd967e1..f640846403 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c @@ -15,5 +15,5 @@ void test_vld1_dupu32 (void) out_uint32x2_t = vld1_dup_u32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c index 262147d79e..17be90a0bc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c @@ -15,5 +15,5 @@ void test_vld1_dupu64 (void) out_uint64x1_t = vld1_dup_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c index 6038bec9ca..5811f25fb4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c @@ -15,5 +15,5 @@ void test_vld1_dupu8 (void) out_uint8x8_t = vld1_dup_u8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c index 3d4b0a4de6..6165897ecf 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c @@ -16,5 +16,5 @@ void test_vld1_lanef32 (void) out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c index 832abbd2a1..feecf1baa2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c @@ -16,5 +16,5 @@ void test_vld1_lanep16 (void) out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c index 04823322e0..0d17299365 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c @@ -16,5 +16,5 @@ void test_vld1_lanep8 (void) out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c index 571f87673f..26272410e3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c @@ -16,5 +16,5 @@ void test_vld1_lanes16 (void) out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c index 057a7ffc30..39575d4568 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c @@ -16,5 +16,5 @@ void test_vld1_lanes32 (void) out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c index 1e46d6a1f9..1216405bfc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c @@ -16,5 +16,5 @@ void test_vld1_lanes64 (void) out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c index eeebc9bbd0..7c763fd909 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c @@ -16,5 +16,5 @@ void test_vld1_lanes8 (void) out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c index 116a35f03b..9d2c45ed93 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c @@ -16,5 +16,5 @@ void test_vld1_laneu16 (void) out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c index f4907d202b..3a7f3eec96 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c @@ -16,5 +16,5 @@ void test_vld1_laneu32 (void) out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c index b5058b0f80..b9e5d2042e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c @@ -16,5 +16,5 @@ void test_vld1_laneu64 (void) out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c index caa08f6372..7e4835afe4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c @@ -16,5 +16,5 @@ void test_vld1_laneu8 (void) out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c index 17deac967c..2d90ac5590 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c @@ -15,5 +15,5 @@ void test_vld1f32 (void) out_float32x2_t = vld1_f32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c index ef2e73ac59..62aa89e8af 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c @@ -15,5 +15,5 @@ void test_vld1p16 (void) out_poly16x4_t = vld1_p16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c index 048bdeb06b..60e47c2d56 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c @@ -15,5 +15,5 @@ void test_vld1p8 (void) out_poly8x8_t = vld1_p8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c index 39e12d76cd..1d4cf525fd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c @@ -15,5 +15,5 @@ void test_vld1s16 (void) out_int16x4_t = vld1_s16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c index 80fbfd07d7..7af67c383a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c @@ -15,5 +15,5 @@ void test_vld1s32 (void) out_int32x2_t = vld1_s32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c index 3ea125d36b..dadb9de226 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c @@ -15,5 +15,5 @@ void test_vld1s64 (void) out_int64x1_t = vld1_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c index 599c323453..c27ebcd061 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c @@ -15,5 +15,5 @@ void test_vld1s8 (void) out_int8x8_t = vld1_s8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c index 550ca118b6..f973d6ec5c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c @@ -15,5 +15,5 @@ void test_vld1u16 (void) out_uint16x4_t = vld1_u16 (0); } -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c index e0b673cf8b..4b455b2929 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c @@ -15,5 +15,5 @@ void test_vld1u32 (void) out_uint32x2_t = vld1_u32 (0); } -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c index eba002cd7d..1504215d8e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c @@ -15,5 +15,5 @@ void test_vld1u64 (void) out_uint64x1_t = vld1_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c index a63bcf2cd4..600d035184 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld1u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c @@ -15,5 +15,5 @@ void test_vld1u8 (void) out_uint8x8_t = vld1_u8 (0); } -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c index de05fd78f4..9afbbecf72 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c @@ -16,5 +16,5 @@ void test_vld2Q_lanef32 (void) out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c index 30dd2d9b72..e1b85aad9d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c @@ -16,5 +16,5 @@ void test_vld2Q_lanep16 (void) out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c index bc256dd67d..467c02b64b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c @@ -16,5 +16,5 @@ void test_vld2Q_lanes16 (void) out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c index bf184df22c..5f9c4a8b23 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c @@ -16,5 +16,5 @@ void test_vld2Q_lanes32 (void) out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c index 37919becf4..851572917b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c @@ -16,5 +16,5 @@ void test_vld2Q_laneu16 (void) out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c index d42638cd15..65ec23a6f4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c @@ -16,5 +16,5 @@ void test_vld2Q_laneu32 (void) out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c index 6e7d1d3d53..afde42c20a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c @@ -15,6 +15,6 @@ void test_vld2Qf32 (void) out_float32x4x2_t = vld2q_f32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c index 18ee431698..f74004628d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c @@ -15,6 +15,6 @@ void test_vld2Qp16 (void) out_poly16x8x2_t = vld2q_p16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c index 4751de7b8a..9e4ff25f3d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c @@ -15,6 +15,6 @@ void test_vld2Qp8 (void) out_poly8x16x2_t = vld2q_p8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c index 638f24accf..97c8a2c5f8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c @@ -15,6 +15,6 @@ void test_vld2Qs16 (void) out_int16x8x2_t = vld2q_s16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c index 51d7dc87fb..cd03e17d2e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c @@ -15,6 +15,6 @@ void test_vld2Qs32 (void) out_int32x4x2_t = vld2q_s32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c index b3fb47d55f..b33a5a8f4e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c @@ -15,6 +15,6 @@ void test_vld2Qs8 (void) out_int8x16x2_t = vld2q_s8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c index 7955de6aec..76169af569 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c @@ -15,6 +15,6 @@ void test_vld2Qu16 (void) out_uint16x8x2_t = vld2q_u16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c index 6099c06c62..347e164bf0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c @@ -15,6 +15,6 @@ void test_vld2Qu32 (void) out_uint32x4x2_t = vld2q_u32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c index 82632ed383..3b738a7aed 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c @@ -15,6 +15,6 @@ void test_vld2Qu8 (void) out_uint8x16x2_t = vld2q_u8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c index aa74e38ec4..54fbd3da97 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c @@ -15,5 +15,5 @@ void test_vld2_dupf32 (void) out_float32x2x2_t = vld2_dup_f32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c index 71be4c1279..b5ec4e227f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c @@ -15,5 +15,5 @@ void test_vld2_dupp16 (void) out_poly16x4x2_t = vld2_dup_p16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c index 17d4ec1b73..2ad81b53ab 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c @@ -15,5 +15,5 @@ void test_vld2_dupp8 (void) out_poly8x8x2_t = vld2_dup_p8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c index 128e715bec..43b245d3de 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c @@ -15,5 +15,5 @@ void test_vld2_dups16 (void) out_int16x4x2_t = vld2_dup_s16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c index 41461be872..51e4fc8e63 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c @@ -15,5 +15,5 @@ void test_vld2_dups32 (void) out_int32x2x2_t = vld2_dup_s32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c index e9d4b53823..644db84cab 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c @@ -15,5 +15,5 @@ void test_vld2_dups64 (void) out_int64x1x2_t = vld2_dup_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c index 8b3f7979ae..0159233920 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c @@ -15,5 +15,5 @@ void test_vld2_dups8 (void) out_int8x8x2_t = vld2_dup_s8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c index 6b9df90eb9..85bbc4681f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c @@ -15,5 +15,5 @@ void test_vld2_dupu16 (void) out_uint16x4x2_t = vld2_dup_u16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c index d34acecf5c..3549fde1ca 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c @@ -15,5 +15,5 @@ void test_vld2_dupu32 (void) out_uint32x2x2_t = vld2_dup_u32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c index 16b0465740..a830f83102 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c @@ -15,5 +15,5 @@ void test_vld2_dupu64 (void) out_uint64x1x2_t = vld2_dup_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c index 94c80a9819..c3763c8f2c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c @@ -15,5 +15,5 @@ void test_vld2_dupu8 (void) out_uint8x8x2_t = vld2_dup_u8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c index 2e02a2831a..f60279efd0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c @@ -16,5 +16,5 @@ void test_vld2_lanef32 (void) out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c index d52864b895..0d7f415b77 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c @@ -16,5 +16,5 @@ void test_vld2_lanep16 (void) out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c index 07938a1877..8174e7bee0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c @@ -16,5 +16,5 @@ void test_vld2_lanep8 (void) out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c index c19aacf514..5a1eb54bdc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c @@ -16,5 +16,5 @@ void test_vld2_lanes16 (void) out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c index 6394d9a348..a663c52ff9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c @@ -16,5 +16,5 @@ void test_vld2_lanes32 (void) out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c index 603d3234cf..073ba54179 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c @@ -16,5 +16,5 @@ void test_vld2_lanes8 (void) out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c index e6a873b12c..7250b562ed 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c @@ -16,5 +16,5 @@ void test_vld2_laneu16 (void) out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c index 58e806faa4..9a46c65d00 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c @@ -16,5 +16,5 @@ void test_vld2_laneu32 (void) out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c index b662354f82..ba2007109b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c @@ -16,5 +16,5 @@ void test_vld2_laneu8 (void) out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c index 75974376a9..c790de9412 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c @@ -15,5 +15,5 @@ void test_vld2f32 (void) out_float32x2x2_t = vld2_f32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c index f166d3554e..4c4338cfc1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c @@ -15,5 +15,5 @@ void test_vld2p16 (void) out_poly16x4x2_t = vld2_p16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c index 612fab6fa7..d319c22e2f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c @@ -15,5 +15,5 @@ void test_vld2p8 (void) out_poly8x8x2_t = vld2_p8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c index 70f6af946b..f725d79de5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c @@ -15,5 +15,5 @@ void test_vld2s16 (void) out_int16x4x2_t = vld2_s16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c index 4a84effcc8..3f417eeee9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c @@ -15,5 +15,5 @@ void test_vld2s32 (void) out_int32x2x2_t = vld2_s32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c index 0a388d0901..b9900893fd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c @@ -15,5 +15,5 @@ void test_vld2s64 (void) out_int64x1x2_t = vld2_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c index 110e88320f..1df9eee6fc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c @@ -15,5 +15,5 @@ void test_vld2s8 (void) out_int8x8x2_t = vld2_s8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c index f2e721bf82..7440e0c087 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c @@ -15,5 +15,5 @@ void test_vld2u16 (void) out_uint16x4x2_t = vld2_u16 (0); } -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c index f0f069e983..940fd74977 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c @@ -15,5 +15,5 @@ void test_vld2u32 (void) out_uint32x2x2_t = vld2_u32 (0); } -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c index 1d2a3bccb3..35c046a0c5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c @@ -15,5 +15,5 @@ void test_vld2u64 (void) out_uint64x1x2_t = vld2_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c index eb0c5a6d4f..2231e26c07 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld2u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c @@ -15,5 +15,5 @@ void test_vld2u8 (void) out_uint8x8x2_t = vld2_u8 (0); } -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c index 6c6f52032f..6bdc1e14ad 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c @@ -16,5 +16,5 @@ void test_vld3Q_lanef32 (void) out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c index e4e60bc65f..12b3be0efa 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c @@ -16,5 +16,5 @@ void test_vld3Q_lanep16 (void) out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c index 0456d3b4bf..8ed21e3d7c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c @@ -16,5 +16,5 @@ void test_vld3Q_lanes16 (void) out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c index fca11ae202..af0118da00 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c @@ -16,5 +16,5 @@ void test_vld3Q_lanes32 (void) out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c index 56c94b2f26..7880b98e49 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c @@ -16,5 +16,5 @@ void test_vld3Q_laneu16 (void) out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c index a73a5a2662..0b1bce5c53 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c @@ -16,5 +16,5 @@ void test_vld3Q_laneu32 (void) out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c index 4589917695..6f16d9d870 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c @@ -15,6 +15,6 @@ void test_vld3Qf32 (void) out_float32x4x3_t = vld3q_f32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c index 8c3e5beb4d..ff4ef8653b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c @@ -15,6 +15,6 @@ void test_vld3Qp16 (void) out_poly16x8x3_t = vld3q_p16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c index 0197f51751..a23749378c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c @@ -15,6 +15,6 @@ void test_vld3Qp8 (void) out_poly8x16x3_t = vld3q_p8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c index ea7709690b..cfa01367f5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c @@ -15,6 +15,6 @@ void test_vld3Qs16 (void) out_int16x8x3_t = vld3q_s16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c index 10896957fe..e1721ef3df 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c @@ -15,6 +15,6 @@ void test_vld3Qs32 (void) out_int32x4x3_t = vld3q_s32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c index ca389ad1c4..9f762ca6fb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c @@ -15,6 +15,6 @@ void test_vld3Qs8 (void) out_int8x16x3_t = vld3q_s8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c index efef26fd75..a2308729fd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c @@ -15,6 +15,6 @@ void test_vld3Qu16 (void) out_uint16x8x3_t = vld3q_u16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c index 077533c2be..21f20f880e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c @@ -15,6 +15,6 @@ void test_vld3Qu32 (void) out_uint32x4x3_t = vld3q_u32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c index c8093b8c1a..7cbcc46908 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c @@ -15,6 +15,6 @@ void test_vld3Qu8 (void) out_uint8x16x3_t = vld3q_u8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c index e38a135413..5423369716 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c @@ -15,5 +15,5 @@ void test_vld3_dupf32 (void) out_float32x2x3_t = vld3_dup_f32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c index d9f3d14bc4..6c08c8343c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c @@ -15,5 +15,5 @@ void test_vld3_dupp16 (void) out_poly16x4x3_t = vld3_dup_p16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c index 43c7fe8e22..fd4a6603fe 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c @@ -15,5 +15,5 @@ void test_vld3_dupp8 (void) out_poly8x8x3_t = vld3_dup_p8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c index 8fec7c5120..4c11e7ef8e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c @@ -15,5 +15,5 @@ void test_vld3_dups16 (void) out_int16x4x3_t = vld3_dup_s16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c index 1118d2467e..b500c24a90 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c @@ -15,5 +15,5 @@ void test_vld3_dups32 (void) out_int32x2x3_t = vld3_dup_s32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c index 2e49c0ed98..cf11f5c1c7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c @@ -15,5 +15,5 @@ void test_vld3_dups64 (void) out_int64x1x3_t = vld3_dup_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c index 7327c9fca0..4f0c8300de 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c @@ -15,5 +15,5 @@ void test_vld3_dups8 (void) out_int8x8x3_t = vld3_dup_s8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c index d188fad754..57e3597bf1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c @@ -15,5 +15,5 @@ void test_vld3_dupu16 (void) out_uint16x4x3_t = vld3_dup_u16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c index 17436e047b..e4abde4f38 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c @@ -15,5 +15,5 @@ void test_vld3_dupu32 (void) out_uint32x2x3_t = vld3_dup_u32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c index cedf058298..a917126238 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c @@ -15,5 +15,5 @@ void test_vld3_dupu64 (void) out_uint64x1x3_t = vld3_dup_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c index 1ebe615941..8426187852 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c @@ -15,5 +15,5 @@ void test_vld3_dupu8 (void) out_uint8x8x3_t = vld3_dup_u8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c index 3ee94ed0bb..ccbe45f00c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c @@ -16,5 +16,5 @@ void test_vld3_lanef32 (void) out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c index 3c8598869e..94b4ce4215 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c @@ -16,5 +16,5 @@ void test_vld3_lanep16 (void) out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c index f5f9761d03..12b0786bdc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c @@ -16,5 +16,5 @@ void test_vld3_lanep8 (void) out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c index 51cf8a3cf9..5ab744fc2b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c @@ -16,5 +16,5 @@ void test_vld3_lanes16 (void) out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c index 59a29f77e2..168f3f3639 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c @@ -16,5 +16,5 @@ void test_vld3_lanes32 (void) out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c index e4513aeb96..9d0d1a4b56 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c @@ -16,5 +16,5 @@ void test_vld3_lanes8 (void) out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c index 86a787c09a..baf97a98a8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c @@ -16,5 +16,5 @@ void test_vld3_laneu16 (void) out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c index e4bca9e39f..05d7107f2e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c @@ -16,5 +16,5 @@ void test_vld3_laneu32 (void) out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c index 554178a735..af75563506 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c @@ -16,5 +16,5 @@ void test_vld3_laneu8 (void) out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c index ba18fe0d30..120f834d5b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c @@ -15,5 +15,5 @@ void test_vld3f32 (void) out_float32x2x3_t = vld3_f32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c index 513a3ad77a..2c47f5e8e5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c @@ -15,5 +15,5 @@ void test_vld3p16 (void) out_poly16x4x3_t = vld3_p16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c index c93984ea7e..77c2462e2c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c @@ -15,5 +15,5 @@ void test_vld3p8 (void) out_poly8x8x3_t = vld3_p8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c index f9e6212bd4..355ede8c8e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c @@ -15,5 +15,5 @@ void test_vld3s16 (void) out_int16x4x3_t = vld3_s16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c index cd1256649b..8d18a8843c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c @@ -15,5 +15,5 @@ void test_vld3s32 (void) out_int32x2x3_t = vld3_s32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c index 5a62f84ccf..67bb3568f9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c @@ -15,5 +15,5 @@ void test_vld3s64 (void) out_int64x1x3_t = vld3_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c index b3c3125f93..1be5d11bf8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c @@ -15,5 +15,5 @@ void test_vld3s8 (void) out_int8x8x3_t = vld3_s8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c index 0cd5499865..4db18f0498 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c @@ -15,5 +15,5 @@ void test_vld3u16 (void) out_uint16x4x3_t = vld3_u16 (0); } -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c index bdb66e0008..82c10ff160 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c @@ -15,5 +15,5 @@ void test_vld3u32 (void) out_uint32x2x3_t = vld3_u32 (0); } -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c index ba9465d4e8..bca1df48f1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c @@ -15,5 +15,5 @@ void test_vld3u64 (void) out_uint64x1x3_t = vld3_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c index ec6e2a4db4..c8ac20af1a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld3u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c @@ -15,5 +15,5 @@ void test_vld3u8 (void) out_uint8x8x3_t = vld3_u8 (0); } -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c index 9e596b71bb..5c2499cdc6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c @@ -16,5 +16,5 @@ void test_vld4Q_lanef32 (void) out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c index 3ca293a883..1d2d84e637 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c @@ -16,5 +16,5 @@ void test_vld4Q_lanep16 (void) out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c index f6de5e378e..df23d281c6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c @@ -16,5 +16,5 @@ void test_vld4Q_lanes16 (void) out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c index 0c3c071516..db1daff7b8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c @@ -16,5 +16,5 @@ void test_vld4Q_lanes32 (void) out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c index 301cf8f24a..e2da0ea27c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c @@ -16,5 +16,5 @@ void test_vld4Q_laneu16 (void) out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c index 4ff7a9d7b7..d2960ecfc4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c @@ -16,5 +16,5 @@ void test_vld4Q_laneu32 (void) out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c index 2b59415cc9..0a6e7e6bea 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c @@ -15,6 +15,6 @@ void test_vld4Qf32 (void) out_float32x4x4_t = vld4q_f32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c index 510e0f20cf..5d902f531d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c @@ -15,6 +15,6 @@ void test_vld4Qp16 (void) out_poly16x8x4_t = vld4q_p16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c index c89ae63496..e6d66b048a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c @@ -15,6 +15,6 @@ void test_vld4Qp8 (void) out_poly8x16x4_t = vld4q_p8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c index 98f42705f8..04394215d5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c @@ -15,6 +15,6 @@ void test_vld4Qs16 (void) out_int16x8x4_t = vld4q_s16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c index 16d6133c60..4101fa1bf9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c @@ -15,6 +15,6 @@ void test_vld4Qs32 (void) out_int32x4x4_t = vld4q_s32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c index 3a4620f789..9e74f1e4be 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c @@ -15,6 +15,6 @@ void test_vld4Qs8 (void) out_int8x16x4_t = vld4q_s8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c index 197adf8115..6b84331f64 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c @@ -15,6 +15,6 @@ void test_vld4Qu16 (void) out_uint16x8x4_t = vld4q_u16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c index 942ccfb743..55f7e93e92 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c @@ -15,6 +15,6 @@ void test_vld4Qu32 (void) out_uint32x4x4_t = vld4q_u32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c index 93dad16033..9c766c127f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c @@ -15,6 +15,6 @@ void test_vld4Qu8 (void) out_uint8x16x4_t = vld4q_u8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c index c7fe78ff6c..5315db2d17 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c @@ -15,5 +15,5 @@ void test_vld4_dupf32 (void) out_float32x2x4_t = vld4_dup_f32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c index b88a76c2fd..7ed8224cfc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c @@ -15,5 +15,5 @@ void test_vld4_dupp16 (void) out_poly16x4x4_t = vld4_dup_p16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c index cc9d17e709..ca1f8fa981 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c @@ -15,5 +15,5 @@ void test_vld4_dupp8 (void) out_poly8x8x4_t = vld4_dup_p8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c index c167f01c4e..43dab8f2e9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c @@ -15,5 +15,5 @@ void test_vld4_dups16 (void) out_int16x4x4_t = vld4_dup_s16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c index 8279d31b81..183e3e9ef2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c @@ -15,5 +15,5 @@ void test_vld4_dups32 (void) out_int32x2x4_t = vld4_dup_s32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c index 30b1b2b9a0..f4c50493a3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c @@ -15,5 +15,5 @@ void test_vld4_dups64 (void) out_int64x1x4_t = vld4_dup_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c index 1775b524c6..3a4684a097 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c @@ -15,5 +15,5 @@ void test_vld4_dups8 (void) out_int8x8x4_t = vld4_dup_s8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c index 43571141f0..a436cf0929 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c @@ -15,5 +15,5 @@ void test_vld4_dupu16 (void) out_uint16x4x4_t = vld4_dup_u16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c index aefcac61be..6836abd69e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c @@ -15,5 +15,5 @@ void test_vld4_dupu32 (void) out_uint32x2x4_t = vld4_dup_u32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c index 59f6e04c37..244eb61886 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c @@ -15,5 +15,5 @@ void test_vld4_dupu64 (void) out_uint64x1x4_t = vld4_dup_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c index 7ace026a5c..33c7875175 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c @@ -15,5 +15,5 @@ void test_vld4_dupu8 (void) out_uint8x8x4_t = vld4_dup_u8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c index 1fd2726307..0fc0ab5fcb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c @@ -16,5 +16,5 @@ void test_vld4_lanef32 (void) out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c index 0f021aff0f..b7407ade18 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c @@ -16,5 +16,5 @@ void test_vld4_lanep16 (void) out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c index a6d6a9f6a0..7e084106d6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c @@ -16,5 +16,5 @@ void test_vld4_lanep8 (void) out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c index 3b29ec8c9a..0dc653c5ff 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c @@ -16,5 +16,5 @@ void test_vld4_lanes16 (void) out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c index 86383dbdb0..a3bdaf2349 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c @@ -16,5 +16,5 @@ void test_vld4_lanes32 (void) out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c index 80586c3d66..8555220fab 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c @@ -16,5 +16,5 @@ void test_vld4_lanes8 (void) out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c index 4425b5e19f..4a417f744b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c @@ -16,5 +16,5 @@ void test_vld4_laneu16 (void) out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c index 09d27220e3..c1e013a9f2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c @@ -16,5 +16,5 @@ void test_vld4_laneu32 (void) out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c index 5c1a76f283..31dcf8ae6d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c @@ -16,5 +16,5 @@ void test_vld4_laneu8 (void) out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c index e3315813ee..aa755c0f23 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c @@ -15,5 +15,5 @@ void test_vld4f32 (void) out_float32x2x4_t = vld4_f32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c index d5b415eca5..e0300e8b48 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c @@ -15,5 +15,5 @@ void test_vld4p16 (void) out_poly16x4x4_t = vld4_p16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c index 785e86a2fa..7fbb29cf3d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c @@ -15,5 +15,5 @@ void test_vld4p8 (void) out_poly8x8x4_t = vld4_p8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c index b725e5d9c5..a5ef07b202 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c @@ -15,5 +15,5 @@ void test_vld4s16 (void) out_int16x4x4_t = vld4_s16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c index eaa7b36d58..08b929475e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c @@ -15,5 +15,5 @@ void test_vld4s32 (void) out_int32x2x4_t = vld4_s32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c index 3bc5e43f11..99ea548037 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c @@ -15,5 +15,5 @@ void test_vld4s64 (void) out_int64x1x4_t = vld4_s64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c index 94789dca9c..c9574671ee 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c @@ -15,5 +15,5 @@ void test_vld4s8 (void) out_int8x8x4_t = vld4_s8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c index bd4cef90b5..4dea8af02b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c @@ -15,5 +15,5 @@ void test_vld4u16 (void) out_uint16x4x4_t = vld4_u16 (0); } -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c index d98f0d4768..aee2225897 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c @@ -15,5 +15,5 @@ void test_vld4u32 (void) out_uint32x2x4_t = vld4_u32 (0); } -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c index 55418309a8..2e8575406f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c @@ -15,5 +15,5 @@ void test_vld4u64 (void) out_uint64x1x4_t = vld4_u64 (0); } -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c index af2e686e06..ec1d9f9c40 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vld4u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c @@ -15,5 +15,5 @@ void test_vld4u8 (void) out_uint8x8x4_t = vld4_u8 (0); } -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c index 4b09964191..1f95128e64 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c @@ -16,5 +16,5 @@ void test_vst1Q_lanef32 (void) vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c index d619d5fc94..90e7ccc1bf 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c @@ -16,5 +16,5 @@ void test_vst1Q_lanep16 (void) vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c index 9bc250befe..6abb646c41 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c @@ -16,5 +16,5 @@ void test_vst1Q_lanep8 (void) vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c index 81281a25d1..ec283e228a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c @@ -16,5 +16,5 @@ void test_vst1Q_lanes16 (void) vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c index 43f769e6d7..6e73d6e118 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c @@ -16,5 +16,5 @@ void test_vst1Q_lanes32 (void) vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c index 7ea5940d44..46d369c99a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c @@ -16,5 +16,5 @@ void test_vst1Q_lanes64 (void) vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c index f34faa5e2d..d7b3a1c12a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c @@ -16,5 +16,5 @@ void test_vst1Q_lanes8 (void) vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c index e90dccf96d..27958f6d07 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c @@ -16,5 +16,5 @@ void test_vst1Q_laneu16 (void) vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c index 42816c0431..b4aa760e48 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c @@ -16,5 +16,5 @@ void test_vst1Q_laneu32 (void) vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c index 8b87921a16..54faaa3fec 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c @@ -16,5 +16,5 @@ void test_vst1Q_laneu64 (void) vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c index 4eeee81bbe..9b09e72c2c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c @@ -16,5 +16,5 @@ void test_vst1Q_laneu8 (void) vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c index bd25c0656a..a4b3d8a1cd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c @@ -16,5 +16,5 @@ void test_vst1Qf32 (void) vst1q_f32 (arg0_float32_t, arg1_float32x4_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c index a055bb63a6..9b48733716 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c @@ -16,5 +16,5 @@ void test_vst1Qp16 (void) vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c index fa98e7ab8a..f3843399e5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c @@ -16,5 +16,5 @@ void test_vst1Qp8 (void) vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c index 4265f3118c..e6c39cf35f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c @@ -16,5 +16,5 @@ void test_vst1Qs16 (void) vst1q_s16 (arg0_int16_t, arg1_int16x8_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c index d252f9a348..587dcf0ecd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c @@ -16,5 +16,5 @@ void test_vst1Qs32 (void) vst1q_s32 (arg0_int32_t, arg1_int32x4_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c index 01aeebf982..50511d1ea2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c @@ -16,5 +16,5 @@ void test_vst1Qs64 (void) vst1q_s64 (arg0_int64_t, arg1_int64x2_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c index 860b8c5f21..2de9814b07 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c @@ -16,5 +16,5 @@ void test_vst1Qs8 (void) vst1q_s8 (arg0_int8_t, arg1_int8x16_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c index 2c3cc222da..81d8cc5ef9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c @@ -16,5 +16,5 @@ void test_vst1Qu16 (void) vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c index f67fc1abe4..408c6b29ea 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c @@ -16,5 +16,5 @@ void test_vst1Qu32 (void) vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c index e0a4d98412..1c17e5b0c1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c @@ -16,5 +16,5 @@ void test_vst1Qu64 (void) vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c index ff9c66fc9d..1605e27568 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c @@ -16,5 +16,5 @@ void test_vst1Qu8 (void) vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c index 57f1106008..7817031403 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c @@ -16,5 +16,5 @@ void test_vst1_lanef32 (void) vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c index a5fc94fe10..c6a19daf2b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c @@ -16,5 +16,5 @@ void test_vst1_lanep16 (void) vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c index 6a5ca7ea93..1b5dd4f77f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c @@ -16,5 +16,5 @@ void test_vst1_lanep8 (void) vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c index 9e1ee3a7fa..4efdc50249 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c @@ -16,5 +16,5 @@ void test_vst1_lanes16 (void) vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c index 251b8a9680..9c3c1354cb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c @@ -16,5 +16,5 @@ void test_vst1_lanes32 (void) vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c index fb48c8b62c..64fed4a100 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c @@ -16,5 +16,5 @@ void test_vst1_lanes64 (void) vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c index bc932aed41..59646f8a0f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c @@ -16,5 +16,5 @@ void test_vst1_lanes8 (void) vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c index 0ba3d3838d..6ae7166472 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c @@ -16,5 +16,5 @@ void test_vst1_laneu16 (void) vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c index bf953c4b2d..369abf7fa3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c @@ -16,5 +16,5 @@ void test_vst1_laneu32 (void) vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c index 4f486d3f19..7296fee8bd 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c @@ -16,5 +16,5 @@ void test_vst1_laneu64 (void) vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c index 144864f788..ba6076e1f7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c @@ -16,5 +16,5 @@ void test_vst1_laneu8 (void) vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c index 3690958bcd..f3460f5e7c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c @@ -16,5 +16,5 @@ void test_vst1f32 (void) vst1_f32 (arg0_float32_t, arg1_float32x2_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c index aa38de1117..7504c5cf8a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c @@ -16,5 +16,5 @@ void test_vst1p16 (void) vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c index bfef51d6d5..3059aac60e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c @@ -16,5 +16,5 @@ void test_vst1p8 (void) vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c index a5e785d3e3..fbddb2fd79 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c @@ -16,5 +16,5 @@ void test_vst1s16 (void) vst1_s16 (arg0_int16_t, arg1_int16x4_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c index a0088ae51d..f264db0363 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c @@ -16,5 +16,5 @@ void test_vst1s32 (void) vst1_s32 (arg0_int32_t, arg1_int32x2_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c index fc304f92a7..64de48bb01 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c @@ -16,5 +16,5 @@ void test_vst1s64 (void) vst1_s64 (arg0_int64_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c index b63274004a..7916448d88 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c @@ -16,5 +16,5 @@ void test_vst1s8 (void) vst1_s8 (arg0_int8_t, arg1_int8x8_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c index 381a47e89e..797aef16f8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c @@ -16,5 +16,5 @@ void test_vst1u16 (void) vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); } -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c index ec73ac6812..563ea9dc39 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c @@ -16,5 +16,5 @@ void test_vst1u32 (void) vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); } -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c index 8cd9a28d81..b95f5d587a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c @@ -16,5 +16,5 @@ void test_vst1u64 (void) vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c index ff557cee44..75358e769a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst1u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c @@ -16,5 +16,5 @@ void test_vst1u8 (void) vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); } -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c index 2d35d1ce4d..4857356321 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c @@ -16,5 +16,5 @@ void test_vst2Q_lanef32 (void) vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c index 8a8a84672d..bed15034c2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c @@ -16,5 +16,5 @@ void test_vst2Q_lanep16 (void) vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c index 5b01c0ce70..57867352f1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c @@ -16,5 +16,5 @@ void test_vst2Q_lanes16 (void) vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c index 81e125f20d..cf0dc15dd4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c @@ -16,5 +16,5 @@ void test_vst2Q_lanes32 (void) vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c index ed4a1e610a..b751e6b97a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c @@ -16,5 +16,5 @@ void test_vst2Q_laneu16 (void) vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c index d2f39ffd1b..b5fbe0e281 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c @@ -16,5 +16,5 @@ void test_vst2Q_laneu32 (void) vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c index 426a19570c..56f9adcda5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c @@ -16,6 +16,6 @@ void test_vst2Qf32 (void) vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c index aeae48c0f0..1841990339 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c @@ -16,6 +16,6 @@ void test_vst2Qp16 (void) vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c index d18410cb50..2d98ec910e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c @@ -16,6 +16,6 @@ void test_vst2Qp8 (void) vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c index 9fad004eb5..39395f6d02 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c @@ -16,6 +16,6 @@ void test_vst2Qs16 (void) vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c index 6cd063d757..1768d47868 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c @@ -16,6 +16,6 @@ void test_vst2Qs32 (void) vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c index c09dea2e31..423cb8c8f7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c @@ -16,6 +16,6 @@ void test_vst2Qs8 (void) vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c index 6a5cf5635f..a25958a720 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c @@ -16,6 +16,6 @@ void test_vst2Qu16 (void) vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c index 4b4d27fb4b..47722b3521 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c @@ -16,6 +16,6 @@ void test_vst2Qu32 (void) vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c index e1b32e84ef..b794780266 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c @@ -16,6 +16,6 @@ void test_vst2Qu8 (void) vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c index 5aa11e799e..e7752920e7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c @@ -16,5 +16,5 @@ void test_vst2_lanef32 (void) vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c index 27fe65056d..be9913b396 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c @@ -16,5 +16,5 @@ void test_vst2_lanep16 (void) vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c index b6ee44109c..0a95e268d6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c @@ -16,5 +16,5 @@ void test_vst2_lanep8 (void) vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c index 00303752f4..728593ccba 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c @@ -16,5 +16,5 @@ void test_vst2_lanes16 (void) vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c index 6f2cf260d1..32d49b58c6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c @@ -16,5 +16,5 @@ void test_vst2_lanes32 (void) vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c index 5e32ccb61c..9e67eb3234 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c @@ -16,5 +16,5 @@ void test_vst2_lanes8 (void) vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c index bfdf447b15..d56f209615 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c @@ -16,5 +16,5 @@ void test_vst2_laneu16 (void) vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c index 22580003f6..053704cea0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c @@ -16,5 +16,5 @@ void test_vst2_laneu32 (void) vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c index b10c78abf1..a35360088b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c @@ -16,5 +16,5 @@ void test_vst2_laneu8 (void) vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c index 45c084f082..b43c4135ba 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c @@ -16,5 +16,5 @@ void test_vst2f32 (void) vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c index 9f29ddf26d..1d112ff658 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c @@ -16,5 +16,5 @@ void test_vst2p16 (void) vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c index 92ae9c40a8..59c4d62e34 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c @@ -16,5 +16,5 @@ void test_vst2p8 (void) vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c index 30b6a2b043..eb6cb59a40 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c @@ -16,5 +16,5 @@ void test_vst2s16 (void) vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c index 208e2586b8..a17b58dc47 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c @@ -16,5 +16,5 @@ void test_vst2s32 (void) vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c index 4cc53b4679..668ae50a43 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c @@ -16,5 +16,5 @@ void test_vst2s64 (void) vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c index e56b49341f..343414e34d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c @@ -16,5 +16,5 @@ void test_vst2s8 (void) vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c index 7d8d83ec53..903279d0dc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c @@ -16,5 +16,5 @@ void test_vst2u16 (void) vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); } -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c index dafab12ca5..1396ed119e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c @@ -16,5 +16,5 @@ void test_vst2u32 (void) vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); } -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c index 64f433b18e..006e31f257 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c @@ -16,5 +16,5 @@ void test_vst2u64 (void) vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c index 1b1b6e2660..55cd347799 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst2u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c @@ -16,5 +16,5 @@ void test_vst2u8 (void) vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); } -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c index 334bc26adc..8e4f0dca93 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c @@ -16,5 +16,5 @@ void test_vst3Q_lanef32 (void) vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c index c108bac1db..f8fcb977f5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c @@ -16,5 +16,5 @@ void test_vst3Q_lanep16 (void) vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c index c32ffb6fca..3fde1a3afc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c @@ -16,5 +16,5 @@ void test_vst3Q_lanes16 (void) vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c index faafb9333c..1eb428922e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c @@ -16,5 +16,5 @@ void test_vst3Q_lanes32 (void) vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c index f3fc1c60d9..ca98dded6f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c @@ -16,5 +16,5 @@ void test_vst3Q_laneu16 (void) vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c index e11f4a395e..a2a59d7a78 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c @@ -16,5 +16,5 @@ void test_vst3Q_laneu32 (void) vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c index 61dc577d7b..b4b480fb78 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c @@ -16,6 +16,6 @@ void test_vst3Qf32 (void) vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c index 87d7696427..aa34886f97 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c @@ -16,6 +16,6 @@ void test_vst3Qp16 (void) vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c index 0681c9a47f..b13fcd7e28 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c @@ -16,6 +16,6 @@ void test_vst3Qp8 (void) vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c index e9b8640751..6cac405f05 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c @@ -16,6 +16,6 @@ void test_vst3Qs16 (void) vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c index 2ec2ef0b7c..3c8437094f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c @@ -16,6 +16,6 @@ void test_vst3Qs32 (void) vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c index d6362573a8..fee56af424 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c @@ -16,6 +16,6 @@ void test_vst3Qs8 (void) vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c index f10c69f4d6..af3910b7f4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c @@ -16,6 +16,6 @@ void test_vst3Qu16 (void) vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c index 08820891e6..8828885aff 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c @@ -16,6 +16,6 @@ void test_vst3Qu32 (void) vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c index 919a1cbbb0..c273fe6dc9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c @@ -16,6 +16,6 @@ void test_vst3Qu8 (void) vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c index d527c7803a..de654e9078 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c @@ -16,5 +16,5 @@ void test_vst3_lanef32 (void) vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c index 491f8eb399..de733ff676 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c @@ -16,5 +16,5 @@ void test_vst3_lanep16 (void) vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c index 0546c3ab57..a9a26447f9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c @@ -16,5 +16,5 @@ void test_vst3_lanep8 (void) vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c index 4825789195..a98b40714d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c @@ -16,5 +16,5 @@ void test_vst3_lanes16 (void) vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c index 51da4144d7..5b2450c675 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c @@ -16,5 +16,5 @@ void test_vst3_lanes32 (void) vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c index b75f2109ba..8cd04f7164 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c @@ -16,5 +16,5 @@ void test_vst3_lanes8 (void) vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c index 9686054976..692058d911 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c @@ -16,5 +16,5 @@ void test_vst3_laneu16 (void) vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c index da1af40523..32a5193a35 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c @@ -16,5 +16,5 @@ void test_vst3_laneu32 (void) vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c index 47eccc0dff..952ffcbec0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c @@ -16,5 +16,5 @@ void test_vst3_laneu8 (void) vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c index ac871786a9..e80b8e9162 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c @@ -16,5 +16,5 @@ void test_vst3f32 (void) vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c index 08a861b9f4..1d7831264e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c @@ -16,5 +16,5 @@ void test_vst3p16 (void) vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c index d357fdfadf..ca8c5ec439 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c @@ -16,5 +16,5 @@ void test_vst3p8 (void) vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c index 4fc940e691..5c1bcf9ded 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c @@ -16,5 +16,5 @@ void test_vst3s16 (void) vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c index 82b4cfa6a7..3f5a3aad14 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c @@ -16,5 +16,5 @@ void test_vst3s32 (void) vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c index a8e86d2368..8c6a851db9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c @@ -16,5 +16,5 @@ void test_vst3s64 (void) vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c index 563534db21..8853fbaf51 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c @@ -16,5 +16,5 @@ void test_vst3s8 (void) vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c index 679d7b833e..e17c6c8d68 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c @@ -16,5 +16,5 @@ void test_vst3u16 (void) vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); } -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c index 8705c5eb64..3b7d8ce20b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c @@ -16,5 +16,5 @@ void test_vst3u32 (void) vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); } -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c index 4b15e68b32..08d9c7a084 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c @@ -16,5 +16,5 @@ void test_vst3u64 (void) vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c index 0e31b3b3ab..78944cba08 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst3u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c @@ -16,5 +16,5 @@ void test_vst3u8 (void) vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); } -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c index cb2de05bb4..adbb4d5699 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c @@ -16,5 +16,5 @@ void test_vst4Q_lanef32 (void) vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c index 3d0f81d0c7..587477c87f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c @@ -16,5 +16,5 @@ void test_vst4Q_lanep16 (void) vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c index 6e174a0c9d..3febdf7d86 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c @@ -16,5 +16,5 @@ void test_vst4Q_lanes16 (void) vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c index 323626c925..71406af83b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c @@ -16,5 +16,5 @@ void test_vst4Q_lanes32 (void) vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c index 5a396ac3e2..1229c86a3f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c @@ -16,5 +16,5 @@ void test_vst4Q_laneu16 (void) vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c index 4c3dd6a85d..5e0683f30e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c @@ -16,5 +16,5 @@ void test_vst4Q_laneu32 (void) vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c index 4da79bff12..2ecb6b173a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c @@ -16,6 +16,6 @@ void test_vst4Qf32 (void) vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c index 4892d6df4e..a9b9b7ca95 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c @@ -16,6 +16,6 @@ void test_vst4Qp16 (void) vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c index 3d51e97137..17142c1a06 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c @@ -16,6 +16,6 @@ void test_vst4Qp8 (void) vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c index 9fccc6a622..8511619fe3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c @@ -16,6 +16,6 @@ void test_vst4Qs16 (void) vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c index faa1db202a..f65894eabe 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c @@ -16,6 +16,6 @@ void test_vst4Qs32 (void) vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c index c68fc821dc..a74d58b5f1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c @@ -16,6 +16,6 @@ void test_vst4Qs8 (void) vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c index 98f9b094d3..b124c7cc99 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c @@ -16,6 +16,6 @@ void test_vst4Qu16 (void) vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c index c9bfd05f23..fa7d2130db 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c @@ -16,6 +16,6 @@ void test_vst4Qu32 (void) vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c index 8b86161fa8..d853b12bd1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c @@ -16,6 +16,6 @@ void test_vst4Qu8 (void) vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c index 4bdde6ea5f..acef9f0a31 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c @@ -16,5 +16,5 @@ void test_vst4_lanef32 (void) vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c index c9889b382b..64e4713ff0 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c @@ -16,5 +16,5 @@ void test_vst4_lanep16 (void) vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c index 3d8ef6e4f0..1ac58df28f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c @@ -16,5 +16,5 @@ void test_vst4_lanep8 (void) vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c index 255b4b9b79..e7e1e2aead 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c @@ -16,5 +16,5 @@ void test_vst4_lanes16 (void) vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c index fc5217381a..2c99611a86 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c @@ -16,5 +16,5 @@ void test_vst4_lanes32 (void) vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c index e9dec5d88c..7eebc1644e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c @@ -16,5 +16,5 @@ void test_vst4_lanes8 (void) vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c index ee513a6409..decc7caf22 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c @@ -16,5 +16,5 @@ void test_vst4_laneu16 (void) vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c index 516d04c884..4cfeddbbbb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c @@ -16,5 +16,5 @@ void test_vst4_laneu32 (void) vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c index 531c2b9749..217ced27a9 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c @@ -16,5 +16,5 @@ void test_vst4_laneu8 (void) vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c index e3268f9b8e..931b8ed157 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4f32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c @@ -16,5 +16,5 @@ void test_vst4f32 (void) vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c index 67f32f2969..ea58c44fd3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4p16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c @@ -16,5 +16,5 @@ void test_vst4p16 (void) vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c index 2ed766a8db..95e5ccdf13 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4p8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c @@ -16,5 +16,5 @@ void test_vst4p8 (void) vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c index 94794662dd..7811d74c13 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4s16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c @@ -16,5 +16,5 @@ void test_vst4s16 (void) vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c index 8d22a04061..f93ea4097e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4s32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c @@ -16,5 +16,5 @@ void test_vst4s32 (void) vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c index c9dffec77e..796762a3e8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4s64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c @@ -16,5 +16,5 @@ void test_vst4s64 (void) vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c index 0dbdfc0476..877e2c4077 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4s8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c @@ -16,5 +16,5 @@ void test_vst4s8 (void) vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c index 4eddaf6d64..5de43f591a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4u16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c @@ -16,5 +16,5 @@ void test_vst4u16 (void) vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); } -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c index 06a5d33cba..1ae9e5e600 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4u32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c @@ -16,5 +16,5 @@ void test_vst4u32 (void) vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); } -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c index 063a046afc..2453d6bd51 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4u64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c @@ -16,5 +16,5 @@ void test_vst4u64 (void) vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); } -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c index d4da67b929..380acc647f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vst4u8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c @@ -16,5 +16,5 @@ void test_vst4u8 (void) vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); } -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/no-wmla-1.c b/gcc/testsuite/gcc.target/arm/no-wmla-1.c new file mode 100644 index 0000000000..1be162e055 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/no-wmla-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +int +foo (int a, short b, short c) +{ + int bc = b * c; + return a + (short)bc; +} + +/* { dg-final { scan-assembler "\tmul\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr42575.c b/gcc/testsuite/gcc.target/arm/pr42575.c index 474bf6cf60..1998e323df 100644 --- a/gcc/testsuite/gcc.target/arm/pr42575.c +++ b/gcc/testsuite/gcc.target/arm/pr42575.c @@ -1,4 +1,4 @@ -/* { dg-options "-O2 -march=armv7-a" } */ +/* { dg-options "-O2" } */ /* Make sure RA does good job allocating registers and avoids unnecessary moves. */ /* { dg-final { scan-assembler-not "mov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr42835.c b/gcc/testsuite/gcc.target/arm/pr42835.c index 71c51ebe31..867dd0287f 100644 --- a/gcc/testsuite/gcc.target/arm/pr42835.c +++ b/gcc/testsuite/gcc.target/arm/pr42835.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mthumb -Os" } */ +/* { dg-options "-mthumb -Os -fno-tree-tail-merge" } */ /* { dg-require-effective-target arm_thumb2_ok } */ int foo(int *p, int i) diff --git a/gcc/testsuite/gcc.target/arm/pr42879.c b/gcc/testsuite/gcc.target/arm/pr42879.c index 9961a839fb..9fcdad694a 100644 --- a/gcc/testsuite/gcc.target/arm/pr42879.c +++ b/gcc/testsuite/gcc.target/arm/pr42879.c @@ -4,6 +4,9 @@ struct A { +#ifdef __ARMEB__ + int dummy:31; +#endif int v:1; }; diff --git a/gcc/testsuite/gcc.target/arm/pr43597.c b/gcc/testsuite/gcc.target/arm/pr43597.c new file mode 100644 index 0000000000..af382ba72d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr43597.c @@ -0,0 +1,28 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -save-temps -mthumb" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +extern int bar (); +extern void bar2 (int); + +int +foo4 () +{ + int result = 0; + int f = -1; + f = bar (); + if (f < 0) + { + result = 1; + goto bail; + } + bar (); + bail: + bar2 (f); + return result; +} + +/* { dg-final { scan-assembler-times "sub" 1 } } */ +/* { dg-final { scan-assembler-times "cmp" 0 } } */ +/* { dg-final { object-size text <= 30 } } */ +/* { dg-final { cleanup-saved-temps "pr43597" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr43698.c b/gcc/testsuite/gcc.target/arm/pr43698.c index 407cf7eac2..1fc497c22c 100644 --- a/gcc/testsuite/gcc.target/arm/pr43698.c +++ b/gcc/testsuite/gcc.target/arm/pr43698.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-Os -march=armv7-a" } */ +/* { dg-options "-Os" } */ #include <stdint.h> #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/pr43920-1.c b/gcc/testsuite/gcc.target/arm/pr43920-1.c new file mode 100644 index 0000000000..d673f1e88b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr43920-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +f (int start, int end, int *start_) +{ + if (start == -1 || end == -1) + return -1; + + if (end - start) + return -1; + + *start_ = start; + + return 0; +} + +/* { dg-final { scan-assembler-times "\torr" 0 } } */ +/* { dg-final { scan-assembler-times "\tit\t" 0 } } */ +/* { dg-final { scan-assembler "\tbeq" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr43920-2.c b/gcc/testsuite/gcc.target/arm/pr43920-2.c new file mode 100644 index 0000000000..f647165bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr43920-2.c @@ -0,0 +1,30 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os -save-temps" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +#include <stdio.h> + +int getFileStartAndLength (int fd, int *start_, size_t *length_) +{ + int start, end; + size_t length; + + start = lseek (fd, 0L, SEEK_CUR); + end = lseek (fd, 0L, SEEK_END); + + if (start == -1 || end == -1) + return -1; + + length = end - start; + if (length == 0) + return -1; + + *start_ = start; + *length_ = length; + + return 0; +} + +/* { dg-final { scan-assembler-times "pop" 2 } } */ +/* { dg-final { scan-assembler-times "beq" 3 } } */ +/* { dg-final { object-size text <= 54 } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr46329.c b/gcc/testsuite/gcc.target/arm/pr46329.c new file mode 100644 index 0000000000..9dd939c7f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr46329.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +int __attribute__ ((vector_size (32))) x; +void +foo (void) +{ + x <<= x; +} diff --git a/gcc/testsuite/gcc.target/arm/pr46975.c b/gcc/testsuite/gcc.target/arm/pr46975.c new file mode 100644 index 0000000000..60d773b1e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr46975.c @@ -0,0 +1,9 @@ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "subs" } } */ +/* { dg-final { scan-assembler "adcs" } } */ + +int foo (int s) +{ + return s == 1; +} diff --git a/gcc/testsuite/gcc.target/arm/pr48183.c b/gcc/testsuite/gcc.target/arm/pr48183.c new file mode 100644 index 0000000000..f021825b10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr48183.c @@ -0,0 +1,25 @@ +/* testsuite/gcc.target/arm/pr48183.c */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O -g" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n) +{ + unsigned i; + int16x4x2_t input; + int32x4x2_t mid; + int32x4x2_t output; + + for (i = 0; i < n/2; i += 8) { + input = vld2_s16(src + i); + mid.val[0] = vmovl_s16(input.val[0]); + mid.val[1] = vmovl_s16(input.val[1]); + output.val[0] = vshlq_n_s32(mid.val[0], 8); + output.val[1] = vshlq_n_s32(mid.val[1], 8); + vst2q_s32((int32_t *)dst + i, output); + } +} diff --git a/gcc/testsuite/gcc.target/arm/pr49641.c b/gcc/testsuite/gcc.target/arm/pr49641.c new file mode 100644 index 0000000000..7f9b3769c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr49641.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */ +typedef struct { + void *t1, *t2, *t3; +} z; +extern volatile int y; +static inline void foo(z *x) { + x->t1 = &x->t2; + x->t2 = ((void *)0); + x->t3 = &x->t1; +} +extern z v; +void bar (void) { + y = 0; + foo(&v); +} diff --git a/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc/testsuite/gcc.target/arm/pr50099.c new file mode 100644 index 0000000000..c0d143dd57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr50099.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long long foo (signed char * arg) +{ + long long temp_1; + + temp_1 = arg[256]; + return temp_1; +} diff --git a/gcc/testsuite/gcc.target/arm/pr50305.c b/gcc/testsuite/gcc.target/arm/pr50305.c new file mode 100644 index 0000000000..2f6ad5cfea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr50305.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */ + +struct event { + unsigned long long id; + unsigned int flag; +}; + +void dummy(void) +{ + /* This is here to ensure that the offset of perf_event_id below + relative to the LANCHOR symbol exceeds the allowed displacement. */ + static int __warned[300]; + __warned[0] = 1; +} + +extern void *kmem_cache_alloc_trace (void *cachep); +extern void *cs_cachep; +extern int nr_cpu_ids; + +struct event * +event_alloc (int cpu) +{ + static unsigned long long __attribute__((aligned(8))) perf_event_id; + struct event *event; + unsigned long long result; + unsigned long tmp; + + if (cpu >= nr_cpu_ids) + return 0; + + event = kmem_cache_alloc_trace (cs_cachep); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + __asm__ __volatile__("@ atomic64_add_return\n" +"1: ldrexd %0, %H0, [%3]\n" +" adds %0, %0, %4\n" +" adc %H0, %H0, %H4\n" +" strexd %1, %0, %H0, [%3]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id) + : "r" (&perf_event_id), "r" (1LL) + : "cc"); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + event->id = result; + + if (cpu) + event->flag = 1; + + for (cpu = 0; cpu < nr_cpu_ids; cpu++) + kmem_cache_alloc_trace (cs_cachep); + + return event; +} + diff --git a/gcc/testsuite/gcc.target/arm/pr50318-1.c b/gcc/testsuite/gcc.target/arm/pr50318-1.c new file mode 100644 index 0000000000..05885e1b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr50318-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long test (unsigned int sec, unsigned long long nsecs) +{ + return (long long)(long)sec * 1000000000L + (long long)(unsigned + long)nsecs; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr51835.c b/gcc/testsuite/gcc.target/arm/pr51835.c new file mode 100644 index 0000000000..6d462d9159 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr51835.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-skip-if "avoid conflicting -mfpu" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv4-sp-d16" "-mfpu=vfpv3xd" "-mfpu=vfpv3xd-fp16" } } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=hard -mfpu=fpv4-sp-d16" } */ + +int func1 (double d) +{ + return (int)d; +} +unsigned int func2 (double d) +{ + return (unsigned int)d; +} + +/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */ +/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr51915.c b/gcc/testsuite/gcc.target/arm/pr51915.c new file mode 100644 index 0000000000..144d522f85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr51915.c @@ -0,0 +1,15 @@ +/* PR target/51915 */ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ + +struct S { int s1; void *s2; }; +struct T { struct S t1; unsigned long long t2; }; +struct S *foo (unsigned long long); + +struct S * +bar (struct S *x) +{ + return foo (((struct T *) x)->t2); +} diff --git a/gcc/testsuite/gcc.target/arm/pr51968.c b/gcc/testsuite/gcc.target/arm/pr51968.c new file mode 100644 index 0000000000..f0506c267f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr51968.c @@ -0,0 +1,32 @@ +/* PR target/51968 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ +/* { dg-require-effective-target arm_neon_ok } */ + +typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_qi int8x16_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_hi int16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_si int32x4_t __attribute__ ((__vector_size__ (16))); +struct T { int8x8_t val[2]; }; +int y; + +void +foo (int8x8_t z, int8x8_t x, int16x8_t b, int8x8_t n) +{ + if (y) + { + struct T m; + __builtin_neon_vuzpv8qi (&m.val[0], z, x); + } + for (;;) + { + int8x16_t g; + int8x8_t h, j, k; + struct T m; + j = __builtin_neon_vqmovunv8hi (b, 1); + g = __builtin_neon_vcombinev8qi (j, h); + k = __builtin_neon_vget_lowv16qi (g); + __builtin_neon_vuzpv8qi (&m.val[0], k, n); + } +} diff --git a/gcc/testsuite/gcc.target/arm/pr52006.c b/gcc/testsuite/gcc.target/arm/pr52006.c new file mode 100644 index 0000000000..c274449ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr52006.c @@ -0,0 +1,21 @@ +/* PR target/52006 */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicts with multilib flags" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2 -fPIC" } */ + +unsigned long a; +static int b; + +void +foo (void) +{ + asm volatile ("" : "=r" (b)); +} + +void +bar (float f) +{ + if (f < b / 100.0) + a = 1; +} diff --git a/gcc/testsuite/gcc.target/arm/pr52375.c b/gcc/testsuite/gcc.target/arm/pr52375.c new file mode 100644 index 0000000000..0405c6685f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr52375.c @@ -0,0 +1,15 @@ +/* PR target/52375 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -O -ftree-vectorize" } */ + +struct C { int c, d; }; + +unsigned +foo (struct C *p) +{ + unsigned int b = 0, i; + for (i = 0; i < 64; i++) + b |= 0x80000000U >> p[i].c; + return b; +} diff --git a/gcc/testsuite/gcc.target/arm/pr52633.c b/gcc/testsuite/gcc.target/arm/pr52633.c new file mode 100644 index 0000000000..b904d59d95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr52633.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/52633 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */ + +void +test (unsigned short *x, signed char *y) +{ + int i; + for (i = 0; i < 32; i++) + x[i] = (short) (y[i] << 5); +} + diff --git a/gcc/testsuite/gcc.target/arm/pr53187.c b/gcc/testsuite/gcc.target/arm/pr53187.c new file mode 100644 index 0000000000..b40dbbb310 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr53187.c @@ -0,0 +1,15 @@ +/* PR target/53187 */ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ + +void bar (int); + +void +foo (int x, double y, double z) +{ + _Bool t = z >= y; + if (!t || x) + bar (t ? 1 : 16); +} diff --git a/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc/testsuite/gcc.target/arm/pr54892.c new file mode 100644 index 0000000000..a7fe1bc667 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr54892.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +int set_role(unsigned char role_id, short m_role) +{ + return __sync_bool_compare_and_swap(&m_role, -1, role_id); +} + diff --git a/gcc/testsuite/gcc.target/arm/scd42-2.c b/gcc/testsuite/gcc.target/arm/scd42-2.c index 0c372983a5..e077402344 100644 --- a/gcc/testsuite/gcc.target/arm/scd42-2.c +++ b/gcc/testsuite/gcc.target/arm/scd42-2.c @@ -2,6 +2,8 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=xscale -O" } */ /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm32 } */ unsigned load2(void) __attribute__ ((naked)); diff --git a/gcc/testsuite/gcc.target/arm/shiftable.c b/gcc/testsuite/gcc.target/arm/shiftable.c new file mode 100644 index 0000000000..f3080620a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/shiftable.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ + +/* ARM has shift-and-alu insns. Depending on the ALU op GCC represents some + of these as a left shift, others as a multiply. Check that we match the + right one. */ + +int +plus (int a, int b) +{ + return (a * 64) + b; +} + +/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */ + +int +minus (int a, int b) +{ + return a - (b * 64); +} + +/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */ + +int +ior (int a, int b) +{ + return (a * 64) | b; +} + +/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */ + +int +xor (int a, int b) +{ + return (a * 64) ^ b; +} + +/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */ + +int +and (int a, int b) +{ + return (a * 64) & b; +} + +/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */ + +int +rsb (int a, int b) +{ + return (a * 64) - b; +} + +/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */ + +int +mvn (int a, int b) +{ + return ~(a * 64); +} + +/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */ diff --git a/gcc/testsuite/gcc.target/arm/sibcall-2.c b/gcc/testsuite/gcc.target/arm/sibcall-2.c new file mode 100644 index 0000000000..921c0f3028 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/sibcall-2.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=aapcs" } */ + + +extern void __attribute__((weak)) wfunc(void); +void main(void) +{ + wfunc(); /* Must not tail-call. */ +} + +/* { dg-final { scan-assembler-not "b\[\\t \]+wfunc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/smlaltb-1.c b/gcc/testsuite/gcc.target/arm/smlaltb-1.c new file mode 100644 index 0000000000..1472c9b3fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long int +foo (long long x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltb\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/smlaltt-1.c b/gcc/testsuite/gcc.target/arm/smlaltt-1.c new file mode 100644 index 0000000000..6bcbce0b95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltt-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long int +foo (long long x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltt\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/smlatb-1.c b/gcc/testsuite/gcc.target/arm/smlatb-1.c new file mode 100644 index 0000000000..d73aa18ea7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +int +foo (int x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatb\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/smlatt-1.c b/gcc/testsuite/gcc.target/arm/smlatt-1.c new file mode 100644 index 0000000000..d7fb034000 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatt-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +int +foo (int x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatt\\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc/testsuite/gcc.target/arm/stack-red-zone.c new file mode 100644 index 0000000000..b9f0f99371 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stack-red-zone.c @@ -0,0 +1,12 @@ +/* No stack red zone. PR38644. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */ + +extern int doStreamReadBlock (int *, char *, int size, int); + +char readStream (int *s) +{ + char c = 0; + doStreamReadBlock (s, &c, 1, *s); + return c; +} diff --git a/gcc/testsuite/gcc.target/arm/sync-1.c b/gcc/testsuite/gcc.target/arm/sync-1.c index ad85a04b39..d1b6481051 100644 --- a/gcc/testsuite/gcc.target/arm/sync-1.c +++ b/gcc/testsuite/gcc.target/arm/sync-1.c @@ -1,5 +1,6 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=armv7-a" } */ + +/* { dg-do run { target sync_int_long } } */ +/* { dg-options "-O2" } */ volatile int mem; diff --git a/gcc/testsuite/gcc.target/arm/synchronize.c b/gcc/testsuite/gcc.target/arm/synchronize.c index 8626d8ee0a..cf5dcdf5c5 100644 --- a/gcc/testsuite/gcc.target/arm/synchronize.c +++ b/gcc/testsuite/gcc.target/arm/synchronize.c @@ -1,4 +1,4 @@ -/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */ +/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi* } } } */ void *foo (void) { diff --git a/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c new file mode 100644 index 0000000000..f2c0225a4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c @@ -0,0 +1,40 @@ +/* Wrong method to get number of arg reg will cause argument corruption. */ +/* { dg-do run } */ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-options "-mthumb -O1" } */ + +extern void abort (void); + +int foo (int, int, int, int) __attribute__((noinline)); + +int +foo (int a, int b, int c, int d) +{ + register int m asm ("r8"); + + m = a; + m += b; + m += c; + m += d; + + asm ("" : "=r" (m) : "0" (m)); + + return m; +} + +int +main () +{ + volatile int a = 10; + volatile int b = 20; + volatile int c = 30; + volatile int d = 40; + volatile int sum = 0; + + sum = foo (a, b, c, d); + + if (sum != 100) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c new file mode 100644 index 0000000000..45ab605e72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpne" } } */ + +int f(int i, int j) +{ + if ( (i == '+') || (j == '-') ) { + return 1; + } else { + return 0; + } +} diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c new file mode 100644 index 0000000000..17d9a8f76d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpeq" } } */ + +int f(int i, int j) +{ + if ( (i == '+') && (j == '-') ) { + return 1; + } else { + return 0; + } +} diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c new file mode 100644 index 0000000000..6b2a79b1a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j > '-') : 0) + return 1; + else + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c new file mode 100644 index 0000000000..80e1076fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j <= '-') : 1) + return 1; + else + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c new file mode 100644 index 0000000000..e10ea03758 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c @@ -0,0 +1,27 @@ +/* Ensure simple replicated constant immediates work. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a + 0xfefefefe; +} + +/* { dg-final { scan-assembler "add.*#-16843010" } } */ + +int +foo2 (int a) +{ + return a - 0xab00ab00; +} + +/* { dg-final { scan-assembler "sub.*#-1426019584" } } */ + +int +foo3 (int a) +{ + return a & 0x00cd00cd; +} + +/* { dg-final { scan-assembler "and.*#13435085" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c new file mode 100644 index 0000000000..3739adba59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c @@ -0,0 +1,75 @@ +/* Ensure split constants can use replicated patterns. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a + 0xfe00fe01; +} + +/* { dg-final { scan-assembler "add.*#-33489408" } } */ +/* { dg-final { scan-assembler "add.*#1" } } */ + +int +foo2 (int a) +{ + return a + 0xdd01dd00; +} + +/* { dg-final { scan-assembler "add.*#-587145984" } } */ +/* { dg-final { scan-assembler "add.*#65536" } } */ + +int +foo3 (int a) +{ + return a + 0x00443344; +} + +/* { dg-final { scan-assembler "add.*#4456516" } } */ +/* { dg-final { scan-assembler "add.*#13056" } } */ + +int +foo4 (int a) +{ + return a + 0x77330033; +} + +/* { dg-final { scan-assembler "add.*#1996488704" } } */ +/* { dg-final { scan-assembler "add.*#3342387" } } */ + +int +foo5 (int a) +{ + return a + 0x11221122; +} + +/* { dg-final { scan-assembler "add.*#285217024" } } */ +/* { dg-final { scan-assembler "add.*#2228258" } } */ + +int +foo6 (int a) +{ + return a + 0x66666677; +} + +/* { dg-final { scan-assembler "add.*#1717986918" } } */ +/* { dg-final { scan-assembler "add.*#17" } } */ + +int +foo7 (int a) +{ + return a + 0x99888888; +} + +/* { dg-final { scan-assembler "add.*#-2004318072" } } */ +/* { dg-final { scan-assembler "add.*#285212672" } } */ + +int +foo8 (int a) +{ + return a + 0xdddddfff; +} + +/* { dg-final { scan-assembler "add.*#-572662307" } } */ +/* { dg-final { scan-assembler "addw.*#546" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c new file mode 100644 index 0000000000..eb6ad443c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c @@ -0,0 +1,28 @@ +/* Ensure negated/inverted replicated constant immediates work. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a | 0xffffff00; +} + +/* { dg-final { scan-assembler "orn.*#255" } } */ + +int +foo2 (int a) +{ + return a & 0xffeeffee; +} + +/* { dg-final { scan-assembler "bic.*#1114129" } } */ + +int +foo3 (int a) +{ + return a & 0xaaaaaa00; +} + +/* { dg-final { scan-assembler "and.*#-1431655766" } } */ +/* { dg-final { scan-assembler "bic.*#170" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c new file mode 100644 index 0000000000..24efdcf34e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c @@ -0,0 +1,22 @@ +/* Ensure replicated constants don't make things worse. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + /* It might be tempting to use 0x01000100, but it wouldn't help. */ + return a + 0x01f001e0; +} + +/* { dg-final { scan-assembler "add.*#32505856" } } */ +/* { dg-final { scan-assembler "add.*#480" } } */ + +int +foo2 (int a) +{ + return a + 0x0f100e10; +} + +/* { dg-final { scan-assembler "add.*#252706816" } } */ +/* { dg-final { scan-assembler "add.*#3600" } } */ diff --git a/gcc/testsuite/gcc.target/arm/tlscall.c b/gcc/testsuite/gcc.target/arm/tlscall.c new file mode 100644 index 0000000000..366c1ae712 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/tlscall.c @@ -0,0 +1,31 @@ +/* Test non-duplication of tlscall insn */ + +/* { dg-do assemble } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +typedef struct _IO_FILE FILE; + +extern int foo(void); +extern int bar(void); + +void uuid__generate_time() +{ + static int has_init = 0; + static __thread int state_fd = -2; + static __thread FILE *state_f; + + if (!has_init) { + foo(); + has_init = 1; + } + + if (state_fd == -2) { + if (!state_f) { + state_fd = -1; + } + } + if (state_fd >= 0) { + while (bar() < 0) {} + } + +} diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c new file mode 100644 index 0000000000..c4f5640422 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +void unknown_alignment (char *dest, char *src) +{ + memcpy (dest, src, 15); +} + +/* We should see three unaligned word loads and store pairs, one unaligned + ldrh/strh pair, and an ldrb/strb pair. Sanity check that. */ + +/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c new file mode 100644 index 0000000000..c7d24c9c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char dest[16]; + +void aligned_dest (char *src) +{ + memcpy (dest, src, 15); +} + +/* Expect a multi-word store for the main part of the copy, but subword + loads/stores for the remainder. */ + +/* { dg-final { scan-assembler-times "stmia" 1 } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c new file mode 100644 index 0000000000..5f0413738c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char src[16]; + +void aligned_src (char *dest) +{ + memcpy (dest, src, 15); +} + +/* Expect a multi-word load for the main part of the copy, but subword + loads/stores for the remainder. */ + +/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c new file mode 100644 index 0000000000..99957086e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char src[16]; +char dest[16]; + +void aligned_both (void) +{ + memcpy (dest, src, 15); +} + +/* We know both src and dest to be aligned: expect multiword loads/stores. */ + +/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +/* { dg-final { scan-assembler-times "stmia" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c new file mode 100644 index 0000000000..3b4ab048fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo (unsigned char c) +{ + return (c >= '0') && (c <= '9'); +} + +/* { dg-final { scan-assembler-not "uxtb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c new file mode 100644 index 0000000000..b610b73617 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O" } */ + +unsigned short foo (unsigned short x) +{ + unsigned char i = 0; + for (i = 0; i < 8; i++) + { + x >>= 1; + x &= 0x7fff; + } + return x; +} + +/* { dg-final { scan-assembler "ands" } } */ +/* { dg-final { scan-assembler-not "uxtb" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc/testsuite/gcc.target/arm/vfp-1.c index a020622070..d455ea42fe 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/vfp-1.c @@ -127,13 +127,13 @@ void test_convert () { void test_ldst (float f[], double d[]) { /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */ - /* { dg-final { scan-assembler "flds.+ \\\[r0, #-1020\\\]" } } */ + /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ /* { dg-final { scan-assembler "add.+ r0, #1024" } } */ - /* { dg-final { scan-assembler "fsts.+ \\\[r0, #0\\\]\n" } } */ + /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */ f[256] = f[255] + f[-255]; /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */ - /* { dg-final { scan-assembler "fldd.+ \\\[r1, #-1016\\\]" } } */ + /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */ d[32] = d[127] + d[-127]; } diff --git a/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c b/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c new file mode 100644 index 0000000000..805dab1642 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c @@ -0,0 +1,30 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ +/* { dg-final { scan-assembler-not "strb" } } */ + +struct thing { + unsigned a: 8; + unsigned b: 8; + unsigned c: 8; + unsigned d: 8; +}; + +struct thing2 { + volatile unsigned a: 8; + volatile unsigned b: 8; + volatile unsigned c: 8; + volatile unsigned d: 8; +}; + +void test1(volatile struct thing *t) +{ + t->a = 5; +} + +void test2(struct thing2 *t) +{ + t->a = 5; +} diff --git a/gcc/testsuite/gcc.target/arm/wmul-1.c b/gcc/testsuite/gcc.target/arm/wmul-1.c index 426c9393f2..ddddd509fe 100644 --- a/gcc/testsuite/gcc.target/arm/wmul-1.c +++ b/gcc/testsuite/gcc.target/arm/wmul-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_dsp } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ int mac(const short *a, const short *b, int sqr, int *sum) { diff --git a/gcc/testsuite/gcc.target/arm/wmul-10.c b/gcc/testsuite/gcc.target/arm/wmul-10.c new file mode 100644 index 0000000000..5ffd169ba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-10.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + + +unsigned long long +foo (unsigned short a, unsigned short *b, unsigned short *c) +{ + return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-11.c b/gcc/testsuite/gcc.target/arm/wmul-11.c new file mode 100644 index 0000000000..904f0153a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-11.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *b) +{ + return 10 * (long long)*b; +} + +/* { dg-final { scan-assembler "smull" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-12.c b/gcc/testsuite/gcc.target/arm/wmul-12.c new file mode 100644 index 0000000000..5c6b5b9882 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-12.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *b, int *c) +{ + long long tmp = (long long)*b * *c; + return 10 + tmp; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-13.c b/gcc/testsuite/gcc.target/arm/wmul-13.c new file mode 100644 index 0000000000..a73d80f63c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-13.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *a, int *b) +{ + return *a + (long long)*b * 10; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-2.c b/gcc/testsuite/gcc.target/arm/wmul-2.c index 898b5f065c..2ea55f9fbe 100644 --- a/gcc/testsuite/gcc.target/arm/wmul-2.c +++ b/gcc/testsuite/gcc.target/arm/wmul-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_dsp } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ void vec_mpy(int y[], const short x[], short scaler) { diff --git a/gcc/testsuite/gcc.target/arm/wmul-3.c b/gcc/testsuite/gcc.target/arm/wmul-3.c index 83f73fba72..144b553082 100644 --- a/gcc/testsuite/gcc.target/arm/wmul-3.c +++ b/gcc/testsuite/gcc.target/arm/wmul-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_dsp } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ int mac(const short *a, const short *b, int sqr, int *sum) { diff --git a/gcc/testsuite/gcc.target/arm/wmul-4.c b/gcc/testsuite/gcc.target/arm/wmul-4.c index a297bda218..68f9866746 100644 --- a/gcc/testsuite/gcc.target/arm/wmul-4.c +++ b/gcc/testsuite/gcc.target/arm/wmul-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_dsp } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ int mac(const int *a, const int *b, long long sqr, long long *sum) { diff --git a/gcc/testsuite/gcc.target/arm/wmul-5.c b/gcc/testsuite/gcc.target/arm/wmul-5.c new file mode 100644 index 0000000000..9f29a81c0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, char *b, char *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-6.c b/gcc/testsuite/gcc.target/arm/wmul-6.c new file mode 100644 index 0000000000..babdaab1ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, unsigned char *b, signed char *c) +{ + return a + (long long)*b * (long long)*c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-7.c b/gcc/testsuite/gcc.target/arm/wmul-7.c new file mode 100644 index 0000000000..2db4ad4e10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-7.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +unsigned long long +foo (unsigned long long a, unsigned char *b, unsigned short *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-8.c b/gcc/testsuite/gcc.target/arm/wmul-8.c new file mode 100644 index 0000000000..5ae110d3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, int *b, int *c) +{ + return a + (long long)*b * *c; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-9.c b/gcc/testsuite/gcc.target/arm/wmul-9.c new file mode 100644 index 0000000000..40ed0219a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-9.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, short *b, char *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c b/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c new file mode 100644 index 0000000000..2e9da59233 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +struct bf +{ + int a : 3; + int b : 15; + int c : 3; +}; + +long long +foo (long long a, struct bf b, struct bf c) +{ + return a + b.b * c.b; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c b/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c new file mode 100644 index 0000000000..07ba9a84d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +struct bf +{ + int a : 3; + unsigned int b : 15; + int c : 3; +}; + +long long +foo (long long a, struct bf b, struct bf c) +{ + return a + b.b * c.c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/xor-and.c b/gcc/testsuite/gcc.target/arm/xor-and.c new file mode 100644 index 0000000000..53dff85f8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/xor-and.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv6" } */ +/* { dg-prune-output "switch .* conflicts with" } */ + +unsigned short foo (unsigned short x) +{ + x ^= 0x4002; + x >>= 1; + x |= 0x8000; + return x; +} + +/* { dg-final { scan-assembler "orr" } } */ +/* { dg-final { scan-assembler-not "mvn" } } */ +/* { dg-final { scan-assembler-not "uxth" } } */ diff --git a/gcc/testsuite/gcc.target/avr/avr.exp b/gcc/testsuite/gcc.target/avr/avr.exp index 90aeed41e1..a552a96856 100644 --- a/gcc/testsuite/gcc.target/avr/avr.exp +++ b/gcc/testsuite/gcc.target/avr/avr.exp @@ -34,7 +34,7 @@ if ![info exists DEFAULT_CFLAGS] then { dg-init
# Main loop.
-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{\[cCS\],cpp}]] \
"" $DEFAULT_CFLAGS
# All done.
diff --git a/gcc/testsuite/gcc.target/avr/exit-abort.h b/gcc/testsuite/gcc.target/avr/exit-abort.h new file mode 100644 index 0000000000..cf7df203a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/exit-abort.h @@ -0,0 +1,8 @@ +#ifdef __cplusplus +extern "C" { +#endif + extern void exit (int); + extern void abort (void); +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/avr/pr46779-1.c b/gcc/testsuite/gcc.target/avr/pr46779-1.c new file mode 100644 index 0000000000..24522f175b --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr46779-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fsplit-wide-types" } */ + +/* This testcase should uncover bugs like + PR46779 + PR45291 + PR41894 + + The inline asm just serves to direct y into the Y register. + Otherwise, it is hard to write a "stable" test case that + also fails with slight variations in source code, middle- resp. + backend. + + The problem is that Y is also the frame-pointer, and + avr.c:avr_hard_regno_mode_ok disallows QI to get in Y-reg. + However, the y.a = 0 generates a + (set (subreg:QI (reg:HI pseudo)) ...) + where pseudo gets allocated to Y. + + Reload fails to generate the right spill. +*/ + +#include <stdlib.h> + +struct S +{ + unsigned char a, b; +} ab = {12, 34}; + +void yoo (struct S y) +{ + __asm volatile ("ldi %B0, 56" : "+y" (y)); + y.a = 0; + __asm volatile ("; y = %0" : "+y" (y)); + ab = y; +} + +int main () +{ + yoo (ab); + + if (ab.a != 0) + abort(); + + if (ab.b != 56) + abort(); + + exit (0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/pr46779-2.c b/gcc/testsuite/gcc.target/avr/pr46779-2.c new file mode 100644 index 0000000000..682070b5ef --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr46779-2.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-split-wide-types" } */ + +/* This testcase should uncover bugs like + PR46779 + PR45291 + PR41894 + + The inline asm just serves to direct y into the Y register. + Otherwise, it is hard to write a "stable" test case that + also fails with slight variations in source code, middle- resp. + backend. + + The problem is that Y is also the frame-pointer, and + avr.c:avr_hard_regno_mode_ok disallows QI to get in Y-reg. + However, the y.a = 0 generates a + (set (subreg:QI (reg:HI pseudo)) ...) + where pseudo gets allocated to Y. + + Reload fails to generate the right spill. +*/ + +#include <stdlib.h> + +struct S +{ + unsigned char a, b; +} ab = {12, 34}; + +void yoo (struct S y) +{ + __asm volatile ("ldi %B0, 56" : "+y" (y)); + y.a = 0; + __asm volatile ("; y = %0" : "+y" (y)); + ab = y; +} + +int main () +{ + yoo (ab); + + if (ab.a != 0) + abort(); + + if (ab.b != 56) + abort(); + + exit (0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/progmem-error-1.c b/gcc/testsuite/gcc.target/avr/progmem-error-1.c new file mode 100644 index 0000000000..cf53cc8e92 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/progmem-error-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ + +#include "progmem.h" + +char str[] PROGMEM = "Hallo"; /* { dg-error "must be const" } */ diff --git a/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp b/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp new file mode 100644 index 0000000000..cf53cc8e92 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp @@ -0,0 +1,5 @@ +/* { dg-do compile } */ + +#include "progmem.h" + +char str[] PROGMEM = "Hallo"; /* { dg-error "must be const" } */ diff --git a/gcc/testsuite/gcc.target/avr/progmem-warning-1.c b/gcc/testsuite/gcc.target/avr/progmem-warning-1.c new file mode 100644 index 0000000000..67af05fe5b --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/progmem-warning-1.c @@ -0,0 +1,7 @@ +/* PR target/34734 */ +/* { dg-do compile } */ +/* { dg-options "-Wuninitialized" } */ + +#include "progmem.h" + +const char c PROGMEM; /* { dg-warning "uninitialized variable 'c' put into program memory area" } */ diff --git a/gcc/testsuite/gcc.target/avr/progmem.h b/gcc/testsuite/gcc.target/avr/progmem.h new file mode 100644 index 0000000000..17bb771537 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/progmem.h @@ -0,0 +1,25 @@ +#define PROGMEM __attribute__((progmem)) + +#define PSTR(s) \ + (__extension__({ \ + static const char __c[] PROGMEM = (s); \ + &__c[0];})) + +#ifdef __AVR_HAVE_LPMX__ +#define pgm_read_char(addr) \ + (__extension__({ \ + unsigned int __addr16 = (unsigned int)(addr); \ + char __result; \ + __asm__ ("lpm %0, %a1" \ + : "=r" (__result) : "z" (__addr16)); \ + __result; })) +#else +#define pgm_read_char(addr) \ + (__extension__({ \ + unsigned int __addr16 = (unsigned int)(addr); \ + char __result; \ + __asm__ ("lpm" "\n\t" \ + "mov %0, r0" \ + : "=r" (__result) : "z" (__addr16)); \ + __result; })) +#endif diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c new file mode 100644 index 0000000000..880654201d --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99" } */ +/* { dg-do run } */ + +#define __as __flash + +#include "addr-space-1.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c new file mode 100644 index 0000000000..1375265277 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */ +/* { dg-do run } */ + +#define __as __flash1 + +#include "addr-space-1.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c new file mode 100644 index 0000000000..60feca1458 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99" } */ +/* { dg-do run } */ + +#define __as + +#include "addr-space-1.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c new file mode 100644 index 0000000000..0b3c43a4be --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99" } */ +/* { dg-do run } */ + +#define __as __memx + +#include "addr-space-1.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h b/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h new file mode 100644 index 0000000000..322a5b8b3b --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h @@ -0,0 +1,83 @@ +#include <stdlib.h> +#include <string.h> + +typedef struct +{ + char i1; + short i2; + long i4; + long long i8; + char str[2][10]; +} a_t; + +const __as a_t A = + { + 12, 345, 678910, 1234567891011ll, + { + "xxx..xxx", + "yyy..yyy" + } + }; + +const __as volatile a_t V = + { + 12+1, 345+1, 678910+1, 1234567891011ll+1, + { + "XXX..XXX", + "YYY..YYY" + } + }; + +a_t A2; +volatile a_t V2; + +int main (void) +{ + if (A.i1 != 12 + || A.i1 != V.i1 -1) + abort(); + + if (A.i2 != 345 + || A.i2 != V.i2 -1) + abort(); + + if (A.i4 != 678910 + || A.i4 != V.i4 -1) + abort(); + + if (A.i8 != 1234567891011ll + || A.i8 != V.i8 -1) + abort(); + + A2 = A; + V2 = V; + + if (A2.i1 != 12 + || A2.i1 != V2.i1 -1) + abort(); + + if (A2.i2 != 345 + || A2.i2 != V2.i2 -1) + abort(); + + if (A2.i4 != 678910 + || A2.i4 != V2.i4 -1) + abort(); + + if (A2.i8 != 1234567891011ll + || A2.i8 != V2.i8 -1) + abort(); + + if (strcmp (A2.str[0], "xxx..xxx")) + abort(); + if (strcmp (A2.str[1], "yyy..yyy")) + abort(); + + if (strcmp ((const char*) V2.str[0], "XXX..XXX")) + abort(); + if (strcmp ((const char*) V2.str[1], "YYY..YYY")) + abort(); + + exit (0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c new file mode 100644 index 0000000000..d5d4f92a93 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99" } */ +/* { dg-do run } */ + +#define __as __flash + +#include "addr-space-2.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c new file mode 100644 index 0000000000..c8041f7d1e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */ +/* { dg-do run } */ + +#define __as __flash1 + +#include "addr-space-2.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c new file mode 100644 index 0000000000..ad0b2b8410 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c @@ -0,0 +1,6 @@ +/* { dg-options "-std=gnu99" } */ +/* { dg-do run } */ + +#define __as + +#include "addr-space-2.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c new file mode 100644 index 0000000000..846cca47dd --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c @@ -0,0 +1,9 @@ +/* { dg-options "-std=gnu99 -Wa,--no-warn" } */ +/* { dg-do run } */ + +/* --no-warn because: "assembling 24-bit address needs binutils extension" + see binutils PR13503. */ + +#define __as __memx + +#include "addr-space-2.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h b/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h new file mode 100644 index 0000000000..c95a1631ab --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h @@ -0,0 +1,106 @@ +extern void exit (int); +extern void abort (void); + +typedef struct T +{ + char val; + const __as struct T *l, *r; +} tree; + +/* + abcd + / \ + ab cd + / \ / \ + a b c d +*/ + +const __as tree a = { 'a', 0, 0 }; +const __as tree b = { 'b', 0, 0 }; +const __as tree c = { 'c', 0, 0 }; +const __as tree d = { 'd', 0, 0 }; + +const __as tree ab = { 'A', &a, &b }; +const __as tree cd = { 'C', &c, &d }; + +const __as tree abcd = { '*', &ab, &cd }; + +static void +test1 (void) +{ + if (abcd.val != '*') + abort(); + + if (abcd.l->val != 'A') + abort(); + if (abcd.r->val != 'C') + abort(); + + if (abcd.l->l->val != 'a') + abort(); + if (abcd.l->r->val != 'b') + abort(); + if (abcd.r->l->val != 'c') + abort(); + if (abcd.r->r->val != 'd') + abort(); +} + +static void +test2 (const __as tree *t) +{ + if (t->val != '*') + abort(); + + if (t->l->val != 'A') + abort(); + if (t->r->val != 'C') + abort(); + + if (t->l->l->val != 'a') + abort(); + if (t->l->r->val != 'b') + abort(); + if (t->r->l->val != 'c') + abort(); + if (t->r->r->val != 'd') + abort(); +} + +static void +test3 (const __as tree *pt) +{ + tree t = *pt; + + if (t.val != '*') + abort(); + + if (t.l->val != 'A') + abort(); + if (t.r->val != 'C') + abort(); + + if (t.l->l->val != 'a') + abort(); + if (t.l->r->val != 'b') + abort(); + if (t.r->l->val != 'c') + abort(); + if (t.r->r->val != 'd') + abort(); +} + +int main (void) +{ + const __as tree *t = &abcd; + test1(); + test2 (&abcd); + test3 (&abcd); + + __asm ("" : "+r" (t)); + test2 (t); + test3 (t); + + exit (0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp b/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp index 355b3ad88b..61cd3197fb 100644 --- a/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp +++ b/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp @@ -1,61 +1,64 @@ -# Copyright (C) 2008 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3. If not see
-# <http://www.gnu.org/licenses/>.
-
-# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
-# optimization options.
-
-# Exit immediately if this isn't a AVR target.
-if { ![istarget avr-*-*] } then {
- return
-}
-
-# Load support procs.
-load_lib gcc-dg.exp
-
-# If a testcase doesn't have special options, use these.
-global DEFAULT_CFLAGS
-if ![info exists DEFAULT_CFLAGS] then {
- set DEFAULT_CFLAGS " -ansi -pedantic-errors"
-}
-
-# Initialize `dg'.
-dg-init
-
- set AVR_TORTURE_OPTIONS [list \
- { -O0 } \
- { -O1 } \
- { -O2 } \
- { -O2 -mcall-prologues } \
- { -Os -fomit-frame-pointer } \
- { -Os -fomit-frame-pointer -finline-functions } \
- { -O3 -g } \
- { -Os -mcall-prologues} ]
-
-
-#Initialize use of torture lists.
-torture-init
-
-set-torture-options $AVR_TORTURE_OPTIONS
-
-
-# Main loop.
-gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS
-
-# Finalize use of torture lists.
-torture-finish
-
-# All done.
-dg-finish
+# Copyright (C) 2008 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `gcc-dg.exp' driver, looping over +# optimization options. + +# Exit immediately if this isn't a AVR target. +if { ![istarget avr-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + + set AVR_TORTURE_OPTIONS [list \ + { -O0 } \ + { -O1 } \ + { -O2 } \ + { -Os -flto } \ + { -O2 -mcall-prologues } \ + { -O2 -fdata-sections } \ + { -O2 -fmerge-all-constants } \ + { -Os -fomit-frame-pointer } \ + { -Os -fomit-frame-pointer -finline-functions } \ + { -O3 -g } \ + { -Os -mcall-prologues} ] + + +#Initialize use of torture lists. +torture-init + +set-torture-options $AVR_TORTURE_OPTIONS + + +# Main loop. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{\[cS\],cpp}]] $DEFAULT_CFLAGS + +# Finalize use of torture lists. +torture-finish + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c b/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c new file mode 100644 index 0000000000..fe20c91631 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c @@ -0,0 +1,97 @@ +/* { dg-do run } */ + +#include <stdlib.h> + +#define MASK_F(M) \ + (0 \ + | ((0xf == (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0) \ + | ((0xf == (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0) \ + | ((0xf == (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0) \ + | ((0xf == (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0) \ + | ((0xf == (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0) \ + | ((0xf == (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0) \ + | ((0xf == (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0) \ + | ((0xf == (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0) \ + | 0) + +#define MASK_0_7(M) \ + (0 \ + | ((8 > (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0) \ + | ((8 > (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0) \ + | ((8 > (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0) \ + | ((8 > (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0) \ + | ((8 > (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0) \ + | ((8 > (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0) \ + | ((8 > (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0) \ + | ((8 > (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0) \ + | 0) + +#define INSERT_BITS(M,B,V) \ + (__extension__({ \ + unsigned char _n, _r = 0; \ + _n = 0xf & (M >> (4*0)); if (_n<8) _r |= (!!(B & (1 << _n))) << 0; \ + _n = 0xf & (M >> (4*1)); if (_n<8) _r |= (!!(B & (1 << _n))) << 1; \ + _n = 0xf & (M >> (4*2)); if (_n<8) _r |= (!!(B & (1 << _n))) << 2; \ + _n = 0xf & (M >> (4*3)); if (_n<8) _r |= (!!(B & (1 << _n))) << 3; \ + _n = 0xf & (M >> (4*4)); if (_n<8) _r |= (!!(B & (1 << _n))) << 4; \ + _n = 0xf & (M >> (4*5)); if (_n<8) _r |= (!!(B & (1 << _n))) << 5; \ + _n = 0xf & (M >> (4*6)); if (_n<8) _r |= (!!(B & (1 << _n))) << 6; \ + _n = 0xf & (M >> (4*7)); if (_n<8) _r |= (!!(B & (1 << _n))) << 7; \ + (unsigned char) ((V) & MASK_F(M)) | _r; \ + })) + +#define MASK_USED(M) (MASK_F(M) | MASK_0_7(M)) + +#define TEST2(M,B,V) \ + do { \ + __asm volatile (";" #M); \ + r1 = MASK_USED (M) \ + & __builtin_avr_insert_bits (M,B,V); \ + r2 = INSERT_BITS (M,B,V); \ + if (r1 != r2) \ + abort (); \ + } while(0) + +#define TEST1(M,X) \ + do { \ + TEST2 (M,X,0x00); TEST2 (M,0x00,X); \ + TEST2 (M,X,0xff); TEST2 (M,0xff,X); \ + TEST2 (M,X,0xaa); TEST2 (M,0xaa,X); \ + TEST2 (M,X,0xcc); TEST2 (M,0xcc,X); \ + TEST2 (M,X,0x96); TEST2 (M,0x96,X); \ + } while(0) + + + +void test8 (void) +{ + unsigned char r1, r2; + unsigned char ib; + + static const unsigned char V[] = + { + 0, 0xaa, 0xcc, 0xf0, 0xff, 0x5b, 0x4d + }; + + for (ib = 0; ib < sizeof (V) / sizeof (*V); ib++) + { + unsigned char b = V[ib]; + + TEST1 (0x76543210, b); + TEST1 (0x3210ffff, b); + TEST1 (0x67452301, b); + TEST1 (0xf0f1f2f3, b); + TEST1 (0xff10ff54, b); + TEST1 (0x01234567, b); + TEST1 (0xff765f32, b); + } +} + +/****************************************************************/ + +int main() +{ + test8(); + + exit(0); +} diff --git a/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c b/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c new file mode 100644 index 0000000000..06cafd6afa --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c @@ -0,0 +1,94 @@ +/* { dg-do run } */ + +#include <stdlib.h> + +#define MASK_F(M) \ + (0 \ + | ((0xf == (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0) \ + | ((0xf == (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0) \ + | ((0xf == (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0) \ + | ((0xf == (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0) \ + | ((0xf == (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0) \ + | ((0xf == (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0) \ + | ((0xf == (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0) \ + | ((0xf == (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0) \ + | 0) + +#define MASK_0_7(M) \ + (0 \ + | ((8 > (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0) \ + | ((8 > (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0) \ + | ((8 > (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0) \ + | ((8 > (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0) \ + | ((8 > (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0) \ + | ((8 > (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0) \ + | ((8 > (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0) \ + | ((8 > (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0) \ + | 0) + +#define INSERT_BITS(M,B,V) \ + (__extension__({ \ + unsigned char _n, _r = 0; \ + _n = 0xf & (M >> (4*0)); if (_n<8) _r |= (!!(B & (1 << _n))) << 0; \ + _n = 0xf & (M >> (4*1)); if (_n<8) _r |= (!!(B & (1 << _n))) << 1; \ + _n = 0xf & (M >> (4*2)); if (_n<8) _r |= (!!(B & (1 << _n))) << 2; \ + _n = 0xf & (M >> (4*3)); if (_n<8) _r |= (!!(B & (1 << _n))) << 3; \ + _n = 0xf & (M >> (4*4)); if (_n<8) _r |= (!!(B & (1 << _n))) << 4; \ + _n = 0xf & (M >> (4*5)); if (_n<8) _r |= (!!(B & (1 << _n))) << 5; \ + _n = 0xf & (M >> (4*6)); if (_n<8) _r |= (!!(B & (1 << _n))) << 6; \ + _n = 0xf & (M >> (4*7)); if (_n<8) _r |= (!!(B & (1 << _n))) << 7; \ + (unsigned char) ((V) & MASK_F(M)) | _r; \ + })) + +#define MASK_USED(M) (MASK_F(M) | MASK_0_7(M)) + +#define TEST2(M,B,V) \ + do { \ + __asm volatile (";" #M); \ + r1 = MASK_USED (M) \ + & __builtin_avr_insert_bits (M,B,V); \ + r2 = INSERT_BITS (M,B,V); \ + if (r1 != r2) \ + abort (); \ + } while(0) + +void test8 (void) +{ + unsigned char r1, r2; + unsigned char ib, iv; + + static const unsigned char V[] = + { + 0, 0xaa, 0xcc, 0xf0, 0xff, 0x5b, 0x4d + }; + + for (ib = 0; ib < sizeof (V) / sizeof (*V); ib++) + { + unsigned char b = V[ib]; + + for (iv = 0; iv < sizeof (V) / sizeof (*V); iv++) + { + unsigned char v = V[iv]; + + TEST2 (0x76543210, b, v); + TEST2 (0xffffffff, b, v); + TEST2 (0x3210ffff, b, v); + TEST2 (0x67452301, b, v); + TEST2 (0xf0f1f2f3, b, v); + TEST2 (0xff10ff54, b, v); + TEST2 (0x0765f321, b, v); + TEST2 (0x11223344, b, v); + TEST2 (0x01234567, b, v); + TEST2 (0xff7765f3, b, v); + } + } +} + +/****************************************************************/ + +int main() +{ + test8(); + + exit(0); +} diff --git a/gcc/testsuite/gcc.target/avr/torture/builtins-1.c b/gcc/testsuite/gcc.target/avr/torture/builtins-1.c new file mode 100644 index 0000000000..1fa3aaaaeb --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/builtins-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ + +void nop (void) { __builtin_avr_nop (); } +void sei (void) { __builtin_avr_sei (); } +void cli (void) { __builtin_avr_cli (); } +void wdr (void) { __builtin_avr_wdr (); } +void sleep (void) { __builtin_avr_sleep (); } + +char fmul (char a, char b) { return __builtin_avr_fmul (a, b); } +char fmuls (char a, char b) { return __builtin_avr_fmuls (a, b); } +char fmulsu (char a, char b) { return __builtin_avr_fmulsu (a, b); } + +char swap1 (char a) +{ + return __builtin_avr_swap (a+1); +} + +char swap2 (char a) +{ + return __builtin_avr_swap (__builtin_avr_swap (a+1)); +} + +char swap15 (void) +{ + return __builtin_avr_swap (15); +} + +void delay0 (void) { __builtin_avr_delay_cycles (0); } +void delay1 (void) { __builtin_avr_delay_cycles (1); } +void delay2 (void) { __builtin_avr_delay_cycles (2); } +void delay3 (void) { __builtin_avr_delay_cycles (3); } + +void delay_1 (void) { __builtin_avr_delay_cycles (44); } +void delay_2 (void) { __builtin_avr_delay_cycles (0x1234); } +void delay_3 (void) { __builtin_avr_delay_cycles (0x123456); } +void delay_4 (void) { __builtin_avr_delay_cycles (-1ul); } + +/* { dg-final { scan-assembler-not "__builtin_avr_" } } */ diff --git a/gcc/testsuite/gcc.target/avr/torture/builtins-2.c b/gcc/testsuite/gcc.target/avr/torture/builtins-2.c new file mode 100644 index 0000000000..ae207d9a93 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/builtins-2.c @@ -0,0 +1,46 @@ +/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */ +/* { dg-do run } */ + +#include <stdlib.h> +#include "../progmem.h" + +int volatile a; + +void f1 (void) +{ + __builtin_avr_sei (); + __builtin_avr_cli (); + __builtin_avr_wdr (); + __builtin_avr_sleep (); + __builtin_avr_nop (); + a = __builtin_avr_swap (a); + a = __builtin_avr_fmul (1,a); + a = __builtin_avr_fmuls (1,a); + a = __builtin_avr_fmulsu (1,a); + a = __builtin_avr_insert_bits (0x1f2f5364, a, a); +} + +const __flash char c0 = 1; +const __flash1 char c1 = 1; + +int main (void) +{ + const __memx void *p; + + f1(); + __builtin_avr_delay_cycles (1000); + + p = &c0; + if (__builtin_avr_flash_segment (p) != 0) + abort(); + + p = &c1; + if (__builtin_avr_flash_segment (p) != 1) + abort(); + + if (__builtin_avr_flash_segment ("p") != -1) + abort(); + + exit (0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/builtins-error.c b/gcc/testsuite/gcc.target/avr/torture/builtins-error.c new file mode 100644 index 0000000000..692b8afd85 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/builtins-error.c @@ -0,0 +1,11 @@ +/* { dg-do assemble } */ + +char insert (long a) +{ + return __builtin_avr_insert_bits (15.3f+a, 0, 0); /* { dg-error "expects a compile time" } */ +} + +void delay (long a) +{ + __builtin_avr_delay_cycles (a); /* { dg-error "expects a compile time" } */ +} diff --git a/gcc/testsuite/gcc.target/avr/torture/int24-mul.c b/gcc/testsuite/gcc.target/avr/torture/int24-mul.c new file mode 100644 index 0000000000..c85d932771 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/int24-mul.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-options "-w" } */ + +#include <stdlib.h> + +const __flash __int24 vals[] = + { + 0, 1, 2, 3, -1, -2, -3, 0xff, 0x100, 0x101, + 0xffL * 0xff, 0xfffL * 0xfff, 0x101010L, 0xaaaaaaL + }; + +void test_u (void) +{ + unsigned int i; + unsigned long la, lb, lc; + __uint24 a, b, c; + + int S = sizeof (vals) / sizeof (*vals); + + for (i = 0; i < 500; i++) + { + if (i < S*S) + { + a = vals[i / S]; + b = vals[i % S]; + } + else + { + if (i & 1) + a += 0x7654321L; + else + b += 0x5fe453L; + } + + c = a * b; + + la = a; + lb = b; + lc = 0xffffff & (la * lb); + + if (c != lc) + abort(); + } +} + +#define TEST_N_U(A1,A2,B) \ + do { \ + if ((0xffffff & (A1*B)) != A2*B) \ + abort(); \ + } while (0) + +void test_nu (void) +{ + unsigned long la; + unsigned int i; + int S = sizeof (vals) / sizeof (*vals); + __uint24 a; + + for (i = 0; i < 500; i++) + { + a = i < S + ? vals[i % S] + : a + 0x7654321; + + la = a; + + TEST_N_U (la, a, 2); + TEST_N_U (la, a, 3); + TEST_N_U (la, a, 4); + TEST_N_U (la, a, 5); + TEST_N_U (la, a, 15); + TEST_N_U (la, a, 16); + TEST_N_U (la, a, 128); + TEST_N_U (la, a, 0x1000); + } +} + +int main (void) +{ + test_u(); + test_nu(); + + exit(0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr39633.c b/gcc/testsuite/gcc.target/avr/torture/pr39633.c new file mode 100644 index 0000000000..c5f5b0450e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr39633.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ + +#include <stdlib.h> + +char c = 42; + +void __attribute__((noinline,noclone)) +pr39633 (char a) +{ + a >>= 7; + if (a) + c = a; +} + +int main() +{ + pr39633 (6); + + if (c != 42) + abort(); + + exit(0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr41885.c b/gcc/testsuite/gcc.target/avr/torture/pr41885.c index 90d0012125..f46bc5a758 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr41885.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr41885.c @@ -1,4 +1,4 @@ -/* { dg-options "-w -std=c99" } */ +/* { dg-options "-w -std=c99 -fno-inline" } */ /* { dg-do run } */ #include <limits.h> diff --git a/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c b/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c new file mode 100644 index 0000000000..9c98ea5f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c @@ -0,0 +1,15 @@ +/* PR rtl-optimization/51374 */ +/* { dg-do compile } */ + +void vector_18 (void) +{ + extern char slot; + unsigned char status = (*(volatile unsigned char*) 0x2B); + unsigned char data = (*(volatile unsigned char*) 0x2C); + + if (status & 0x10) + slot = 0; +} + +/* { dg-final { scan-assembler-not "\tsbic " } } */ +/* { dg-final { scan-assembler-not "\tsbis " } } */ diff --git a/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c b/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c new file mode 100644 index 0000000000..ff0f9d45fa --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c @@ -0,0 +1,51 @@ +/* PR middle-end/51782 */ +/* { dg-do run } */ +/* { dg-options { "-std=gnu99" } } */ + +#include <stdlib.h> + +struct R { char r; }; +struct RGB { char r,g,b; }; + +__flash const struct R r1 = { 12 }; +__flash const struct RGB r3 = { 23, 56, 78 }; + +char __attribute__((noinline,noclone)) +read1_bug (const __flash struct R *s) +{ + struct R t = *s; + return t.r; +} + +char __attribute__((noinline,noclone)) +read1_ok (const __flash struct R *s) +{ + return s->r; +} + +char __attribute__((noinline,noclone)) +read3_bug (const __flash struct RGB *s) +{ + struct RGB t = *s; + return t.r + t.g + t.b; +} + +char __attribute__((noinline,noclone)) +read3_ok (const __flash struct RGB *s) +{ + return s->r + s->g + s->b; +} + +__flash const struct R * volatile p1 = &r1; +__flash const struct RGB * volatile p3 = &r3; + +int main (void) +{ + if (read1_bug (p1) != read1_ok (p1)) + abort(); + + if (read3_bug (p3) != read3_ok (p3)) + abort(); + + exit (0); +} diff --git a/gcc/testsuite/gcc.target/avr/torture/progmem-1.c b/gcc/testsuite/gcc.target/avr/torture/progmem-1.c new file mode 100644 index 0000000000..790c676c91 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/progmem-1.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ + +#include "../exit-abort.h" +#include "../progmem.h" + +const char strA[] PROGMEM = "@A"; +const char strc PROGMEM = 'c'; + +unsigned int volatile s = 2; + +int main() +{ + char c; + + c = pgm_read_char (&strA[s-1]); + if (c != 'A') + abort(); + + c = pgm_read_char (&PSTR ("@@B")[s]); + if (c != 'B') + abort(); + + c = pgm_read_char (&strc); + if (c != 'c') + abort(); + + exit (0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp b/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp new file mode 100644 index 0000000000..a1df9e78e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp @@ -0,0 +1,2 @@ +/* { dg-do run } */ +#include "progmem-1.c" diff --git a/gcc/testsuite/gcc.target/avr/torture/trivial.c b/gcc/testsuite/gcc.target/avr/torture/trivial.c index 91163f9226..f1beecb1ec 100644 --- a/gcc/testsuite/gcc.target/avr/torture/trivial.c +++ b/gcc/testsuite/gcc.target/avr/torture/trivial.c @@ -1,14 +1,15 @@ -/* { dg-do run } */
-#include <stdio.h>
-
-#define __ATTR_PROGMEM__ __attribute__((__progmem__))
-
-#define PROGMEM __ATTR_PROGMEM__
-char PROGMEM a1 = 0x12;
-int PROGMEM a2 = 0x2345;
-long PROGMEM a3 = 0x12345678;
-int main(void)
-{
- printf("Hello World\n");
- return 0;
-}
+/* { dg-do run } */ + +#include <stdio.h> + +#define PROGMEM __attribute__((__progmem__)) + +const char PROGMEM a1 = 0x12; +const int PROGMEM a2 = 0x2345; +const long PROGMEM a3 = 0x12345678; + +int main(void) +{ + printf ("Hello World\n"); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/trivial.c b/gcc/testsuite/gcc.target/avr/trivial.c index 91163f9226..f1beecb1ec 100644 --- a/gcc/testsuite/gcc.target/avr/trivial.c +++ b/gcc/testsuite/gcc.target/avr/trivial.c @@ -1,14 +1,15 @@ -/* { dg-do run } */
-#include <stdio.h>
-
-#define __ATTR_PROGMEM__ __attribute__((__progmem__))
-
-#define PROGMEM __ATTR_PROGMEM__
-char PROGMEM a1 = 0x12;
-int PROGMEM a2 = 0x2345;
-long PROGMEM a3 = 0x12345678;
-int main(void)
-{
- printf("Hello World\n");
- return 0;
-}
+/* { dg-do run } */ + +#include <stdio.h> + +#define PROGMEM __attribute__((__progmem__)) + +const char PROGMEM a1 = 0x12; +const int PROGMEM a2 = 0x2345; +const long PROGMEM a3 = 0x12345678; + +int main(void) +{ + printf ("Hello World\n"); + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c new file mode 100644 index 0000000000..9ca524d29f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_abs_fr1x16 (0x7777); + if (t1 != 0x7777) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c new file mode 100644 index 0000000000..00ef1dc169 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_abs_fr1x16 (0x8000); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c new file mode 100644 index 0000000000..a464c02d58 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_abs_fr1x32 (0x77777777); + if (t != 0x77777777) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c new file mode 100644 index 0000000000..9d642b1231 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_abs_fr1x32 (0x80000000); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c new file mode 100644 index 0000000000..86badedce1 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + + t = __builtin_bfin_abs_fr2x16 (a); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x5fff || t2 != 0x1) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c new file mode 100644 index 0000000000..80844bdaf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_abs_fr2x16 (a); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x1001 || t2 != 0x0001) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c new file mode 100644 index 0000000000..bd8f46d838 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c @@ -0,0 +1,14 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_add_fr1x16 (0x3000, 0x2000); + if (t1 != 0x5000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c new file mode 100644 index 0000000000..1054e95aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c @@ -0,0 +1,14 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_add_fr1x16 (0x3000, 0xd000); + if (t1 != 0x0) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c new file mode 100644 index 0000000000..a14ad688dd --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_add_fr1x32 (0x40003000, 0x50002000); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c new file mode 100644 index 0000000000..2345cb09e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_add_fr1x32 (0x40003000, 0xc000d000); + if (t != 0x00010000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c new file mode 100644 index 0000000000..69736978bc --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + b = __builtin_bfin_compose_2x16 (0x8000, 0x5000); + + t = __builtin_bfin_add_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffc000 || t2 != 0x7000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c new file mode 100644 index 0000000000..f7a309b8c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x7000, 0xc000); + b = __builtin_bfin_compose_2x16 (0x8000, 0xc000); + + t = __builtin_bfin_add_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffff000 || t2 != 0xffff8000) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp b/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp new file mode 100644 index 0000000000..645460e03c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp @@ -0,0 +1,39 @@ +# Copyright (C) 2009 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `c-torture.exp' driver, looping over +# optimization options. + +load_lib c-torture.exp +load_lib target-supports.exp +load_lib torture-options.exp + +if { ![istarget bfin-*-*] } then { + return +} + + +torture-init +set-torture-options [list {} -Os -O0 -O1 -O2 -O3 {-ffast-math -mfast-fp -O2} {-mfast-fp -O2} {-ffast-math -O2}] +set additional_flags "-W -Wall" + +foreach src [lsort [find $srcdir/$subdir *.c]] { + if {[runtest_file_p $runtests $src]} { + c-torture-execute [list $src] $additional_flags + } +} + +torture-finish diff --git a/gcc/testsuite/gcc.target/bfin/builtins/circptr.c b/gcc/testsuite/gcc.target/bfin/builtins/circptr.c new file mode 100644 index 0000000000..8419aa680c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/circptr.c @@ -0,0 +1,29 @@ +#include <stdlib.h> + +int t[] = { 1, 2, 3, 4, 5, 6, 7 }; +int expect[] = { 1, 3, 6, 10, 15, 21, 28, 29, 31, 34, 38, 43, 49, 56 }; + +int foo (int n) +{ + int *p = t; + int sum = 0; + int i; + for (i = 0; i < n; i++) { + sum += *p; + p = __builtin_bfin_circptr (p, sizeof *p, t, sizeof t); + } + return sum; +} + +int main () +{ + int i; + int *p = expect; + for (i = 0; i < 14; i++) { + int sum = foo (i + 1); + if (sum != *p) + abort (); + p = __builtin_bfin_circptr (p, sizeof *p, expect, sizeof expect); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c new file mode 100644 index 0000000000..17344bf06e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, c, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + b = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + c = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + + t = __builtin_bfin_cmplx_mac (a, b, c); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x2800 || t2 != 0x0a00) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c new file mode 100644 index 0000000000..9947116519 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, c, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + b = __builtin_bfin_compose_2x16 (0xb000, 0xe000); + c = __builtin_bfin_compose_2x16 (0xa000, 0x8000); + + t = __builtin_bfin_cmplx_mac (a, b, c); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != 0xfffff400) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c new file mode 100644 index 0000000000..10fcd4ca4f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, c, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x0000, 0x0000); + b = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + c = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + + t = __builtin_bfin_cmplx_msu (a, b, c); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffff800 || t2 != 0x600) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c new file mode 100644 index 0000000000..b2a7c5db39 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, c, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + b = __builtin_bfin_compose_2x16 (0xb000, 0xe000); + c = __builtin_bfin_compose_2x16 (0xa000, 0x8000); + + t = __builtin_bfin_cmplx_msu (a, b, c); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffb800 || t2 != 0x2c00) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c new file mode 100644 index 0000000000..c6b12257e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + b = __builtin_bfin_compose_2x16 (0x2000, 0x1000); + + t = __builtin_bfin_cmplx_mul (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x800 || t2 != 0xfffffa00) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c new file mode 100644 index 0000000000..d31fc15676 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xa000, 0x8000); + b = __builtin_bfin_compose_2x16 (0xb000, 0xe000); + + t = __builtin_bfin_cmplx_mul (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x6800 || t2 != 0xffffe400) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c new file mode 100644 index 0000000000..1d1c0f701a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + + t = __builtin_bfin_diff_hl_fr2x16 (a); + if (t != 0x6000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c new file mode 100644 index 0000000000..329ff2eb8a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_diff_hl_fr2x16 (a); + if (t != 0x1000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c new file mode 100644 index 0000000000..02d93e758f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + + t = __builtin_bfin_diff_lh_fr2x16 (a); + if (t != 0xffffa000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c new file mode 100644 index 0000000000..1e5dc699f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_diff_lh_fr2x16 (a); + if (t != -0x1000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c new file mode 100644 index 0000000000..cb66ecfb36 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x3000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_dspaddsubsat (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != 0x1000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c new file mode 100644 index 0000000000..8d6cab6913 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xd000, 0x8000); + b = __builtin_bfin_compose_2x16 (0x1000, 0x5000); + + t = __builtin_bfin_dspaddsubsat (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffe000 || t2 != 0xffff8000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c new file mode 100644 index 0000000000..0a16a4894e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x3000); + b = __builtin_bfin_compose_2x16 (0x6000, 0x6000); + + t = __builtin_bfin_dspsubaddsat (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != -0x1000 || t2 != 0x7fff) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c new file mode 100644 index 0000000000..a69451ebac --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xd000, 0xa000); + b = __builtin_bfin_compose_2x16 (0x1000, 0xc000); + + t = __builtin_bfin_dspsubaddsat (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffc000 || t2 != 0xffff8000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/hisilh.c b/gcc/testsuite/gcc.target/bfin/builtins/hisilh.c index 4efbfd4491..4efbfd4491 100644 --- a/gcc/testsuite/gcc.target/bfin/hisilh.c +++ b/gcc/testsuite/gcc.target/bfin/builtins/hisilh.c diff --git a/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c new file mode 100644 index 0000000000..c27d56a96d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_lshl_fr1x16 (0x1101, 4); + if (t1 != 0x1010) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c new file mode 100644 index 0000000000..9be2abf888 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_lshl_fr1x16 (0x4004, -4); + if (t1 != 0x0400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c new file mode 100644 index 0000000000..b9cf84f187 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_lshl_fr2x16 (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffff0 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c new file mode 100644 index 0000000000..c2f13d57e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_lshl_fr2x16 (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x0cff || t2 != 0x0fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c new file mode 100644 index 0000000000..1d364b28a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_max_fr1x16 (0x7777, 0x7000); + if (t1 != 0x7777) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c new file mode 100644 index 0000000000..eadf2fb050 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_max_fr1x16 (0x8000, 0xc000); + if (t1 != -0x4000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c new file mode 100644 index 0000000000..90adcef064 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_max_fr1x32 (0x77777777, 0x70007000); + if (t != 0x77777777) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c new file mode 100644 index 0000000000..b2ed2afa8e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_max_fr1x32 (0x80000000, 0xc0000000); + if (t != 0xc0000000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c new file mode 100644 index 0000000000..2d968fd333 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + b = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_max_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x5fff || t2 != 0x0001) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c new file mode 100644 index 0000000000..369c208519 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0xd000); + b = __builtin_bfin_compose_2x16 (0xc000, 0x2000); + + t = __builtin_bfin_max_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x5000 || t2 != 0x2000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c new file mode 100644 index 0000000000..686dcdceff --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_min_fr1x16 (0x7777, 0x7000); + if (t1 != 0x7000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c new file mode 100644 index 0000000000..655804034a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_min_fr1x16 (0x7000, 0xc001); + if (t1 != -0x3fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c new file mode 100644 index 0000000000..a824e76ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_min_fr1x32 (0x77777777, 0x70007000); + if (t != 0x70007000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c new file mode 100644 index 0000000000..72151016e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_min_fr1x32 (0x70007000, 0xc000c000); + if (t != 0xc000c000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c new file mode 100644 index 0000000000..2f2b401e5e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + b = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_min_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x1001 || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c new file mode 100644 index 0000000000..af564f4314 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0xd000); + b = __builtin_bfin_compose_2x16 (0xc000, 0x2000); + + t = __builtin_bfin_min_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffc000 || t2 != 0xffffd000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c new file mode 100644 index 0000000000..06790c94a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x7000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_mulhisihh (a, b); + if (t != 0x14000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c new file mode 100644 index 0000000000..ef070584ee --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0xc000, 0xa000); + b = __builtin_bfin_compose_2x16 (0x7000, 0x2000); + + t = __builtin_bfin_mulhisihh (a, b); + if (t != 0xe4000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c new file mode 100644 index 0000000000..e2768e399c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x7000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_mulhisihl (a, b); + if (t != 0xa000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c new file mode 100644 index 0000000000..b64eabe6bf --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0xa000, 0x7000); + b = __builtin_bfin_compose_2x16 (0xe000, 0x5000); + + t = __builtin_bfin_mulhisihl (a, b); + if (t != 0xe2000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c new file mode 100644 index 0000000000..99faef51aa --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x7000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_mulhisilh (a, b); + if (t != 0x1c000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c new file mode 100644 index 0000000000..3aef80cf87 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x7000); + b = __builtin_bfin_compose_2x16 (0xa000, 0x5000); + + t = __builtin_bfin_mulhisilh (a, b); + if (t != 0xd6000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c new file mode 100644 index 0000000000..acf1e9e1bd --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0x7000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_mulhisill (a, b); + if (t != 0xe000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c new file mode 100644 index 0000000000..147d8e14b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b; + int t; + + a = __builtin_bfin_compose_2x16 (0x5000, 0xa000); + b = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + + t = __builtin_bfin_mulhisill (a, b); + if (t != 0xf4000000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c new file mode 100644 index 0000000000..614b444414 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_mult_fr1x16 (0x7777, 0x0007); + if (t1 != 0x0006) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c new file mode 100644 index 0000000000..aec3b7ccf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_mult_fr1x16 (0x0002, 0x0001); + if (t1 != 0x0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c new file mode 100644 index 0000000000..8c8ad87bda --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32 (0x7777, 0x0001); + if (t != 0x0000eeee) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c new file mode 100644 index 0000000000..95d4f9d12a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32 (0x0002, 0x0001); + if (t != 0x0004) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c new file mode 100644 index 0000000000..ff41bf5cfb --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32x32 (0x80000000, 0x80000000); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c new file mode 100644 index 0000000000..6f5d5cbdbc --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32x32 (0x7fff0000, 0x00000007); + if (t != 0x6) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c new file mode 100644 index 0000000000..9bdfae632d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32x32NS (0x80000000, 0x80000000); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c new file mode 100644 index 0000000000..cb3f18c50a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_mult_fr1x32x32NS (0x7fff0000, 0x00000007); + if (t != 0x6) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c new file mode 100644 index 0000000000..d15dd4516c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + b = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_mult_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x0c00 || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c new file mode 100644 index 0000000000..6592eaf866 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0xd000); + b = __builtin_bfin_compose_2x16 (0xc000, 0x2000); + + t = __builtin_bfin_mult_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffd800 || t2 != 0xfffff400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c new file mode 100644 index 0000000000..3612d9320d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_multr_fr1x16 (0x7777, 0x0007); + if (t1 != 0x0007) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c new file mode 100644 index 0000000000..e5fb2173e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_multr_fr1x16 (0x0002, 0x0001); + if (t1 != 0x0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c new file mode 100644 index 0000000000..33d5b4a42d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + b = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_multr_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xc01 || t2 != 0x0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c new file mode 100644 index 0000000000..a2feed2f10 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5000, 0xd000); + b = __builtin_bfin_compose_2x16 (0xc000, 0x2000); + + t = __builtin_bfin_multr_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffffd800 || t2 != 0xfffff400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c new file mode 100644 index 0000000000..10b2626c73 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_negate_fr1x16 (0x7fff); + if (t1 != -0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c new file mode 100644 index 0000000000..c839dce321 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_negate_fr1x16 (0x8000); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c new file mode 100644 index 0000000000..0462de20af --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_negate_fr1x16 (0xc000); + if (t1 != 0x4000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c new file mode 100644 index 0000000000..c7ba22c719 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_negate_fr1x32 (0x7fffffff); + if (t != -0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c new file mode 100644 index 0000000000..70532f4abf --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_negate_fr1x32 (0x80000000); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c new file mode 100644 index 0000000000..449d8b8ac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + + t = __builtin_bfin_negate_fr2x16 (a); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != -0x5fff || t2 != 0x1) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c new file mode 100644 index 0000000000..db750648ca --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c @@ -0,0 +1,21 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + t = __builtin_bfin_negate_fr2x16 (a); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != -0x1001 || t2 != -0x1) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c new file mode 100644 index 0000000000..b8a53dd0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x16 (0x1234); + if (a != 2) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c new file mode 100644 index 0000000000..2534e9ff90 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef short fract16; + +int main () +{ + fract16 f = 0x1234, g; + int a; + + a = __builtin_bfin_norm_fr1x16 (f); + g = f << a; + if (g != (fract16) 0x48d0) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c new file mode 100644 index 0000000000..24b6fcbee8 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x16 (0xfedc); + if (a != 6) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c new file mode 100644 index 0000000000..986af6c552 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef short fract16; + +int main () +{ + fract16 f = 0xfedc, g; + int a; + + a = __builtin_bfin_norm_fr1x16 (f); + g = f << a; + if (g != (fract16) 0xb700) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c new file mode 100644 index 0000000000..f85ce96ab3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x16 (0); + if (a != 15) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c new file mode 100644 index 0000000000..bc30f23da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef short fract16; + +int main () +{ + fract16 f = 0, g; + int a; + + a = __builtin_bfin_norm_fr1x16 (f); + g = f << a; + if (g != (fract16) 0) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c new file mode 100644 index 0000000000..4edb00f343 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x16 (0xffff); + if (a != 15) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c b/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c new file mode 100644 index 0000000000..c04219f4d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef short fract16; + +int main () +{ + fract16 f = 0xffff, g; + int a; + + a = __builtin_bfin_norm_fr1x16 (f); + g = f << a; + if (g != (fract16) 0x8000) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c new file mode 100644 index 0000000000..f8c6b93caf --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0x12345678); + if (a != 2) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c new file mode 100644 index 0000000000..ba4ad920c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0x1234, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0x48d00000) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c new file mode 100644 index 0000000000..ae675b0d22 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0xfffffedc); + if (a != 22) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c new file mode 100644 index 0000000000..b7fbea7acb --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0xfffffedc, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0xb7000000) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c new file mode 100644 index 0000000000..4972ed43d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0x12345678, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0x48d159e0) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c new file mode 100644 index 0000000000..cc565b7290 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0xfedcba98); + if (a != 6) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c new file mode 100644 index 0000000000..1b3ae8ddee --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0xfedcba98, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0xb72ea600) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c new file mode 100644 index 0000000000..33c927917f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0); + if (a != 31) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c new file mode 100644 index 0000000000..2150c5a98b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c new file mode 100644 index 0000000000..87f4579f1e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0xffffffff); + if (a != 31) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c new file mode 100644 index 0000000000..4918a06a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c @@ -0,0 +1,18 @@ +extern void abort (void); +extern void exit (int); + +typedef int fract32; + +int main () +{ + fract32 f = 0xffffffff, g; + int a; + + a = __builtin_bfin_norm_fr1x32 (f); + g = f << a; + if (g != 0x80000000) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c b/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c new file mode 100644 index 0000000000..08468ac3d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c @@ -0,0 +1,14 @@ +extern void abort (void); +extern void exit (int); + +int main () +{ + int a; + + a = __builtin_bfin_norm_fr1x32 (0x1234); + if (a != 18) + abort (); + + exit (0); +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c new file mode 100644 index 0000000000..ad80cd4c1c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + int m; + + m = __builtin_bfin_norm_fr1x16 (0x1000); + if (m != 2) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c new file mode 100644 index 0000000000..59e868daa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + int m; + + m = __builtin_bfin_norm_fr1x16 (0x4000); + if (m != 0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c new file mode 100644 index 0000000000..c769240b03 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + int m; + + m = __builtin_bfin_norm_fr1x16 (0xe000); + if (m != 2) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c new file mode 100644 index 0000000000..fe476f58f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c @@ -0,0 +1,13 @@ +extern void abort (void); + +int main () +{ + int m; + + m = __builtin_bfin_norm_fr1x32 (0xefffeff1); + if (m != 2) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c new file mode 100644 index 0000000000..7cf1ebecaa --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c @@ -0,0 +1,13 @@ +extern void abort (void); + +int main () +{ + int m; + + m = __builtin_bfin_norm_fr1x32 (0x0000eff1); + if (m != 15) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c new file mode 100644 index 0000000000..f234bc9bf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shl_fr1x16 (0x1101, 4); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c new file mode 100644 index 0000000000..95e3bfb0c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shl_fr1x16 (0x4004, -4); + if (t1 != 0x0400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c new file mode 100644 index 0000000000..1c77a7c01b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shl_fr1x16 (0xc101, 4); + if (t1 != 0xffff8000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c new file mode 100644 index 0000000000..7cb9e8c687 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shl_fr1x16 (0xd004, -4); + if (t1 != 0xfffffd00) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c new file mode 100644 index 0000000000..251ff1e18d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x1101, 4); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c new file mode 100644 index 0000000000..8d50f20910 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x4004, -4); + if (t1 != 0x0400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c new file mode 100644 index 0000000000..f78303a180 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0xc101, 4); + if (t1 != 0xffff8000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c new file mode 100644 index 0000000000..cea723f338 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0xd004, -4); + if (t1 != 0xfffffd00) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c new file mode 100644 index 0000000000..c85adfe565 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shl_fr1x32 (0x7feff4ff, 4); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c new file mode 100644 index 0000000000..0a42ddc76f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shl_fr1x32 (0x7feff4ff, -4); + if (t != 0x7feff4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c new file mode 100644 index 0000000000..a98bc0c98a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shl_fr1x32 (0xc000e4ff, 4); + if (t != 0x80000000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c new file mode 100644 index 0000000000..f2d18b3703 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shl_fr1x32 (0xc000e4ff, -4); + if (t != 0xfc000e4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c new file mode 100644 index 0000000000..2883c18754 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shl_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0x7feff4ff, 4); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c new file mode 100644 index 0000000000..94a4cde1db --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shl_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0x7feff4ff, -4); + if (t != 0x7feff4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c new file mode 100644 index 0000000000..f32423500c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shl_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0xc000e4ff, 4); + if (t != 0x80000000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c new file mode 100644 index 0000000000..9300650857 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shl_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0xc000e4ff, -4); + if (t != 0xfc000e4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c new file mode 100644 index 0000000000..f24a266cc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c @@ -0,0 +1,19 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shl_fr1x32 (f, n); +} + +int main () +{ + fract32 f; + + f = foo (0x12345678, 4); + if (f != 0x7fffffff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c new file mode 100644 index 0000000000..029378ad81 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ + +typedef int fract32; + +extern void abort (void); + +int main () +{ + fract32 f; + + f = __builtin_bfin_shl_fr1x32 (0x12345678, 4); + if (f != 0x7fffffff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c new file mode 100644 index 0000000000..53ca96047c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shl_fr2x16 (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffff8000 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c new file mode 100644 index 0000000000..9e24db38b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shl_fr2x16 (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffcff || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c new file mode 100644 index 0000000000..6d91625d83 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_shl_fr2x16 (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != 0x10) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c new file mode 100644 index 0000000000..9b12e847a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_shl_fr2x16 (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x100 || t2 != 0x0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c new file mode 100644 index 0000000000..af9ac3f158 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffff8000 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c new file mode 100644 index 0000000000..cc08086786 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffcff || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c new file mode 100644 index 0000000000..dd235c891f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = foo (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != 0x10) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c new file mode 100644 index 0000000000..ed90541a4b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = foo (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x100 || t2 != 0x0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c new file mode 100644 index 0000000000..5a9df3de25 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shr_fr1x16 (0x1101, -4); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c new file mode 100644 index 0000000000..39dd3a999a --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shr_fr1x16 (0x4004, 4); + if (t1 != 0x0400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c new file mode 100644 index 0000000000..fff331f6e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shr_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x1101, -4); + if (t1 != 0x7fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c new file mode 100644 index 0000000000..8425b7a834 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shr_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x4004, 4); + if (t1 != 0x0400) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c new file mode 100644 index 0000000000..3a5e12fd60 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shr_fr1x32 (0x7feff4ff, -4); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c new file mode 100644 index 0000000000..6f73462cf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shr_fr1x32 (0x7feff4ff, 4); + if (t != 0x7feff4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c new file mode 100644 index 0000000000..664516365d --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shr_fr1x32 (0xc000e4ff, -4); + if (t != 0x80000000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c new file mode 100644 index 0000000000..56ffe17c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_shr_fr1x32 (0xc000e4ff, 4); + if (t != 0xfc000e4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c new file mode 100644 index 0000000000..6dbb7f2e2b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shr_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0x7feff4ff, -4); + if (t != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c new file mode 100644 index 0000000000..ef8915474f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shr_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0x7feff4ff, 4); + if (t != 0x7feff4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c new file mode 100644 index 0000000000..720546a71f --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shr_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0xc000e4ff, -4); + if (t != 0x80000000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c new file mode 100644 index 0000000000..9422f790b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shr_fr1x32 (f, n); +} + +int main () +{ + fract32 t; + + t = foo (0xc000e4ff, 4); + if (t != 0xfc000e4f) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c new file mode 100644 index 0000000000..caf17203dd --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c @@ -0,0 +1,19 @@ +extern void abort (void); + +typedef long fract32; + +fract32 foo (fract32 f, short n) +{ + return __builtin_bfin_shr_fr1x32 (f, n); +} + +int main () +{ + fract32 f; + + f = foo (0x87654321, 4); + if (f != 0xf8765432) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c new file mode 100644 index 0000000000..8be9ecfd11 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ + +typedef int fract32; + +extern void abort (void); + +int main () +{ + fract32 f; + + f = __builtin_bfin_shr_fr1x32 (0x87654321, 4); + if (f != 0xf8765432) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c new file mode 100644 index 0000000000..6e93695472 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shr_fr2x16 (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffff8000 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c new file mode 100644 index 0000000000..1c83d29149 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shr_fr2x16 (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffcff || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c new file mode 100644 index 0000000000..5b6af8b4b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shr_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xffff8000 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c new file mode 100644 index 0000000000..63bbb8bc76 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shr_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffcff || t2 != 0xffffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c new file mode 100644 index 0000000000..0de251ee2b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shrl_fr1x16 (0x8101, 4); + if (t1 != 0x0810) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c new file mode 100644 index 0000000000..c6b88b6d36 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_shrl_fr1x16 (0x4004, -4); + if (t1 != 0x0040) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c new file mode 100644 index 0000000000..0f8e168f68 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shrl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x8101, 4); + if (t1 != 0x0810) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c new file mode 100644 index 0000000000..d266ce0953 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short fract16; + +fract16 foo (fract16 f, short n) +{ + return __builtin_bfin_shrl_fr1x16 (f, n); +} + +int main () +{ + fract16 t1; + + t1 = foo (0x4004, -4); + if (t1 != 0x0040) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c new file mode 100644 index 0000000000..1252b4d755 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shrl_fr2x16 (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffff0 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c new file mode 100644 index 0000000000..b4bec6e6db --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c @@ -0,0 +1,22 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = __builtin_bfin_shrl_fr2x16 (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x0cff || t2 != 0x0fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c new file mode 100644 index 0000000000..4036dbf53e --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shrl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, -4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0xfffffff0 || t2 != 0xfffffff0) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c new file mode 100644 index 0000000000..b6473fa4d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c @@ -0,0 +1,27 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +fract2x16 foo (fract2x16 f, short n) +{ + return __builtin_bfin_shrl_fr2x16 (f, n); +} + +int main () +{ + fract2x16 a, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff); + + t = foo (a, 4); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x0cff || t2 != 0x0fff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c new file mode 100644 index 0000000000..b97bf8d633 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c @@ -0,0 +1,14 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_sub_fr1x16 (0x3000, 0x2000); + if (t1 != 0x1000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c new file mode 100644 index 0000000000..5e45680341 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c @@ -0,0 +1,14 @@ +extern void abort (void); + +typedef short fract16; + +int main () +{ + fract16 t1; + + t1 = __builtin_bfin_sub_fr1x16 (0x3000, 0x4000); + if (t1 != -0x1000) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c new file mode 100644 index 0000000000..5aedd9199b --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t1; + + t1 = __builtin_bfin_sub_fr1x32 (0x40003000, 0xc0003000); + if (t1 != 0x7fffffff) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c new file mode 100644 index 0000000000..8ac4a5aade --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c @@ -0,0 +1,15 @@ +extern void abort (void); + +typedef long fract32; + +int main () +{ + fract32 t; + + t = __builtin_bfin_sub_fr1x32 (0x40003000, 0x70002000); + if (t != 0xd0001000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c new file mode 100644 index 0000000000..34b8ac87d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x4000, 0x2000); + b = __builtin_bfin_compose_2x16 (0x8000, 0x5000); + + t = __builtin_bfin_sub_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != -0x3000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c new file mode 100644 index 0000000000..52f7d8052c --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c @@ -0,0 +1,23 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a, b, t; + fract16 t1, t2; + + a = __builtin_bfin_compose_2x16 (0x7000, 0xc000); + b = __builtin_bfin_compose_2x16 (0xc000, 0xd000); + + t = __builtin_bfin_sub_fr2x16 (a, b); + t1 = __builtin_bfin_extract_hi (t); + t2 = __builtin_bfin_extract_lo (t); + if (t1 != 0x7fff || t2 != -0x1000) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c b/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c new file mode 100644 index 0000000000..56c4f191ea --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff); + + t = __builtin_bfin_sum_fr2x16 (a); + if (t != 0x5ffe) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c b/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c new file mode 100644 index 0000000000..2f75bfdfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c @@ -0,0 +1,20 @@ +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); +typedef __v2hi fract2x16; +typedef short fract16; + +int main () +{ + fract2x16 a; + fract16 t; + + a = __builtin_bfin_compose_2x16 (0x1001, 0x0001); + + t = __builtin_bfin_sum_fr2x16 (a); + if (t != 0x1002) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/bfin/hisilh-O0.c b/gcc/testsuite/gcc.target/bfin/hisilh-O0.c deleted file mode 100644 index 50786b8be6..0000000000 --- a/gcc/testsuite/gcc.target/bfin/hisilh-O0.c +++ /dev/null @@ -1,46 +0,0 @@ -/* { dg-do run { target bfin*-*-* } } */ -/* { dg-options "-O0" } */ -#include <stdlib.h> -typedef short raw2x16 __attribute__ ((vector_size(4))); - -int x; - -int ll(raw2x16 a, raw2x16 b) -{ - x = __builtin_bfin_mulhisill(a, b); - return x; -} - -int lh(raw2x16 a, raw2x16 b) -{ - x = __builtin_bfin_mulhisilh(a, b); - return x; -} - -int hl(raw2x16 a, raw2x16 b) -{ - x = __builtin_bfin_mulhisihl(a, b); - return x; -} - -int hh(raw2x16 a, raw2x16 b) -{ - x = __builtin_bfin_mulhisihh(a, b); - return x; -} - -int main () -{ - raw2x16 a = __builtin_bfin_compose_2x16 (0x1234, 0x5678); - raw2x16 b = __builtin_bfin_compose_2x16 (0xFEDC, 0xBA98); - if (ll (a, b) != 0xe88e8740) - abort (); - if (lh (a, b) != 0xff9d5f20) - abort (); - if (hl (a, b) != 0xfb1096e0) - abort (); - if (hh (a, b) != 0xffeb3cb0) - abort (); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c index 71fbcf38df..fa2d56d1a4 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c @@ -10,39 +10,8 @@ #error "__ADSPBF51x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" -#endif - -#ifndef __WORKAROUNDS_ENABLED -#error "__WORKAROUNDS_ENABLED is not defined" -#endif - -#ifdef __WORKAROUND_RETS -#error "__WORKAROUND_RETS is defined" -#endif - -#ifndef __WORKAROUND_SPECULATIVE_LOADS -#error "__WORKAROUND_SPECULATIVE_LOADS is not defined" -#endif - -#ifdef __WORKAROUND_SPECULATIVE_SYNCS -#error "__WORKAROUND_SPECULATIVE_SYNCS is defined" -#endif -/* Test for -mcpu=. */ -/* { dg-do preprocess } */ -/* { dg-bfin-options "-mcpu=bf512" } */ - -#ifndef __ADSPBF512__ -#error "__ADSPBF512__ is not defined" -#endif - -#ifndef __ADSPBF51x__ -#error "__ADSPBF51x__ is not defined" -#endif - -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" +#if __SILICON_REVISION__ != 0x0002 +#error "__SILICON_REVISION__ is not 0x0002" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c index b1ae2a2ce0..f6c0829119 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c @@ -10,39 +10,8 @@ #error "__ADSPBF51x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" -#endif - -#ifndef __WORKAROUNDS_ENABLED -#error "__WORKAROUNDS_ENABLED is not defined" -#endif - -#ifdef __WORKAROUND_RETS -#error "__WORKAROUND_RETS is defined" -#endif - -#ifndef __WORKAROUND_SPECULATIVE_LOADS -#error "__WORKAROUND_SPECULATIVE_LOADS is not defined" -#endif - -#ifdef __WORKAROUND_SPECULATIVE_SYNCS -#error "__WORKAROUND_SPECULATIVE_SYNCS is defined" -#endif -/* Test for -mcpu=. */ -/* { dg-do preprocess } */ -/* { dg-bfin-options "-mcpu=bf514" } */ - -#ifndef __ADSPBF514__ -#error "__ADSPBF514__ is not defined" -#endif - -#ifndef __ADSPBF51x__ -#error "__ADSPBF51x__ is not defined" -#endif - -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" +#if __SILICON_REVISION__ != 0x0002 +#error "__SILICON_REVISION__ is not 0x0002" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c index 675d2659d2..439b3f40eb 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c @@ -10,39 +10,8 @@ #error "__ADSPBF51x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" -#endif - -#ifndef __WORKAROUNDS_ENABLED -#error "__WORKAROUNDS_ENABLED is not defined" -#endif - -#ifdef __WORKAROUND_RETS -#error "__WORKAROUND_RETS is defined" -#endif - -#ifndef __WORKAROUND_SPECULATIVE_LOADS -#error "__WORKAROUND_SPECULATIVE_LOADS is not defined" -#endif - -#ifdef __WORKAROUND_SPECULATIVE_SYNCS -#error "__WORKAROUND_SPECULATIVE_SYNCS is defined" -#endif -/* Test for -mcpu=. */ -/* { dg-do preprocess } */ -/* { dg-bfin-options "-mcpu=bf516" } */ - -#ifndef __ADSPBF516__ -#error "__ADSPBF516__ is not defined" -#endif - -#ifndef __ADSPBF51x__ -#error "__ADSPBF51x__ is not defined" -#endif - -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" +#if __SILICON_REVISION__ != 0x0002 +#error "__SILICON_REVISION__ is not 0x0002" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c index d0675783b4..aff7f6989c 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c @@ -10,39 +10,8 @@ #error "__ADSPBF51x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" -#endif - -#ifndef __WORKAROUNDS_ENABLED -#error "__WORKAROUNDS_ENABLED is not defined" -#endif - -#ifdef __WORKAROUND_RETS -#error "__WORKAROUND_RETS is defined" -#endif - -#ifndef __WORKAROUND_SPECULATIVE_LOADS -#error "__WORKAROUND_SPECULATIVE_LOADS is not defined" -#endif - -#ifdef __WORKAROUND_SPECULATIVE_SYNCS -#error "__WORKAROUND_SPECULATIVE_SYNCS is defined" -#endif -/* Test for -mcpu=. */ -/* { dg-do preprocess } */ -/* { dg-bfin-options "-mcpu=bf518" } */ - -#ifndef __ADSPBF518__ -#error "__ADSPBF518__ is not defined" -#endif - -#ifndef __ADSPBF51x__ -#error "__ADSPBF51x__ is not defined" -#endif - -#if __SILICON_REVISION__ != 0x0000 -#error "__SILICON_REVISION__ is not 0x0000" +#if __SILICON_REVISION__ != 0x0002 +#error "__SILICON_REVISION__ is not 0x0002" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c index 4d95d65def..c8999713d8 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c @@ -10,8 +10,8 @@ #error "__ADSPBF54x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0002 -#error "__SILICON_REVISION__ is not 0x0002" +#if __SILICON_REVISION__ != 0x0004 +#error "__SILICON_REVISION__ is not 0x0004" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c index 39314b0089..9269785057 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c @@ -10,8 +10,8 @@ #error "__ADSPBF54x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0002 -#error "__SILICON_REVISION__ is not 0x0002" +#if __SILICON_REVISION__ != 0x0004 +#error "__SILICON_REVISION__ is not 0x0004" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c index 4036c02f41..8f724335c2 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c @@ -10,8 +10,8 @@ #error "__ADSPBF54x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0002 -#error "__SILICON_REVISION__ is not 0x0002" +#if __SILICON_REVISION__ != 0x0004 +#error "__SILICON_REVISION__ is not 0x0004" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c index 71d3bb87ba..7b1d2ff2d7 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c @@ -10,8 +10,8 @@ #error "__ADSPBF54x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0002 -#error "__SILICON_REVISION__ is not 0x0002" +#if __SILICON_REVISION__ != 0x0004 +#error "__SILICON_REVISION__ is not 0x0004" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c index 201b1019b7..83c79de3ff 100644 --- a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c @@ -10,8 +10,8 @@ #error "__ADSPBF54x__ is not defined" #endif -#if __SILICON_REVISION__ != 0x0002 -#error "__SILICON_REVISION__ is not 0x0002" +#if __SILICON_REVISION__ != 0x0004 +#error "__SILICON_REVISION__ is not 0x0004" #endif #ifndef __WORKAROUNDS_ENABLED diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c new file mode 100644 index 0000000000..27e865e551 --- /dev/null +++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c @@ -0,0 +1,31 @@ +/* Test for -mcpu=. */ +/* { dg-do preprocess } */ +/* { dg-bfin-options "-mcpu=bf592" } */ + +#ifndef __ADSPBF592__ +#error "__ADSPBF592__ is not defined" +#endif + +#ifndef __ADSPBF59x__ +#error "__ADSPBF59x__ is not defined" +#endif + +#if __SILICON_REVISION__ != 0x0001 +#error "__SILICON_REVISION__ is not 0x0001" +#endif + +#ifndef __WORKAROUNDS_ENABLED +#error "__WORKAROUNDS_ENABLED is not defined" +#endif + +#ifdef __WORKAROUND_RETS +#error "__WORKAROUND_RETS is defined" +#endif + +#ifndef __WORKAROUND_SPECULATIVE_LOADS +#error "__WORKAROUND_SPECULATIVE_LOADS is not defined" +#endif + +#ifdef __WORKAROUND_SPECULATIVE_SYNCS +#error "__WORKAROUND_SPECULATIVE_SYNCS is defined" +#endif diff --git a/gcc/testsuite/gcc.target/epiphany/epiphany.exp b/gcc/testsuite/gcc.target/epiphany/epiphany.exp new file mode 100644 index 0000000000..dc9fecc728 --- /dev/null +++ b/gcc/testsuite/gcc.target/epiphany/epiphany.exp @@ -0,0 +1,41 @@ +# Copyright (C) 2007, 2011 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an epiphany target. +if ![istarget epiphany*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/epiphany/fmadd-1.c b/gcc/testsuite/gcc.target/epiphany/fmadd-1.c new file mode 100644 index 0000000000..868d5bd022 --- /dev/null +++ b/gcc/testsuite/gcc.target/epiphany/fmadd-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "fmadd\[ \ta-zA-Z0-9\]*," 2 } } */ + +#include <epiphany_intrinsics.h> + +float +f1 (float a, float b, float c) +{ + return __builtin_epiphany_fmadd (a, b, c); +} + +float +f2 (float a, float b, float c) +{ + return a + b * c; +} diff --git a/gcc/testsuite/gcc.target/epiphany/fmsub-1.c b/gcc/testsuite/gcc.target/epiphany/fmsub-1.c new file mode 100644 index 0000000000..ff7fefa7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/epiphany/fmsub-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "fmsub\[ \ta-zA-Z0-9\]*," 2 } } */ + +#include <epiphany_intrinsics.h> + +float +f1 (float a, float b, float c) +{ + return __builtin_epiphany_fmsub (a, b, c); +} + +float +f2 (float a, float b, float c) +{ + return a - b * c; +} diff --git a/gcc/testsuite/gcc.target/epiphany/interrupt-2.c b/gcc/testsuite/gcc.target/epiphany/interrupt-2.c new file mode 100644 index 0000000000..4c0de6c5d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/epiphany/interrupt-2.c @@ -0,0 +1,24 @@ +/* { dg-options "-g" } */ + +void __attribute__((interrupt)) +universal_handler (void) +{ +} + +void __attribute__((interrupt("dma0","Vss","dma1"))) +g (void) +{ /* { dg-warning "is not \"reset\"" } */ +} + +void __attribute__((interrupt("dma0","dma1","timer1","reset"), + forwarder_section("test"))) +misc_handler (void) +{ +} + +void __attribute__((interrupt(dma0,42))) +h (void) +{ /* { dg-warning "is not a string constant" } */ +} + +/* { dg-final { scan-assembler-times "b\[ \t\]*_misc_handler" 4 } } */ diff --git a/gcc/testsuite/gcc.target/epiphany/interrupt.c b/gcc/testsuite/gcc.target/epiphany/interrupt.c new file mode 100644 index 0000000000..86fb255613 --- /dev/null +++ b/gcc/testsuite/gcc.target/epiphany/interrupt.c @@ -0,0 +1,18 @@ +/* { dg-options "-g" } */ + +void __attribute__((interrupt("dma0"))) +dma0_handler (void) +{ +} + +void __attribute__((interrupt("Vss"))) +g (void) +{ /* { dg-warning "is not \"reset\"" } */ +} + +void __attribute__((interrupt(42))) +h (void) +{ /* { dg-warning "is not a string constant" } */ +} + +/* { dg-final { scan-assembler-times "b\[ \t\]*_dma0_handler" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/20000609-1.c b/gcc/testsuite/gcc.target/i386/20000609-1.c index e094bba55f..a083a5d53a 100644 --- a/gcc/testsuite/gcc.target/i386/20000609-1.c +++ b/gcc/testsuite/gcc.target/i386/20000609-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -ffast-math -march=i686" } */ diff --git a/gcc/testsuite/gcc.target/i386/20000720-1.c b/gcc/testsuite/gcc.target/i386/20000720-1.c index 076a22bad7..84e136c52f 100644 --- a/gcc/testsuite/gcc.target/i386/20000720-1.c +++ b/gcc/testsuite/gcc.target/i386/20000720-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mpreferred-stack-boundary=2 -march=i586 -O2 -fomit-frame-pointer" } */ extern void *foo(void *a, const void *b, unsigned c); diff --git a/gcc/testsuite/gcc.target/i386/20000724-1.c b/gcc/testsuite/gcc.target/i386/20000724-1.c index b3be437b51..cbcd4f1f1d 100644 --- a/gcc/testsuite/gcc.target/i386/20000724-1.c +++ b/gcc/testsuite/gcc.target/i386/20000724-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target *-*-linux* } } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/20011107-1.c b/gcc/testsuite/gcc.target/i386/20011107-1.c index 3bf84e5baa..c1cfe88a4e 100644 --- a/gcc/testsuite/gcc.target/i386/20011107-1.c +++ b/gcc/testsuite/gcc.target/i386/20011107-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mtune=k6" } */ void diff --git a/gcc/testsuite/gcc.target/i386/20011119-1.c b/gcc/testsuite/gcc.target/i386/20011119-1.c index 4dd657ef7f..9e85f6f5a2 100644 --- a/gcc/testsuite/gcc.target/i386/20011119-1.c +++ b/gcc/testsuite/gcc.target/i386/20011119-1.c @@ -1,6 +1,6 @@ /* Test for reload failing to eliminate from argp to sp. */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target nonpic } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ diff --git a/gcc/testsuite/gcc.target/i386/20020201-3.c b/gcc/testsuite/gcc.target/i386/20020201-3.c index da700c192c..9d7265457d 100644 --- a/gcc/testsuite/gcc.target/i386/20020201-3.c +++ b/gcc/testsuite/gcc.target/i386/20020201-3.c @@ -1,7 +1,7 @@ /* This testcase ICEd because a SFmode variable was given a MMX register for which there is no movsf exists. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=i686 -mmmx -fno-strict-aliasing" } */ struct A { unsigned int a, b; }; diff --git a/gcc/testsuite/gcc.target/i386/20020218-1.c b/gcc/testsuite/gcc.target/i386/20020218-1.c index 13a835ed08..4d3d256afc 100644 --- a/gcc/testsuite/gcc.target/i386/20020218-1.c +++ b/gcc/testsuite/gcc.target/i386/20020218-1.c @@ -1,6 +1,6 @@ /* Verify that X86-64 only SSE registers aren't restored on IA-32. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -msse" } */ /* { dg-final { scan-assembler-not "xmm8" } } */ diff --git a/gcc/testsuite/gcc.target/i386/20020729-1.c b/gcc/testsuite/gcc.target/i386/20020729-1.c index d4ef9bfcd2..7e1abafd2c 100644 --- a/gcc/testsuite/gcc.target/i386/20020729-1.c +++ b/gcc/testsuite/gcc.target/i386/20020729-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=k6" } */ static inline void * diff --git a/gcc/testsuite/gcc.target/i386/20030926-1.c b/gcc/testsuite/gcc.target/i386/20030926-1.c index 0425f2456a..ebde340851 100644 --- a/gcc/testsuite/gcc.target/i386/20030926-1.c +++ b/gcc/testsuite/gcc.target/i386/20030926-1.c @@ -1,7 +1,7 @@ /* PR optimization/11741 */ /* { dg-do compile } */ /* { dg-options "-O2 -minline-all-stringops" } */ -/* { dg-options "-O2 -minline-all-stringops -march=pentium4" { target ilp32 } } */ +/* { dg-options "-O2 -minline-all-stringops -march=pentium4" { target ia32 } } */ extern void *memcpy (void *, const void *, __SIZE_TYPE__); extern __SIZE_TYPE__ strlen (const char *); diff --git a/gcc/testsuite/gcc.target/i386/20060125-1.c b/gcc/testsuite/gcc.target/i386/20060125-1.c index f445b7e99f..ed9dcce84e 100644 --- a/gcc/testsuite/gcc.target/i386/20060125-1.c +++ b/gcc/testsuite/gcc.target/i386/20060125-1.c @@ -1,6 +1,6 @@ /* PR rtl-optimization/25703 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mtune=i486" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/20060125-2.c b/gcc/testsuite/gcc.target/i386/20060125-2.c index 55ef839552..1747a634dc 100644 --- a/gcc/testsuite/gcc.target/i386/20060125-2.c +++ b/gcc/testsuite/gcc.target/i386/20060125-2.c @@ -1,6 +1,6 @@ /* PR rtl-optimization/25703 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mtune=pentiumpro" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/20060512-1.c b/gcc/testsuite/gcc.target/i386/20060512-1.c index ae432e79c0..374d18aea5 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-1.c +++ b/gcc/testsuite/gcc.target/i386/20060512-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-std=gnu99 -msse2 -mpreferred-stack-boundary=4" } */ /* { dg-require-effective-target sse2 } */ diff --git a/gcc/testsuite/gcc.target/i386/20060512-2.c b/gcc/testsuite/gcc.target/i386/20060512-2.c index fe1af56357..d3a779cb4e 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-2.c +++ b/gcc/testsuite/gcc.target/i386/20060512-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-std=gnu99 -mpreferred-stack-boundary=4" } */ int outer_function (int x, int y) diff --git a/gcc/testsuite/gcc.target/i386/20060512-3.c b/gcc/testsuite/gcc.target/i386/20060512-3.c index 4b62b16602..3370b9ec25 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-3.c +++ b/gcc/testsuite/gcc.target/i386/20060512-3.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-std=gnu99 -msse2 -mstackrealign -mpreferred-stack-boundary=4" } */ diff --git a/gcc/testsuite/gcc.target/i386/20060512-4.c b/gcc/testsuite/gcc.target/i386/20060512-4.c index ee7b8a4ad8..bf76937997 100644 --- a/gcc/testsuite/gcc.target/i386/20060512-4.c +++ b/gcc/testsuite/gcc.target/i386/20060512-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mstackrealign -mpreferred-stack-boundary=4" } */ int outer_function (int x, int y) diff --git a/gcc/testsuite/gcc.target/i386/387-1.c b/gcc/testsuite/gcc.target/i386/387-1.c index 83af71f964..c4ea1e7d4c 100644 --- a/gcc/testsuite/gcc.target/i386/387-1.c +++ b/gcc/testsuite/gcc.target/i386/387-1.c @@ -1,6 +1,6 @@ /* Verify that -mno-fancy-math-387 works. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ /* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */ /* { dg-final { scan-assembler "call\t(.*)sin" } } */ diff --git a/gcc/testsuite/gcc.target/i386/387-2.c b/gcc/testsuite/gcc.target/i386/387-2.c index bd6dbcdda9..8d5dba1f9c 100644 --- a/gcc/testsuite/gcc.target/i386/387-2.c +++ b/gcc/testsuite/gcc.target/i386/387-2.c @@ -1,6 +1,6 @@ /* Verify that -march overrides -mno-fancy-math-387. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */ /* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */ /* { dg-final { scan-assembler "fsin" } } */ diff --git a/gcc/testsuite/gcc.target/i386/387-5.c b/gcc/testsuite/gcc.target/i386/387-5.c index 027799a878..a39f77a588 100644 --- a/gcc/testsuite/gcc.target/i386/387-5.c +++ b/gcc/testsuite/gcc.target/i386/387-5.c @@ -1,6 +1,6 @@ /* Verify that -mno-fancy-math-387 works. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ /* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */ /* { dg-final { scan-assembler "call\t(.*)atan" } } */ diff --git a/gcc/testsuite/gcc.target/i386/387-6.c b/gcc/testsuite/gcc.target/i386/387-6.c index 7b254d1302..f9506ba79e 100644 --- a/gcc/testsuite/gcc.target/i386/387-6.c +++ b/gcc/testsuite/gcc.target/i386/387-6.c @@ -1,6 +1,6 @@ /* Verify that -march overrides -mno-fancy-math-387. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */ /* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */ /* { dg-final { scan-assembler "fpatan" } } */ diff --git a/gcc/testsuite/gcc.target/i386/47698.c b/gcc/testsuite/gcc.target/i386/47698.c new file mode 100644 index 0000000000..2c751093ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/47698.c @@ -0,0 +1,10 @@ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "cmov" } } */ + +extern volatile unsigned long mmio; +unsigned long foo(int cond) +{ + if (cond) + return mmio; + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/980312-1.c b/gcc/testsuite/gcc.target/i386/980312-1.c index 72cdd5e3f3..3a125f2598 100644 --- a/gcc/testsuite/gcc.target/i386/980312-1.c +++ b/gcc/testsuite/gcc.target/i386/980312-1.c @@ -1,5 +1,5 @@ /* { dg-do link } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentiumpro" } */ extern __inline double diff --git a/gcc/testsuite/gcc.target/i386/980313-1.c b/gcc/testsuite/gcc.target/i386/980313-1.c index 3b5263cd57..8698aa61c7 100644 --- a/gcc/testsuite/gcc.target/i386/980313-1.c +++ b/gcc/testsuite/gcc.target/i386/980313-1.c @@ -1,5 +1,5 @@ /* { dg-do link } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentiumpro" } */ extern __inline double diff --git a/gcc/testsuite/gcc.target/i386/990117-1.c b/gcc/testsuite/gcc.target/i386/990117-1.c index 3a40e7fdfc..a89dad119a 100644 --- a/gcc/testsuite/gcc.target/i386/990117-1.c +++ b/gcc/testsuite/gcc.target/i386/990117-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentiumpro" } */ extern __inline double diff --git a/gcc/testsuite/gcc.target/i386/990424-1.c b/gcc/testsuite/gcc.target/i386/990424-1.c index 95628e12fa..dd29139924 100644 --- a/gcc/testsuite/gcc.target/i386/990424-1.c +++ b/gcc/testsuite/gcc.target/i386/990424-1.c @@ -2,7 +2,7 @@ with stdcall functions. */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options -mpreferred-stack-boundary=4 } */ void __attribute__((stdcall)) foo(int a, int b, int c); diff --git a/gcc/testsuite/gcc.target/i386/990524-1.c b/gcc/testsuite/gcc.target/i386/990524-1.c index 7d8205cd07..295ffacc9b 100644 --- a/gcc/testsuite/gcc.target/i386/990524-1.c +++ b/gcc/testsuite/gcc.target/i386/990524-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentiumpro" } */ typedef struct t_anim_info { diff --git a/gcc/testsuite/gcc.target/i386/991129-1.c b/gcc/testsuite/gcc.target/i386/991129-1.c index d0d58e8f9e..038979a778 100644 --- a/gcc/testsuite/gcc.target/i386/991129-1.c +++ b/gcc/testsuite/gcc.target/i386/991129-1.c @@ -1,7 +1,7 @@ /* Test against a problem in push_reload. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ unsigned long foo (unsigned long long x, unsigned long y) diff --git a/gcc/testsuite/gcc.target/i386/991214-1.c b/gcc/testsuite/gcc.target/i386/991214-1.c index 3d9a72ed02..74b603da7f 100644 --- a/gcc/testsuite/gcc.target/i386/991214-1.c +++ b/gcc/testsuite/gcc.target/i386/991214-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ /* Test against a problem with the combiner substituting explicit hard reg diff --git a/gcc/testsuite/gcc.target/i386/991230-1.c b/gcc/testsuite/gcc.target/i386/991230-1.c index a57cc98ea8..2c9f011cea 100644 --- a/gcc/testsuite/gcc.target/i386/991230-1.c +++ b/gcc/testsuite/gcc.target/i386/991230-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O -ffast-math -mtune=i486" } */ /* Test that floating point greater-than tests are compiled correctly with diff --git a/gcc/testsuite/gcc.target/i386/addr-sel-1.c b/gcc/testsuite/gcc.target/i386/addr-sel-1.c index 9cc820fee5..27623ffd96 100644 --- a/gcc/testsuite/gcc.target/i386/addr-sel-1.c +++ b/gcc/testsuite/gcc.target/i386/addr-sel-1.c @@ -2,7 +2,7 @@ /* Origin: Lev Makhlis <lmakhlis@bmc.com> */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target nonpic } */ /* { dg-options "-O2 -mtune=i686" } */ diff --git a/gcc/testsuite/gcc.target/i386/aggregate-ret1.c b/gcc/testsuite/gcc.target/i386/aggregate-ret1.c index 1cd314b5c2..6d46dc5ef7 100644 --- a/gcc/testsuite/gcc.target/i386/aggregate-ret1.c +++ b/gcc/testsuite/gcc.target/i386/aggregate-ret1.c @@ -3,7 +3,7 @@ not pop the stack for the implicit pointer arg when returning a large structure in memory. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ struct foo { int a; diff --git a/gcc/testsuite/gcc.target/i386/aggregate-ret2.c b/gcc/testsuite/gcc.target/i386/aggregate-ret2.c index 50aa0bbe6d..16e0109ef4 100644 --- a/gcc/testsuite/gcc.target/i386/aggregate-ret2.c +++ b/gcc/testsuite/gcc.target/i386/aggregate-ret2.c @@ -3,7 +3,7 @@ pops the stack for the implicit pointer arg when returning a large structure in memory. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ struct foo { int a; diff --git a/gcc/testsuite/gcc.target/i386/aggregate-ret3.c b/gcc/testsuite/gcc.target/i386/aggregate-ret3.c new file mode 100644 index 0000000000..e3c5b09439 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/aggregate-ret3.c @@ -0,0 +1,28 @@ +/* Check that, with keep_aggregate_return_pointer attribute, callee does + not pop the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((ms_abi)) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler-not "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc/testsuite/gcc.target/i386/aggregate-ret4.c b/gcc/testsuite/gcc.target/i386/aggregate-ret4.c new file mode 100644 index 0000000000..6e70f49f77 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/aggregate-ret4.c @@ -0,0 +1,28 @@ +/* Check that, with dont_keep_aggregate_return_pointer attribute, callee + pops the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((sysv_abi)) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc/testsuite/gcc.target/i386/align-main-1.c b/gcc/testsuite/gcc.target/i386/align-main-1.c index 699c7f80c5..f62284f437 100644 --- a/gcc/testsuite/gcc.target/i386/align-main-1.c +++ b/gcc/testsuite/gcc.target/i386/align-main-1.c @@ -4,10 +4,12 @@ /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ #include <stddef.h> #define ALIGNMENT 128 + typedef int aligned __attribute__((aligned(ALIGNMENT))); extern void abort(void); diff --git a/gcc/testsuite/gcc.target/i386/align-main-2.c b/gcc/testsuite/gcc.target/i386/align-main-2.c index 65c49e7f5d..b817589183 100644 --- a/gcc/testsuite/gcc.target/i386/align-main-2.c +++ b/gcc/testsuite/gcc.target/i386/align-main-2.c @@ -4,7 +4,7 @@ /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ - +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ #include <stddef.h> #define ALIGNMENT 32 diff --git a/gcc/testsuite/gcc.target/i386/align-main-3.c b/gcc/testsuite/gcc.target/i386/align-main-3.c index d2f88d8596..6f8c758035 100644 --- a/gcc/testsuite/gcc.target/i386/align-main-3.c +++ b/gcc/testsuite/gcc.target/i386/align-main-3.c @@ -1,5 +1,5 @@ /* Test for stack alignment with sibcall optimization. */ -/* { dg-do compile { target { *-*-linux* && ilp32 } } } */ +/* { dg-do compile { target { *-*-linux* && ia32 } } } */ /* { dg-options "-O2 -mpreferred-stack-boundary=4 -mincoming-stack-boundary=2" } */ /* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler "call\[\\t \]*foo" } } */ diff --git a/gcc/testsuite/gcc.target/i386/all_one_m256i.c b/gcc/testsuite/gcc.target/i386/all_one_m256i.c new file mode 100644 index 0000000000..1c3ca08b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/all_one_m256i.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32))); +typedef int __v8si __attribute__ ((__vector_size__ (32))); + +__m256i foo () +{ + __m256i minus_1 = (__m256i) (__v8si) { -1, -1, -1, -1, -1, -1, -1, -1 }; + + return minus_1; +} + +/* { dg-final { scan-assembler "vpcmpeqd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-1.c b/gcc/testsuite/gcc.target/i386/amd64-abi-1.c index d3df77a49f..8988f79c73 100644 --- a/gcc/testsuite/gcc.target/i386/amd64-abi-1.c +++ b/gcc/testsuite/gcc.target/i386/amd64-abi-1.c @@ -1,6 +1,6 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-mno-sse" } */ +/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */ double foo(void) { return 0; } /* { dg-error "SSE disabled" } */ void bar(double x) { } diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-2.c b/gcc/testsuite/gcc.target/i386/amd64-abi-2.c index fefc88a4e8..6146e8efa2 100644 --- a/gcc/testsuite/gcc.target/i386/amd64-abi-2.c +++ b/gcc/testsuite/gcc.target/i386/amd64-abi-2.c @@ -1,7 +1,8 @@ /* PR target/26223 */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-mno-80387" } */ +/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */ + long double foo(long double x) { return x; } /* { dg-error "x87 disabled" } */ long double bar(long double x) { return x; } diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-4.c b/gcc/testsuite/gcc.target/i386/amd64-abi-4.c index 8f32029662..e88fde6aff 100644 --- a/gcc/testsuite/gcc.target/i386/amd64-abi-4.c +++ b/gcc/testsuite/gcc.target/i386/amd64-abi-4.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mno-sse" } */ #include <stdarg.h> diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-5.c b/gcc/testsuite/gcc.target/i386/amd64-abi-5.c index e4ba1fd5d2..da2a14ee42 100644 --- a/gcc/testsuite/gcc.target/i386/amd64-abi-5.c +++ b/gcc/testsuite/gcc.target/i386/amd64-abi-5.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-options "-O2" } */ #include <stdarg.h> diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-6.c b/gcc/testsuite/gcc.target/i386/amd64-abi-6.c index 255b5479eb..6d076ad381 100644 --- a/gcc/testsuite/gcc.target/i386/amd64-abi-6.c +++ b/gcc/testsuite/gcc.target/i386/amd64-abi-6.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-options "-O2" } */ #include <stdarg.h> diff --git a/gcc/testsuite/gcc.target/i386/asm-1.c b/gcc/testsuite/gcc.target/i386/asm-1.c index 348dc32dd3..999c576796 100644 --- a/gcc/testsuite/gcc.target/i386/asm-1.c +++ b/gcc/testsuite/gcc.target/i386/asm-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-m32" } */ register unsigned int EAX asm ("r14"); /* { dg-error "register name" } */ diff --git a/gcc/testsuite/gcc.target/i386/asm-3.c b/gcc/testsuite/gcc.target/i386/asm-3.c index 6c23237de1..ec37898ab7 100644 --- a/gcc/testsuite/gcc.target/i386/asm-3.c +++ b/gcc/testsuite/gcc.target/i386/asm-3.c @@ -1,6 +1,6 @@ /* PR inline-asm/6806 */ /* { dg-do run } */ -/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/asm-5.c b/gcc/testsuite/gcc.target/i386/asm-5.c index 966a824b3c..d412980238 100644 --- a/gcc/testsuite/gcc.target/i386/asm-5.c +++ b/gcc/testsuite/gcc.target/i386/asm-5.c @@ -1,6 +1,6 @@ /* PR inline-asm/11676 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/asm-6.c b/gcc/testsuite/gcc.target/i386/asm-6.c index d69cf5d3df..6aa37ef427 100644 --- a/gcc/testsuite/gcc.target/i386/asm-6.c +++ b/gcc/testsuite/gcc.target/i386/asm-6.c @@ -3,7 +3,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fpic" { target fpic } } */ -/* { dg-xfail-if "" { i?86-pc-solaris2.1[0-9] && ilp32 } } */ int f0 (int, int, int, int, int); int f1 (void); diff --git a/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc/testsuite/gcc.target/i386/attributes-error.c index 1a5b0eadee..405eda5010 100644 --- a/gcc/testsuite/gcc.target/i386/attributes-error.c +++ b/gcc/testsuite/gcc.target/i386/attributes-error.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index f76d02db85..4f40abb260 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -maes -mpclmul" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -maes -mpclmul" } */ #include <mm_malloc.h> @@ -49,6 +49,39 @@ #define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) #define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) #define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_mpsadbw256(X, Y, M) __builtin_ia32_mpsadbw256(X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, M) __builtin_ia32_palignr256(X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, M) __builtin_ia32_pblendw256(X, Y, 8) +#define __builtin_ia32_pshufd256(X, M) __builtin_ia32_pshufd256(X, 8) +#define __builtin_ia32_pshufhw256(X, M) __builtin_ia32_pshufhw256(X, 8) +#define __builtin_ia32_pshuflw256(X, M) __builtin_ia32_pshuflw256(X, 8) +#define __builtin_ia32_pslldqi256(X, M) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, M) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, M) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, M) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, M) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, M) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, M) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, M) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, M) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(A, B, C, D, M) __builtin_ia32_gathersiv2df(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4df(A, B, C, D, M) __builtin_ia32_gathersiv4df(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv2df(A, B, C, D, M) __builtin_ia32_gatherdiv2df(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4df(A, B, C, D, M) __builtin_ia32_gatherdiv4df(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4sf(A, B, C, D, M) __builtin_ia32_gathersiv4sf(A, B, C, D, 1) +#define __builtin_ia32_gathersiv8sf(A, B, C, D, M) __builtin_ia32_gathersiv8sf(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4sf(A, B, C, D, M) __builtin_ia32_gatherdiv4sf(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4sf256(A, B, C, D, M) \ + __builtin_ia32_gatherdiv4sf256(A, B, C, D, 1) +#define __builtin_ia32_gathersiv2di(A, B, C, D, M) __builtin_ia32_gathersiv2di(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4di(A, B, C, D, M) __builtin_ia32_gathersiv4di(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv2di(A, B, C, D, M) __builtin_ia32_gatherdiv2di(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4di(A, B, C, D, M) __builtin_ia32_gatherdiv4di(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4si(A, B, C, D, M) __builtin_ia32_gathersiv4si(A, B, C, D, 1) +#define __builtin_ia32_gathersiv8si(A, B, C, D, M) __builtin_ia32_gathersiv8si(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4si(A, B, C, D, M) __builtin_ia32_gatherdiv4si(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4si256(A, B, C, D, M) \ + __builtin_ia32_gatherdiv4si256(A, B, C, D, 1) /* wmmintrin.h */ #define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1) diff --git a/gcc/testsuite/gcc.target/i386/avx-2.c b/gcc/testsuite/gcc.target/i386/avx-2.c index c3616ba340..17bc64e4de 100644 --- a/gcc/testsuite/gcc.target/i386/avx-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -msse4a -maes -mpclmul" } */ #include <mm_malloc.h> diff --git a/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c b/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c new file mode 100644 index 0000000000..bf48b80717 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceil (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c new file mode 100644 index 0000000000..ac0911fe84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceil-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c b/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c new file mode 100644 index 0000000000..0e76ab8026 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceil-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c new file mode 100644 index 0000000000..789b78e76a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceilf-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c b/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c new file mode 100644 index 0000000000..c324a9b4f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceilf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-cond-1.c b/gcc/testsuite/gcc.target/i386/avx-cond-1.c new file mode 100644 index 0000000000..e233ec9622 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cond-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse4_1-cond-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c b/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c index 130c4066be..9b45a093a7 100644 --- a/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c +++ b/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c @@ -2,26 +2,7 @@ /* { dg-require-effective-target avx } */ /* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ -#include "avx-check.h" +#define CHECK_H "avx-check.h" +#define TEST avx_test -extern double copysign (double, double); - -#define N 16 - -double a[N] = {-0.1,-3.2,-6.3,-9.4,-12.5,-15.6,-18.7,-21.8,24.9,27.1,30.2,33.3,36.4,39.5,42.6,45.7}; -double b[N] = {-1.2,3.4,-5.6,7.8,-9.0,1.0,-2.0,3.0,-4.0,-5.0,6.0,7.0,-8.0,-9.0,10.0,11.0}; -double r[N]; - -static void -avx_test (void) -{ - int i; - - for (i = 0; i < N; i++) - r[i] = copysign (a[i], b[i]); - - /* check results: */ - for (i = 0; i < N; i++) - if (r[i] != copysign (a[i], b[i])) - abort (); -} +#include "sse2-copysign-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c b/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c index 9ed3ab727c..00aa6f57ff 100644 --- a/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c +++ b/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c @@ -2,26 +2,7 @@ /* { dg-require-effective-target avx } */ /* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ -#include "avx-check.h" +#define CHECK_H "avx-check.h" +#define TEST avx_test -extern float copysignf (float, float); - -#define N 16 - -float a[N] = {-0.1f,-3.2f,-6.3f,-9.4f,-12.5f,-15.6f,-18.7f,-21.8f,24.9f,27.1f,30.2f,33.3f,36.4f,39.5f,42.6f,45.7f}; -float b[N] = {-1.2f,3.4f,-5.6f,7.8f,-9.0f,1.0f,-2.0f,3.0f,-4.0f,-5.0f,6.0f,7.0f,-8.0f,-9.0f,10.0f,11.0f}; -float r[N]; - -static void -avx_test (void) -{ - int i; - - for (i = 0; i < N; i++) - r[i] = copysignf (a[i], b[i]); - - /* check results: */ - for (i = 0; i < N; i++) - if (r[i] != copysignf (a[i], b[i])) - abort (); -} +#include "sse-copysignf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-1.c b/gcc/testsuite/gcc.target/i386/avx-cvt-1.c new file mode 100644 index 0000000000..ce651649d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cvt-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ +/* { dg-require-effective-target avx_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse2-cvt-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c b/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c new file mode 100644 index 0000000000..0081dcf381 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=sse"))) +TEST (void) +{ + double a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (float) a[i]; + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (float) a[i]) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-2.c b/gcc/testsuite/gcc.target/i386/avx-cvt-2.c new file mode 100644 index 0000000000..de1afeccaf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -fdump-tree-vect-details" } */ + +#include "avx-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-3.c b/gcc/testsuite/gcc.target/i386/avx-cvt-3.c new file mode 100644 index 0000000000..a9b898a95a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cvt-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -mprefer-avx128 -fdump-tree-vect-details" } */ + +#include "avx-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%xmm|xmm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*xmm\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c b/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c new file mode 100644 index 0000000000..4dcfa39895 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvt-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-extract-1.c b/gcc/testsuite/gcc.target/i386/avx-extract-1.c new file mode 100644 index 0000000000..2684125f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-extract-1.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +#include "sse2-extract-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c b/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c new file mode 100644 index 0000000000..275199cf8f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floor (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c new file mode 100644 index 0000000000..efa557cf79 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floor-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-floor-vec.c b/gcc/testsuite/gcc.target/i386/avx-floor-vec.c new file mode 100644 index 0000000000..1d7fe50431 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-floor-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floor-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c new file mode 100644 index 0000000000..0c1587a120 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floorf-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c b/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c new file mode 100644 index 0000000000..73da85be9e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floorf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c b/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c new file mode 100644 index 0000000000..2df65d2035 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-lrint-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c b/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c new file mode 100644 index 0000000000..e08b2f5657 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-lrintf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-mul-1.c b/gcc/testsuite/gcc.target/i386/avx-mul-1.c new file mode 100644 index 0000000000..0d511c95cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -mavx" } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-recip-vec.c b/gcc/testsuite/gcc.target/i386/avx-recip-vec.c new file mode 100644 index 0000000000..efeff7ece8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-recip-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-recip-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-reduc-1.c b/gcc/testsuite/gcc.target/i386/avx-reduc-1.c new file mode 100644 index 0000000000..1df1ee032c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-reduc-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +extern void abort (void); +double ad[1024]; +float af[1024]; +short as[1024]; +int ai[1024]; +long long all[1024]; +unsigned short aus[1024]; +unsigned int au[1024]; +unsigned long long aull[1024]; + +#define F(var) \ +__attribute__((noinline, noclone)) __typeof (var[0]) \ +f##var (void) \ +{ \ + int i; \ + __typeof (var[0]) r = 0; \ + for (i = 0; i < 1024; i++) \ + r = r > var[i] ? r : var[i]; \ + return r; \ +} + +#define TESTS \ +F (ad) F (af) F (as) F (ai) F (all) F (aus) F (au) F (aull) + +TESTS + +int +main () +{ + int i; + for (i = 0; i < 1024; i++) + { +#undef F +#define F(var) var[i] = i; + TESTS + } + for (i = 1023; i < 32 * 1024; i += 1024 + 271) + { +#undef F +#define F(var) var[i & 1023] = i; if (f##var () != i) abort (); + TESTS + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c b/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c new file mode 100644 index 0000000000..9f273af5cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c new file mode 100644 index 0000000000..824f2eb7d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rint-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-rint-vec.c b/gcc/testsuite/gcc.target/i386/avx-rint-vec.c new file mode 100644 index 0000000000..c1d420c6c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-rint-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rint-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c new file mode 100644 index 0000000000..e5ddf790d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rintf-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c b/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c new file mode 100644 index 0000000000..caf365da68 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rintf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c b/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c new file mode 100644 index 0000000000..ddb46d9252 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c new file mode 100644 index 0000000000..5adfffa5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-round-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-round-vec.c b/gcc/testsuite/gcc.target/i386/avx-round-vec.c new file mode 100644 index 0000000000..c43c057049 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-round-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-round-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c new file mode 100644 index 0000000000..1fd4591233 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundf-sfix-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c b/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c new file mode 100644 index 0000000000..978013eb12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c b/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c new file mode 100644 index 0000000000..a1ee6d461f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-truncf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c b/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c new file mode 100644 index 0000000000..a1ee6d461f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-truncf-vec.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c index a5b04fa5ea..f462c63651 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c index 49096cfceb..36f411e59b 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c index 765c455f87..8dc0b35c18 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c index 5160b8de10..b9afab7f6a 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c index dcf487afb5..84bdb9f3af 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c b/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c index 14b072146c..b3c68eaf69 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c b/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c index 9397729340..515ee418cb 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c +++ b/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target ilp32 } } */ +/* { dg-do run { target ia32 } } */ /* { dg-require-effective-target avx } */ /* { dg-options "-O2 -mfpmath=sse -mavx -mtune=geode" } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c b/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c new file mode 100644 index 0000000000..24b5bba77d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-maskmovdqu.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c b/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c index 3c3732baf7..02b0d2229d 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c @@ -1,6 +1,5 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c b/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c index cf0f4eb694..8306d39cc3 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c +++ b/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c b/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c index 26944d1186..a6d624749a 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c +++ b/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c b/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c index 1ffe007a14..59e70b2d85 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c b/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c new file mode 100644 index 0000000000..3ae122c7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-phminposuw-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c b/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c new file mode 100644 index 0000000000..4a37ba542a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +#include "avx-vphminposuw-2.c" + +/* { dg-final { scan-assembler "vphminposuw\[^\n\r\]*xmm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c b/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c index 3b9d26a291..595fc1baa3 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c @@ -1,6 +1,5 @@ -/* { dg-do run } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target avx } */ -/* { dg-require-effective-target lp64 } */ /* { dg-options "-O2 -mavx" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c b/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c new file mode 100644 index 0000000000..5e1a7cb91c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pinsrw.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c index ad46d35dc2..bc6e0d23c7 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c @@ -1,12 +1,11 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target lp64 } } */ /* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */ typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); extern __m256 x; -extern __m256 __attribute__ ((sysv_abi)) bar (__m256); +extern __m256 __attribute__ ((sysv_abi)) bar (__m256); void foo (void) @@ -15,4 +14,4 @@ foo (void) } /* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ -/* { dg-final { scan-assembler-times "\\*call_value_0_rex64_ms_sysv" 1 } } */ +/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c index 5b5c64bc0c..5d3aa48397 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target lp64 } } */ /* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */ typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); @@ -15,4 +14,4 @@ foo (void) } /* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ -/* { dg-final { scan-assembler-times "\\*call_value_1_rex64_ms_sysv" 1 } } */ +/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c index 541f77d767..06307525d4 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target lp64 } } */ /* { dg-options "-O0 -mavx -mabi=ms -mtune=generic -dp" } */ typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); @@ -15,4 +14,4 @@ foo (void) } /* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ -/* { dg-final { scan-assembler-times "\\*call_1_rex64_ms_sysv" 1 } } */ +/* { dg-final { scan-assembler-times "\\*call_rex64_ms_sysv" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c index c55c814316..4676617607 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c index a14460cf8a..0f54602b8c 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx2-check.h b/gcc/testsuite/gcc.target/i386/avx2-check.h new file mode 100644 index 0000000000..424335dbb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-check.h @@ -0,0 +1,47 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m256-check.h" +#include "avx-os-support.h" + +static void avx2_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + avx2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run AVX2 test only if host has AVX2 support. */ + if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE)) + { + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + if ((avx_os_support ()) && ((ebx & bit_AVX2) == bit_AVX2)) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c b/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c new file mode 100644 index 0000000000..9626a0666d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "sse2-cvt-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c b/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c new file mode 100644 index 0000000000..4826e9b6d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2 -mtune=generic -fdump-tree-vect-details" } */ + +#include "avx2-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-1.c b/gcc/testsuite/gcc.target/i386/avx2-gather-1.c new file mode 100644 index 0000000000..7ed567dc49 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-gather-1.c @@ -0,0 +1,215 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include "avx2-check.h" + +#define N 1024 +float vf1[N+16], vf2[N]; +double vd1[N+16], vd2[N]; +int k[N]; +long l[N]; +short n[N]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f3 (int x) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f4 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f7 (int x) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f8 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f11 (long x) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f12 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f13 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f14 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f15 (long x) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f16 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[l[i] + x]; +} + +static void +avx2_test (void) +{ + int i; + + for (i = 0; i < N + 16; i++) + { + asm (""); + vf1[i] = 17.0f + i; + vd1[i] = 19.0 + i; + } + for (i = 0; i < N; i++) + { + asm (""); + k[i] = (i * 731) & (N - 1); + l[i] = (i * 657) & (N - 1); + } + + f1 (); + f2 (); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 731) & (N - 1)) + 17 + || n[i] != ((i * 731) & (N - 1)) + 17) + abort (); + + f3 (12); + f4 (14); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 731) & (N - 1)) + 17 + 12 + || n[i] != ((i * 731) & (N - 1)) + 17 + 14) + abort (); + + f5 (); + f6 (); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 731) & (N - 1)) + 19 + || n[i] != ((i * 731) & (N - 1)) + 19) + abort (); + + f7 (7); + f8 (9); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 731) & (N - 1)) + 19 + 7 + || n[i] != ((i * 731) & (N - 1)) + 19 + 9) + abort (); + + f9 (); + f10 (); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 657) & (N - 1)) + 17 + || n[i] != ((i * 657) & (N - 1)) + 17) + abort (); + + f11 (2); + f12 (4); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 657) & (N - 1)) + 17 + 2 + || n[i] != ((i * 657) & (N - 1)) + 17 + 4) + abort (); + + f13 (); + f14 (); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 657) & (N - 1)) + 19 + || n[i] != ((i * 657) & (N - 1)) + 19) + abort (); + + f15 (13); + f16 (15); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 657) & (N - 1)) + 19 + 13 + || n[i] != ((i * 657) & (N - 1)) + 19 + 15) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-2.c b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c new file mode 100644 index 0000000000..8a7fe95a23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2 -fdump-tree-vect-details" } */ + +#include "avx2-gather-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 16 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-3.c b/gcc/testsuite/gcc.target/i386/avx2-gather-3.c new file mode 100644 index 0000000000..fb6289c0e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-gather-3.c @@ -0,0 +1,167 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2 -ffast-math" } */ + +#include "avx2-check.h" + +#define N 1024 +float f[N]; +double d[N]; +int k[N]; +float *l[N]; +double *n[N]; +int **m[N]; +long **o[N]; +long q[N]; +long *r[N]; +int *s[N]; + +__attribute__((noinline, noclone)) float +f1 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += f[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f2 (float *p) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f3 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += *l[i]; + return g; +} + +__attribute__((noinline, noclone)) int +f4 (void) +{ + int i; + int g = 0; + for (i = 0; i < N / 2; i++) + g += **m[i]; + return g; +} + +__attribute__((noinline, noclone)) double +f5 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += d[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f6 (double *p) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f7 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += *n[i]; + return g; +} + +__attribute__((noinline, noclone)) int +f8 (void) +{ + int i; + int g = 0; + for (i = 0; i < N / 2; i++) + g += **o[i]; + return g; +} + +__attribute__((noinline, noclone)) float +f9 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += f[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f10 (float *p) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f11 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += d[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f12 (double *p) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[q[i]]; + return g; +} + +static void +avx2_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + asm (""); + f[i] = -256.0f + i; + d[i] = -258.0 + i; + k[i] = (i * 731) & (N - 1); + q[i] = (i * 657) & (N - 1); + l[i] = &f[(i * 239) & (N - 1)]; + n[i] = &d[(i * 271) & (N - 1)]; + r[i] = &q[(i * 323) & (N - 1)]; + s[i] = &k[(i * 565) & (N - 1)]; + m[i] = &s[(i * 13) & (N - 1)]; + o[i] = &r[(i * 19) & (N - 1)]; + } + + if (f1 () != 136448.0f || f2 (f) != 136448.0f || f3 () != 130304.0) + abort (); + if (f4 () != 261376 || f5 () != 135424.0 || f6 (d) != 135424.0) + abort (); + if (f7 () != 129280.0 || f8 () != 259840L || f9 () != 130816.0f) + abort (); + if (f10 (f) != 130816.0f || f11 () != 129792.0 || f12 (d) != 129792.0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-4.c b/gcc/testsuite/gcc.target/i386/avx2-gather-4.c new file mode 100644 index 0000000000..440a9c9b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-gather-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include "avx2-check.h" + +#define N 1024 +int a[N], b[N], c[N], d[N]; + +__attribute__((noinline, noclone)) void +foo (float *__restrict p, float *__restrict q, float *__restrict r, + long s1, long s2, long s3) +{ + int i; + for (i = 0; i < N; i++) + p[i] = q[a[i] * s1 + b[i] * s2 + s3] * r[c[i] * s1 + d[i] * s2 + s3]; +} + +static void +avx2_test (void) +{ + int i; + float e[N], f[N], g[N]; + for (i = 0; i < N; i++) + { + a[i] = (i * 7) & (N / 8 - 1); + b[i] = (i * 13) & (N / 8 - 1); + c[i] = (i * 23) & (N / 8 - 1); + d[i] = (i * 5) & (N / 8 - 1); + e[i] = 16.5 + i; + f[i] = 127.5 - i; + } + foo (g, e, f, 3, 2, 4); + for (i = 0; i < N; i++) + if (g[i] != (float) ((20.5 + a[i] * 3 + b[i] * 2) + * (123.5 - c[i] * 3 - d[i] * 2))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c new file mode 100644 index 0000000000..ae3b1d577b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_epi32 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c new file mode 100644 index 0000000000..7d3f3474d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd (int *s1, int *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128i_d res; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i32gather_epi32 (s1, idx.x, 2); + + compute_i32gatherd (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c new file mode 100644 index 0000000000..fc8fedea07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c new file mode 100644 index 0000000000..2cc3a792ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd (int *src, int *s1, int *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128i_d res, src, mask; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c new file mode 100644 index 0000000000..afc73b9b18 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_epi32 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c new file mode 100644 index 0000000000..e5bcbee1fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd256 (int *s1, int *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 8; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256i_d res; + int s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i32gather_epi32 (s1, idx.x, 2); + + compute_i32gatherd256 (s1, idx.a, 2, res_ref); + + if (check_union256i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c new file mode 100644 index 0000000000..d0c8642944 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c new file mode 100644 index 0000000000..a80530912d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd256 (int *src, + int *s1, int *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 8; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256i_d res, src, mask; + int s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c new file mode 100644 index 0000000000..860cac448d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c new file mode 100644 index 0000000000..475f623ec8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (double *s1, int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128d res; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i32gather_pd (s1, idx.x, 2); + + compute_i32gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c new file mode 100644 index 0000000000..5e1d4864bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_pd (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c new file mode 100644 index 0000000000..12c533f9d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (double *src, + double *s1, int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128d res, src, mask; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c new file mode 100644 index 0000000000..00b6a35c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c new file mode 100644 index 0000000000..a45801ba94 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (double *s1, int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union256d res; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i32gather_pd (s1, idx.x, 2); + + compute_i32gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c new file mode 100644 index 0000000000..336fb299b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_pd (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c new file mode 100644 index 0000000000..f24acbd7fe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (double *src, + double *s1, + int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union256d res, src, mask; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, divide by 2 + to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c new file mode 100644 index 0000000000..c43687c4d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_ps (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c new file mode 100644 index 0000000000..1174ddad51 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps (float *s1, int *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128 res; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i32gather_ps (s1, idx.x, 2); + + compute_i32gatherps (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c new file mode 100644 index 0000000000..76b46fb23a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_ps (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c new file mode 100644 index 0000000000..94b9213d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps (float *src, + float *s1, int *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128 res, src, mask; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c new file mode 100644 index 0000000000..f09a0ff32f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_ps (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c new file mode 100644 index 0000000000..654c6f676e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps256 (float *s1, int *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 8; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256 res; + float s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i32gather_ps (s1, idx.x, 2); + + compute_i32gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union256 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c new file mode 100644 index 0000000000..34b7b8d72f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_ps (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c new file mode 100644 index 0000000000..07c2abacbf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps256 (float *src, + float *s1, int *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 8; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256 res, src, mask; + float s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c new file mode 100644 index 0000000000..0b250e5dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_epi64 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c new file mode 100644 index 0000000000..54838e7102 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (long long *s1, int *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union128i_q res; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i32gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i32gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c new file mode 100644 index 0000000000..d87400c77d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c new file mode 100644 index 0000000000..4770d0adae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (long long *src, + long long *s1, + int *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union128i_q res, src, mask; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = + _mm_mask_i32gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2); + + compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c new file mode 100644 index 0000000000..e8651438a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_epi64 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c new file mode 100644 index 0000000000..85e576797f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (long long *s1, int *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union256i_q res; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i32gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i32gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c new file mode 100644 index 0000000000..7b6f4491aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c new file mode 100644 index 0000000000..3eab9be5c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (long long *src, + long long *s1, + int *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union256i_q res, src, mask; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, divide by 2 + to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i32gather_epi64 (src.x, + (long long int *) s1, + idx.x, mask.x, 2); + + compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c new file mode 100644 index 0000000000..f2ade8415d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_epi32 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c new file mode 100644 index 0000000000..f475a4a734 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (int *s1, long long *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128i_d res; + int s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i64gather_epi32 (s1, idx.x, 2); + + compute_i64gatherps (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c new file mode 100644 index 0000000000..265713da50 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c new file mode 100644 index 0000000000..77c8747f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (int *src, + int *s1, long long *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128i_d res, src, mask; + int s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c new file mode 100644 index 0000000000..ccc16e523c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_epi32 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c new file mode 100644 index 0000000000..0f88b20b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (int *s1, long long *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128i_d res; + int s1[8], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i64gather_epi32 (s1, idx.x, 2); + + compute_i64gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c new file mode 100644 index 0000000000..815e708282 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c new file mode 100644 index 0000000000..6c4bdd60ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (int *src, + int *s1, long long *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128i_d res, src, mask; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c new file mode 100644 index 0000000000..895b248c72 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c new file mode 100644 index 0000000000..5a119712e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (double *s1, long long *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128d res; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i64gather_pd (s1, idx.x, 2); + + compute_i64gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c new file mode 100644 index 0000000000..436ffe90a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_pd (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c new file mode 100644 index 0000000000..61cb1f8d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (double *src, + double *s1, + long long int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128d res, src, mask; + double s1[2], res_ref[2] = { 0, 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c new file mode 100644 index 0000000000..bc22f02e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_pd (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c new file mode 100644 index 0000000000..99e192d754 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd256 (double *s1, long long int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union256d res; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i64gather_pd (s1, idx.x, 2); + + compute_i64gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c new file mode 100644 index 0000000000..505722a8a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_pd (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c new file mode 100644 index 0000000000..09a5f8a14e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd256 (double *src, + double *s1, + long long int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union256d res, src, mask; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c new file mode 100644 index 0000000000..c7d7c0787b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_ps (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c new file mode 100644 index 0000000000..527e4e8124 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (float *s1, long long *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128 res; + float s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i64gather_ps (s1, idx.x, 2); + + compute_i64gatherps (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c new file mode 100644 index 0000000000..ca7162ad92 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_ps (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c new file mode 100644 index 0000000000..ada4e49ff4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (float *src, + float *s1, + long long *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128 res, src, mask; + float s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c new file mode 100644 index 0000000000..6612e99400 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_ps (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c new file mode 100644 index 0000000000..d2fe7c1fb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (float *s1, long long *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128 res; + float s1[8], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i64gather_ps (s1, idx.x, 2); + + compute_i64gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c new file mode 100644 index 0000000000..f05e4a208c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_ps (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c new file mode 100644 index 0000000000..8185cd839c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (float *src, + float *s1, + long long *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128 res, src, mask; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c new file mode 100644 index 0000000000..8f9752d2c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_epi64 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c new file mode 100644 index 0000000000..a2d7a99686 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (long long *s1, long long *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_q idx; + union128i_q res; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i64gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i64gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c new file mode 100644 index 0000000000..c1c31c7288 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c new file mode 100644 index 0000000000..cbc8e31f1a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (long long *src, + long long *s1, + long long *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_q idx; + union128i_q res, src, mask; + long long s1[2], res_ref[2] = { 0, 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = + _mm_mask_i64gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2); + + compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c new file mode 100644 index 0000000000..c873cb9548 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_epi64 (base, idx, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c new file mode 100644 index 0000000000..3ac3e2e013 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherq256 (long long *s1, long long *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union256i_q idx; + union256i_q res; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i64gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i64gatherq256 (s1, idx.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c new file mode 100644 index 0000000000..f60ad22746 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +long long int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c new file mode 100644 index 0000000000..355c8c2b06 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherq256 (long long *src, + long long *s1, + long long *s2, + long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union256i_q idx; + union256i_q res, src, mask; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i64gather_epi64 (src.x, + (long long int *) s1, + idx.x, mask.x, 2); + + compute_i64gatherq256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c new file mode 100644 index 0000000000..740e14163a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-final { scan-assembler "mpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + /* imm = 13 is arbitrary here */ + x = _mm256_mpsadbw_epu8 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c new file mode 100644 index 0000000000..18118e4420 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c @@ -0,0 +1,132 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define msk0 0xC0 +#define msk1 0x01 +#define msk2 0xF2 +#define msk3 0x03 +#define msk4 0x84 +#define msk5 0x05 +#define msk6 0xE6 +#define msk7 0x67 + + +static void +compute_mpsadbw (int *i1, int *i2, int mask, int *r) +{ + unsigned char s[4]; + int i, j; + int offs1, offs2; + unsigned char *v1 = (char *) i1; + unsigned char *v2 = (char *) i2; + unsigned short *ret = (unsigned short *) r; + + memset (ret, 0, 32); + + /* Lower part */ + offs2 = 4 * (mask & 3); + for (i = 0; i < 4; i++) + s[i] = v2[offs2 + i]; + + offs1 = 4 * ((mask & 4) >> 2); + for (j = 0; j < 8; j++) + for (i = 0; i < 4; i++) + ret[j] += abs (v1[offs1 + j + i] - s[i]); + + /* Higher part */ + offs2 = 4 * ((mask >> 3) & 3) + 16; + for (i = 0; i < 4; i++) + s[i] = v2[offs2 + i]; + + offs1 = 4 * ((mask & 0x20) >> 5) + 16; + for (j = 0; j < 8; j++) + for (i = 0; i < 4; i++) + ret[j + 8] += abs (v1[offs1 + j + i] - s[i]); +} + +static void +avx2_test (void) +{ + union256i_d val1, val2, val3[8], res[8]; + int tmp[8]; + unsigned char masks[8]; + int i, j; + + val1.a[0] = 0x35251505; + val1.a[1] = 0x75655545; + val1.a[2] = 0xB5A59585; + val1.a[3] = 0xF5E5D5C5; + + val1.a[4] = 0x35251505; + val1.a[5] = 0x75655545; + val1.a[6] = 0xB5A59585; + val1.a[7] = 0xF5E5D5C5; + + val2.a[0] = 0x31211101; + val2.a[1] = 0x71615141; + val2.a[2] = 0xB1A19181; + val2.a[3] = 0xF1E1D1C1; + + val2.a[4] = 0x31211101; + val2.a[5] = 0x71615141; + val2.a[6] = 0xB1A19181; + val2.a[7] = 0xF1E1D1C1; + + for (i = 0; i < 8; i++) + switch (i % 3) + { + case 1: + val3[i].a[0] = 0xF1E1D1C1; + val3[i].a[1] = 0xB1A19181; + val3[i].a[2] = 0x71615141; + val3[i].a[3] = 0x31211101; + break; + default: + val3[i].x = val2.x; + break; + } + + /* Check mpsadbw imm8, ymm, ymm. */ + res[0].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk0); + res[1].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk1); + res[2].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk2); + res[3].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk3); + res[4].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk4); + res[5].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk5); + res[6].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk6); + res[7].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i = 0; i < 8; i++) + { + compute_mpsadbw (val1.a, val2.a, masks[i], tmp); + if (check_union256i_d (res[i], tmp)) + abort (); + } + + /* Check mpsadbw imm8, m256, ymm. */ + for (i = 0; i < 8; i++) + { + res[i].x = _mm256_mpsadbw_epu8 (val1.x, val3[i].x, msk4); + masks[i] = msk4; + } + + for (i = 0; i < 8; i++) + { + compute_mpsadbw (val1.a, val3[i].a, masks[i], tmp); + if (check_union256i_d (res[i], tmp)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-mul-1.c b/gcc/testsuite/gcc.target/i386/avx2-mul-1.c new file mode 100644 index 0000000000..0351fbb7c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c new file mode 100644 index 0000000000..80964e39d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastsd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m128d x; +__m256d y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastsd_pd (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c new file mode 100644 index 0000000000..ee323f5af3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128d s1; + union256d res; + double res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm256_broadcastsd_pd (s1.x); + + for (j = 0; j < 4; j++) + memcpy (res_ref + j, s1.a, 8); + + fail += check_union256d (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c new file mode 100644 index 0000000000..c0592d5086 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcasti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm_broadcastsi128_si256 (y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c new file mode 100644 index 0000000000..6d3af38ff2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128i_q s1; + union256i_q res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + s1.a[j] = j * i; + + res.x = _mm_broadcastsi128_si256 (s1.x); + + memcpy (res_ref, s1.a, 16); + memcpy (res_ref + 2, s1.a, 16); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c new file mode 100644 index 0000000000..d9d47e2a9a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastss_ps (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c new file mode 100644 index 0000000000..1637e703bc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128 s1, res; + float res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm_broadcastss_ps (s1.x); + + for (j = 0; j < 4; j++) + memcpy (res_ref + j, s1.a, 4); + + fail += check_union128 (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c new file mode 100644 index 0000000000..dfac3916b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +__m256 y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastss_ps (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c new file mode 100644 index 0000000000..9f90e2e852 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128 s1; + union256 res; + float res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm256_broadcastss_ps (s1.x); + + for (j = 0; j < 8; j++) + memcpy (res_ref + j, s1.a, 4); + + fail += check_union256 (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c new file mode 100644 index 0000000000..a032e3c9b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vextracti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + y = _mm256_extracti128_si256 (x, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c new file mode 100644 index 0000000000..7d3c561a14 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1; + union128i_q res; + long long int res_ref[2]; + int j; + + for (j = 0; j < 4; j++) + s1.a[j] = j * j; + + res.x = _mm256_extracti128_si256 (s1.x, 0); + + memset (res_ref, 0, 16); + memcpy (res_ref, s1.a, 16); + + if (check_union128i_q (res, res_ref)) + abort (); + + res.x = _mm256_extracti128_si256 (s1.x, 1); + + memset (res_ref, 0, 16); + memcpy (res_ref, s1.a + 2, 16); + + if (check_union128i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c new file mode 100644 index 0000000000..2d0f7c51af --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vinserti128\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_inserti128_si256 (x, y, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c new file mode 100644 index 0000000000..f6361cd472 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int j; + + for (j = 0; j < 4; j++) + s1.a[j] = j * j; + + for (j = 0; j < 2; j++) + s2.a[j] = j * j * j; + + res.x = _mm256_inserti128_si256 (s1.x, s2.x, 0); + + memcpy (res_ref, s1.a, 32); + memcpy (res_ref, s2.a, 16); + + if (check_union256i_q (res, res_ref)) + abort (); + + res.x = _mm256_inserti128_si256 (s1.x, s2.x, 1); + + memcpy (res_ref, s1.a, 32); + memcpy (res_ref + 2, s2.a, 16); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c b/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c new file mode 100644 index 0000000000..4c44f082d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vmovntdqa\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m256i *y; + +void extern +avx2_test (void) +{ + x = _mm256_stream_load_si256 (y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c b/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c new file mode 100644 index 0000000000..f1eda70bd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1, res; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_stream_load_si256 (&s1.x); + + fail += check_union256i_q (res, s1.a); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c new file mode 100644 index 0000000000..0607a886cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi8 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c new file mode 100644 index 0000000000..05db8a4072 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, char *r) +{ + char *b1 = (char *) i1; + int i; + + for (i = 0; i < 32; i++) + if (b1[i] < 0) + r[i] = -b1[i]; + else + r[i] = b1[i]; +} + +static void +avx2_test (void) +{ + int i; + char ck[32]; + int fail = 0; + + union256i_b s, d; + + for (i = 0; i < 256; ++i) + { + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi8 (s.x); + + fail += check_union256i_b (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c new file mode 100644 index 0000000000..396077ff12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c new file mode 100644 index 0000000000..4c88024b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + if (i1[i] < 0) + r[i] = -i1[i]; + else + r[i] = i1[i]; +} + +static void +avx2_test (void) +{ + int i; + int ck[8]; + int fail = 0; + + union256i_d s, d; + + for (i = 0; i < 256; ++i) + { + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi32 (s.x); + + fail += check_union256i_d (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c new file mode 100644 index 0000000000..2dc7692ce1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi16 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c new file mode 100644 index 0000000000..fa4efd2984 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, short *r) +{ + short *b1 = (short *) i1; + int i; + + for (i = 0; i < 16; i++) + if (b1[i] < 0) + r[i] = -b1[i]; + else + r[i] = b1[i]; +} + +static void +avx2_test (void) +{ + int i; + short ck[16]; + int fail = 0; + + union256i_w s, d; + + for (i = 0; i < 256; ++i) + { + /* Using only first 2 bytes of int */ + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi16 (s.x); + + fail += check_union256i_w (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c new file mode 100644 index 0000000000..6d5667a644 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackssdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packs_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c new file mode 100644 index 0000000000..16f0d23f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static short +int_to_short (int iVal) +{ + short sVal; + + if (iVal < -32768) + sVal = -32768; + else if (iVal > 32767) + sVal = 32767; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2; + union256i_w u; + short e[16]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90); + + s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, -65000); + + u.x = _mm256_packs_epi32 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[i] = int_to_short (s1.a[i]); + e[i + 4] = int_to_short (s2.a[i]); + e[i + 8] = int_to_short (s1.a[i + 4]); + e[i + 12] = int_to_short (s2.a[i + 4]); + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c new file mode 100644 index 0000000000..00faf844ad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpacksswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packs_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c new file mode 100644 index 0000000000..8b2a1c1118 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static char +short_to_byte (short iVal) +{ + char sVal; + + if (iVal < -128) + sVal = -128; + else if (iVal > 127) + sVal = 127; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2; + union256i_b u; + char e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90, + 88, 44, 33, 22, 11, 98, 78, -1000); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650, + 1, 2, 3, 4, 6500, 20, 30, 90); + + u.x = _mm256_packs_epi16 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[i] = short_to_byte (s1.a[i]); + e[i + 8] = short_to_byte (s2.a[i]); + e[i + 16] = short_to_byte (s1.a[i + 8]); + e[i + 24] = short_to_byte (s2.a[i + 8]); + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c new file mode 100644 index 0000000000..1f0a7ff9de --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packus_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c new file mode 100644 index 0000000000..afc102610f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static unsigned short +int_to_ushort (int iVal) +{ + unsigned short sVal; + + if (iVal < 0) + sVal = 0; + else if (iVal > 65536) + sVal = 65535; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2; + union256i_w u; + unsigned short e[16]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, -65000, 20, 30, 90); + + s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, 120000); + + u.x = _mm256_packus_epi32 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[i] = int_to_ushort (s1.a[i]); + e[i + 4] = int_to_ushort (s2.a[i]); + e[i + 8] = int_to_ushort (s1.a[i + 4]); + e[i + 12] = int_to_ushort (s2.a[i + 4]); + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c new file mode 100644 index 0000000000..7b30a66667 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackuswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packus_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c new file mode 100644 index 0000000000..abeee3e6d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static unsigned char +short_to_ubyte (short iVal) +{ + unsigned char sVal; + + if (iVal < 0) + sVal = 0; + else if (iVal > 255) + sVal = 255; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2; + union256i_b u; + char e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90, + 88, 44, 33, 22, 11, 98, 78, -1000); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650, + 1, 2, 3, 4, 6500, 20, 30, 90); + + u.x = _mm256_packus_epi16 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[i] = short_to_ubyte (s1.a[i]); + e[i + 8] = short_to_ubyte (s2.a[i]); + e[i + 16] = short_to_ubyte (s1.a[i + 8]); + e[i + 24] = short_to_ubyte (s2.a[i + 8]); + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c new file mode 100644 index 0000000000..b6ceef16f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c new file mode 100644 index 0000000000..8abeb50c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + unsigned i; + + s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84, + 29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72, + 92, 9, 4, 23, 17, 99, 43, 72, 17); + + s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200, + 17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43, + 27, 112, 71, 50, 32, 72, 84, 17, 27, 96); + + u.x = _mm256_add_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c new file mode 100644 index 0000000000..238f020921 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE char +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c new file mode 100644 index 0000000000..14142ec0ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c new file mode 100644 index 0000000000..c3b1961965 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + unsigned i; + + s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4); + s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000); + + u.x = _mm256_add_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c new file mode 100644 index 0000000000..c57ef8fea3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c new file mode 100644 index 0000000000..9fcf9aaad0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c new file mode 100644 index 0000000000..03b011f3f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q u, s1, s2; + long long e[4]; + unsigned i; + + s1.x = _mm256_set_epi64x (100, 74, 50000, 4); + s2.x = _mm256_set_epi64x (88, 44, 33, 220); + + u.x = _mm256_add_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c new file mode 100644 index 0000000000..801bd39d82 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE long long int +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c new file mode 100644 index 0000000000..77978d9362 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c new file mode 100644 index 0000000000..d07a6a7814 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_adds_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c new file mode 100644 index 0000000000..128f5309f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c new file mode 100644 index 0000000000..19bbe0a77c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, + -40, -100, -15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100, + -34, -78, -39, 6, 3, 4, 5, 119); + + u.x = _mm256_adds_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c new file mode 100644 index 0000000000..f6cf4019c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c new file mode 100644 index 0000000000..68ad4f03fe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + unsigned i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15, + 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76, + 200, 34, 78, 39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39, + 6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90, + 80, 40, 100, 15, 98, 25, 98, 7); + + u.x = _mm256_adds_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = (unsigned char) s1.a[i] + (unsigned char) s2.a[i]; + + if (tmp > 255) + tmp = 255; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c new file mode 100644 index 0000000000..a4c1dd9bd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c new file mode 100644 index 0000000000..937b93c21a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[32]; + unsigned i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, + 65531, 40, 100, 15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 219); + + u.x = _mm256_adds_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = (unsigned short) s1.a[i] + (unsigned short) s2.a[i]; + + if (tmp > 65535) + tmp = 65535; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c new file mode 100644 index 0000000000..052e3a352a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c new file mode 100644 index 0000000000..f7dbf2053a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + unsigned i; + + s1.x = _mm256_set_epi16 (100, 74, 50000, 4, 6999, 39999, 1000, 4, + 874, 2783, 29884, 2904, 2889, 3279, 1, 3); + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 4556, 2999, 2, 9000, + 238, 194, 274, 17, 3, 5739, 2, 379); + + u.x = _mm256_add_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c new file mode 100644 index 0000000000..facee9f2d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c new file mode 100644 index 0000000000..a87a207d4e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-final { scan-assembler "vpalignr\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + /* imm = 13 is arbitrary here */ + x = _mm256_alignr_epi8 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c new file mode 100644 index 0000000000..5be64c0cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c @@ -0,0 +1,177 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Test the 256-bit form */ +static void +avx2_test_palignr256 (__m256i t1, __m256i t2, unsigned int imm, __m256i * r) +{ + switch (imm) + { + case 0: + *r = _mm256_alignr_epi8 (t1, t2, 0); + break; + case 1: + *r = _mm256_alignr_epi8 (t1, t2, 1); + break; + case 2: + *r = _mm256_alignr_epi8 (t1, t2, 2); + break; + case 3: + *r = _mm256_alignr_epi8 (t1, t2, 3); + break; + case 4: + *r = _mm256_alignr_epi8 (t1, t2, 4); + break; + case 5: + *r = _mm256_alignr_epi8 (t1, t2, 5); + break; + case 6: + *r = _mm256_alignr_epi8 (t1, t2, 6); + break; + case 7: + *r = _mm256_alignr_epi8 (t1, t2, 7); + break; + case 8: + *r = _mm256_alignr_epi8 (t1, t2, 8); + break; + case 9: + *r = _mm256_alignr_epi8 (t1, t2, 9); + break; + case 10: + *r = _mm256_alignr_epi8 (t1, t2, 10); + break; + case 11: + *r = _mm256_alignr_epi8 (t1, t2, 11); + break; + case 12: + *r = _mm256_alignr_epi8 (t1, t2, 12); + break; + case 13: + *r = _mm256_alignr_epi8 (t1, t2, 13); + break; + case 14: + *r = _mm256_alignr_epi8 (t1, t2, 14); + break; + case 15: + *r = _mm256_alignr_epi8 (t1, t2, 15); + break; + case 16: + *r = _mm256_alignr_epi8 (t1, t2, 16); + break; + case 17: + *r = _mm256_alignr_epi8 (t1, t2, 17); + break; + case 18: + *r = _mm256_alignr_epi8 (t1, t2, 18); + break; + case 19: + *r = _mm256_alignr_epi8 (t1, t2, 19); + break; + case 20: + *r = _mm256_alignr_epi8 (t1, t2, 20); + break; + case 21: + *r = _mm256_alignr_epi8 (t1, t2, 21); + break; + case 22: + *r = _mm256_alignr_epi8 (t1, t2, 22); + break; + case 23: + *r = _mm256_alignr_epi8 (t1, t2, 23); + break; + case 24: + *r = _mm256_alignr_epi8 (t1, t2, 24); + break; + case 25: + *r = _mm256_alignr_epi8 (t1, t2, 25); + break; + case 26: + *r = _mm256_alignr_epi8 (t1, t2, 26); + break; + case 27: + *r = _mm256_alignr_epi8 (t1, t2, 27); + break; + case 28: + *r = _mm256_alignr_epi8 (t1, t2, 28); + break; + case 29: + *r = _mm256_alignr_epi8 (t1, t2, 29); + break; + case 30: + *r = _mm256_alignr_epi8 (t1, t2, 30); + break; + case 31: + *r = _mm256_alignr_epi8 (t1, t2, 31); + break; + default: + *r = _mm256_alignr_epi8 (t1, t2, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result_256 (int *i1, int *i2, unsigned int imm, int *r) +{ + char buf[32]; + char *bout = (char *) r; + int i; + + /* Fill lowers 128 bit of ymm */ + memcpy (&buf[0], i2, 16); + memcpy (&buf[16], i1, 16); + + for (i = 0; i < 16; i++) + if (imm >= 32 || imm + i >= 32) + bout[i] = 0; + else + bout[i] = buf[imm + i]; + + /* Fill higher 128 bit of ymm */ + bout += 16; + memcpy (&buf[0], i2 + 4, 16); + memcpy (&buf[16], i1 + 4, 16); + + for (i = 0; i < 16; i++) + if (imm >= 32 || imm + i >= 32) + bout[i] = 0; + else + bout[i] = buf[imm + i]; +} + +static void +avx2_test (void) +{ + int i; + int ck[8]; + int r[8]; + unsigned int imm; + int fail = 0; + + union256i_q s1, s2, d; + + for (i = 0; i < 256; i += 16) + for (imm = 0; imm < 100; imm++) + { + /* Recompute the results for 256-bits */ + compute_correct_result_256 (&vals[i + 0], &vals[i + 8], imm, ck); + + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 0]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + /* Run the 256-bit tests */ + avx2_test_palignr256 (s1.x, s2.x, imm, &d.x); + + _mm256_storeu_si256 ((__m256i *) r, d.x); + + fail += checkVi (r, ck, 8); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c new file mode 100644 index 0000000000..e77e36982b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_and_si256 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c new file mode 100644 index 0000000000..ffd3404e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_and_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = source1[i] & source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c new file mode 100644 index 0000000000..67ca4a7cda --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define BIN_OP(a, b) ((a) & (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c new file mode 100644 index 0000000000..b068898844 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpandn\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_andnot_si256 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c new file mode 100644 index 0000000000..06d3cbd239 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_andnot_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = (~source1[i]) & source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c new file mode 100644 index 0000000000..a7abd6751a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpavgb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_avg_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c new file mode 100644 index 0000000000..8519e9bc34 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + int tmp; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_avg_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = ((unsigned char) s1.a[i] + (unsigned char) s2.a[i] + 1) >> 1; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c new file mode 100644 index 0000000000..dc68b8a6b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpavgw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_avg_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c new file mode 100644 index 0000000000..d222a9d4a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, 80, + 40, 100, 15, 98, 25, 98, 7); + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 119); + + u.x = _mm256_avg_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] + s2.a[i] + 1) >> 1; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c new file mode 100644 index 0000000000..92f7e1b8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_blend_epi32 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c new file mode 100644 index 0000000000..44732cc6f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xf1 + +static void +init_pblendd128 (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendd128 (int *src1, int *src2, unsigned int mask, int *dst) +{ + int i; + + memcpy (dst, src1, 16); + for (i = 0; i < 4; i++) + if (mask & (1 << i)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union128i_d src1, src2, dst; + int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendd128 (src1.a, src2.a, i); + + dst.x = _mm_blend_epi32 (src1.x, src2.x, MASK); + calc_pblendd128 (src1.a, src2.a, MASK, dst_ref); + + if (check_union128i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c new file mode 100644 index 0000000000..ab74988543 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blend_epi32 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c new file mode 100644 index 0000000000..fc5e3f7be9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xf1 + +static void +init_pblendd256 (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendd256 (int *src1, int *src2, unsigned int mask, int *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + if (mask & (1 << i)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_d src1, src2, dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendd256 (src1.a, src2.a, i); + + dst.x = _mm256_blend_epi32 (src1.x, src2.x, MASK); + calc_pblendd256 (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c new file mode 100644 index 0000000000..09ff4bccae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendvb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blendv_epi8 (x, x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c new file mode 100644 index 0000000000..c0e1d71ea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c @@ -0,0 +1,56 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +static void +init_pblendb (char *src1, char *src2, char *mask, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 32; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + + if (sign > 0) + mask[i] = 1 << 7; + else + mask[i] = 0; + } +} + +static void +calc_pblendb (char *src1, char *src2, char *mask, char *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 32; i++) + if (mask[i] & (1 << 7)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_b src1, src2, mask, dst; + char dst_ref[32]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendb (src1.a, src2.a, mask.a, i); + + dst.x = _mm256_blendv_epi8 (src1.x, src2.x, mask.x); + calc_pblendb (src1.a, src2.a, mask.a, dst_ref); + + if (check_union256i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c new file mode 100644 index 0000000000..7bbb93e4a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blend_epi16 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c new file mode 100644 index 0000000000..0500d351e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xfe + +static void +init_pblendw (short *src1, short *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendw (short *src1, short *src2, unsigned int mask, short *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 16; i++) + if (mask & (1 << (i % 8))) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_w src1, src2, dst; + short dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendw (src1.a, src2.a, i); + + dst.x = _mm256_blend_epi16 (src1.x, src2.x, MASK); + calc_pblendw (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c new file mode 100644 index 0000000000..14b9a7c095 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastb_epi8 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c new file mode 100644 index 0000000000..927755b2ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastb128 (char *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastb128 (char *src, char *dst) +{ + int i; + + for (i = 0; i < 16; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_b src, dst; + char dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastb128 (src.a, i); + + dst.x = _mm_broadcastb_epi8 (src.x); + calc_pbroadcastb128 (src.a, dst_ref); + + if (check_union128i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c new file mode 100644 index 0000000000..8e1247aac4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastb_epi8 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c new file mode 100644 index 0000000000..9b0e564697 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastb256 (char *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastb256 (char *src, char *dst) +{ + int i; + + for (i = 0; i < 32; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_b src; + union256i_b dst; + char dst_ref[32]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastb256 (src.a, i); + + dst.x = _mm256_broadcastb_epi8 (src.x); + calc_pbroadcastb256 (src.a, dst_ref); + + if (check_union256i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c new file mode 100644 index 0000000000..8a396678e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastd_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c new file mode 100644 index 0000000000..c9d2b46d21 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastd128 (int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastd128 (int *src, int *dst) +{ + int i; + + for (i = 0; i < 4; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_d src, dst; + int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastd128 (src.a, i); + + dst.x = _mm_broadcastd_epi32 (src.x); + calc_pbroadcastd128 (src.a, dst_ref); + + if (check_union128i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c new file mode 100644 index 0000000000..57f1bc78e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastd_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c new file mode 100644 index 0000000000..fe009da1a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastd256 (int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastd256 (int *src, int *dst) +{ + int i; + + for (i = 0; i < 8; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_d src; + union256i_d dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastd256 (src.a, i); + + dst.x = _mm256_broadcastd_epi32 (src.x); + calc_pbroadcastd256 (src.a, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c new file mode 100644 index 0000000000..6714ae7ff7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastq_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c new file mode 100644 index 0000000000..e6446de7da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastq128 (long long int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 2; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastq128 (long long int *src, long long int *dst) +{ + int i; + + for (i = 0; i < 2; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_q src, dst; + long long int dst_ref[2]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastq128 (src.a, i); + + dst.x = _mm_broadcastq_epi64 (src.x); + calc_pbroadcastq128 (src.a, dst_ref); + + if (check_union128i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c new file mode 100644 index 0000000000..bf1532b1e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastq_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c new file mode 100644 index 0000000000..4702631565 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastq256 (long long int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 2; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastq256 (long long int *src, long long int *dst) +{ + int i; + + for (i = 0; i < 4; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_q src; + union256i_q dst; + long long int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastq256 (src.a, i); + + dst.x = _mm256_broadcastq_epi64 (src.x); + calc_pbroadcastq256 (src.a, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c new file mode 100644 index 0000000000..ff5ee87410 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastw_epi16 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c new file mode 100644 index 0000000000..e8673a9dda --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastw128 (short *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastw128 (short *src, short *dst) +{ + int i; + + for (i = 0; i < 8; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_w src, dst; + short dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastw128 (src.a, i); + + dst.x = _mm_broadcastw_epi16 (src.x); + calc_pbroadcastw128 (src.a, dst_ref); + + if (check_union128i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c new file mode 100644 index 0000000000..14462a19bc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastw_epi16 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c new file mode 100644 index 0000000000..bac748fef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastw256 (short *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastw256 (short *src, short *dst) +{ + int i; + + for (i = 0; i < 16; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_w src; + union256i_w dst; + short dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastw256 (src.a, i); + + dst.x = _mm256_broadcastw_epi16 (src.x); + calc_pbroadcastw256 (src.a, dst_ref); + + if (check_union256i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c new file mode 100644 index 0000000000..063cb57500 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c new file mode 100644 index 0000000000..87a8fa42c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 25, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_cmpeq_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c new file mode 100644 index 0000000000..002b696860 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c new file mode 100644 index 0000000000..0cc10458fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000); + + s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100); + + u.x = _mm256_cmpeq_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c new file mode 100644 index 0000000000..196e3c311f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c new file mode 100644 index 0000000000..4abe781986 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_q u, s1, s2; + long long int e[4]; + int i; + + s1.x = _mm256_set_epi64x (1, 2, 3, 4); + + s2.x = _mm256_set_epi64x (88, 44, 3, 220000); + + u.x = _mm256_cmpeq_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c new file mode 100644 index 0000000000..1efa291431 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c new file mode 100644 index 0000000000..9fb38de2cd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 76, -100, -34, -78, -31000); + + s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + 30, 90, -80, -40, -100, -15); + + u.x = _mm256_cmpeq_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c new file mode 100644 index 0000000000..d8b35bba72 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c new file mode 100644 index 0000000000..b76077c200 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 25, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_cmpgt_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c new file mode 100644 index 0000000000..75e4b24e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c new file mode 100644 index 0000000000..371bd79fa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000); + + s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100); + + u.x = _mm256_cmpgt_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c new file mode 100644 index 0000000000..7a983808b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c new file mode 100644 index 0000000000..8d5cf3ee86 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_q u, s1, s2; + long long int e[4]; + int i; + + s1.x = _mm256_set_epi64x (1, 2, 3, 4); + + s2.x = _mm256_set_epi64x (88, 44, 3, 220000); + + u.x = _mm256_cmpgt_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c new file mode 100644 index 0000000000..f2ed472983 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c new file mode 100644 index 0000000000..490878f8bc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 76, -100, -34, -78, -31000); + + s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + 30, 90, -80, -40, -100, -15); + + u.x = _mm256_cmpgt_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c new file mode 100644 index 0000000000..518ff333bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vperm2i128\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permute2x128_si256 (x, x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c new file mode 100644 index 0000000000..96f32b8f05 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +#define MASK 0xf1 + +static void +init_perm2i128 (unsigned long long *src1, unsigned long long *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed) * seed * sign; + sign = -sign; + } +} + +static void +calc_perm2i128 (unsigned long long *src1, + unsigned long long *src2, + unsigned int mask, unsigned long long *dst) +{ + int i, temp; + + temp = mask & 3; + + switch (temp) + { + case 0: + memcpy (dst, src1, 16); + case 1: + memcpy (dst, src1 + 2, 16); + case 2: + memcpy (dst, src2, 16); + case 3: + memcpy (dst, src1 + 2, 16); + } + + temp = (mask >> 4) & 3; + + switch (temp) + { + case 0: + memcpy (dst + 2, src1, 16); + case 1: + memcpy (dst + 2, src1 + 2, 16); + case 2: + memcpy (dst + 2, src2, 16); + case 3: + memcpy (dst + 2, src1 + 2, 16); + } + + if ((mask >> 3) & 1) + memset (dst, 0, 16); + + if ((mask >> 7) & 1) + memset (dst + 2, 0, 16); +} + +static void +avx2_test (void) +{ + union256i_q src1, src2, dst; + unsigned long long dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_perm2i128 (src1.a, src2.a, i); + + dst.x = _mm256_permute2x128_si256 (src1.x, src2.x, MASK); + calc_perm2i128 (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c new file mode 100644 index 0000000000..939f338953 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permutevar8x32_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c new file mode 100644 index 0000000000..a663337e9a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_permd (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_permd (int *src1, int *src2, int *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + { + temp = src2[i]; + dst[i] = src1[temp & 7]; + } +} + +static void +avx2_test (void) +{ + union256i_d src1, src2, dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permd (src1.a, src2.a, i); + + dst.x = _mm256_permutevar8x32_epi32 (src1.x, src2.x); + calc_permd (src1.a, src2.a, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c new file mode 100644 index 0000000000..62ca67cc41 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermpd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m256d x; + +void extern +avx2_test (void) +{ + x = _mm256_permute4x64_pd (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c new file mode 100644 index 0000000000..1097e5cd18 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define MASK 0x1a + +#define NUM 10 + +static void +init_permpd (double *src1, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_permpd (double *src1, int mask, double *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 4; i++) + { + temp = mask >> (i * 2); + dst[i] = src1[temp & 3]; + } +} + +static void +avx2_test (void) +{ + union256d src1, dst; + double dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permpd (src1.a, i); + + dst.x = _mm256_permute4x64_pd (src1.x, MASK); + calc_permpd (src1.a, MASK, dst_ref); + + if (check_union256d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c new file mode 100644 index 0000000000..bf436599d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermps\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +__m256i y; + +void extern +avx2_test (void) +{ + x = _mm256_permutevar8x32_ps (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c new file mode 100644 index 0000000000..4190189a89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_permps (float *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_permps (float *src1, int *src2, float *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + { + temp = src2[i]; + dst[i] = src1[temp & 7]; + } +} + +static void +avx2_test (void) +{ + union256 src1, dst; + union256i_d src2; + float dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permps (src1.a, src2.a, i); + + dst.x = _mm256_permutevar8x32_ps (src1.x, src2.x); + calc_permps (src1.a, src2.a, dst_ref); + + if (check_union256 (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c new file mode 100644 index 0000000000..533af89a95 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permute4x64_epi64 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c new file mode 100644 index 0000000000..2d8c344028 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +#define MASK 0xf1 + +static void +init_permq (unsigned long long *src1, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_permq (unsigned long long *src1, unsigned int mask, + unsigned long long *dst) +{ + int i, temp; + + for (i = 0; i < 4; i++) + { + temp = (mask >> (2 * i)) & 3; + dst[i] = src1[temp]; + } +} + +static void +avx2_test (void) +{ + union256i_q src1, dst; + unsigned long long dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permq (src1.a, i); + + dst.x = _mm256_permute4x64_epi64 (src1.x, MASK); + calc_permq (src1.a, MASK, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c new file mode 100644 index 0000000000..2fb0fd7f2f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadd_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c new file mode 100644 index 0000000000..0d686cb4f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phaddd256 (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i + 0] = i1[2 * i] + i1[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] + i2[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 4] = i1[2 * i + 4] + i1[2 * i + 5]; + + for (i = 0; i < 2; i++) + r[i + 6] = i2[2 * i + 4] + i2[2 * i + 5]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadd_epi32 (s1.x, s2.x); + + compute_phaddd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c new file mode 100644 index 0000000000..dbedf69dea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadds_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c new file mode 100644 index 0000000000..371984776f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_phaddsw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = signed_saturate_to_word (i1[2 * i] + i1[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 4] = signed_saturate_to_word (i2[2 * i] + i2[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] + i1[2 * i + 9]); + + for (i = 0; i < 4; i++) + r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] + i2[2 * i + 9]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadds_epi16 (s1.x, s2.x); + + compute_phaddsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c new file mode 100644 index 0000000000..c0bdac2f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadd_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c new file mode 100644 index 0000000000..8811e99d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phaddw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = i1[2 * i] + i1[2 * i + 1]; + + for (i = 0; i < 4; i++) + r[i + 4] = i2[2 * i] + i2[2 * i + 1]; + + for (i = 0; i < 4; i++) + r[i + 8] = i1[2 * i + 8] + i1[2 * i + 9]; + + for (i = 0; i < 4; i++) + r[i + 12] = i2[2 * i + 8] + i2[2 * i + 9]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadd_epi16 (s1.x, s2.x); + + compute_phaddw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c new file mode 100644 index 0000000000..d4ede9db01 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsub_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c new file mode 100644 index 0000000000..ba49367922 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phsubd256 (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i + 0] = i1[2 * i] - i1[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] - i2[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 4] = i1[2 * i + 4] - i1[2 * i + 5]; + + for (i = 0; i < 2; i++) + r[i + 6] = i2[2 * i + 4] - i2[2 * i + 5]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hsub_epi32 (s1.x, s2.x); + + compute_phsubd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c new file mode 100644 index 0000000000..d941f44b3f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsubs_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c new file mode 100644 index 0000000000..1ed0990907 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_phsubsw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = signed_saturate_to_word (i1[2 * i] - i1[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 4] = signed_saturate_to_word (i2[2 * i] - i2[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] - i1[2 * i + 9]); + + for (i = 0; i < 4; i++) + r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] - i2[2 * i + 9]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hsubs_epi16 (s1.x, s2.x); + + compute_phsubsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c new file mode 100644 index 0000000000..f336fad487 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsub_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c new file mode 100644 index 0000000000..6ab19103d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaddubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_maddubs_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c new file mode 100644 index 0000000000..5761d8f441 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c @@ -0,0 +1,59 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_pmaddubsw256 (short *i1, short *i2, short *r) +{ + unsigned char *ub1 = (unsigned char *) i1; + char *sb2 = (char *) i2; + short *sout = (short *) r; + int t0; + int i; + + for (i = 0; i < 16; i++) + { + t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] + + (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]); + sout[i] = signed_saturate_to_word (t0); + } +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_maddubs_epi16 (s1.x, s2.x); + + compute_pmaddubsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c new file mode 100644 index 0000000000..97de707ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaddwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_madd_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c new file mode 100644 index 0000000000..d539d39433 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_pmaddwd256 (short *i1, short *i2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = ((int) i1[2 * i] * (int) i2[2 * i] + + (int) i1[2 * i + 1] * (int) i2[2 * i + 1]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2; + union256i_d res; + int res_ref[8]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_madd_epi16 (s1.x, s2.x); + + compute_pmaddwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c new file mode 100644 index 0000000000..917de5136d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *y; + +void extern +avx2_test (void) +{ + x = _mm_maskload_epi32 (y, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c new file mode 100644 index 0000000000..9bc3f31bed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + int s[4] = { 1, 2, 3, 4 }; + union128i_d u, mask; + int e[4] = { 0 }; + + mask.x = _mm_loadu_si128 ((__m128i *) m); + u.x = _mm_maskload_epi32 (s, mask.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c new file mode 100644 index 0000000000..aa9438c93a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *y; + +void extern +avx2_test (void) +{ + x = _mm256_maskload_epi32 (y, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c new file mode 100644 index 0000000000..b5a82bddde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[8] = + { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5), +mask_v (6), mask_v (7) }; + int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + union256i_d u, mask; + int e[8] = { 0 }; + + mask.x = _mm256_loadu_si256 ((__m256i *) m); + u.x = _mm256_maskload_epi32 (s, mask.x); + + for (i = 0; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c new file mode 100644 index 0000000000..24768b8f87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *y; + +void extern +avx2_test (void) +{ + x = _mm_maskload_epi64 (y, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c new file mode 100644 index 0000000000..ca7abadcac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[2] = { mask_v (0), mask_v (1) }; + long long s[2] = { 1, 2 }; + union128i_q u, mask; + long long e[2] = { 0 }; + + mask.x = _mm_loadu_si128 ((__m128i *) m); + u.x = _mm_maskload_epi64 (s, mask.x); + + for (i = 0; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c new file mode 100644 index 0000000000..9b824eb576 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *y; + +void extern +avx2_test (void) +{ + x = _mm256_maskload_epi64 (y, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c new file mode 100644 index 0000000000..c74d15304e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + long long s[4] = { 1, 2, 3, 4 }; + union256i_q u, mask; + long long e[4] = { 0 }; + + mask.x = _mm256_loadu_si256 ((__m256i *) m); + u.x = _mm256_maskload_epi64 (s, mask.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c new file mode 100644 index 0000000000..0731d1ae16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *y; + +void extern +avx2_test (void) +{ + _mm_maskstore_epi32 (y, x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c new file mode 100644 index 0000000000..89b54f5941 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + int s[4] = { 1, 2, 3, 4 }; + union128i_d src, mask; + int e[4] = { 0 }; + int d[4] = { 0 }; + + src.x = _mm_loadu_si128 ((__m128i *) s); + mask.x = _mm_loadu_si128 ((__m128i *) m); + _mm_maskstore_epi32 (d, mask.x, src.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVi (d, e, 4)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c new file mode 100644 index 0000000000..4e2944de07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *y; + +void extern +avx2_test (void) +{ + _mm256_maskstore_epi32 (y, x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c new file mode 100644 index 0000000000..7b66a08977 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[8] = + { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5), +mask_v (6), mask_v (7) }; + int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + union256i_d src, mask; + int e[8] = { 0 }; + int d[8] = { 0 }; + + src.x = _mm256_loadu_si256 ((__m256i *) s); + mask.x = _mm256_loadu_si256 ((__m256i *) m); + _mm256_maskstore_epi32 (d, mask.x, src.x); + + for (i = 0; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c new file mode 100644 index 0000000000..f1075bf253 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *y; + +void extern +avx2_test (void) +{ + _mm_maskstore_epi64 (y, x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c new file mode 100644 index 0000000000..bd9e394707 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[2] = { mask_v (0), mask_v (1) }; + long long s[2] = { 1, 2 }; + long long e[2] = { 0 }; + long long d[2] = { 0 }; + union128i_q src, mask; + + src.x = _mm_loadu_si128 ((__m128i *) s); + mask.x = _mm_loadu_si128 ((__m128i *) m); + _mm_maskstore_epi64 (d, mask.x, src.x); + + for (i = 0; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVl (d, e, 2)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c new file mode 100644 index 0000000000..0d0520b81a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *y; + +void extern +avx2_test (void) +{ + _mm256_maskstore_epi64 (y, x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c new file mode 100644 index 0000000000..091791ac63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + long long s[4] = { 1, 2, 3, 4 }; + long long e[4] = { 0 }; + long long d[4] = { 0 }; + union256i_q src, mask; + + src.x = _mm256_loadu_si256 ((__m256i *) s); + mask.x = _mm256_loadu_si256 ((__m256i *) m); + _mm256_maskstore_epi64 (d, mask.x, src.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVl (d, e, 4)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c new file mode 100644 index 0000000000..2cbbcff9dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c new file mode 100644 index 0000000000..4b1b1dd2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 20) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi8 (s1.x, s2.x); + + compute_pmaxsb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c new file mode 100644 index 0000000000..1b227e6145 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c new file mode 100644 index 0000000000..e488a6ea15 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi32 (s1.x, s2.x); + + compute_pmaxsd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c new file mode 100644 index 0000000000..8fb2d29cd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c new file mode 100644 index 0000000000..6ada1cd23c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi16 (s1.x, s2.x); + + compute_pmaxsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c new file mode 100644 index 0000000000..6d0fe9828d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c new file mode 100644 index 0000000000..f0654e0327 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxub256 (unsigned char *s1, unsigned char *s2, unsigned char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + unsigned char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 200; + } + + res.x = _mm256_max_epu8 (s1.x, s2.x); + + compute_pmaxub256 ((unsigned char *) s1.a, + (unsigned char *) s2.a, (unsigned char *) res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c new file mode 100644 index 0000000000..5784148c70 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c new file mode 100644 index 0000000000..a61314d193 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxud256 (unsigned int *s1, unsigned int *s2, unsigned int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + unsigned int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_max_epu32 (s1.x, s2.x); + + compute_pmaxud256 ((unsigned *) s1.a, (unsigned *) s2.a, + (unsigned *) res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c new file mode 100644 index 0000000000..dbadc254c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c new file mode 100644 index 0000000000..2631f0cf08 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_max_epu16 (s1.x, s2.x); + + compute_pmaxuw256 ((unsigned short *) s1.a, + (unsigned short *) s2.a, (unsigned short *) res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c new file mode 100644 index 0000000000..35cbdb3128 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c new file mode 100644 index 0000000000..2dc5b109f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 20) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi8 (s1.x, s2.x); + + compute_pminsb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c new file mode 100644 index 0000000000..97c99f24c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c new file mode 100644 index 0000000000..e2c69e7e87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi32 (s1.x, s2.x); + + compute_pminsd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c new file mode 100644 index 0000000000..43f5c72ac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c new file mode 100644 index 0000000000..05be8ce905 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi16 (s1.x, s2.x); + + compute_pminsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c new file mode 100644 index 0000000000..44663e8ad1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c new file mode 100644 index 0000000000..16c5f76286 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminub256 (unsigned char *s1, unsigned char *s2, unsigned char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + unsigned char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 200; + } + + res.x = _mm256_min_epu8 (s1.x, s2.x); + + compute_pminub256 ((unsigned char *) s1.a, + (unsigned char *) s2.a, (unsigned char *) res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c new file mode 100644 index 0000000000..d6acb8b474 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c new file mode 100644 index 0000000000..97ff742266 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminud256 (unsigned int *s1, unsigned int *s2, unsigned int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + unsigned int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_min_epu32 (s1.x, s2.x); + + compute_pminud256 ((unsigned *) s1.a, (unsigned *) s2.a, + (unsigned *) res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c new file mode 100644 index 0000000000..c018a49c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c new file mode 100644 index 0000000000..7de87d00da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_min_epu16 (s1.x, s2.x); + + compute_pminuw256 ((unsigned short *) s1.a, + (unsigned short *) s2.a, (unsigned short *) res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c new file mode 100644 index 0000000000..1a37b1bef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int res; + +void extern +avx2_test (void) +{ + res = _mm256_movemask_epi8 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c new file mode 100644 index 0000000000..e5a9c10e14 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b s; + int res, res_ref; + int i, e = 0; + + s.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 15, 98, 25, 98, 7, 1, 2, 3, 4, 10, 20, 30, 90, + -80, -40, -100, -15, 98, 25, 98, 7); + + res = _mm256_movemask_epi8 (s.x); + + for (i = 0; i < 32; i++) + if (s.a[i] & (1 << 7)) + res_ref = res_ref | (1 << i); + + if (res != res_ref) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c new file mode 100644 index 0000000000..d438248b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c new file mode 100644 index 0000000000..3b641b0ca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbd (char *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi32 (s.x); + + compute_movsxbd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c new file mode 100644 index 0000000000..12c817ffb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c new file mode 100644 index 0000000000..23aae5bdb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbq (char *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi64 (s.x); + + compute_movsxbq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c new file mode 100644 index 0000000000..bf98e3154c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi16 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c new file mode 100644 index 0000000000..d1c02ea863 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbw (char *s, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_w res; + short res_ref[16]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi16 (s.x); + + compute_movsxbw (s.a, res_ref); + + if (check_union256i_w (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c new file mode 100644 index 0000000000..9c72c41e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi32_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c new file mode 100644 index 0000000000..7e87f316fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxdq (int *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_d s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + + res.x = _mm256_cvtepi32_epi64 (s.x); + + compute_movsxdq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c new file mode 100644 index 0000000000..39627ced8c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi16_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c new file mode 100644 index 0000000000..5a95e376e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxwd (short *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi16 (1, -2, 3, 4, 200, 5000, -6, 8); + + res.x = _mm256_cvtepi16_epi32 (s.x); + + compute_movsxwd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c new file mode 100644 index 0000000000..9fa613b342 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi16_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c new file mode 100644 index 0000000000..f096de5776 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxwq (short *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, -200, 50, 6, 8); + + res.x = _mm256_cvtepi16_epi64 (s.x); + + compute_movsxwq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c new file mode 100644 index 0000000000..bde8c134dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c new file mode 100644 index 0000000000..7a212c89dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbd (unsigned char *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi32 (s.x); + + compute_movzxbd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c new file mode 100644 index 0000000000..da8e0584ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c new file mode 100644 index 0000000000..c09c21d67e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbq (unsigned char *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 150, 6, 8, 1, 2, 3, 4, 20, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi64 (s.x); + + compute_movzxbq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c new file mode 100644 index 0000000000..f7a926de10 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi16 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c new file mode 100644 index 0000000000..5ef4b15357 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbw (unsigned char *s, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_w res; + short res_ref[16]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 200, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi16 (s.x); + + compute_movzxbw (s.a, res_ref); + + if (check_union256i_w (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c new file mode 100644 index 0000000000..3f0c400c3a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu32_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c new file mode 100644 index 0000000000..20986b6448 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxdq (unsigned *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_d s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi32 (1, 2, 3, 4); + + res.x = _mm256_cvtepu32_epi64 (s.x); + + compute_movzxdq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c new file mode 100644 index 0000000000..902cd6df87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu16_epi32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c new file mode 100644 index 0000000000..b4d2b2da68 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxwd (unsigned short *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8); + + res.x = _mm256_cvtepu16_epi32 (s.x); + + compute_movzxwd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c new file mode 100644 index 0000000000..4eaa65aebb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu16_epi64 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c new file mode 100644 index 0000000000..8a9250aeca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxwq (unsigned short *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8); + + res.x = _mm256_cvtepu16_epi64 (s.x); + + compute_movzxwq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c new file mode 100644 index 0000000000..e1c232da32 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmuldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mul_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c new file mode 100644 index 0000000000..b67f25fc4c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmuldq256 (int *s1, int *s2, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i * 2] * s2[i * 2]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2; + union256i_q res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mul_epi32 (s1.x, s2.x); + compute_pmuldq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c new file mode 100644 index 0000000000..7c6692b81d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhrsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhrs_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c new file mode 100644 index 0000000000..c6d8742224 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhrsw256 (short *s1, short *s2, short *r) +{ + int i; + int t0; + + for (i = 0; i < 16; i++) + { + t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1; + r[i] = (short) (t0 >> 1); + } +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mulhrs_epi16 (s1.x, s2.x); + + compute_pmulhrsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c new file mode 100644 index 0000000000..d9a2fa7cee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhi_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c new file mode 100644 index 0000000000..734b20cfb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (s1[i] * s2[i]) >> 16; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j; + s2.a[j] = j + 20; + } + + res.x = _mm256_mulhi_epu16 (s1.x, s2.x); + + compute_pmulhuw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c new file mode 100644 index 0000000000..a626f19199 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhi_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c new file mode 100644 index 0000000000..ea0bde2bea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (s1[i] * s2[i]) >> 16; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mulhi_epi16 (s1.x, s2.x); + + compute_pmulhw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c new file mode 100644 index 0000000000..4e2e5250fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mullo_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c new file mode 100644 index 0000000000..74443a24d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulld256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = (int) ((long long int) s1[i] * (long long int) s2[i]); +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mullo_epi32 (s1.x, s2.x); + + compute_pmulld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c new file mode 100644 index 0000000000..b2d539ba49 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) * (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c new file mode 100644 index 0000000000..61cc758840 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mullo_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c new file mode 100644 index 0000000000..81d05ccab2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmullw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (short) ((int) s1[i] * (int) s2[i]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mullo_epi16 (s1.x, s2.x); + + compute_pmullw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c new file mode 100644 index 0000000000..46d173fc37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) * (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c new file mode 100644 index 0000000000..4fa1bf155a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmuludq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mul_epu32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c new file mode 100644 index 0000000000..619b7358e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmuludq256 (unsigned int *s1, unsigned int *s2, unsigned long long *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i * 2] * s2[i * 2]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2; + union256i_q res; + unsigned long long res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j; + s2.a[j] = j + 20; + } + + res.x = _mm256_mul_epu32 (s1.x, s2.x); + + compute_pmuludq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h b/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h new file mode 100644 index 0000000000..143b54dae0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h @@ -0,0 +1,53 @@ +#include "avx2-check.h" + +#define SIZE 256 + +TYPE a[SIZE]; +TYPE b[SIZE]; +TYPE c[SIZE]; +volatile TYPE c_ref[SIZE]; + +__attribute__ ((__noinline__)) +void +gen_pop () +{ + int i; + for (i = 0; i < SIZE; ++i) +#ifdef BIN_OP + c[i] = BIN_OP (a[i], b[i]); +#else /* Must be UN_OP */ + c[i] = UN_OP (a[i]); +#endif /* BIN_OP */ +} + +void +check_pop () +{ + int i; + for (i = 0; i < SIZE; ++i) +#ifdef BIN_OP + c_ref[i] = BIN_OP (a[i], b[i]); +#else /* Must be UN_OP */ + c_ref[i] = UN_OP (a[i]); +#endif /* BIN_OP */ +} + +void static +avx2_test (void) +{ + int i, j; + for (i = 0; i < 4; ++i ) + { + for ( j = 0; j < SIZE; ++j ) + { + a[i] = i * i + i; + b[i] = i * i * i; + } + + gen_pop (); + check_pop (); + + if (memcmp (c, c_ref, SIZE * sizeof (TYPE))) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c new file mode 100644 index 0000000000..2e0f46d213 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_or_si256 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c new file mode 100644 index 0000000000..fd5da8335c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +static void +compute_por256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i] | s2[i]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_or_si256 (s1.x, s2.x); + compute_por256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c new file mode 100644 index 0000000000..1cd56661cd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sad_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c new file mode 100644 index 0000000000..392613659a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_sadbw256 (unsigned char *s1, unsigned char *s2, unsigned short *r) +{ + int i; + unsigned char tmp[32]; + + for (i = 0; i < 32; i++) + tmp[i] = s1[i] > s2[i] ? s1[i] - s2[i] : s2[i] - s1[i]; + + memset (r, 0, 32); + + for (i = 0; i < 8; i++) + r[0] += tmp[i]; + + for (i = 8; i < 16; i++) + r[4] += tmp[i]; + + for (i = 16; i < 24; i++) + r[8] += tmp[i]; + + for (i = 24; i < 32; i++) + r[12] += tmp[i]; +} + +void static +avx2_test (void) +{ + union256i_b s1, s2; + union256i_w res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sad_epu8 (s1.x, s2.x);; + compute_sadbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c new file mode 100644 index 0000000000..b94563d0ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shuffle_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c new file mode 100644 index 0000000000..ee91493950 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_pshufb256 (char *s1, char *s2, char *r) +{ + int i; + char select; + + for (i = 0; i < 16; i++) + { + select = s2[i]; + if (select & 0x80) + r[i] = 0; + else + r[i] = s1[select & 0xf]; + + select = s2[i + 16]; + if (select & 0x80) + r[i + 16] = 0; + else + r[i + 16] = s1[16 + (select & 0xf)]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_shuffle_epi8 (s1.x, s2.x); + compute_pshufb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c new file mode 100644 index 0000000000..cdfde4654f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shuffle_epi32 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c new file mode 100644 index 0000000000..e799ed7893 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshufd256 (int *s1, unsigned char imm, int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[((N & (0x3 << (2 * i))) >> (2 * i))]; + + for (i = 0; i < 4; i++) + r[i + 4] = s1[((N & (0x3 << (2 * i))) >> (2 * i)) + 4]; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shuffle_epi32 (s1.x, N); + compute_pshufd256 (s1.a, N, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c new file mode 100644 index 0000000000..fa3f809daa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shufflehi_epi16 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c new file mode 100644 index 0000000000..a27ed03b3b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshuflw256 (short *s1, unsigned char imm, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[i] = s1[(imm >> (2 * i)) & 3]; + r[i + 8] = s1[((imm >> (2 * i)) & 3) + 8]; + } + + for (i = 4; i < 8; i++) + { + r[i] = s1[i]; + r[i + 8] = s1[i + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 1; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shufflelo_epi16 (s1.x, N); + compute_pshuflw256 (s1.a, N, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c new file mode 100644 index 0000000000..24e75625ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshuflw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shufflelo_epi16 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c new file mode 100644 index 0000000000..144197348d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshufhw256 (short *s1, unsigned char imm, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[i] = s1[i]; + r[i + 8] = s1[i + 8]; + } + + for (i = 4; i < 8; i++) + { + r[i] = s1[((imm >> (2 * (i - 4))) & 3) + 4]; + r[i + 8] = s1[((imm >> (2 * (i - 4))) & 3) + 12]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 1; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shufflehi_epi16 (s1.x, N); + compute_pshufhw256 (s1.a, N, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c new file mode 100644 index 0000000000..6cd7ca6e85 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c new file mode 100644 index 0000000000..5e3d819fea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi8 (s1.x, s2.x); + compute_psignb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c new file mode 100644 index 0000000000..dab81a3b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c new file mode 100644 index 0000000000..14e61b014e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi32 (s1.x, s2.x); + compute_psignd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c new file mode 100644 index 0000000000..cae04c081b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c new file mode 100644 index 0000000000..bb96a1d53d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignw256 (short int *s1, short int *s2, short int *r) +{ + int i; + + for (i = 0; i < 16; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short int res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi16 (s1.x, s2.x); + compute_psignw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c new file mode 100644 index 0000000000..5140d7ae07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi32 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c new file mode 100644 index 0000000000..84c68feb55 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_pslld256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] << count; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi32 (s1.x, s2.x); + + compute_pslld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c new file mode 100644 index 0000000000..9cea0f6756 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi32 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c new file mode 100644 index 0000000000..dfd7d9a038 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_pslldi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 8; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi32 (s1.x, N); + + compute_pslldi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c new file mode 100644 index 0000000000..5a85a7982a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpslldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +extern volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_si256 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c new file mode 100644 index 0000000000..7bfb5b185f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_pslldq256 (char *s1, char *r) +{ + int i; + + memset (r, 0, 32); + + for (i = 0; i < 16 - N; i++) + r[i + N] = s1[i]; + + for (i = 0; i < 16 - N; i++) + r[i + 16 + N] = s1[i + 16]; +} + + +void static +avx2_test (void) +{ + union256i_b s1, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_si256 (s1.x, N); + + compute_pslldq256 (s1.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c new file mode 100644 index 0000000000..53417a1ace --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi64 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c new file mode 100644 index 0000000000..c0ac89bfe0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] << count; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi64 (s1.x, s2.x); + + compute_psllq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c new file mode 100644 index 0000000000..2851be5e2a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi64 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c new file mode 100644 index 0000000000..9ef49bdb9c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psllqi256 (long long int *s1, long long int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_q s1, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi64 (s1.x, N); + + compute_psllqi256 (s1.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c new file mode 100644 index 0000000000..b57afc4af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_sllv_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c new file mode 100644 index 0000000000..5ab83ae20c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_sllv_epi32 (s1.x, s2.x); + + compute_psllvd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c new file mode 100644 index 0000000000..59063d5c44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sllv_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c new file mode 100644 index 0000000000..407a8f3c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1;; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_sllv_epi32 (s1.x, s2.x); + + compute_psllvd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c new file mode 100644 index 0000000000..245aa5508d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_sllv_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c new file mode 100644 index 0000000000..422ddf5bf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvq128 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 2; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union128i_q s1, s2, res; + long long int res_ref[2]; + int i, j, sign = 2; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_sllv_epi64 (s1.x, s2.x); + + compute_psllvq128 (s1.a, s2.a, res_ref); + + fail += check_union128i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c new file mode 100644 index 0000000000..caae3f2fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sllv_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c new file mode 100644 index 0000000000..c41597b16f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_sllv_epi64 (s1.x, s2.x); + + compute_psllvq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c new file mode 100644 index 0000000000..2fbc43f48b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi16 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c new file mode 100644 index 0000000000..1b26330ddb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllw256 (short *s1, long long int *s2, short *r) +{ + int i; + int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] << count; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi16 (s1.x, s2.x); + + compute_psllw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + + if (fail) + { + for (j = 0; j < 16; ++j) + printf ("%d <->%d\n", res.a[j], res_ref[j]); + abort (); + } + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c new file mode 100644 index 0000000000..10bd08c34b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi16 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c new file mode 100644 index 0000000000..f1d3e11090 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psllwi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi16 (s1.x, N); + + compute_psllwi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c new file mode 100644 index 0000000000..673398e3d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sra_epi32 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c new file mode 100644 index 0000000000..39a579e4f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrad256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> count; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sra_epi32 (s1.x, s2.x); + + compute_psrad256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c new file mode 100644 index 0000000000..97affb4bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c new file mode 100644 index 0000000000..f6bb71a57a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srai_epi32 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c new file mode 100644 index 0000000000..b9cfc7afa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psradi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> N; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_srai_epi16 (s1.x, N); + + compute_psradi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c new file mode 100644 index 0000000000..a20a8868ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srav_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c new file mode 100644 index 0000000000..8438d9a441 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psravd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] >> count; + } +} + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srav_epi32 (s1.x, s2.x); + + compute_psravd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c new file mode 100644 index 0000000000..6adf3049ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srav_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c new file mode 100644 index 0000000000..0be75205b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psravd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = s1[i] >> count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srav_epi32 (s1.x, s2.x); + + compute_psravd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c new file mode 100644 index 0000000000..2b1c3584bf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sra_epi16 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c new file mode 100644 index 0000000000..66fe8a95cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psraw256 (short *s1, long long int *s2, short *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> count; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sra_epi16 (s1.x, s2.x); + + compute_psraw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c new file mode 100644 index 0000000000..e7112565b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsraw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c new file mode 100644 index 0000000000..e8558c35da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srai_epi16 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c new file mode 100644 index 0000000000..c135833a46 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrawi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> N; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_srai_epi16 (s1.x, N); + + compute_psrawi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c new file mode 100644 index 0000000000..5c0605cdd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi32 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c new file mode 100644 index 0000000000..1fab08cd8b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrld256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi32 (s1.x, s2.x); + + compute_psrld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c new file mode 100644 index 0000000000..97affb4bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c new file mode 100644 index 0000000000..feac4c9200 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi32 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c new file mode 100644 index 0000000000..0f109feb38 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrldi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi32 (s1.x, N); + + compute_psrldi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c new file mode 100644 index 0000000000..dd804e04f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +extern volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_si256 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c new file mode 100644 index 0000000000..4c2850903f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrldq256 (char *s1, char *r) +{ + int i; + + memset (r, 0, 32); + + for (i = 0; i < 16 - N; i++) + r[i] = s1[i + N]; + + for (i = 0; i < 16 - N; i++) + r[i + 16] = s1[i + N + 16]; +} + + +void static +avx2_test (void) +{ + union256i_b s1, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_si256 (s1.x, N); + + compute_psrldq256 (s1.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c new file mode 100644 index 0000000000..c19d067a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi64 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c new file mode 100644 index 0000000000..e02da78f65 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi64 (s1.x, s2.x); + + compute_psrlq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c new file mode 100644 index 0000000000..3cab1dc0e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi64 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c new file mode 100644 index 0000000000..1aa23fedc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrlqi256 (long long int *s1, long long int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi64 (s1.x, N); + + compute_psrlqi256 (s1.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c new file mode 100644 index 0000000000..d4d0358429 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srlv_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c new file mode 100644 index 0000000000..c7674c02cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = ((unsigned) s1[i]) >> count; + } +} + + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srlv_epi32 (s1.x, s2.x); + + compute_psrlvd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c new file mode 100644 index 0000000000..ce76c8f80f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srlv_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c new file mode 100644 index 0000000000..e3c3c48415 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = ((unsigned) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srlv_epi32 (s1.x, s2.x); + + compute_psrlvd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c new file mode 100644 index 0000000000..64d7c28efe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srlv_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c new file mode 100644 index 0000000000..842559ff2d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvq128 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 2; ++i) + { + count = s2[i]; + r[i] = ((unsigned long long int) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union128i_q s1, s2, res; + long long int res_ref[2]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srlv_epi64 (s1.x, s2.x); + + compute_psrlvq128 (s1.a, s2.a, res_ref); + + fail += check_union128i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c new file mode 100644 index 0000000000..4e00736e81 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srlv_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c new file mode 100644 index 0000000000..e006d7c275 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = ((unsigned long long) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srlv_epi64 (s1.x, s2.x); + + compute_psrlvq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c new file mode 100644 index 0000000000..f69edbc698 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi16 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c new file mode 100644 index 0000000000..fb7526c0e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlw256 (short *s1, long long int *s2, short *r) +{ + int i; + int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi16 (s1.x, s2.x); + + compute_psrlw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + + if (fail) + { + for (j = 0; j < 16; ++j) + printf ("%d <->%d\n", res.a[j], res_ref[j]); + abort (); + } + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c new file mode 100644 index 0000000000..67f3afc413 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned short +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrlw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c new file mode 100644 index 0000000000..823d81eb42 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi16 (x, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c new file mode 100644 index 0000000000..9baf2dadca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrlwi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi16 (s1.x, N); + + compute_psrlwi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c new file mode 100644 index 0000000000..e5ccd6be8c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c new file mode 100644 index 0000000000..14da9e02c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + unsigned i; + + s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84, + 29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72, + 92, 9, 4, 23, 17, 99, 43, 72, 17); + + s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200, + 17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43, + 27, 112, 71, 50, 32, 72, 84, 17, 27, 96); + + u.x = _mm256_sub_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c new file mode 100644 index 0000000000..843128b4f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE char +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c new file mode 100644 index 0000000000..150f4cbcf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c new file mode 100644 index 0000000000..74a6fec01e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + unsigned i; + + s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4); + s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000); + + u.x = _mm256_sub_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c new file mode 100644 index 0000000000..f8f399f6b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c new file mode 100644 index 0000000000..9460b0d84a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c new file mode 100644 index 0000000000..aa869252ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q u, s1, s2; + long long e[4]; + unsigned i; + + s1.x = _mm256_set_epi64x (100, 74, 50000, 4); + s2.x = _mm256_set_epi64x (88, 44, 33, 220); + + u.x = _mm256_sub_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c new file mode 100644 index 0000000000..0a23a280e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE long long int +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c new file mode 100644 index 0000000000..ad1b986f76 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c new file mode 100644 index 0000000000..5f33f6b89d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_subs_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c new file mode 100644 index 0000000000..c02d275515 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c new file mode 100644 index 0000000000..2f2fc7d604 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, + -40, -100, -15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100, + -34, -78, -39, 6, 3, 4, 5, 119); + + u.x = _mm256_subs_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c new file mode 100644 index 0000000000..917ffa9a89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epu8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c new file mode 100644 index 0000000000..bffb5b6f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15, + 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76, + 200, 34, 78, 39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39, + 6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90, + 80, 40, 100, 15, 98, 25, 98, 7); + + u.x = _mm256_subs_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = (unsigned char) s1.a[i] - (unsigned char) s2.a[i]; + + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c new file mode 100644 index 0000000000..bc0e3df63c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epu16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c new file mode 100644 index 0000000000..7fd16400a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, + 65531, 40, 100, 15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 219); + + u.x = _mm256_subs_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = (unsigned short) s1.a[i] - (unsigned short) s2.a[i]; + + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c new file mode 100644 index 0000000000..1cb90b5a8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c new file mode 100644 index 0000000000..2c7c9bd113 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c new file mode 100644 index 0000000000..3d3f849340 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhbw256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 8; i++) + { + r[2 * i] = s1[i + 8]; + r[2 * i + 1] = s2[i + 8]; + + r[2 * i + 16] = s1[i + 24]; + r[2 * i + 16 + 1] = s2[i + 24]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi8 (s1.x, s2.x); + + compute_punpckhbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c new file mode 100644 index 0000000000..e1e65eae39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c new file mode 100644 index 0000000000..34499f01aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhwd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + { + r[2 * i] = s1[i + 2]; + r[2 * i + 1] = s2[i + 2]; + + r[2 * i + 4] = s1[i + 2 + 4]; + r[2 * i + 4 + 1] = s2[i + 2 + 4]; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi32 (s1.x, s2.x); + + compute_punpckhwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c new file mode 100644 index 0000000000..a8a5f37ad4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c new file mode 100644 index 0000000000..4668571c48 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhqdq256 (long long int *s1, long long int *s2, long long int *r) +{ + r[0] = s1[1]; + r[1] = s2[1]; + r[2] = s1[3]; + r[3] = s2[3]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi64 (s1.x, s2.x); + + compute_punpckhqdq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c new file mode 100644 index 0000000000..1ab034407d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c new file mode 100644 index 0000000000..59c4ed89c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhwd256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[2 * i] = s1[i + 4]; + r[2 * i + 1] = s2[i + 4]; + + r[2 * i + 8] = s1[i + 4 + 8]; + r[2 * i + 8 + 1] = s2[i + 4 + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi16 (s1.x, s2.x); + + compute_punpckhwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c new file mode 100644 index 0000000000..45db9a41e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi8 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c new file mode 100644 index 0000000000..49e41212f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklbw256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 8; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 16] = s1[i + 16]; + r[2 * i + 16 + 1] = s2[i + 16]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi8 (s1.x, s2.x); + + compute_punpcklbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c new file mode 100644 index 0000000000..aff815b295 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi32 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c new file mode 100644 index 0000000000..aba5e8092e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklwd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 4] = s1[i + 4]; + r[2 * i + 4 + 1] = s2[i + 4]; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi32 (s1.x, s2.x); + + compute_punpcklwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c new file mode 100644 index 0000000000..e8dd06da8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi64 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c new file mode 100644 index 0000000000..1c6db718a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklqdq256 (long long int *s1, long long int *s2, long long int *r) +{ + r[0] = s1[0]; + r[1] = s2[0]; + r[2] = s1[2]; + r[3] = s2[2]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi64 (s1.x, s2.x); + + compute_punpcklqdq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c new file mode 100644 index 0000000000..6bcdf9bf94 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi16 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c new file mode 100644 index 0000000000..9f6f9c0d66 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklwd256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 8] = s1[i + 8]; + r[2 * i + 8 + 1] = s2[i + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi16 (s1.x, s2.x); + + compute_punpcklwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c new file mode 100644 index 0000000000..cfd43b0fc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpxor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_xor_si256 (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c b/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c new file mode 100644 index 0000000000..be32644982 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_xor_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = source1[i] ^ source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c b/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c new file mode 100644 index 0000000000..15f20c8365 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "xop-vshift-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c index 023e859b6c..e7eef6d7a9 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler-not "avx_loadups256" } } */ +/* { dg-final { scan-assembler "sse_loadups" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c index 8394e27197..3f4fbf7647 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movdqu/1" } } */ -/* { dg-final { scan-assembler "vinsertf128" } } */ +/* { dg-final { scan-assembler-not "avx_loaddqu256" } } */ +/* { dg-final { scan-assembler "sse2_loaddqu" } } */ +/* { dg-final { scan-assembler "vinsert.128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c index ec7d59d53c..b0e0e79bdd 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mtune=generic" } */ #define N 1024 @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movupd/1" } } */ +/* { dg-final { scan-assembler-not "avx_loadupd256" } } */ +/* { dg-final { scan-assembler "sse2_loadupd" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c index 0d3ef33312..b3927be70a 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c @@ -14,6 +14,6 @@ avx_test (void) b[i] = a[i+3] * 2; } -/* { dg-final { scan-assembler "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler "avx_loadups256" } } */ +/* { dg-final { scan-assembler-not "sse_loadups" } } */ /* { dg-final { scan-assembler-not "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c index 99db55c9d0..1a53ba14a0 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/2" } } */ -/* { dg-final { scan-assembler "movups.*\\*avx_movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler-not "avx_storeups256" } } */ +/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c index 38ee9e2a45..e98d1b684d 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/2" } } */ -/* { dg-final { scan-assembler "movdqu.*\\*avx_movv16qi_internal/3" } } */ -/* { dg-final { scan-assembler "vextractf128" } } */ +/* { dg-final { scan-assembler-not "avx_storedqu256" } } */ +/* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */ +/* { dg-final { scan-assembler "vextract.128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c index eaab6fd775..26c993be7e 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mtune=generic" } */ #define N 1024 @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/2" } } */ -/* { dg-final { scan-assembler "movupd.*\\*avx_movv2df_internal/3" } } */ +/* { dg-final { scan-assembler-not "avx_storeupd256" } } */ +/* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c index 96cca66ae9..6d734faa25 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c @@ -14,7 +14,7 @@ avx_test (void) b[i+3] = a[i] * c[i]; } -/* { dg-final { scan-assembler "\\*avx_movups256/2" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/2" } } */ +/* { dg-final { scan-assembler "avx_storeups256" } } */ +/* { dg-final { scan-assembler-not "sse_storeups" } } */ /* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler-not "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avxfp-1.c b/gcc/testsuite/gcc.target/i386/avxfp-1.c new file mode 100644 index 0000000000..70bc8f1edb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxfp-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ +/* { dg-final { scan-assembler "vmaxsd" } } */ +/* { dg-final { scan-assembler "vminsd" } } */ +double x; +t() +{ + x=x>5?x:5; +} + +double x; +q() +{ + x=x<5?x:5; +} diff --git a/gcc/testsuite/gcc.target/i386/avxfp-2.c b/gcc/testsuite/gcc.target/i386/avxfp-2.c new file mode 100644 index 0000000000..c34a1bd7c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxfp-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ +/* { dg-final { scan-assembler "vmaxsd" } } */ +/* { dg-final { scan-assembler "vminsd" } } */ +double x; +q() +{ + x=x<5?5:x; +} + +double x; +q1() +{ + x=x>5?5:x; +} diff --git a/gcc/testsuite/gcc.target/i386/bitfield1.c b/gcc/testsuite/gcc.target/i386/bitfield1.c index 1590396c2f..00b7bfd716 100644 --- a/gcc/testsuite/gcc.target/i386/bitfield1.c +++ b/gcc/testsuite/gcc.target/i386/bitfield1.c @@ -1,6 +1,6 @@ // Test for bitfield alignment in structs on IA-32 // { dg-do run } -// { dg-require-effective-target ilp32 } +// { dg-require-effective-target ia32 } // { dg-options "-O2" } // { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw*} } diff --git a/gcc/testsuite/gcc.target/i386/bitfield2.c b/gcc/testsuite/gcc.target/i386/bitfield2.c index d665fcb134..e400598920 100644 --- a/gcc/testsuite/gcc.target/i386/bitfield2.c +++ b/gcc/testsuite/gcc.target/i386/bitfield2.c @@ -1,6 +1,6 @@ // Test for bitfield alignment in structs on IA-32 // { dg-do run } -// { dg-require-effective-target ilp32 } +// { dg-require-effective-target ia32 } // { dg-options "-O2" } // { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw* } } diff --git a/gcc/testsuite/gcc.target/i386/bitfield3.c b/gcc/testsuite/gcc.target/i386/bitfield3.c index 139f4d4616..1a161597cf 100644 --- a/gcc/testsuite/gcc.target/i386/bitfield3.c +++ b/gcc/testsuite/gcc.target/i386/bitfield3.c @@ -1,7 +1,8 @@ // Test for bitfield alignment in structs on IA-32 // { dg-do run } // { dg-options "-O2" } -// { dg-options "-mno-align-double -mno-ms-bitfields" { target *-*-interix* } } +// { dg-additional-options "-mno-align-double -mno-ms-bitfields" { target *-*-interix* } } +// { dg-additional-options "-mno-ms-bitfields" { target *-*-mingw* } } extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/bmi-2.c b/gcc/testsuite/gcc.target/i386/bmi-2.c index 4f8c14f3a4..56f73876d0 100644 --- a/gcc/testsuite/gcc.target/i386/bmi-2.c +++ b/gcc/testsuite/gcc.target/i386/bmi-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mbmi " } */ /* { dg-final { scan-assembler "andn\[^\\n]*(%|)rax" } } */ /* { dg-final { scan-assembler "bextr\[^\\n]*(%|)rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-5.c b/gcc/testsuite/gcc.target/i386/bmi-5.c index 906bf217cc..546a593c8f 100644 --- a/gcc/testsuite/gcc.target/i386/bmi-5.c +++ b/gcc/testsuite/gcc.target/i386/bmi-5.c @@ -1,5 +1,4 @@ -/* { dg-do link } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do link { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mbmi" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-1.c b/gcc/testsuite/gcc.target/i386/bmi-andn-1.c new file mode 100644 index 0000000000..bf0685ad38 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-andn-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_andn_u64 (long long src1, + long long src2, + long long dummy) +{ + return (~src1 + dummy) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_andn_u64 (src, src+i, 0); + res = __andn_u64 (src, src+i); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c b/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c new file mode 100644 index 0000000000..a7ee07653c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-andn-1.c" + +/* { dg-final { scan-assembler-times "bmi_andn_di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-2.c b/gcc/testsuite/gcc.target/i386/bmi-andn-2.c new file mode 100644 index 0000000000..bb998f3af2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-andn-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_andn_u32 (int src1, int src2, int dummy) +{ + return (~src1+dummy) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_andn_u32 (src, src+i, 0); + res = __andn_u32 (src, src+i); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c b/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c new file mode 100644 index 0000000000..72fe026392 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-andn-2.c" + +/* { dg-final { scan-assembler-times "bmi_andn_si" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c b/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c new file mode 100644 index 0000000000..4abe63e546 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c @@ -0,0 +1,49 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_bextr_u64 (unsigned long long src1, + unsigned long long src2) +{ + long long res = 0; + unsigned char start = (src2 & 0xff); + unsigned char len = (int) ((src2 >> 8) & 0xff); + if (start < 64) { + unsigned i; + unsigned last = (start+len) < 64 ? start+len : 64; + + src1 >>= start; + for (i=start; i<last; ++i) { + res |= (src1 & 1) << (i-start); + src1 >>= 1; + } + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + unsigned char start, len; + unsigned long long src1 = 0xfacec0ffeefacec0; + unsigned long long res, res_ref, src2; + + for (i=0; i<5; ++i) { + start = (i * 1983) % 64; + len = i + (i * 1983) % 64; + + src1 = src1 * 3; + src2 = start | (((long long)len) << 8); + + res_ref = calc_bextr_u64 (src1, src2); + res = __bextr_u64 (src1, src2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c b/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c new file mode 100644 index 0000000000..4ccfbdc982 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-bextr-1.c" + +/* { dg-final { scan-assembler-times "bmi_bextr_di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c b/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c new file mode 100644 index 0000000000..2ce6259667 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c @@ -0,0 +1,49 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-require-effective-target bmi } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +unsigned calc_bextr_u32 (unsigned src1, unsigned src2) +{ + unsigned res = 0; + unsigned char start = (src2 & 0xff); + unsigned char len = (int) ((src2 >> 8) & 0xff); + if (start < 32) { + unsigned i; + unsigned last = (start+len) < 32 ? start+len : 32; + + src1 >>= start; + for (i=start; i<last; ++i) { + res |= (src1 & 1) << (i-start); + src1 >>= 1; + } + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + unsigned char start, len; + unsigned src1 = 0xfacec0ff; + unsigned res, res_ref, src2; + + for (i=0; i<5; ++i) { + start = (i * 1983) % 32; + len = i + (i * 1983) % 32; + + src1 = src1 * 3; + src2 = start | (((unsigned)len) << 8); + + res_ref = calc_bextr_u32 (src1, src2); + res = __bextr_u32 (src1, src2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c b/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c new file mode 100644 index 0000000000..282a3e4001 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-bextr-2.c" + +/* { dg-final { scan-assembler-times "bmi_bextr_si" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c b/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c new file mode 100644 index 0000000000..e7f2c896d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* To fool compiler, so it not generate blsi here. */ +long long calc_blsi_u64 (long long src1, long long src2) +{ + return (-src1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsi_u64 (src, src); + res = __blsi_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c b/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c new file mode 100644 index 0000000000..e9e0ecb671 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsi-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsi_di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c b/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c new file mode 100644 index 0000000000..b6633a980a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* To fool compiler, so it not generate blsi here. */ +int calc_blsi_u32 (int src1, int src2) +{ + return (-src1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsi_u32 (src, src); + res = __blsi_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c b/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c new file mode 100644 index 0000000000..be9ca3f631 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsi-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsi_si" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c new file mode 100644 index 0000000000..5498007c39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* Trick compiler in order not to generate target insn here. */ +long long calc_blsmsk_u64 (long long src1, long long src2) +{ + return (src1-1) ^ (src2); +} + +static void +bmi_test () +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsmsk_u64 (src, src); + res = __blsmsk_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c new file mode 100644 index 0000000000..4e6cb7b366 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsmsk-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsmsk_di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c new file mode 100644 index 0000000000..be0ebf9005 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* Trick compiler in order not to generate target insn here. */ +int calc_blsmsk_u32 (int src1, int src2) +{ + return (src1-1) ^ (src2); +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsmsk_u32 (src, src); + res = __blsmsk_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c new file mode 100644 index 0000000000..f6f6babff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsmsk-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsmsk_si" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c b/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c new file mode 100644 index 0000000000..68e01f39f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_blsr_u64 (long long src1, long long src2) +{ + return (src1-1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsr_u64 (src, src); + res = __blsr_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c b/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c new file mode 100644 index 0000000000..79241ca8f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsr-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsr_di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c b/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c new file mode 100644 index 0000000000..b3fc4e5e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +int calc_blsr_u32 (int src1, int src2) +{ + return (src1-1) & (src2); +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsr_u32 (src, src); + res = __blsr_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c b/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c new file mode 100644 index 0000000000..d88c16e4de --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsr-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsr_si" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-check.h b/gcc/testsuite/gcc.target/i386/bmi-check.h new file mode 100644 index 0000000000..8fad38ad07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-check.h @@ -0,0 +1,39 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void bmi_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + bmi_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + /* Run BMI test only if host has BMI support. */ + if (ebx & bit_BMI) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c new file mode 100644 index 0000000000..a9fce15ce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_tzcnt_u64 (long long src) +{ + int i; + int res = 0; + + while ( (res<64) && ((src&1) == 0)) { + ++res; + src >>= 1; + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_tzcnt_u64 (src); + res = __tzcnt_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c new file mode 100644 index 0000000000..e283c3154f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include "bmi-tzcnt-1.c" + +/* { dg-final { scan-assembler-times "tzcntq" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c new file mode 100644 index 0000000000..1a9235b59b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +int calc_tzcnt_u32 (int src) +{ + int i; + int res = 0; + + while ( (res<32) && ((src&1) == 0)) { + ++res; + src >>= 1; + } + return res; +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_tzcnt_u32 (src); + res = __tzcnt_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c new file mode 100644 index 0000000000..2cdb3f443c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include "bmi-tzcnt-2.c" + +/* { dg-final { scan-assembler-times "tzcntl" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c new file mode 100644 index 0000000000..68df8b71d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_bzhi_u32 (unsigned a, int l) +{ + unsigned res = a; + int i; + for (i = 0; i < 32 - l; ++i) + res &= ~(1 << (31 - i)); + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0f; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_bzhi_u32 (src, i * 2); + res = _bzhi_u32 (src, i * 2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c new file mode 100644 index 0000000000..05be7a8371 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-bzhi32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_bzhi_si3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c new file mode 100644 index 0000000000..1ffe135b43 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_bzhi_u64 (unsigned long long a, int l) +{ + unsigned long long res = a; + int i; + for (i = 0; i < 64 - l; ++i) + res &= ~(1LL << (63 - i)); + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0ff; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_bzhi_u64 (src, i * 2); + res = _bzhi_u64 (src, i * 2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c new file mode 100644 index 0000000000..dc4a94cc36 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-bzhi64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_bzhi_di3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-check.h b/gcc/testsuite/gcc.target/i386/bmi2-check.h new file mode 100644 index 0000000000..c933a49f28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-check.h @@ -0,0 +1,39 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void bmi2_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + bmi2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + /* Run BMI2 test only if host has BMI2 support. */ + if (ebx & bit_BMI2) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c new file mode 100644 index 0000000000..5e60287813 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { bmi2 && { ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_mul_u32 (unsigned volatile a, unsigned b) +{ + unsigned long long res = 0; + int i; + for (i = 0; i < b; ++i) + res += a; + + return res; +} + +__attribute__((noinline, regparm (2))) +unsigned long long +gen_mulx (unsigned a, unsigned b) +{ + unsigned long long res; + + res = (unsigned long long)a * b; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned a = 0xce7ace0; + unsigned b = 0xfacefff; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u32 (a, b); + res = gen_mulx (a, b); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c new file mode 100644 index 0000000000..cf3bb085cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-mulx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_umulsidi3_1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c new file mode 100644 index 0000000000..7c99b2dae2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { bmi2 && { ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_mul_u32 (unsigned volatile a, unsigned b) +{ + unsigned long long res = 0; + int i; + for (i = 0; i < b; ++i) + res += a; + + return res; +} + +__attribute__((noinline, regparm (2))) +unsigned calc_mulx_u32 (unsigned x, unsigned y, unsigned *res_h) +{ + return (unsigned) _mulx_u32 (x, y, res_h); +} + +static void +bmi2_test () +{ + unsigned i; + unsigned a = 0xce7ace0; + unsigned b = 0xfacefff; + unsigned res_l, res_h; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u32 (a, b); + res_l = calc_mulx_u32 (a, b, &res_h); + + res = ((unsigned long long) res_h << 32) | res_l; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c new file mode 100644 index 0000000000..356d593c7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +#include "bmi2-mulx32-2.c" + +/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c new file mode 100644 index 0000000000..68449466ce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned __int128 +calc_mul_u64 (unsigned long long volatile a, unsigned long long b) +{ + unsigned __int128 res = 0; + int i; + for (i = 0; i < b; ++i) + res += (unsigned __int128) a; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long a = 0xce7ace0ce7ace0; + unsigned long long b = 0xface; + unsigned __int128 res, res_ref; + + for (i=0; i<5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u64 (a, b); + res = (unsigned __int128) a * b; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c new file mode 100644 index 0000000000..592d713e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-mulx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_umulditi3_1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c new file mode 100644 index 0000000000..55b3554628 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c @@ -0,0 +1,51 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned __int128 +calc_mul_u64 (unsigned long long volatile a, unsigned long long b) +{ + unsigned __int128 res = 0; + int i; + for (i = 0; i < b; ++i) + res += (unsigned __int128) a; + + return res; +} + +__attribute__((noinline)) +unsigned long long +calc_mulx_u64 (unsigned long long x, + unsigned long long y, + unsigned long long *res_h) +{ + return _mulx_u64 (x, y, res_h); +} + + +static void +bmi2_test () +{ + unsigned i; + unsigned long long a = 0xce7ace0ce7ace0; + unsigned long long b = 0xface; + unsigned long long res_l, res_h; + unsigned __int128 res, res_ref; + + for (i=0; i<5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u64 (a, b); + + res_l = calc_mulx_u64 (a, b, &res_h); + + res = ((unsigned __int128) res_h << 64) | res_l; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c new file mode 100644 index 0000000000..d8b3e0ecca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +#include "bmi2-mulx64-2.c" + +/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c new file mode 100644 index 0000000000..5aecf5717d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_pdep_u32 (unsigned a, int mask) +{ + unsigned res = 0; + int i, k = 0; + + for (i = 0; i < 32; ++i) + if (mask & (1 << i)) { + res |= ((a & (1 << k)) >> k) << i; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7acc; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pdep_u32 (src, i * 3); + res = _pdep_u32 (src, i * 3); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c new file mode 100644 index 0000000000..87888fcff8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pdep32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pdep_si3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c new file mode 100644 index 0000000000..f718b2f358 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_pdep_u64 (unsigned long long a, unsigned long long mask) +{ + unsigned long long res = 0; + unsigned long long i, k = 0; + + for (i = 0; i < 64; ++i) + if (mask & (1LL << i)) { + res |= ((a & (1LL << k)) >> k) << i; + ++k; + } + return res; +} + +static void +bmi2_test () +{ + unsigned long long i; + unsigned long long src = 0xce7acce7acce7ac; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pdep_u64 (src, ~(i * 3)); + res = _pdep_u64 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c new file mode 100644 index 0000000000..8163c4062a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pdep64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pdep_di3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c new file mode 100644 index 0000000000..7fe78378eb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_pext_u32 (unsigned a, unsigned mask) +{ + unsigned res = 0; + int i, k = 0; + + for (i = 0; i < 32; ++i) + if (mask & (1 << i)) { + res |= ((a & (1 << i)) >> i) << k; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7acc; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pext_u32 (src, ~(i * 3)); + res = _pext_u32 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c new file mode 100644 index 0000000000..c4a6deecae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pext32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pext_si3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c new file mode 100644 index 0000000000..6850749660 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_pext_u64 (unsigned long long a, unsigned long long mask) +{ + unsigned long long res = 0; + int i, k = 0; + + for (i = 0; i < 64; ++i) + if (mask & (1LL << i)) { + res |= ((a & (1LL << i)) >> i) << k; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned long long i; + unsigned long long src = 0xce7acce7acce7ac; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pext_u64 (src, ~(i * 3)); + res = _pext_u64 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c new file mode 100644 index 0000000000..aaf06c1f20 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pext64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pext_di3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c new file mode 100644 index 0000000000..d7f6f3b62d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_rorx_u32 (unsigned a, int l) +{ + unsigned volatile res = a; + int i; + for (i = 0; i < l; ++i) + res = (res >> 1) | ((res & 1) << 31); + + return res; +} + +#define SHIFT_VAL 0x0e + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_rorx_u32 (src, SHIFT_VAL); + res = (src >> SHIFT_VAL) | (src << (32 - SHIFT_VAL)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c new file mode 100644 index 0000000000..bb3b28d6c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-rorx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_rorxsi3_1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c new file mode 100644 index 0000000000..ccd60c28a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_rorx_u64 (unsigned long long a, int l) +{ + unsigned long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res = (res >> 1) | ((res&1)<< 63); + + return res; +} + +#define SHIFT_VAL 0x1e + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_rorx_u64 (src, SHIFT_VAL); + res = (src >> SHIFT_VAL) | (src << (64 - SHIFT_VAL)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c new file mode 100644 index 0000000000..2a7a7a08ce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-rorx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_rorxdi3_1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c new file mode 100644 index 0000000000..8224b6f60d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +int +calc_sarx_u32 (int a, int l) +{ + int volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + int src = 0xfce7ace0; + int res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_sarx_u32 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c new file mode 100644 index 0000000000..f10d60b3ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-sarx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashrsi3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c new file mode 100644 index 0000000000..a43b2025d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +long long +calc_sarx_u64 (long long a, int l) +{ + long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + long long src = 0xfce7ace0ce7ace0; + long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_sarx_u64 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c new file mode 100644 index 0000000000..bcf0fd44c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-sarx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashrdi3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c new file mode 100644 index 0000000000..0bf970282f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +int +calc_shlx_u32 (int a, int l) +{ + int volatile res = a; + int i; + for (i = 0; i < l; ++i) + res <<= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + int src = 0xfce7ace0; + int res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shlx_u32 (src, i + 1); + res = src << (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c new file mode 100644 index 0000000000..215e5d3d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shlx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashlsi3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c b/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c new file mode 100644 index 0000000000..2d2ec155e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_shrx_u32 (unsigned a, int l) +{ + unsigned volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shrx_u32 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c new file mode 100644 index 0000000000..24c53d4580 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shrx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_lshrsi3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c b/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c new file mode 100644 index 0000000000..81d232e765 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_shrx_u64 (unsigned long long a, int l) +{ + unsigned long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shrx_u64 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c b/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c new file mode 100644 index 0000000000..783043935f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shrx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_lshrdi3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/branch-cost1.c b/gcc/testsuite/gcc.target/i386/branch-cost1.c new file mode 100644 index 0000000000..ed873fa713 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/branch-cost1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */ + +extern int doo (void); + +int +foo (int a, int b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */ +/* { dg-final { scan-tree-dump-not " & " "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.target/i386/branch-cost2.c b/gcc/testsuite/gcc.target/i386/branch-cost2.c new file mode 100644 index 0000000000..4d754d57b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/branch-cost2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */ + +extern int doo (void); + +int +foo (int a, int b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */ +/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.target/i386/branch-cost3.c b/gcc/testsuite/gcc.target/i386/branch-cost3.c new file mode 100644 index 0000000000..3b69f503fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/branch-cost3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */ + +extern int doo (void); + +int +foo (_Bool a, _Bool b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */ +/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.target/i386/branch-cost4.c b/gcc/testsuite/gcc.target/i386/branch-cost4.c new file mode 100644 index 0000000000..5904b0da2b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/branch-cost4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */ + +extern int doo (void); + +int +foo (_Bool a, _Bool b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */ +/* { dg-final { scan-tree-dump-not " & " "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c b/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c index f6477e264a..badfe03a97 100644 --- a/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c +++ b/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c @@ -11,7 +11,7 @@ /* { dg-do run { xfail { ! *-*-darwin* } } } */ /* { dg-options "-O2 -mmmx" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ #include "mmx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c b/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c new file mode 100644 index 0000000000..4acf48bdc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mno-avx" } */ + +void +test1 (double *out1, double *out2, double *out3, double *in1, + double *in2, int len) +{ + int i; + double *__restrict o1 = __builtin_assume_aligned (out1, 16); + double *__restrict o2 = __builtin_assume_aligned (out2, 16); + double *__restrict o3 = __builtin_assume_aligned (out3, 16); + double *__restrict i1 = __builtin_assume_aligned (in1, 16); + double *__restrict i2 = __builtin_assume_aligned (in2, 16); + for (i = 0; i < len; ++i) + { + o1[i] = i1[i] * i2[i]; + o2[i] = i1[i] + i2[i]; + o3[i] = i1[i] - i2[i]; + } +} + +void +test2 (double *out1, double *out2, double *out3, double *in1, + double *in2, int len) +{ + int i, align = 32, misalign = 16; + out1 = __builtin_assume_aligned (out1, align, misalign); + out2 = __builtin_assume_aligned (out2, align, 16); + out3 = __builtin_assume_aligned (out3, 32, misalign); + in1 = __builtin_assume_aligned (in1, 32, 16); + in2 = __builtin_assume_aligned (in2, 32, 0); + for (i = 0; i < len; ++i) + { + out1[i] = in1[i] * in2[i]; + out2[i] = in1[i] + in2[i]; + out3[i] = in1[i] - in2[i]; + } +} + +/* { dg-final { scan-assembler-not "movhpd" } } */ +/* { dg-final { scan-assembler-not "movlpd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/builtin-copysign.c b/gcc/testsuite/gcc.target/i386/builtin-copysign.c index c20a0b6cb4..175b931c7c 100644 --- a/gcc/testsuite/gcc.target/i386/builtin-copysign.c +++ b/gcc/testsuite/gcc.target/i386/builtin-copysign.c @@ -11,6 +11,4 @@ MODE test5##CEXT(MODE a, MODE b) { return __builtin_copysign##CEXT(a, b); } TEST_SET (float, f) TEST_SET (double, ) TEST_SET (long double, l) -#if defined (__LP64__) TEST_SET (__float128, q) -#endif diff --git a/gcc/testsuite/gcc.target/i386/builtin-unreachable.c b/gcc/testsuite/gcc.target/i386/builtin-unreachable.c index 802cf16d39..91923a2dff 100644 --- a/gcc/testsuite/gcc.target/i386/builtin-unreachable.c +++ b/gcc/testsuite/gcc.target/i386/builtin-unreachable.c @@ -1,7 +1,7 @@ /* This should return 1 without setting up a stack frame or jumping. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ int h (char *p) { diff --git a/gcc/testsuite/gcc.target/i386/cleanup-2.c b/gcc/testsuite/gcc.target/i386/cleanup-2.c index 2bd18025f6..36dd80da91 100644 --- a/gcc/testsuite/gcc.target/i386/cleanup-2.c +++ b/gcc/testsuite/gcc.target/i386/cleanup-2.c @@ -1,5 +1,4 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { *-*-linux* && { ! { ia32 } } } } } */ /* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */ /* Test complex CFA value expressions. */ diff --git a/gcc/testsuite/gcc.target/i386/clearcapv2.map b/gcc/testsuite/gcc.target/i386/clearcapv2.map new file mode 100644 index 0000000000..95cb14cc5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/clearcapv2.map @@ -0,0 +1,7 @@ +# clear all hardware capabilities emitted by Sun as: the tests here +# guard against execution at runtime +# uses mapfile v2 syntax which is the only way to clear AT_SUN_CAP_HW2 flags +$mapfile_version 2 +CAPABILITY { + HW = ; +}; diff --git a/gcc/testsuite/gcc.target/i386/clobbers.c b/gcc/testsuite/gcc.target/i386/clobbers.c index 17987db970..1a70688d74 100644 --- a/gcc/testsuite/gcc.target/i386/clobbers.c +++ b/gcc/testsuite/gcc.target/i386/clobbers.c @@ -16,7 +16,7 @@ int main () Ditto for any x86 system that is ilp32 && pic. */ #if !(defined (__MACH__)) -#if ! defined (__PIC__) || defined (__LP64__) +#if ! defined (__PIC__) || defined (__x86_64__) __asm__ ("movl $1,%0\n\txorl %%ebx,%%ebx" : "=r" (i) : : "ebx"); if (i != 1) abort (); diff --git a/gcc/testsuite/gcc.target/i386/cmov8.c b/gcc/testsuite/gcc.target/i386/cmov8.c index 639fb62b0c..2d95c25da0 100644 --- a/gcc/testsuite/gcc.target/i386/cmov8.c +++ b/gcc/testsuite/gcc.target/i386/cmov8.c @@ -1,6 +1,6 @@ /* PR target/36936 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=i686" } */ /* { dg-final { scan-assembler "cmov\[^8\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c b/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c index fd266f5a01..e3402014e5 100644 --- a/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c +++ b/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mcx16" } */ typedef int TItype __attribute__ ((mode (TI))); @@ -11,4 +10,4 @@ void test(TItype x_128) m_128 = __sync_val_compare_and_swap (&m_128, x_128, m_128); } -/* { dg-final { scan-assembler "cmpxchg16b" } } */ +/* { dg-final { scan-assembler "cmpxchg16b\[ \\t]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c b/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c index fa69eedaa7..e4d71c21c4 100644 --- a/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c +++ b/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ /* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387 -fpic" } */ double foo (double x) { diff --git a/gcc/testsuite/gcc.target/i386/compress-float-387.c b/gcc/testsuite/gcc.target/i386/compress-float-387.c index bed2986bc4..03a834d2b3 100644 --- a/gcc/testsuite/gcc.target/i386/compress-float-387.c +++ b/gcc/testsuite/gcc.target/i386/compress-float-387.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387" } */ double foo (double x) { return x + 1.75; diff --git a/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c b/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c index 2c9be7cd9f..ef024dd0b0 100644 --- a/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c +++ b/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ /* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse -fpic" } */ double foo (double x) { diff --git a/gcc/testsuite/gcc.target/i386/compress-float-sse.c b/gcc/testsuite/gcc.target/i386/compress-float-sse.c index 48db611110..c56be1300e 100644 --- a/gcc/testsuite/gcc.target/i386/compress-float-sse.c +++ b/gcc/testsuite/gcc.target/i386/compress-float-sse.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse" } */ double foo (double x) { return x + 1.75; diff --git a/gcc/testsuite/gcc.target/i386/conversion.c b/gcc/testsuite/gcc.target/i386/conversion.c new file mode 100644 index 0000000000..c1718f0273 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/conversion.c @@ -0,0 +1,57 @@ +/* Check that conversion functions don't leak into global namespace. */ + +/* { dg-do link } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options c99_runtime } */ + +#include "../../gcc.dg/builtins-config.h" + +int ifloor (double a) { return __builtin_ifloor (a); } +#ifdef HAVE_C99_RUNTIME +int ifloorf (float a) { return __builtin_ifloorf (a); } +int ifloorl (long double a) { return __builtin_ifloorl (a); } +#endif + +long lfloor (double a) { return __builtin_lfloor (a); } +#ifdef HAVE_C99_RUNTIME +long lfloorf (float a) { return __builtin_lfloorf (a); } +long lfloorl (long double a) { return __builtin_lfloorl (a); } +#endif + +long long llfloor (double a) { return __builtin_llfloor (a); } +#ifdef HAVE_C99_RUNTIME +long long llfloorf (float a) { return __builtin_llfloorf (a); } +long long llfloorl (long double a) { return __builtin_llfloorl (a); } +#endif + +int iceil (double a) { return __builtin_iceil (a); } +#ifdef HAVE_C99_RUNTIME +int iceilf (float a) { return __builtin_iceilf (a); } +int iceill (long double a) { return __builtin_iceill (a); } +#endif + +long lceil (double a) { return __builtin_lceil (a); } +#ifdef HAVE_C99_RUNTIME +long lceilf (float a) { return __builtin_lceilf (a); } +long lceill (long double a) { return __builtin_lceill (a); } +#endif + +long long llceil (double a) { return __builtin_llceil (a); } +#ifdef HAVE_C99_RUNTIME +long long llceilf (float a) { return __builtin_llceilf (a); } +long long llceill (long double a) { return __builtin_llceill (a); } +#endif + +int iround (double a) { return __builtin_iround (a); } +#ifdef HAVE_C99_RUNTIME +int iroundf (float a) { return __builtin_iroundf (a); } +int iroundl (long double a) { return __builtin_iroundl (a); } +#endif + +int irint (double a) { return __builtin_irint (a); } +#ifdef HAVE_C99_RUNTIME +int irintf (float a) { return __builtin_irintf (a); } +int irintl (long double a) { return __builtin_irintl (a); } +#endif + +int main () { return 0; } diff --git a/gcc/testsuite/gcc.target/i386/crc32-2.c b/gcc/testsuite/gcc.target/i386/crc32-2.c index e7af9ab45f..678cfd5a45 100644 --- a/gcc/testsuite/gcc.target/i386/crc32-2.c +++ b/gcc/testsuite/gcc.target/i386/crc32-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mcrc32" } */ -/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target lp64 } } } */ +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! { ia32 } } } } } */ unsigned long long crc32d (unsigned long long x, unsigned long long y) diff --git a/gcc/testsuite/gcc.target/i386/crc32-3.c b/gcc/testsuite/gcc.target/i386/crc32-3.c index e77d7d99d1..7518a45269 100644 --- a/gcc/testsuite/gcc.target/i386/crc32-3.c +++ b/gcc/testsuite/gcc.target/i386/crc32-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mcrc32" } */ /* { dg-final { scan-assembler "__builtin_ia32_crc32di" } } */ diff --git a/gcc/testsuite/gcc.target/i386/divmod-7.c b/gcc/testsuite/gcc.target/i386/divmod-7.c index 20a4cd3095..de4a1fb939 100644 --- a/gcc/testsuite/gcc.target/i386/divmod-7.c +++ b/gcc/testsuite/gcc.target/i386/divmod-7.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -m8bit-idiv" } */ -/* { dg-require-effective-target lp64 } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/divmod-8.c b/gcc/testsuite/gcc.target/i386/divmod-8.c index 5192b98d67..eb09a6d7b2 100644 --- a/gcc/testsuite/gcc.target/i386/divmod-8.c +++ b/gcc/testsuite/gcc.target/i386/divmod-8.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -m8bit-idiv" } */ extern void foo (long long, long long, long long, long long, diff --git a/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c b/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c index 1a55a3d60e..3f33f6b21a 100644 --- a/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c +++ b/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-mpreferred-stack-boundary=4 -msse" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c new file mode 100644 index 0000000000..7e73402fcb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fmadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c new file mode 100644 index 0000000000..4b61ad5f8a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmaddsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmaddsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union256 (e, d)) + abort (); +} + +void +check_mm256_fmaddsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmaddsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union256d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmaddsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmaddsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c new file mode 100644 index 0000000000..d92aec0ec5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + + +void +check_mm256_fmsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fmsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c new file mode 100644 index 0000000000..84a41c4c0b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmsubadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmsubadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union256 (e, d)) + abort (); +} + +void +check_mm256_fmsubadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmsubadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union256d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmsubadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmsubadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c new file mode 100644 index 0000000000..c0dfa6900b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fnmadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fnmadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fnmadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fnmadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fnmadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fnmadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c b/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c new file mode 100644 index 0000000000..ac4705e5c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + + +void +check_mm256_fnmsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fnmsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fnmsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fnmsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fnmsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fnmsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-check.h b/gcc/testsuite/gcc.target/i386/fma-check.h new file mode 100644 index 0000000000..8390f5088b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-check.h @@ -0,0 +1,25 @@ +#include <stdlib.h> + +#include "cpuid.h" + +static void fma_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + fma_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run FMA test only if host has FMA support. */ + if (ecx & bit_FMA) + do_test (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/fma-compile.c b/gcc/testsuite/gcc.target/i386/fma-compile.c new file mode 100644 index 0000000000..0445f7bc0a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-compile.c @@ -0,0 +1,221 @@ +/* Test that the compiler properly generates floating point multiply + and add instructions FMA systems. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -mfma" } */ + +#include <x86intrin.h> + +__m128d +check_mm_fmadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmadd_pd (a, b, c); +} + +__m256d +check_mm256_fmadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmadd_pd (a, b, c); +} + +__m128 +check_mm_fmadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmadd_ps (a, b, c); +} + +__m256 +check_mm256_fmadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmadd_ps (a, b, c); +} + +__m128d +check_mm_fmadd_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmadd_sd (a, b, c); +} + +__m128 +check_mm_fmadd_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmadd_ss (a, b, c); +} + +__m128d +check_mm_fmsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsub_pd (a, b, c); +} + +__m256d +check_mm256_fmsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmsub_pd (a, b, c); +} + +__m128 +check_mm_fmsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsub_ps (a, b, c); +} + +__m256 +check_mm256_fmsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmsub_ps (a, b, c); +} + +__m128d +check_mm_fmsub_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsub_sd (a, b, c); +} + +__m128 +check_mm_fmsub_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsub_ss (a, b, c); +} + +__m128d +check_mm_fnmadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmadd_pd (a, b, c); +} + +__m256d +check_mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fnmadd_pd (a, b, c); +} + +__m128 +check_mm_fnmadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmadd_ps (a, b, c); +} + +__m256 +check_mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fnmadd_ps (a, b, c); +} + +__m128d +check_mm_fnmadd_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmadd_sd (a, b, c); +} + +__m128 +check_mm_fnmadd_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmadd_ss (a, b, c); +} + +__m128d +check_mm_fnmsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmsub_pd (a, b, c); +} + +__m256d +check_mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fnmsub_pd (a, b, c); +} + +__m128 +check_mm_fnmsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmsub_ps (a, b, c); +} + +__m256 +check_mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fnmsub_ps (a, b, c); +} + +__m128d +check_mm_fnmsub_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmsub_sd (a, b, c); +} + +__m128 +check_mm_fnmsub_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmsub_ss (a, b, c); +} + +__m128d +check_mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmaddsub_pd (a, b, c); +} + +__m256d +check_mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmaddsub_pd (a, b, c); +} + +__m128 +check_mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmaddsub_ps (a, b, c); +} + +__m256 +check_mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmaddsub_ps (a, b, c); +} + +__m128d +check_mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsubadd_pd (a, b, c); +} + +__m256d +check_mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmsubadd_pd (a, b, c); +} + +__m128 +check_mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsubadd_ps (a, b, c); +} + +__m256 +check_mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmsubadd_ps (a, b, c); +} + + +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddsub...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsubadd...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddsub...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsubadd...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...sd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c b/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c new file mode 100644 index 0000000000..43ef9e8071 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c @@ -0,0 +1,102 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmadd_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmadd_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] + c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmadd_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmadd_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] + c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmadd_sd (b[0].x, b[1].x, b[2].x); + check_mm_fmadd_ps (a[0].x, a[1].x, a[2].x); + check_mm_fmadd_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c b/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c new file mode 100644 index 0000000000..89c816392f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmaddsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmaddsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmaddsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmaddsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmaddsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmaddsub_ps (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c b/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c new file mode 100644 index 0000000000..3d92d4b25a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmsub_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsub_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] - c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmsub_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsub_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] - c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmsub_sd (b[0].x, b[1].x, b[2].x); + check_mm_fmsub_ps (a[0].x, a[1].x, a[2].x); + check_mm_fmsub_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c b/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c new file mode 100644 index 0000000000..b03f875319 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmsubadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsubadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmsubadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsubadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmsubadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmsubadd_ps (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c b/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c new file mode 100644 index 0000000000..f23a6c5e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fnmadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmadd_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmadd_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] + c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmadd_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmadd_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] + c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fnmadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fnmadd_sd (b[0].x, b[1].x, b[2].x); + check_mm_fnmadd_ps (a[0].x, a[1].x, a[2].x); + check_mm_fnmadd_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c b/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c new file mode 100644 index 0000000000..d17c7f2ed1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fnmsub_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmsub_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] - c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmsub_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmsub_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] - c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fnmsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fnmsub_sd (b[0].x, b[1].x, b[2].x); + check_mm_fnmsub_ps (a[0].x, a[1].x, a[2].x); + check_mm_fnmsub_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc/testsuite/gcc.target/i386/fma3-builtin.c b/gcc/testsuite/gcc.target/i386/fma3-builtin.c index ba8af5520e..2d9c5c73a9 100644 --- a/gcc/testsuite/gcc.target/i386/fma3-builtin.c +++ b/gcc/testsuite/gcc.target/i386/fma3-builtin.c @@ -1,8 +1,7 @@ /* Test that the compiler properly generates floating point multiply and add instructions FMA3 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma -mno-fma4" } */ #ifndef __FP_FAST_FMAF diff --git a/gcc/testsuite/gcc.target/i386/fma3-fma.c b/gcc/testsuite/gcc.target/i386/fma3-fma.c index 1cedba8ddc..f18f97bf3c 100644 --- a/gcc/testsuite/gcc.target/i386/fma3-fma.c +++ b/gcc/testsuite/gcc.target/i386/fma3-fma.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes floating point multiply and add instructions FMA3 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma -mno-fma4" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/fma4-256-vector.c b/gcc/testsuite/gcc.target/i386/fma4-256-vector.c index 1bd2ce4ddf..edaa21a2d3 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-256-vector.c +++ b/gcc/testsuite/gcc.target/i386/fma4-256-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes floating point multiply and add instructions vector into vfmaddps on FMA4 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/fma4-builtin.c b/gcc/testsuite/gcc.target/i386/fma4-builtin.c index 5659cf4f02..7135cc9339 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-builtin.c +++ b/gcc/testsuite/gcc.target/i386/fma4-builtin.c @@ -1,8 +1,7 @@ /* Test that the compiler properly generates floating point multiply and add instructions FMA4 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma4" } */ #ifndef __FP_FAST_FMAF diff --git a/gcc/testsuite/gcc.target/i386/fma4-check.h b/gcc/testsuite/gcc.target/i386/fma4-check.h index dc7ee57487..33cd9628c0 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-check.h +++ b/gcc/testsuite/gcc.target/i386/fma4-check.h @@ -23,5 +23,5 @@ main () if (ecx & bit_FMA4) do_test (); - exit (0); + return 0; } diff --git a/gcc/testsuite/gcc.target/i386/fma4-fma-2.c b/gcc/testsuite/gcc.target/i386/fma4-fma-2.c index 23f6ec167e..c15be1edac 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-fma-2.c +++ b/gcc/testsuite/gcc.target/i386/fma4-fma-2.c @@ -2,8 +2,7 @@ and add instructions into vfmaddss, vfmsubss, vfnmaddss, vfnmsubss on FMA4 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -funsafe-math-optimizations -mfma4" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/fma4-fma.c b/gcc/testsuite/gcc.target/i386/fma4-fma.c index cb90691611..63b35dc4bc 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-fma.c +++ b/gcc/testsuite/gcc.target/i386/fma4-fma.c @@ -2,8 +2,7 @@ and add instructions into vfmaddss, vfmsubss, vfnmaddss, vfnmsubss on FMA4 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma4" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/fma4-vector-2.c b/gcc/testsuite/gcc.target/i386/fma4-vector-2.c index 2f3ec96dc9..d8b0d0813b 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-vector-2.c +++ b/gcc/testsuite/gcc.target/i386/fma4-vector-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ float r[256], s[256]; diff --git a/gcc/testsuite/gcc.target/i386/fma4-vector.c b/gcc/testsuite/gcc.target/i386/fma4-vector.c index da12780d77..db5ffdd339 100644 --- a/gcc/testsuite/gcc.target/i386/fma4-vector.c +++ b/gcc/testsuite/gcc.target/i386/fma4-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes floating point multiply and add instructions vector into vfmaddps on FMA4 systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/fma_1.h b/gcc/testsuite/gcc.target/i386/fma_1.h new file mode 100644 index 0000000000..72d7373946 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_1.h @@ -0,0 +1,101 @@ + +#ifndef fma_1 +#define fma_1 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a - b; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_2.h b/gcc/testsuite/gcc.target/i386/fma_2.h new file mode 100644 index 0000000000..c5d38d19a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_2.h @@ -0,0 +1,101 @@ + +#ifndef fma_2 +#define fma_2 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a - c; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_3.h b/gcc/testsuite/gcc.target/i386/fma_3.h new file mode 100644 index 0000000000..efa88b5d97 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_3.h @@ -0,0 +1,101 @@ + +#ifndef fma_3 +#define fma_3 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b - a; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_4.h b/gcc/testsuite/gcc.target/i386/fma_4.h new file mode 100644 index 0000000000..9fbb3efdf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_4.h @@ -0,0 +1,101 @@ + +#ifndef fma_4 +#define fma_4 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b - c; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_5.h b/gcc/testsuite/gcc.target/i386/fma_5.h new file mode 100644 index 0000000000..3409db8f4f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_5.h @@ -0,0 +1,101 @@ + +#ifndef fma_5 +#define fma_5 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c - a; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_6.h b/gcc/testsuite/gcc.target/i386/fma_6.h new file mode 100644 index 0000000000..a6bb4b0cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_6.h @@ -0,0 +1,101 @@ + +#ifndef fma_6 +#define fma_6 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c - b; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_double_1.c b/gcc/testsuite/gcc.target/i386/fma_double_1.c new file mode 100644 index 0000000000..c3aa3e83c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231sd" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_double_2.c b/gcc/testsuite/gcc.target/i386/fma_double_2.c new file mode 100644 index 0000000000..843eff0a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_double_3.c b/gcc/testsuite/gcc.target/i386/fma_double_3.c new file mode 100644 index 0000000000..ac69684fee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231sd" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_double_4.c b/gcc/testsuite/gcc.target/i386/fma_double_4.c new file mode 100644 index 0000000000..51fc111adb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_double_5.c b/gcc/testsuite/gcc.target/i386/fma_double_5.c new file mode 100644 index 0000000000..3eca38c149 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_double_6.c b/gcc/testsuite/gcc.target/i386/fma_double_6.c new file mode 100644 index 0000000000..7b75a224f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_1.c b/gcc/testsuite/gcc.target/i386/fma_float_1.c new file mode 100644 index 0000000000..67b1f3fe7c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ss" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_2.c b/gcc/testsuite/gcc.target/i386/fma_float_2.c new file mode 100644 index 0000000000..a54644d0c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_3.c b/gcc/testsuite/gcc.target/i386/fma_float_3.c new file mode 100644 index 0000000000..afb88b6074 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ss" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_4.c b/gcc/testsuite/gcc.target/i386/fma_float_4.c new file mode 100644 index 0000000000..d9689d9a7a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_5.c b/gcc/testsuite/gcc.target/i386/fma_float_5.c new file mode 100644 index 0000000000..cb067ca4a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_float_6.c b/gcc/testsuite/gcc.target/i386/fma_float_6.c new file mode 100644 index 0000000000..c758073683 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_float_6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fma_main.h b/gcc/testsuite/gcc.target/i386/fma_main.h new file mode 100644 index 0000000000..24464ab508 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_main.h @@ -0,0 +1,117 @@ + +#ifndef fma_main +#define fma_main + +#if DEBUG +#include <stdio.h> +#endif + +TYPE m1[32] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 + }; +TYPE m2[32] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 + }; +TYPE m3[32] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + }; +TYPE m4[32]; +int test_fails = 0; + +void +compare_result(char * title, TYPE *res) +{ + int i; + int good = 1; + for (i =0; i < 32; i++) + if (m4[i] != res[i]) + { + if (good) + { +#if DEBUG + printf ("!!!! %s miscompare\n", title); +#endif + good = 0; + } +#if DEBUG + printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]); +#endif + } + if (!good) + test_fails = 1; +} + +static void fma_test () +{ + int i; + for (i=0; i <32; i++) + m4[i] = test_noneg_add_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test0000", res_test0000); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0001", res_test0001); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test0010", res_test0010); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0011", res_test0011); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test0100", res_test0100); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0101", res_test0101); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test0110", res_test0110); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0111", res_test0111); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test1000", res_test1000); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1001", res_test1001); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test1010", res_test1010); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1011", res_test1011); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test1100", res_test1100); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1101", res_test1101); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test1110", res_test1110); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1111", res_test1111); + + if (test_fails) abort (); +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_1.c b/gcc/testsuite/gcc.target/i386/fma_run_double_1.c new file mode 100644 index 0000000000..a2f2aae9e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_1.h" + +#include "fma_run_double_results_1.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_2.c b/gcc/testsuite/gcc.target/i386/fma_run_double_2.c new file mode 100644 index 0000000000..a389473a89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_2.h" + +#include "fma_run_double_results_2.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_3.c b/gcc/testsuite/gcc.target/i386/fma_run_double_3.c new file mode 100644 index 0000000000..7b9d6273ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_3.h" + +#include "fma_run_double_results_3.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_4.c b/gcc/testsuite/gcc.target/i386/fma_run_double_4.c new file mode 100644 index 0000000000..1c0456dbad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_4.h" + +#include "fma_run_double_results_4.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_5.c b/gcc/testsuite/gcc.target/i386/fma_run_double_5.c new file mode 100644 index 0000000000..6c09f0bb8a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_5.h" + +#include "fma_run_double_results_5.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_6.c b/gcc/testsuite/gcc.target/i386/fma_run_double_6.c new file mode 100644 index 0000000000..32e51bf319 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_6.h" + +#include "fma_run_double_results_6.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h new file mode 100644 index 0000000000..27f325b86b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_1 +#define fma_run_double_results_1 + +TYPE res_test0000[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test0001[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; +TYPE res_test0010[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test0011[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test0100[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test0101[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test0110[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test0111[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1000[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test1001[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1010[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test1011[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test1100[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test1101[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test1110[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test1111[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h new file mode 100644 index 0000000000..f9327ce650 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_2 +#define fma_run_double_results_2 + +TYPE res_test0000[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test0001[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; +TYPE res_test0010[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test0011[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test0100[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test0101[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test0110[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test0111[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1000[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test1001[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1010[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test1011[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test1100[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test1101[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test1110[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test1111[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h new file mode 100644 index 0000000000..44cf82735d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_3 +#define fma_run_double_results_3 + +TYPE res_test0000[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test0001[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; +TYPE res_test0010[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test0011[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test0100[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test0101[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test0110[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test0111[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1000[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test1001[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1010[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test1011[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test1100[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test1101[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test1110[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test1111[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h new file mode 100644 index 0000000000..0b7f85775c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_4 +#define fma_run_double_results_4 + +TYPE res_test0000[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test0001[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; +TYPE res_test0010[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test0011[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test0100[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test0101[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test0110[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test0111[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1000[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test1001[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1010[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test1011[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test1100[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test1101[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test1110[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test1111[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h new file mode 100644 index 0000000000..0f96cad011 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_5 +#define fma_run_double_results_5 + +TYPE res_test0000[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test0001[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; +TYPE res_test0010[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test0011[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test0100[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test0101[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test0110[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test0111[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1000[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test1001[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1010[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test1011[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test1100[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test1101[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test1110[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test1111[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h b/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h new file mode 100644 index 0000000000..29ae9256c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_6 +#define fma_run_double_results_6 + +TYPE res_test0000[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test0001[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; +TYPE res_test0010[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test0011[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test0100[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test0101[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test0110[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test0111[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1000[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test1001[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1010[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test1011[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test1100[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test1101[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test1110[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test1111[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_1.c b/gcc/testsuite/gcc.target/i386/fma_run_float_1.c new file mode 100644 index 0000000000..eccf60a88c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_1.h" + +#include "fma_run_float_results_1.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_2.c b/gcc/testsuite/gcc.target/i386/fma_run_float_2.c new file mode 100644 index 0000000000..18177520ac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_2.h" + +#include "fma_run_float_results_2.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_3.c b/gcc/testsuite/gcc.target/i386/fma_run_float_3.c new file mode 100644 index 0000000000..b206a0775d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_3.h" + +#include "fma_run_float_results_3.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_4.c b/gcc/testsuite/gcc.target/i386/fma_run_float_4.c new file mode 100644 index 0000000000..31c5a4dbbf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_4.h" + +#include "fma_run_float_results_4.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_5.c b/gcc/testsuite/gcc.target/i386/fma_run_float_5.c new file mode 100644 index 0000000000..615886cedb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_5.h" + +#include "fma_run_float_results_5.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_6.c b/gcc/testsuite/gcc.target/i386/fma_run_float_6.c new file mode 100644 index 0000000000..ca6cf5b1c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_6.h" + +#include "fma_run_float_results_6.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h new file mode 100644 index 0000000000..65f52f2c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_1 +#define fma_run_float_results_1 + +TYPE res_test0000[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test0001[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; +TYPE res_test0010[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test0011[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test0100[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test0101[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test0110[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test0111[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1000[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test1001[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1010[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test1011[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test1100[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test1101[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test1110[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test1111[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h new file mode 100644 index 0000000000..d215efd587 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_2 +#define fma_run_float_results_2 + +TYPE res_test0000[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test0001[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; +TYPE res_test0010[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test0011[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test0100[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test0101[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test0110[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test0111[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1000[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test1001[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1010[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test1011[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test1100[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test1101[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test1110[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test1111[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h new file mode 100644 index 0000000000..11751f131a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_3 +#define fma_run_float_results_3 + +TYPE res_test0000[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test0001[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; +TYPE res_test0010[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test0011[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test0100[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test0101[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test0110[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test0111[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1000[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test1001[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1010[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test1011[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test1100[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test1101[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test1110[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test1111[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h new file mode 100644 index 0000000000..13906dbdde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_4 +#define fma_run_float_results_4 + +TYPE res_test0000[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test0001[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; +TYPE res_test0010[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test0011[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test0100[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test0101[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test0110[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test0111[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1000[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test1001[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1010[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test1011[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test1100[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test1101[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test1110[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test1111[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h new file mode 100644 index 0000000000..f156bef6f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_5 +#define fma_run_float_results_5 + +TYPE res_test0000[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test0001[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; +TYPE res_test0010[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test0011[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test0100[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test0101[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test0110[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test0111[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1000[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test1001[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1010[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test1011[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test1100[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test1101[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test1110[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test1111[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h b/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h new file mode 100644 index 0000000000..d2c2e1f972 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_6 +#define fma_run_float_results_6 + +TYPE res_test0000[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test0001[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; +TYPE res_test0010[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test0011[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test0100[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test0101[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test0110[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test0111[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1000[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test1001[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1010[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test1011[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test1100[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test1101[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test1110[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test1111[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; + +#endif diff --git a/gcc/testsuite/gcc.target/i386/funcspec-1.c b/gcc/testsuite/gcc.target/i386/funcspec-1.c index bd8e67d0c1..742e3a19e2 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-1.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-1.c @@ -2,11 +2,8 @@ 32-bit, which does not generate SSE2 by default, but still generate 387 code for a function that doesn't use attribute((option)). */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ -/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ -/* { dg-options "-O3 -ftree-vectorize -march=i386" } */ -/* { dg-final { scan-assembler "addps\[ \t\]" } } */ -/* { dg-final { scan-assembler "fsubs\[ \t\]" } } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O3 -ftree-vectorize -mno-sse" } */ #ifndef SIZE #define SIZE 1024 @@ -33,3 +30,6 @@ i387_subnums (void) for (; i < SIZE; ++i) a[i] = b[i] - c[i]; } + +/* { dg-final { scan-assembler "addps\[ \t\]" } } */ +/* { dg-final { scan-assembler "fsubs\[ \t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/funcspec-10.c b/gcc/testsuite/gcc.target/i386/funcspec-10.c index 9526e7df2e..de39ff00e7 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-10.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-10.c @@ -1,6 +1,6 @@ /* PR target/36936 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=i686" } */ /* { dg-final { scan-assembler-not "cmov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/funcspec-11.c b/gcc/testsuite/gcc.target/i386/funcspec-11.c index 065ca3ccaa..7c39f4cd2a 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-11.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-11.c @@ -1,6 +1,6 @@ /* PR target/36936 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=i386" } */ /* { dg-final { scan-assembler "cmov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/funcspec-2.c b/gcc/testsuite/gcc.target/i386/funcspec-2.c index c132fc9a96..88c14b29b2 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-2.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-2.c @@ -1,6 +1,5 @@ /* Test whether using target specific options, we can generate FMA4 code. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -march=k8" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-3.c b/gcc/testsuite/gcc.target/i386/funcspec-3.c index 01c7e4ca05..f3f4db76a8 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-3.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-3.c @@ -2,7 +2,7 @@ setting the architecture. */ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O2 -march=k8" } */ +/* { dg-options "-O2 -march=k8 -mno-sse3" } */ extern void exit (int); extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-5.c b/gcc/testsuite/gcc.target/i386/funcspec-5.c index 1e18dcf871..df97a2d7bd 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-5.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-5.c @@ -1,7 +1,7 @@ /* Test whether all of the 32-bit function specific options are accepted without error. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ extern void test_abm (void) __attribute__((__target__("abm"))); extern void test_aes (void) __attribute__((__target__("aes"))); @@ -20,6 +20,8 @@ extern void test_sse4a (void) __attribute__((__target__("sse4a"))); extern void test_fma4 (void) __attribute__((__target__("fma4"))); extern void test_ssse3 (void) __attribute__((__target__("ssse3"))); extern void test_tbm (void) __attribute__((__target__("tbm"))); +extern void test_avx (void) __attribute__((__target__("avx"))); +extern void test_avx2 (void) __attribute__((__target__("avx2"))); extern void test_no_abm (void) __attribute__((__target__("no-abm"))); extern void test_no_aes (void) __attribute__((__target__("no-aes"))); @@ -38,6 +40,8 @@ extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a"))); extern void test_no_fma4 (void) __attribute__((__target__("no-fma4"))); extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3"))); extern void test_no_tbm (void) __attribute__((__target__("no-tbm"))); +extern void test_no_avx (void) __attribute__((__target__("no-avx"))); +extern void test_no_avx2 (void) __attribute__((__target__("no-avx2"))); extern void test_arch_i386 (void) __attribute__((__target__("arch=i386"))); extern void test_arch_i486 (void) __attribute__((__target__("arch=i486"))); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-6.c b/gcc/testsuite/gcc.target/i386/funcspec-6.c index 92a3cb52d7..e28b38c440 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-6.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-6.c @@ -1,7 +1,6 @@ /* Test whether all of the 64-bit function specific options are accepted without error. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ extern void test_abm (void) __attribute__((__target__("abm"))); extern void test_aes (void) __attribute__((__target__("aes"))); @@ -20,6 +19,8 @@ extern void test_sse4a (void) __attribute__((__target__("sse4a"))); extern void test_fma4 (void) __attribute__((__target__("fma4"))); extern void test_ssse3 (void) __attribute__((__target__("ssse3"))); extern void test_tbm (void) __attribute__((__target__("tbm"))); +extern void test_avx (void) __attribute__((__target__("avx"))); +extern void test_avx2 (void) __attribute__((__target__("avx2"))); extern void test_no_abm (void) __attribute__((__target__("no-abm"))); extern void test_no_aes (void) __attribute__((__target__("no-aes"))); @@ -38,6 +39,8 @@ extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a"))); extern void test_no_fma4 (void) __attribute__((__target__("no-fma4"))); extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3"))); extern void test_no_tbm (void) __attribute__((__target__("no-tbm"))); +extern void test_no_avx (void) __attribute__((__target__("no-avx"))); +extern void test_no_avx2 (void) __attribute__((__target__("no-avx2"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c index d20a717603..6d6ce992b1 100644 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c @@ -1,5 +1,5 @@ /* { dg-do preprocess } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ /* { dg-options "-march=i386" } */ diff --git a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c index 01a49b64a8..08c4e0b854 100644 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c @@ -1,5 +1,5 @@ /* { dg-do preprocess } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */ /* { dg-options "-march=i486" } */ diff --git a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c index bc5a559892..40dd9357fe 100644 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c @@ -1,5 +1,5 @@ /* { dg-do preprocess } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-march=i586" } */ #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 diff --git a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c index 27928699f6..ab250ddfab 100644 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c @@ -1,5 +1,4 @@ -/* { dg-do preprocess } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do preprocess { target { ! { ia32 } } } } */ /* { dg-options "-mcx16" } */ #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 32dbf5eac0..b8bbe1c74f 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -172,6 +172,20 @@ proc check_effective_target_fma4 { } { } "-O2 -mfma4" ] } +# Return 1 if fma instructions can be compiled. +proc check_effective_target_fma { } { + return [check_no_compiler_messages fma object { + typedef float __m128 __attribute__ ((__vector_size__ (16))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) + { + return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, + (__v4sf)__B, + (__v4sf)__C); + } + } "-O2 -mfma" ] +} + # Return 1 if xop instructions can be compiled. proc check_effective_target_xop { } { return [check_no_compiler_messages xop object { @@ -186,14 +200,68 @@ proc check_effective_target_xop { } { } "-O2 -mxop" ] } +# Return 1 if lzcnt instruction can be compiled. +proc check_effective_target_lzcnt { } { + return [check_no_compiler_messages lzcnt object { + unsigned short _lzcnt (unsigned short __X) + { + return __builtin_clzs (__X); + } + } "-mlzcnt" ] +} + +# Return 1 if avx2 instructions can be compiled. +proc check_effective_target_avx2 { } { + return [check_no_compiler_messages avx2 object { + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + __v4di + mm256_is32_andnotsi256 (__v4di __X, __v4di __Y) + { + return __builtin_ia32_andnotsi256 (__X, __Y); + } + } "-O0 -mavx2" ] +} + +# Return 1 if bmi instructions can be compiled. +proc check_effective_target_bmi { } { + return [check_no_compiler_messages bmi object { + unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y) + { + return __builtin_ia32_bextr_u32 (__X, __Y); + } + } "-mbmi" ] +} + +# Return 1 if bmi2 instructions can be compiled. +proc check_effective_target_bmi2 { } { + return [check_no_compiler_messages bmi2 object { + unsigned int + _bzhi_u32 (unsigned int __X, unsigned int __Y) + { + return __builtin_ia32_bzhi_si (__X, __Y); + } + } "-mbmi2" ] +} + # If the linker used understands -M <mapfile>, pass it to clear hardware # capabilities set by the Sun assembler. -set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcap.map" +# Try mapfile syntax v2 first which is the only way to clear hwcap_2 flags. +set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcapv2.map" -if [check_no_compiler_messages mapfile executable { +if ![check_no_compiler_messages mapfilev2 executable { + int main (void) { return 0; } +} $clearcap_ldflags ] { + # If this doesn't work, fall back to the less capable v1 syntax. + set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcap.map" + + if ![check_no_compiler_messages mapfile executable { int main (void) { return 0; } - } $clearcap_ldflags ] { + } $clearcap_ldflags ] { + unset clearcap_ldflags + } +} +if [info exists clearcap_ldflags] { if { [info procs gcc_target_compile] != [list] \ && [info procs saved_gcc_target_compile] == [list] } { rename gcc_target_compile saved_gcc_target_compile diff --git a/gcc/testsuite/gcc.target/i386/incoming-1.c b/gcc/testsuite/gcc.target/i386/incoming-1.c index 86e98a79b4..c59b208a6f 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-1.c +++ b/gcc/testsuite/gcc.target/i386/incoming-1.c @@ -1,5 +1,5 @@ /* PR middle-end/37009 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-10.c b/gcc/testsuite/gcc.target/i386/incoming-10.c index 31d9e6180b..1fb9ef4f0f 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-10.c +++ b/gcc/testsuite/gcc.target/i386/incoming-10.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */ struct s { diff --git a/gcc/testsuite/gcc.target/i386/incoming-11.c b/gcc/testsuite/gcc.target/i386/incoming-11.c index e5787af7a6..a7b7db53aa 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-11.c +++ b/gcc/testsuite/gcc.target/i386/incoming-11.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */ void g(); diff --git a/gcc/testsuite/gcc.target/i386/incoming-12.c b/gcc/testsuite/gcc.target/i386/incoming-12.c index d7ef1038bb..21f3f01f7f 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-12.c +++ b/gcc/testsuite/gcc.target/i386/incoming-12.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-13.c b/gcc/testsuite/gcc.target/i386/incoming-13.c index bbc8993d57..cad47a9c6b 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-13.c +++ b/gcc/testsuite/gcc.target/i386/incoming-13.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ extern double y(double *s3); diff --git a/gcc/testsuite/gcc.target/i386/incoming-14.c b/gcc/testsuite/gcc.target/i386/incoming-14.c index d27179d957..03ef50b693 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-14.c +++ b/gcc/testsuite/gcc.target/i386/incoming-14.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ extern int y(int *s3); diff --git a/gcc/testsuite/gcc.target/i386/incoming-15.c b/gcc/testsuite/gcc.target/i386/incoming-15.c index e6a1749044..897f3bc3cd 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-15.c +++ b/gcc/testsuite/gcc.target/i386/incoming-15.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ extern long long y(long long *s3); diff --git a/gcc/testsuite/gcc.target/i386/incoming-2.c b/gcc/testsuite/gcc.target/i386/incoming-2.c index 2947d3347c..4fc5629f0d 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-2.c +++ b/gcc/testsuite/gcc.target/i386/incoming-2.c @@ -1,5 +1,5 @@ /* PR middle-end/37009 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-3.c b/gcc/testsuite/gcc.target/i386/incoming-3.c index 1edbfda0b3..1d39b03f8b 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-3.c +++ b/gcc/testsuite/gcc.target/i386/incoming-3.c @@ -1,5 +1,5 @@ /* PR middle-end/37009 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-4.c b/gcc/testsuite/gcc.target/i386/incoming-4.c index 80c169c246..c3be961bc6 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-4.c +++ b/gcc/testsuite/gcc.target/i386/incoming-4.c @@ -1,5 +1,5 @@ /* PR middle-end/37009 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ #include <stdarg.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-5.c b/gcc/testsuite/gcc.target/i386/incoming-5.c index f083d40311..9bbecdb95e 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-5.c +++ b/gcc/testsuite/gcc.target/i386/incoming-5.c @@ -1,5 +1,5 @@ /* PR middle-end/37009 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-m32 -mincoming-stack-boundary=2 -mpreferred-stack-boundary=2" } */ extern void bar (double *); diff --git a/gcc/testsuite/gcc.target/i386/incoming-6.c b/gcc/testsuite/gcc.target/i386/incoming-6.c index 5cc4ab3f76..a2448ec3a3 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-6.c +++ b/gcc/testsuite/gcc.target/i386/incoming-6.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-7.c b/gcc/testsuite/gcc.target/i386/incoming-7.c index cdd6037968..0b8bbd5702 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-7.c +++ b/gcc/testsuite/gcc.target/i386/incoming-7.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-8.c b/gcc/testsuite/gcc.target/i386/incoming-8.c index 2dd8800fd6..61d9cb37d7 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-8.c +++ b/gcc/testsuite/gcc.target/i386/incoming-8.c @@ -1,6 +1,6 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ -/* { dg-options "-w -mstackrealign -O3 -msse2 -mpreferred-stack-boundary=4" } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O3 -msse2 -mno-avx -mpreferred-stack-boundary=4" } */ float foo (float f) diff --git a/gcc/testsuite/gcc.target/i386/incoming-9.c b/gcc/testsuite/gcc.target/i386/incoming-9.c index e43cbd6bc1..178693791f 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-9.c +++ b/gcc/testsuite/gcc.target/i386/incoming-9.c @@ -1,5 +1,5 @@ /* PR target/40838 */ -/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ /* { dg-options "-w -mstackrealign -O3 -mno-sse -mpreferred-stack-boundary=4" } */ float diff --git a/gcc/testsuite/gcc.target/i386/l_fma_1.h b/gcc/testsuite/gcc.target/i386/l_fma_1.h new file mode 100644 index 0000000000..4a0fd6e005 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_1.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_1 +#define l_fma_1 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_2.h b/gcc/testsuite/gcc.target/i386/l_fma_2.h new file mode 100644 index 0000000000..fd64b61fdc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_2.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_2 +#define l_fma_2 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_3.h b/gcc/testsuite/gcc.target/i386/l_fma_3.h new file mode 100644 index 0000000000..226af24a0b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_3.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_3 +#define l_fma_3 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_4.h b/gcc/testsuite/gcc.target/i386/l_fma_4.h new file mode 100644 index 0000000000..e33fe25ffd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_4.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_4 +#define l_fma_4 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_5.h b/gcc/testsuite/gcc.target/i386/l_fma_5.h new file mode 100644 index 0000000000..a754812e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_5.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_5 +#define l_fma_5 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_6.h b/gcc/testsuite/gcc.target/i386/l_fma_6.h new file mode 100644 index 0000000000..39be29ad37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_6.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_6 +#define l_fma_6 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_1.c b/gcc/testsuite/gcc.target/i386/l_fma_double_1.c new file mode 100644 index 0000000000..3451227b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213sd" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_2.c b/gcc/testsuite/gcc.target/i386/l_fma_double_2.c new file mode 100644 index 0000000000..e69bd7fe3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_3.c b/gcc/testsuite/gcc.target/i386/l_fma_double_3.c new file mode 100644 index 0000000000..00ed16dad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213sd" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_4.c b/gcc/testsuite/gcc.target/i386/l_fma_double_4.c new file mode 100644 index 0000000000..dbab6430c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_5.c b/gcc/testsuite/gcc.target/i386/l_fma_double_5.c new file mode 100644 index 0000000000..210d5670c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_6.c b/gcc/testsuite/gcc.target/i386/l_fma_double_6.c new file mode 100644 index 0000000000..68164818fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_double_6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_1.c b/gcc/testsuite/gcc.target/i386/l_fma_float_1.c new file mode 100644 index 0000000000..c98ba1169f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213ss" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_2.c b/gcc/testsuite/gcc.target/i386/l_fma_float_2.c new file mode 100644 index 0000000000..1dafed94e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_3.c b/gcc/testsuite/gcc.target/i386/l_fma_float_3.c new file mode 100644 index 0000000000..dbea8fe271 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213ss" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_4.c b/gcc/testsuite/gcc.target/i386/l_fma_float_4.c new file mode 100644 index 0000000000..5ff5dcb6da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_5.c b/gcc/testsuite/gcc.target/i386/l_fma_float_5.c new file mode 100644 index 0000000000..d83ebcc094 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_6.c b/gcc/testsuite/gcc.target/i386/l_fma_float_6.c new file mode 100644 index 0000000000..942ed7d9e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_float_6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/l_fma_main.h b/gcc/testsuite/gcc.target/i386/l_fma_main.h new file mode 100644 index 0000000000..a9dc5cd20e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_main.h @@ -0,0 +1,100 @@ + +#ifndef l_fma_main +#define l_fma_main + +#if DEBUG +#include <stdio.h> +#endif + +TYPE m1[32] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 + }; +TYPE m2[32] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 + }; +TYPE m3[32] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + }; +TYPE m4[32]; +int test_fails = 0; + +void +compare_result(char *title, TYPE *res) +{ + int i; + int good = 1; + for (i =0; i < 32; i++) + if (m4[i] != res[i]) + { + if (good) + { +#if DEBUG + printf ("!!!! %s miscompare\n", title); +#endif + good = 0; + } +#if DEBUG + printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]); +#endif + } + if (!good) + test_fails = 1; +} + +static void fma_test () +{ + test_noneg_add_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test0000", res_test0000); + + test_noneg_add_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test0001", res_test0001); + + test_noneg_add_neg_add (m1, m2, m3, m4, 32); + compare_result ("test0010", res_test0010); + + test_noneg_add_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test0011", res_test0011); + + test_noneg_sub_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test0100", res_test0100); + + test_noneg_sub_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test0101", res_test0101); + + test_noneg_sub_neg_add (m1, m2, m3, m4, 32); + compare_result ("test0110", res_test0110); + + test_noneg_sub_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test0111", res_test0111); + + test_neg_add_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test1000", res_test1000); + + test_neg_add_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test1001", res_test1001); + + test_neg_add_neg_add (m1, m2, m3, m4, 32); + compare_result ("test1010", res_test1010); + + test_neg_add_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test1011", res_test1011); + + test_neg_sub_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test1100", res_test1100); + + test_neg_sub_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test1101", res_test1101); + + test_neg_sub_neg_add (m1, m2, m3, m4, 32); + compare_result ("test1110", res_test1110); + + test_neg_sub_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test1111", res_test1111); + + if (test_fails) abort (); +} + +#endif diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c new file mode 100644 index 0000000000..f1d3c3a6b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_1.h" + +#include "fma_run_double_results_1.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c new file mode 100644 index 0000000000..db85598c10 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_2.h" + +#include "fma_run_double_results_2.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c new file mode 100644 index 0000000000..8043f6fbfb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_3.h" + +#include "fma_run_double_results_3.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c new file mode 100644 index 0000000000..eef05f58ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_4.h" + +#include "fma_run_double_results_4.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c new file mode 100644 index 0000000000..95b4b66d02 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_5.h" + +#include "fma_run_double_results_5.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c b/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c new file mode 100644 index 0000000000..24c1a78cdf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_6.h" + +#include "fma_run_double_results_6.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c new file mode 100644 index 0000000000..8a046131d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_1.h" + +#include "fma_run_float_results_1.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c new file mode 100644 index 0000000000..ea6df76f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_2.h" + +#include "fma_run_float_results_2.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c new file mode 100644 index 0000000000..5789867d35 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_3.h" + +#include "fma_run_float_results_3.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c new file mode 100644 index 0000000000..377370b890 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_4.h" + +#include "fma_run_float_results_4.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c new file mode 100644 index 0000000000..8b0cf3f0fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_5.h" + +#include "fma_run_float_results_5.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c b/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c new file mode 100644 index 0000000000..1300618dac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_6.h" + +#include "fma_run_float_results_6.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc/testsuite/gcc.target/i386/lea.c b/gcc/testsuite/gcc.target/i386/lea.c index f8f967e00f..bba345ef0c 100644 --- a/gcc/testsuite/gcc.target/i386/lea.c +++ b/gcc/testsuite/gcc.target/i386/lea.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentiumpro" } } */ /* { dg-options "-O2 -march=pentiumpro" } */ /* { dg-final { scan-assembler "leal" } } */ diff --git a/gcc/testsuite/gcc.target/i386/local.c b/gcc/testsuite/gcc.target/i386/local.c index 4cb5c81eb8..4423001f66 100644 --- a/gcc/testsuite/gcc.target/i386/local.c +++ b/gcc/testsuite/gcc.target/i386/local.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -funit-at-a-time" } */ -/* { dg-final { scan-assembler "magic\[^\\n\]*eax" { target ilp32 } } } */ -/* { dg-final { scan-assembler "magic\[^\\n\]*edi" { target lp64 } } } */ +/* { dg-final { scan-assembler "magic\[^\\n\]*eax" { target ia32 } } } */ +/* { dg-final { scan-assembler "magic\[^\\n\]*(edi|ecx)" { target { ! { ia32 } } } } } */ /* Verify that local calling convention is used. */ static t(int) __attribute__ ((noinline)); diff --git a/gcc/testsuite/gcc.target/i386/loop-1.c b/gcc/testsuite/gcc.target/i386/loop-1.c index 30cfd68f67..1af62f2849 100644 --- a/gcc/testsuite/gcc.target/i386/loop-1.c +++ b/gcc/testsuite/gcc.target/i386/loop-1.c @@ -1,6 +1,6 @@ /* PR optimization/9888 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mtune=k6 -O3" } */ /* Verify that GCC doesn't emit out of range 'loop' instructions. */ diff --git a/gcc/testsuite/gcc.target/i386/loop-2.c b/gcc/testsuite/gcc.target/i386/loop-2.c index cf44d30276..eec71636ed 100644 --- a/gcc/testsuite/gcc.target/i386/loop-2.c +++ b/gcc/testsuite/gcc.target/i386/loop-2.c @@ -1,7 +1,7 @@ /* PR optimization/9888 */ /* Originator: Jim Bray <jb@as220.org> */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mtune=k6 -Os" } */ enum reload_type diff --git a/gcc/testsuite/gcc.target/i386/loop-3.c b/gcc/testsuite/gcc.target/i386/loop-3.c index 782512f4c3..4fcd390729 100644 --- a/gcc/testsuite/gcc.target/i386/loop-3.c +++ b/gcc/testsuite/gcc.target/i386/loop-3.c @@ -2,7 +2,7 @@ /* Originator: Tim McGrath <misty-@charter.net> */ /* Testcase contributed by Eric Botcazou <ebotcazou@libertysurf.fr> */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mtune=k6 -O3 -ffast-math -funroll-loops" } */ extern void *memset (void *, int, __SIZE_TYPE__); diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-1.c b/gcc/testsuite/gcc.target/i386/lzcnt-1.c new file mode 100644 index 0000000000..f6240d1ba7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt " } */ +/* { dg-final { scan-assembler "lzcntw\[^\\n]*(%|)ax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt16 (unsigned int X) +{ + return __lzcnt16(X); +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-2.c b/gcc/testsuite/gcc.target/i386/lzcnt-2.c new file mode 100644 index 0000000000..329a11f975 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-2.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +short calc_lzcnt_u16 (short src) +{ + int i; + short res = 0; + + while ((res < 16) && (((src >> (15 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + short src = 0x7ace; + short res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u16 (src); + res = __lzcnt16 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-2a.c b/gcc/testsuite/gcc.target/i386/lzcnt-2a.c new file mode 100644 index 0000000000..fe1069feea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-2.c" + +/* { dg-final { scan-assembler "lzcntw" } } */ diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-3.c b/gcc/testsuite/gcc.target/i386/lzcnt-3.c new file mode 100644 index 0000000000..1477951174 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mlzcnt " } */ +/* { dg-final { scan-assembler "lzcntl\[^\\n]*(%|)eax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt32 (unsigned int X) +{ + return __lzcnt32(X); +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-4.c b/gcc/testsuite/gcc.target/i386/lzcnt-4.c new file mode 100644 index 0000000000..20653265bf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-4.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +int calc_lzcnt_u32 (int src) +{ + int i; + int res = 0; + + while ((res < 32) && (((src >> (31 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + int src = 0xce7ace0; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u32 (src); + res = __lzcnt32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-4a.c b/gcc/testsuite/gcc.target/i386/lzcnt-4a.c new file mode 100644 index 0000000000..6bba6a97df --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-4a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-4.c" + +/* { dg-final { scan-assembler "lzcntl" } } */ diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-5.c b/gcc/testsuite/gcc.target/i386/lzcnt-5.c new file mode 100644 index 0000000000..a4b9aafcd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mlzcnt" } */ +/* { dg-final { scan-assembler "lzcntq\[^\\n]*(%|)rax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt64 (unsigned long long X) +{ + return __lzcnt64(X); +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-6.c b/gcc/testsuite/gcc.target/i386/lzcnt-6.c new file mode 100644 index 0000000000..f0bf5dab04 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-6.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt && { ! ia32 } } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +long long calc_lzcnt_u64 (long long src) +{ + int i; + int res = 0; + + while ((res < 64) && (((src >> (63 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + long long src = 0xce7ace0ce7ace0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u64 (src); + res = __lzcnt64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-6a.c b/gcc/testsuite/gcc.target/i386/lzcnt-6a.c new file mode 100644 index 0000000000..209009344b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-6a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-6.c" + +/* { dg-final { scan-assembler "lzcntq" } } */ diff --git a/gcc/testsuite/gcc.target/i386/lzcnt-check.h b/gcc/testsuite/gcc.target/i386/lzcnt-check.h new file mode 100644 index 0000000000..8aad834d6a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/lzcnt-check.h @@ -0,0 +1,37 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void lzcnt_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + lzcnt_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run LZCNT test only if host has LZCNT support. */ + if (ecx & bit_LZCNT) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/max-stack-align.c b/gcc/testsuite/gcc.target/i386/max-stack-align.c index fa8050813f..9f37a63e01 100644 --- a/gcc/testsuite/gcc.target/i386/max-stack-align.c +++ b/gcc/testsuite/gcc.target/i386/max-stack-align.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-fomit-frame-pointer" } */ -/* { dg-require-effective-target lp64 } */ void foo() { diff --git a/gcc/testsuite/gcc.target/i386/memcpy-1.c b/gcc/testsuite/gcc.target/i386/memcpy-1.c index 51797e1891..bc6f95ab6b 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-1.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentiumpro -minline-all-stringops" } */ /* { dg-final { scan-assembler "rep" } } */ /* { dg-final { scan-assembler "movs" } } */ diff --git a/gcc/testsuite/gcc.target/i386/movbe-2.c b/gcc/testsuite/gcc.target/i386/movbe-2.c index d898f20dce..b322f774aa 100644 --- a/gcc/testsuite/gcc.target/i386/movbe-2.c +++ b/gcc/testsuite/gcc.target/i386/movbe-2.c @@ -15,5 +15,5 @@ bar () return __builtin_bswap64 (x); } -/* { dg-final { scan-assembler-times "movbe\[ \t\]" 4 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 4 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 { target { ! { ia32 } } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/movdi-rex64.c b/gcc/testsuite/gcc.target/i386/movdi-rex64.c new file mode 100644 index 0000000000..f8b8388106 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/movdi-rex64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-fPIE" } */ +/* { dg-require-effective-target pie } */ + +char *strcpy (char *dest, const char *src); + +static __thread char buffer[25]; +const char * error_message (void) +{ + strcpy (buffer, "Unknown code "); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/movq-2.c b/gcc/testsuite/gcc.target/i386/movq-2.c index 4a1accb583..37194b88d9 100644 --- a/gcc/testsuite/gcc.target/i386/movq-2.c +++ b/gcc/testsuite/gcc.target/i386/movq-2.c @@ -1,7 +1,7 @@ /* PR target/25199 */ /* { dg-do compile } */ /* { dg-options "-Os -mtune=pentium4" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ struct S { diff --git a/gcc/testsuite/gcc.target/i386/movq.c b/gcc/testsuite/gcc.target/i386/movq.c index ac0dfa2d94..53cb42143c 100644 --- a/gcc/testsuite/gcc.target/i386/movq.c +++ b/gcc/testsuite/gcc.target/i386/movq.c @@ -1,6 +1,6 @@ /* { dg-do compile } /* { dg-options "-Os -march=pentium4 -mtune=prescott" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ register char foo asm("edi"); char x; diff --git a/gcc/testsuite/gcc.target/i386/movsd.c b/gcc/testsuite/gcc.target/i386/movsd.c new file mode 100644 index 0000000000..32a19e79a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/movsd.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mfpmath=sse" } */ + +volatile double y; + +void +test () +{ + int z; + + for (z = 0; z < 1000; z++) + y = 1.23; +} + +/* { dg-final { scan-assembler-not "(fld|fst)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/nrv1.c b/gcc/testsuite/gcc.target/i386/nrv1.c index 5cd8b066d7..a02823697e 100644 --- a/gcc/testsuite/gcc.target/i386/nrv1.c +++ b/gcc/testsuite/gcc.target/i386/nrv1.c @@ -1,7 +1,7 @@ /* Verify that gimple-level NRV is occurring even for SSA_NAMEs. *./ /* { dg-do compile } */ /* { dg-options "-O -fdump-tree-optimized" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ _Complex double foo (_Complex double x) { diff --git a/gcc/testsuite/gcc.target/i386/opt-1.c b/gcc/testsuite/gcc.target/i386/opt-1.c index 28e2ef38c3..2585236a6b 100644 --- a/gcc/testsuite/gcc.target/i386/opt-1.c +++ b/gcc/testsuite/gcc.target/i386/opt-1.c @@ -1,7 +1,7 @@ /* Test the attribute((optimize)) really works. Do this test by checking whether we vectorize a simple loop. */ /* { dg-do compile } */ -/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */ /* { dg-final { scan-assembler "prefetcht0" } } */ /* { dg-final { scan-assembler "addps" } } */ /* { dg-final { scan-assembler "subss" } } */ diff --git a/gcc/testsuite/gcc.target/i386/opt-2.c b/gcc/testsuite/gcc.target/i386/opt-2.c index d2791e071c..1fa18c1f97 100644 --- a/gcc/testsuite/gcc.target/i386/opt-2.c +++ b/gcc/testsuite/gcc.target/i386/opt-2.c @@ -1,7 +1,7 @@ /* Test the attribute((optimize)) really works. Do this test by checking whether we vectorize a simple loop. */ /* { dg-do compile } */ -/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */ /* { dg-final { scan-assembler "prefetcht0" } } */ /* { dg-final { scan-assembler "addps" } } */ /* { dg-final { scan-assembler "subss" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-1.c b/gcc/testsuite/gcc.target/i386/pad-1.c index 770c44d890..c2e27c9e64 100644 --- a/gcc/testsuite/gcc.target/i386/pad-1.c +++ b/gcc/testsuite/gcc.target/i386/pad-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */ -/* { dg-final { scan-assembler "rep" } } */ +/* { dg-final { scan-assembler "rep" { target { ! x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "nop" } } */ void diff --git a/gcc/testsuite/gcc.target/i386/pad-10.c b/gcc/testsuite/gcc.target/i386/pad-10.c index e10d24c7da..d721c64a5c 100644 --- a/gcc/testsuite/gcc.target/i386/pad-10.c +++ b/gcc/testsuite/gcc.target/i386/pad-10.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ /* { dg-final { scan-assembler-not "nop" } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-2.c b/gcc/testsuite/gcc.target/i386/pad-2.c index 37743c483a..fe45c19d14 100644 --- a/gcc/testsuite/gcc.target/i386/pad-2.c +++ b/gcc/testsuite/gcc.target/i386/pad-2.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ -/* { dg-final { scan-assembler-times "nop" 8 } } */ +/* { dg-final { scan-assembler-times "nop" 8 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "rep" } } */ void diff --git a/gcc/testsuite/gcc.target/i386/pad-3.c b/gcc/testsuite/gcc.target/i386/pad-3.c index b9a547d07d..43d654f3f3 100644 --- a/gcc/testsuite/gcc.target/i386/pad-3.c +++ b/gcc/testsuite/gcc.target/i386/pad-3.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom -fno-pic" } */ /* { dg-final { scan-assembler-not "nop" } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-4.c b/gcc/testsuite/gcc.target/i386/pad-4.c index ad6b029e2c..7b198a63d5 100644 --- a/gcc/testsuite/gcc.target/i386/pad-4.c +++ b/gcc/testsuite/gcc.target/i386/pad-4.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom -fPIC" } */ /* { dg-final { scan-assembler-times "nop" 8 } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-5a.c b/gcc/testsuite/gcc.target/i386/pad-5a.c index d29e62816f..3a02262a0a 100644 --- a/gcc/testsuite/gcc.target/i386/pad-5a.c +++ b/gcc/testsuite/gcc.target/i386/pad-5a.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ /* { dg-final { scan-assembler-times "nop" 2 } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-5b.c b/gcc/testsuite/gcc.target/i386/pad-5b.c index 1d95bf32d2..4cd0340923 100644 --- a/gcc/testsuite/gcc.target/i386/pad-5b.c +++ b/gcc/testsuite/gcc.target/i386/pad-5b.c @@ -1,7 +1,8 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ -/* { dg-final { scan-assembler-times "nop" 4 } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "rep" } } */ int diff --git a/gcc/testsuite/gcc.target/i386/pad-6a.c b/gcc/testsuite/gcc.target/i386/pad-6a.c index e2db5ad1f4..97af9f9ca1 100644 --- a/gcc/testsuite/gcc.target/i386/pad-6a.c +++ b/gcc/testsuite/gcc.target/i386/pad-6a.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ /* { dg-final { scan-assembler-times "nop" 4 } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-6b.c b/gcc/testsuite/gcc.target/i386/pad-6b.c index d8f9bec5d4..82a3d331c4 100644 --- a/gcc/testsuite/gcc.target/i386/pad-6b.c +++ b/gcc/testsuite/gcc.target/i386/pad-6b.c @@ -1,7 +1,8 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ -/* { dg-final { scan-assembler-times "nop" 6 } } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "rep" } } */ int diff --git a/gcc/testsuite/gcc.target/i386/pad-7.c b/gcc/testsuite/gcc.target/i386/pad-7.c index 8904eca0bc..a4dbd260be 100644 --- a/gcc/testsuite/gcc.target/i386/pad-7.c +++ b/gcc/testsuite/gcc.target/i386/pad-7.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ /* { dg-final { scan-assembler-not "nop" } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pad-8.c b/gcc/testsuite/gcc.target/i386/pad-8.c index 0e939fa789..634cd7417c 100644 --- a/gcc/testsuite/gcc.target/i386/pad-8.c +++ b/gcc/testsuite/gcc.target/i386/pad-8.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ -/* { dg-final { scan-assembler-times "nop" 6 } } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "rep" } } */ int diff --git a/gcc/testsuite/gcc.target/i386/pad-9.c b/gcc/testsuite/gcc.target/i386/pad-9.c index 69e33446b7..226a0932bf 100644 --- a/gcc/testsuite/gcc.target/i386/pad-9.c +++ b/gcc/testsuite/gcc.target/i386/pad-9.c @@ -1,7 +1,8 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ -/* { dg-final { scan-assembler-times "nop" 4 } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler-not "rep" } } */ extern void bar (void); diff --git a/gcc/testsuite/gcc.target/i386/parity-1.c b/gcc/testsuite/gcc.target/i386/parity-1.c index eaf41cf082..1b0001ef2a 100644 --- a/gcc/testsuite/gcc.target/i386/parity-1.c +++ b/gcc/testsuite/gcc.target/i386/parity-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=k8" } */ +/* { dg-options "-O2 -march=k8 -mno-popcnt" } */ /* { dg-final { scan-assembler "setnp" } } */ int foo(unsigned int x) diff --git a/gcc/testsuite/gcc.target/i386/parity-2.c b/gcc/testsuite/gcc.target/i386/parity-2.c index 03a8061652..9adca35a66 100644 --- a/gcc/testsuite/gcc.target/i386/parity-2.c +++ b/gcc/testsuite/gcc.target/i386/parity-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=k8" } */ +/* { dg-options "-O2 -march=k8 -mno-popcnt" } */ /* { dg-final { scan-assembler "setnp" } } */ int foo(unsigned long long int x) diff --git a/gcc/testsuite/gcc.target/i386/pause-1.c b/gcc/testsuite/gcc.target/i386/pause-1.c new file mode 100644 index 0000000000..50eb8e7e2f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pause-1.c @@ -0,0 +1,11 @@ +/* Test that we generate pause instruction. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-final { scan-assembler-times "\\*pause" 1 } } */ + +#include <x86intrin.h> + +void foo(void) +{ + __pause(); +} diff --git a/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c b/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c index a846aae61b..c840c47e38 100644 --- a/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c +++ b/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentium4" } } */ /* { dg-options "-O2 -march=pentium4" } */ /* { dg-final { scan-assembler-not "imull" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pic-1.c b/gcc/testsuite/gcc.target/i386/pic-1.c index bdf6267c7d..af2424b075 100644 --- a/gcc/testsuite/gcc.target/i386/pic-1.c +++ b/gcc/testsuite/gcc.target/i386/pic-1.c @@ -1,6 +1,6 @@ /* PR target/8340 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ /* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ /* { dg-options "-fPIC" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr12092-1.c b/gcc/testsuite/gcc.target/i386/pr12092-1.c index d85807e8df..c230c84b7b 100644 --- a/gcc/testsuite/gcc.target/i386/pr12092-1.c +++ b/gcc/testsuite/gcc.target/i386/pr12092-1.c @@ -1,7 +1,7 @@ /* PR rtl-optimization/12092 */ /* Test case reduced by Andrew Pinski <pinskia@physics.uc.edu> */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mtune=i486 -march=pentium4 -fprefetch-loop-arrays" } */ void DecodeAC(int index,int *matrix) diff --git a/gcc/testsuite/gcc.target/i386/pr12329.c b/gcc/testsuite/gcc.target/i386/pr12329.c index 601480c028..e7b43a78ea 100644 --- a/gcc/testsuite/gcc.target/i386/pr12329.c +++ b/gcc/testsuite/gcc.target/i386/pr12329.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr21518.c b/gcc/testsuite/gcc.target/i386/pr21518.c index b42d9c9f0b..52cbed6f46 100644 --- a/gcc/testsuite/gcc.target/i386/pr21518.c +++ b/gcc/testsuite/gcc.target/i386/pr21518.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fPIC -fno-tree-pre" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ extern void __attribute__ ((regparm (3))) diff --git a/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc/testsuite/gcc.target/i386/pr22152.c index 4fade89ee7..6d24432cfb 100644 --- a/gcc/testsuite/gcc.target/i386/pr22152.c +++ b/gcc/testsuite/gcc.target/i386/pr22152.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ /* { dg-options "-O2 -msse2 -mno-vect8-ret-in-mem" { target i?86-*-solaris2.[89] *-*-vxworks* } } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ #include <mmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr22362.c b/gcc/testsuite/gcc.target/i386/pr22362.c index a7c78b12f8..04d6b27069 100644 --- a/gcc/testsuite/gcc.target/i386/pr22362.c +++ b/gcc/testsuite/gcc.target/i386/pr22362.c @@ -1,7 +1,7 @@ /* PR target/22362 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ register unsigned int reg0 __asm__ ("esi"); register unsigned int reg1 __asm__ ("edi"); diff --git a/gcc/testsuite/gcc.target/i386/pr22585.c b/gcc/testsuite/gcc.target/i386/pr22585.c index 9ba2da537f..e5f027ce86 100644 --- a/gcc/testsuite/gcc.target/i386/pr22585.c +++ b/gcc/testsuite/gcc.target/i386/pr22585.c @@ -2,7 +2,7 @@ /* Testcase reduced by Volker Reichelt */ /* { dg-do compile } */ /* { dg-options "-march=i386 -O -ffast-math" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ int foo (long double d, int i) diff --git a/gcc/testsuite/gcc.target/i386/pr23098.c b/gcc/testsuite/gcc.target/i386/pr23098.c index d91bf2a5f6..66ab0e1222 100644 --- a/gcc/testsuite/gcc.target/i386/pr23098.c +++ b/gcc/testsuite/gcc.target/i386/pr23098.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fPIC" } */ /* { dg-final { scan-assembler-not "\.LC\[0-9\]" { xfail *-*-vxworks* } } } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ double foo (float); diff --git a/gcc/testsuite/gcc.target/i386/pr25196.c b/gcc/testsuite/gcc.target/i386/pr25196.c index c3b69b87aa..6ebdee1748 100644 --- a/gcc/testsuite/gcc.target/i386/pr25196.c +++ b/gcc/testsuite/gcc.target/i386/pr25196.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-march=i386 -O3 -fomit-frame-pointer" } */ /* For this test case, we used to do an invalid load motion after diff --git a/gcc/testsuite/gcc.target/i386/pr25293.c b/gcc/testsuite/gcc.target/i386/pr25293.c index 6217da2a03..94923aba1b 100644 --- a/gcc/testsuite/gcc.target/i386/pr25293.c +++ b/gcc/testsuite/gcc.target/i386/pr25293.c @@ -1,7 +1,7 @@ /* PR target/25293 */ /* { dg-do compile } */ /* { dg-options "-mpreferred-stack-boundary=2 -mtune=i586 -O2 -fomit-frame-pointer -g" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ struct T { unsigned short t1, t2, t3, t4, t5, t6, t7; }; struct S { struct T s1; unsigned short s2, s3; }; diff --git a/gcc/testsuite/gcc.target/i386/pr25654.c b/gcc/testsuite/gcc.target/i386/pr25654.c index 2d7ef221f3..d53a297947 100644 --- a/gcc/testsuite/gcc.target/i386/pr25654.c +++ b/gcc/testsuite/gcc.target/i386/pr25654.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mpreferred-stack-boundary=2 -march=i686 -frename-registers" } */ extern void abort (void) __attribute__((noreturn)); diff --git a/gcc/testsuite/gcc.target/i386/pr26449.c b/gcc/testsuite/gcc.target/i386/pr26449.c index 7a61296844..4a976ff7fa 100644 --- a/gcc/testsuite/gcc.target/i386/pr26449.c +++ b/gcc/testsuite/gcc.target/i386/pr26449.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -ftree-vectorize -march=pentium4 -std=c99" } */ void matmul_i4 (int bbase_yn, int xcount) diff --git a/gcc/testsuite/gcc.target/i386/pr26778.c b/gcc/testsuite/gcc.target/i386/pr26778.c index 6f6f277258..f871b5d61f 100644 --- a/gcc/testsuite/gcc.target/i386/pr26778.c +++ b/gcc/testsuite/gcc.target/i386/pr26778.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=pentium3" } */ typedef union { diff --git a/gcc/testsuite/gcc.target/i386/pr26826.c b/gcc/testsuite/gcc.target/i386/pr26826.c index 8adab3a363..062e1737f6 100644 --- a/gcc/testsuite/gcc.target/i386/pr26826.c +++ b/gcc/testsuite/gcc.target/i386/pr26826.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O -fomit-frame-pointer -march=i586" } */ void foo(char* p, char c, int i) diff --git a/gcc/testsuite/gcc.target/i386/pr27266.c b/gcc/testsuite/gcc.target/i386/pr27266.c index 73e7c596f3..8735780c77 100644 --- a/gcc/testsuite/gcc.target/i386/pr27266.c +++ b/gcc/testsuite/gcc.target/i386/pr27266.c @@ -2,7 +2,7 @@ The testcase below used to trigger an ICE. */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-march=pentium" } */ signed long long sll; diff --git a/gcc/testsuite/gcc.target/i386/pr29978.c b/gcc/testsuite/gcc.target/i386/pr29978.c index 8c0bf9f5e7..e27bbdcd82 100644 --- a/gcc/testsuite/gcc.target/i386/pr29978.c +++ b/gcc/testsuite/gcc.target/i386/pr29978.c @@ -13,4 +13,4 @@ f (long long v) } /* Verify there are no redundant jumps jl .L2; jle .L2 */ -/* { dg-final { scan-assembler-not "jl\[^e\]*\\.L" { target ilp32 } } } */ +/* { dg-final { scan-assembler-not "jl\[^e\]*\\.L" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr30505.c b/gcc/testsuite/gcc.target/i386/pr30505.c index 9f8fc42677..3cebbe6953 100644 --- a/gcc/testsuite/gcc.target/i386/pr30505.c +++ b/gcc/testsuite/gcc.target/i386/pr30505.c @@ -1,6 +1,6 @@ /* PR inline-asm/30505 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ unsigned long long a, c; diff --git a/gcc/testsuite/gcc.target/i386/pr30961-1.c b/gcc/testsuite/gcc.target/i386/pr30961-1.c index c225943355..c7c5e53833 100644 --- a/gcc/testsuite/gcc.target/i386/pr30961-1.c +++ b/gcc/testsuite/gcc.target/i386/pr30961-1.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2" } */ double diff --git a/gcc/testsuite/gcc.target/i386/pr31628.c b/gcc/testsuite/gcc.target/i386/pr31628.c index 121d9c6362..eece2a0dbe 100644 --- a/gcc/testsuite/gcc.target/i386/pr31628.c +++ b/gcc/testsuite/gcc.target/i386/pr31628.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -fPIC" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ typedef int tt, *lptt; diff --git a/gcc/testsuite/gcc.target/i386/pr32000-2.c b/gcc/testsuite/gcc.target/i386/pr32000-2.c index 6f1056099c..374b23f834 100644 --- a/gcc/testsuite/gcc.target/i386/pr32000-2.c +++ b/gcc/testsuite/gcc.target/i386/pr32000-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "" { ! { ilp32 && dfp } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ /* { dg-options "-O -msse2 -std=gnu99 -mpreferred-stack-boundary=2" } */ /* { dg-require-effective-target sse2 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32661-1.c b/gcc/testsuite/gcc.target/i386/pr32661-1.c index 9411c28872..39cd8f90c8 100644 --- a/gcc/testsuite/gcc.target/i386/pr32661-1.c +++ b/gcc/testsuite/gcc.target/i386/pr32661-1.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr32708-2.c b/gcc/testsuite/gcc.target/i386/pr32708-2.c index dc31c42a73..f28caf91a1 100644 --- a/gcc/testsuite/gcc.target/i386/pr32708-2.c +++ b/gcc/testsuite/gcc.target/i386/pr32708-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mtune=k8" } */ typedef long long __v2di __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr32708-3.c b/gcc/testsuite/gcc.target/i386/pr32708-3.c index dae9a52d12..77e50b241b 100644 --- a/gcc/testsuite/gcc.target/i386/pr32708-3.c +++ b/gcc/testsuite/gcc.target/i386/pr32708-3.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mtune=core2" } */ typedef long long __v2di __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr34256.c b/gcc/testsuite/gcc.target/i386/pr34256.c index e207ecef7c..4ce7e30c5f 100644 --- a/gcc/testsuite/gcc.target/i386/pr34256.c +++ b/gcc/testsuite/gcc.target/i386/pr34256.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=core2" } */ #include <mmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr34312.c b/gcc/testsuite/gcc.target/i386/pr34312.c index 846c285379..876ac40401 100644 --- a/gcc/testsuite/gcc.target/i386/pr34312.c +++ b/gcc/testsuite/gcc.target/i386/pr34312.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ /* { dg-options "-O2 -march=pentium-m -fpic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr34522.c b/gcc/testsuite/gcc.target/i386/pr34522.c index c79745bd75..eb1e03a77c 100644 --- a/gcc/testsuite/gcc.target/i386/pr34522.c +++ b/gcc/testsuite/gcc.target/i386/pr34522.c @@ -1,6 +1,6 @@ /* { dg-options "-O2" } */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ int test(long long a, long long b) { diff --git a/gcc/testsuite/gcc.target/i386/pr35160.c b/gcc/testsuite/gcc.target/i386/pr35160.c index 12394ec6de..259c2a3eae 100644 --- a/gcc/testsuite/gcc.target/i386/pr35160.c +++ b/gcc/testsuite/gcc.target/i386/pr35160.c @@ -1,6 +1,6 @@ /* PR inline-asm/35160 */ /* { dg-do run } */ -/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr35281.c b/gcc/testsuite/gcc.target/i386/pr35281.c index 70e93cbeac..efd5c3d63a 100644 --- a/gcc/testsuite/gcc.target/i386/pr35281.c +++ b/gcc/testsuite/gcc.target/i386/pr35281.c @@ -1,6 +1,6 @@ /* { dg-options "-O2" } */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ unsigned long long a; unsigned int b; diff --git a/gcc/testsuite/gcc.target/i386/pr35767-4.c b/gcc/testsuite/gcc.target/i386/pr35767-4.c index e12f64ffe9..1b58cfd4af 100644 --- a/gcc/testsuite/gcc.target/i386/pr35767-4.c +++ b/gcc/testsuite/gcc.target/i386/pr35767-4.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target dfp } */ /* { dg-options "-O -march=x86-64 -mtune=generic -std=gnu99" } */ /* { dg-final { scan-assembler-not "movdqu" } } */ -/* { dg-final { scan-assembler "movdqa" } } */ +/* { dg-final { scan-assembler "movdqa" { target { ! x86_64-*-mingw* } } } } */ extern _Decimal128 foo (_Decimal128, _Decimal128, _Decimal128); diff --git a/gcc/testsuite/gcc.target/i386/pr36246.c b/gcc/testsuite/gcc.target/i386/pr36246.c index 4f3e155cb3..51b8c349b5 100644 --- a/gcc/testsuite/gcc.target/i386/pr36246.c +++ b/gcc/testsuite/gcc.target/i386/pr36246.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */ typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc/testsuite/gcc.target/i386/pr36533.c index a271fea1ca..8d71ece199 100644 --- a/gcc/testsuite/gcc.target/i386/pr36533.c +++ b/gcc/testsuite/gcc.target/i386/pr36533.c @@ -1,5 +1,5 @@ /* PR target/36533 */ -/* { dg-do run { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */ +/* { dg-do run { target { mmap && ilp32 } } } */ /* { dg-options "-Os" } */ #include <string.h> #include <sys/mman.h> diff --git a/gcc/testsuite/gcc.target/i386/pr36786.c b/gcc/testsuite/gcc.target/i386/pr36786.c index 692518e1bd..6b62e80e75 100644 --- a/gcc/testsuite/gcc.target/i386/pr36786.c +++ b/gcc/testsuite/gcc.target/i386/pr36786.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ typedef int DItype __attribute__ ((mode (DI))); typedef unsigned int UDItype __attribute__ ((mode (DI))); diff --git a/gcc/testsuite/gcc.target/i386/pr37275.c b/gcc/testsuite/gcc.target/i386/pr37275.c index 070dab554c..cf748879e8 100644 --- a/gcc/testsuite/gcc.target/i386/pr37275.c +++ b/gcc/testsuite/gcc.target/i386/pr37275.c @@ -1,5 +1,5 @@ /* PR middle-end/37275 */ -/* { dg-do compile { target ilp32 } } */ +/* { dg-do compile { target ia32 } } */ /* { dg-options "-g -dA -O2 -march=i686 -fstack-protector" } */ /* { dg-require-visibility "" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr37843-3.c b/gcc/testsuite/gcc.target/i386/pr37843-3.c index ed6478ee57..56f1170eba 100644 --- a/gcc/testsuite/gcc.target/i386/pr37843-3.c +++ b/gcc/testsuite/gcc.target/i386/pr37843-3.c @@ -1,5 +1,5 @@ /* Test for stack alignment with sibcall optimization. */ -/* { dg-do compile { target { ilp32 && nonpic } } } */ +/* { dg-do compile { target { ia32 && nonpic } } } */ /* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */ /* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr37843-4.c b/gcc/testsuite/gcc.target/i386/pr37843-4.c index f5e024cc42..cd56bae415 100644 --- a/gcc/testsuite/gcc.target/i386/pr37843-4.c +++ b/gcc/testsuite/gcc.target/i386/pr37843-4.c @@ -1,10 +1,10 @@ /* Test for stack alignment with sibcall optimization. */ -/* { dg-do compile { target { ilp32 && nonpic } } } */ +/* { dg-do compile { target { ia32 && nonpic } } } */ /* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */ /* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ -/* { dg-final { scan-assembler-not "call\[\\t \]*foo" } } */ -/* { dg-final { scan-assembler "jmp\[\\t \]*foo" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */ extern int foo (void); diff --git a/gcc/testsuite/gcc.target/i386/pr38824.c b/gcc/testsuite/gcc.target/i386/pr38824.c index 637abfde88..9fbfc502d6 100644 --- a/gcc/testsuite/gcc.target/i386/pr38824.c +++ b/gcc/testsuite/gcc.target/i386/pr38824.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse" } */ +/* { dg-options "-O2 -msse -mno-sse2" } */ typedef float v4sf __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr39082-1.c b/gcc/testsuite/gcc.target/i386/pr39082-1.c index 0a788d1165..1d8be2a7d9 100644 --- a/gcc/testsuite/gcc.target/i386/pr39082-1.c +++ b/gcc/testsuite/gcc.target/i386/pr39082-1.c @@ -1,7 +1,7 @@ /* PR target/39082 */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ union un { diff --git a/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc/testsuite/gcc.target/i386/pr39162.c index 09ea615e8f..c549106adb 100644 --- a/gcc/testsuite/gcc.target/i386/pr39162.c +++ b/gcc/testsuite/gcc.target/i386/pr39162.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Wno-psabi -msse2 -mno-avx" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/pr39315-3.c b/gcc/testsuite/gcc.target/i386/pr39315-3.c index 07862db603..3b61ad0253 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-3.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-3.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler-not "movups" } } */ /* { dg-final { scan-assembler-not "movlps" } } */ /* { dg-final { scan-assembler-not "movhps" } } */ -/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" { target { ! x86_64-*-mingw* } } } } */ /* { dg-final { scan-assembler "movaps" } } */ typedef float __m128 __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr39431.c b/gcc/testsuite/gcc.target/i386/pr39431.c index 756bdb9ebb..0db7d56430 100644 --- a/gcc/testsuite/gcc.target/i386/pr39431.c +++ b/gcc/testsuite/gcc.target/i386/pr39431.c @@ -1,7 +1,7 @@ /* PR target/39431 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-options "-O2 -march=i686 -fpic" { target { ilp32 && fpic } } } */ +/* { dg-options "-O2 -march=i686 -fpic" { target { ia32 && fpic } } } */ extern void bar (char *, int); diff --git a/gcc/testsuite/gcc.target/i386/pr39496.c b/gcc/testsuite/gcc.target/i386/pr39496.c index e4132a1165..e14c87513c 100644 --- a/gcc/testsuite/gcc.target/i386/pr39496.c +++ b/gcc/testsuite/gcc.target/i386/pr39496.c @@ -1,5 +1,5 @@ /* PR target/39496 */ -/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */ +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && ia32 } } } */ /* { dg-options "-O0 -fverbose-asm -fno-omit-frame-pointer -mtune=i686 -msse2 -mfpmath=sse" } */ /* Verify that {foo,bar}{,2}param are all passed on the stack, using normal calling conventions, when not optimizing. */ diff --git a/gcc/testsuite/gcc.target/i386/pr39543-2.c b/gcc/testsuite/gcc.target/i386/pr39543-2.c index 04e980efa7..7f4e5a42a1 100644 --- a/gcc/testsuite/gcc.target/i386/pr39543-2.c +++ b/gcc/testsuite/gcc.target/i386/pr39543-2.c @@ -1,7 +1,7 @@ /* PR inline-asm/39543 */ /* { dg-do compile } */ /* { dg-options "-O3" } */ -/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ float __attribute__ ((aligned (16))) s0[128]; const float s1 = 0.707; diff --git a/gcc/testsuite/gcc.target/i386/pr39911.c b/gcc/testsuite/gcc.target/i386/pr39911.c index fe63ff005f..8a78c0a289 100644 --- a/gcc/testsuite/gcc.target/i386/pr39911.c +++ b/gcc/testsuite/gcc.target/i386/pr39911.c @@ -33,11 +33,13 @@ bar3 () asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23)); asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23)); +#ifndef __x86_64__ if (sizeof (void *) == sizeof (int)) { asm volatile ("pop%z0 %0": "=m" (foo)); asm volatile ("pop%z0 %0": "=r" (foo)); } +#endif } void diff --git a/gcc/testsuite/gcc.target/i386/pr40718.c b/gcc/testsuite/gcc.target/i386/pr40718.c index f6029ed98a..1df3548e0e 100644 --- a/gcc/testsuite/gcc.target/i386/pr40718.c +++ b/gcc/testsuite/gcc.target/i386/pr40718.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -foptimize-sibling-calls" } */ void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr40906-1.c b/gcc/testsuite/gcc.target/i386/pr40906-1.c index 77e7c9b1ea..233d8fdcb0 100644 --- a/gcc/testsuite/gcc.target/i386/pr40906-1.c +++ b/gcc/testsuite/gcc.target/i386/pr40906-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args" } */ +/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args" { target *-*-mingw* *-*-cygwin* } } */ void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr40906-2.c b/gcc/testsuite/gcc.target/i386/pr40906-2.c index f0eda001cd..58b076e1f5 100644 --- a/gcc/testsuite/gcc.target/i386/pr40906-2.c +++ b/gcc/testsuite/gcc.target/i386/pr40906-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args -m128bit-long-double" } */ +/* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -m128bit-long-double" { target *-*-mingw* *-*-cygwin* } } */ void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr40906-3.c b/gcc/testsuite/gcc.target/i386/pr40906-3.c index d83833fa8d..ac7d183b71 100644 --- a/gcc/testsuite/gcc.target/i386/pr40906-3.c +++ b/gcc/testsuite/gcc.target/i386/pr40906-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target *-*-linux* } } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -msse2 -mpush-args -mno-accumulate-outgoing-args" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr40934.c b/gcc/testsuite/gcc.target/i386/pr40934.c index 41f46f8811..651172299e 100644 --- a/gcc/testsuite/gcc.target/i386/pr40934.c +++ b/gcc/testsuite/gcc.target/i386/pr40934.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -march=i586 -ffast-math" } */ extern double host_frametime; diff --git a/gcc/testsuite/gcc.target/i386/pr41900.c b/gcc/testsuite/gcc.target/i386/pr41900.c index 55f712d1fa..a23214c76f 100644 --- a/gcc/testsuite/gcc.target/i386/pr41900.c +++ b/gcc/testsuite/gcc.target/i386/pr41900.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=2" } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr42589.c b/gcc/testsuite/gcc.target/i386/pr42589.c index 1366ef5b32..863372b562 100644 --- a/gcc/testsuite/gcc.target/i386/pr42589.c +++ b/gcc/testsuite/gcc.target/i386/pr42589.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */ /* { dg-options "-O2 -march=i486" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr43662.c b/gcc/testsuite/gcc.target/i386/pr43662.c index 246c8aafa6..2896a1a52c 100644 --- a/gcc/testsuite/gcc.target/i386/pr43662.c +++ b/gcc/testsuite/gcc.target/i386/pr43662.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target lp64 } } */ /* { dg-options "-O2" } */ void __attribute__ ((ms_abi)) foo (void) diff --git a/gcc/testsuite/gcc.target/i386/pr43671.c b/gcc/testsuite/gcc.target/i386/pr43671.c index 958eaff445..388cd65e03 100644 --- a/gcc/testsuite/gcc.target/i386/pr43671.c +++ b/gcc/testsuite/gcc.target/i386/pr43671.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mtune=i686 -O1 -fpeel-loops -fschedule-insns2 -ftree-vectorize -fsched2-use-superblocks" } */ extern void abort (); diff --git a/gcc/testsuite/gcc.target/i386/pr43766.c b/gcc/testsuite/gcc.target/i386/pr43766.c index 731b780ba6..8ac16137f7 100644 --- a/gcc/testsuite/gcc.target/i386/pr43766.c +++ b/gcc/testsuite/gcc.target/i386/pr43766.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-options "-O2 -msse -mregparm=3" { target ilp32 } } */ +/* { dg-options "-O2 -msse -mregparm=3" { target ia32 } } */ void p (int *a, int i) { diff --git a/gcc/testsuite/gcc.target/i386/pr43869.c b/gcc/testsuite/gcc.target/i386/pr43869.c index fdc6461cb6..4157db1d16 100644 --- a/gcc/testsuite/gcc.target/i386/pr43869.c +++ b/gcc/testsuite/gcc.target/i386/pr43869.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target lp64 } } */ int __attribute__((__noinline__)) bugged(float f1, float f2, float f3, float f4, diff --git a/gcc/testsuite/gcc.target/i386/pr44130.c b/gcc/testsuite/gcc.target/i386/pr44130.c index 5c18bfaf75..3e50c7b153 100644 --- a/gcc/testsuite/gcc.target/i386/pr44130.c +++ b/gcc/testsuite/gcc.target/i386/pr44130.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ +/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler "vmovaps\[\\t \]*%ymm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr44942.c b/gcc/testsuite/gcc.target/i386/pr44942.c index 4664f7e0d5..d8164845c0 100644 --- a/gcc/testsuite/gcc.target/i386/pr44942.c +++ b/gcc/testsuite/gcc.target/i386/pr44942.c @@ -1,5 +1,5 @@ /* PR target/44942 */ -/* { dg-do run { target lp64 } } */ +/* { dg-do run { target { ! { ia32 } } } } */ #include <stdarg.h> #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr44948-2a.c b/gcc/testsuite/gcc.target/i386/pr44948-2a.c index 120346e3ea..d84d1a6b9a 100644 --- a/gcc/testsuite/gcc.target/i386/pr44948-2a.c +++ b/gcc/testsuite/gcc.target/i386/pr44948-2a.c @@ -1,7 +1,7 @@ /* PR target/44948 */ /* { dg-do run } */ /* { dg-options "-O -Wno-psabi -mno-sse -mtune=generic" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target sse2_runtime } */ /* { dg-additional-sources pr44948-2b.c } */ diff --git a/gcc/testsuite/gcc.target/i386/pr45234.c b/gcc/testsuite/gcc.target/i386/pr45234.c index b11096b65e..3996fa27fb 100644 --- a/gcc/testsuite/gcc.target/i386/pr45234.c +++ b/gcc/testsuite/gcc.target/i386/pr45234.c @@ -1,6 +1,6 @@ /* PR middle-end/45234 */ /* { dg-do compile } */ -/* { dg-options "-march=i586" { target ilp32 } } */ +/* { dg-options "-march=i586" { target ia32 } } */ struct S { union { double b[4]; } a[18]; } s, a[5]; void foo (struct S); diff --git a/gcc/testsuite/gcc.target/i386/pr45336-1.c b/gcc/testsuite/gcc.target/i386/pr45336-1.c index e2b4f658a3..db6c9400d3 100644 --- a/gcc/testsuite/gcc.target/i386/pr45336-1.c +++ b/gcc/testsuite/gcc.target/i386/pr45336-1.c @@ -8,7 +8,7 @@ /* { dg-final { scan-assembler-not "cwtl" } } */ /* { dg-final { scan-assembler "pextrb" } } */ /* { dg-final { scan-assembler "pextrw" } } */ -/* { dg-final { scan-assembler "pextrd" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ #include <smmintrin.h> unsigned int foo8(__m128i x) { return _mm_extract_epi8(x, 4); } diff --git a/gcc/testsuite/gcc.target/i386/pr45336-2.c b/gcc/testsuite/gcc.target/i386/pr45336-2.c index 8347002166..3e51591fc4 100644 --- a/gcc/testsuite/gcc.target/i386/pr45336-2.c +++ b/gcc/testsuite/gcc.target/i386/pr45336-2.c @@ -1,6 +1,5 @@ /* PR target/45336 */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -msse4 -mtune=generic" } */ /* { dg-final { scan-assembler-not "movsbl" } } */ /* { dg-final { scan-assembler-not "movswl" } } */ @@ -10,7 +9,7 @@ /* { dg-final { scan-assembler-not "cltq" } } */ /* { dg-final { scan-assembler "pextrb" } } */ /* { dg-final { scan-assembler "pextrw" } } */ -/* { dg-final { scan-assembler "pextrd" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ #include <smmintrin.h> unsigned long long int foo8(__m128i x) { return _mm_extract_epi8(x, 4); } diff --git a/gcc/testsuite/gcc.target/i386/pr45336-3.c b/gcc/testsuite/gcc.target/i386/pr45336-3.c index 055e314870..b2168c006c 100644 --- a/gcc/testsuite/gcc.target/i386/pr45336-3.c +++ b/gcc/testsuite/gcc.target/i386/pr45336-3.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler "(movswl|cwtl)" } } */ /* { dg-final { scan-assembler "pextrb" } } */ /* { dg-final { scan-assembler "pextrw" } } */ -/* { dg-final { scan-assembler "pextrd" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ #include <smmintrin.h> int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); } diff --git a/gcc/testsuite/gcc.target/i386/pr45336-4.c b/gcc/testsuite/gcc.target/i386/pr45336-4.c index 00c9319162..8b66a6a1da 100644 --- a/gcc/testsuite/gcc.target/i386/pr45336-4.c +++ b/gcc/testsuite/gcc.target/i386/pr45336-4.c @@ -1,13 +1,12 @@ /* PR target/45336 */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -msse4 -mtune=generic" } */ /* { dg-final { scan-assembler "movsbq" } } */ /* { dg-final { scan-assembler "movswq" } } */ /* { dg-final { scan-assembler "(cltq|movslq)" } } */ /* { dg-final { scan-assembler "pextrb" } } */ /* { dg-final { scan-assembler "pextrw" } } */ -/* { dg-final { scan-assembler "pextrd" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ #include <smmintrin.h> long long int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); } diff --git a/gcc/testsuite/gcc.target/i386/pr45352-2.c b/gcc/testsuite/gcc.target/i386/pr45352-2.c index 5f9ebb18fc..52e5522a87 100644 --- a/gcc/testsuite/gcc.target/i386/pr45352-2.c +++ b/gcc/testsuite/gcc.target/i386/pr45352-2.c @@ -4,6 +4,8 @@ typedef char uint8_t; typedef uint32_t; typedef vo_frame_t; +__extension__ typedef __SIZE_TYPE__ size_t; + struct vo_frame_s { uint8_t base[3]; @@ -43,7 +45,7 @@ mpeg2dec_accel_t; static int bitstream_init (picture_t * picture, void *start) { picture->bitstream_ptr = start; - return (int) (long) start; + return (int) (size_t) start; } static slice_xvmc_init (picture_t * picture, int code) { @@ -56,7 +58,7 @@ static slice_xvmc_init (picture_t * picture, int code) picture->f_motion.ref [0] [0] - = (char) (long) (forward_reference_frame->base + (offset ? picture->pitches[0] : 0)); + = (char) (size_t) (forward_reference_frame->base + (offset ? picture->pitches[0] : 0)); picture->f_motion.ref[0][1] = (offset); if (picture->picture_structure) picture->pitches[0] <<= picture->pitches[1] <<= 1; @@ -91,7 +93,7 @@ void mpeg2_xvmc_slice (mpeg2dec_accel_t * accel, picture_t * picture, int code, uint8_t buffer,int mba_inc) { - xine_xvmc_t * xvmc = (xine_xvmc_t *) (long) bitstream_init (picture, (void *) (long) buffer); + xine_xvmc_t * xvmc = (xine_xvmc_t *) (size_t) bitstream_init (picture, (void *) (size_t) buffer); slice_xvmc_init (picture, code); while (1) { diff --git a/gcc/testsuite/gcc.target/i386/pr45852.c b/gcc/testsuite/gcc.target/i386/pr45852.c index b0ba0935de..8b7bbfbe7a 100644 --- a/gcc/testsuite/gcc.target/i386/pr45852.c +++ b/gcc/testsuite/gcc.target/i386/pr45852.c @@ -1,6 +1,6 @@ /* PR middle-end/45852 */ /* { dg-options "-O2 -mcmodel=small" } */ -/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && lp64 } } } */ +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && { ! { ia32 } } } } } */ /* { dg-require-visibility "" } */ struct S { int s; }; diff --git a/gcc/testsuite/gcc.target/i386/pr46226.c b/gcc/testsuite/gcc.target/i386/pr46226.c index 389158a03e..168d80e2be 100644 --- a/gcc/testsuite/gcc.target/i386/pr46226.c +++ b/gcc/testsuite/gcc.target/i386/pr46226.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-Os -fomit-frame-pointer -mno-accumulate-outgoing-args -fno-asynchronous-unwind-tables" } */ +/* { dg-options "-Os -fomit-frame-pointer -fno-asynchronous-unwind-tables" { target *-*-mingw* *-*-cygwin* } } */ extern void abort(void); diff --git a/gcc/testsuite/gcc.target/i386/pr46254.c b/gcc/testsuite/gcc.target/i386/pr46254.c new file mode 100644 index 0000000000..512287a5b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr46254.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large" } */ + +__int128 i; + +void test () +{ + __sync_val_compare_and_swap (&i, i, i); +} diff --git a/gcc/testsuite/gcc.target/i386/pr46295.c b/gcc/testsuite/gcc.target/i386/pr46295.c index 219f34e8fe..b7fccb7fb3 100644 --- a/gcc/testsuite/gcc.target/i386/pr46295.c +++ b/gcc/testsuite/gcc.target/i386/pr46295.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -mavx -mtune=generic -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ typedef double EXPRESS[5]; void Parse_Rel_Factor (EXPRESS Express,int *Terms); diff --git a/gcc/testsuite/gcc.target/i386/pr46470.c b/gcc/testsuite/gcc.target/i386/pr46470.c index 256b57f6ad..11eb51a039 100644 --- a/gcc/testsuite/gcc.target/i386/pr46470.c +++ b/gcc/testsuite/gcc.target/i386/pr46470.c @@ -1,12 +1,13 @@ /* { dg-do compile } */ /* The pic register save adds unavoidable stack pointer references. */ -/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ /* These options are selected to ensure 1 word needs to be allocated on the stack to maintain alignment for the call. This should be transformed to push+pop. We also want to force unwind info updates. */ /* { dg-options "-Os -fomit-frame-pointer -fasynchronous-unwind-tables" } */ -/* { dg-options "-Os -fomit-frame-pointer -mpreferred-stack-boundary=3 -fasynchronous-unwind-tables" { target ilp32 } } */ - +/* { dg-options "-Os -fomit-frame-pointer -mpreferred-stack-boundary=3 -fasynchronous-unwind-tables" { target ia32 } } */ +/* ms_abi has reserved stack-region. */ +/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ void f(); void g() { f(); f(); } diff --git a/gcc/testsuite/gcc.target/i386/pr46939.c b/gcc/testsuite/gcc.target/i386/pr46939.c index 2f50e37ee0..0fd8607bbd 100644 --- a/gcc/testsuite/gcc.target/i386/pr46939.c +++ b/gcc/testsuite/gcc.target/i386/pr46939.c @@ -1,5 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ + +__extension__ typedef __SIZE_TYPE__ size_t; + int php_filter_parse_int (char const *str, unsigned int str_len, long *ret) { @@ -23,7 +26,7 @@ php_filter_parse_int (char const *str, unsigned int str_len, long *ret) default:; break; } - if ((unsigned long) str < (unsigned long) end) + if ((size_t) str < (size_t) end) { if ((int const) *str >= 49) { @@ -59,7 +62,7 @@ php_filter_parse_int (char const *str, unsigned int str_len, long *ret) { return (-1); } - while ((unsigned long) str < (unsigned long) end) + while ((size_t) str < (size_t) end) { if ((int const) *str >= 48) { diff --git a/gcc/testsuite/gcc.target/i386/pr47315.c b/gcc/testsuite/gcc.target/i386/pr47315.c new file mode 100644 index 0000000000..871d3f1bd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr47315.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvzeroupper" } */ + +__attribute__ ((__target__ ("avx"))) +float bar (float f) {} + +void foo (float f) +{ + bar (f); +} diff --git a/gcc/testsuite/gcc.target/i386/pr47381.c b/gcc/testsuite/gcc.target/i386/pr47381.c new file mode 100644 index 0000000000..c4b2127c28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr47381.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=atom" } */ + +struct foo_t { + int limit; +} foo[3]; +void +bar () { + int i; + for (i = 0; i < 3; i++) { + __builtin_memset (&foo[i], 0, sizeof(*foo)); + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr47449.c b/gcc/testsuite/gcc.target/i386/pr47449.c new file mode 100644 index 0000000000..99ef32f261 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr47449.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (void *, void *); +int +foo (void *p1, void *p2) +{ + int ret1, ret2; + __asm ("" : "=D" (ret1), "=S" (ret2)); + bar (p1, p2); + return ret1 + ret2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr47502-1.c b/gcc/testsuite/gcc.target/i386/pr47502-1.c new file mode 100644 index 0000000000..727afe944e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr47502-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +foo (const void *xxxxx, void *yyyyy, long y) +{ + asm volatile ("" :: "c" ((xxxxx)), "d" ((yyyyy)), "S" (y)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr47502-2.c b/gcc/testsuite/gcc.target/i386/pr47502-2.c new file mode 100644 index 0000000000..a8dc1ca018 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr47502-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-pic" } */ + +int +foo (int how, const void *set, void *oset) +{ + int resultvar; + asm volatile ("" + : "=a" (resultvar) + : "0" (14) , "b" (how), "c" ((set)), "d" ((oset)), "S" (65 / 8) : "memory", "cc"); + return resultvar; +} diff --git a/gcc/testsuite/gcc.target/i386/pr48037-1.c b/gcc/testsuite/gcc.target/i386/pr48037-1.c new file mode 100644 index 0000000000..1b64a7d19b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48037-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O -fno-math-errno" } */ + +typedef double __m128d __attribute__((vector_size(16))); +__m128d vsqrt1 (__m128d const x) +{ + double const* __restrict__ const y = (double const*)&x; + double const a = __builtin_sqrt(y[0]); + double const b = __builtin_sqrt(y[1]); + return (__m128d) { a, b }; +} + +/* Verify we do not spill x to the stack. */ +/* { dg-final { scan-assembler-not "%rsp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr48084-1.c b/gcc/testsuite/gcc.target/i386/pr48084-1.c new file mode 100644 index 0000000000..d9eef495cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48084-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef float __v2sf __attribute__ ((__vector_size__ (8))); +typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef float __v4sf __attribute__ ((__vector_size__ (16))); +void +_mm_storeh_pi (__m64 *__P, __m128 __A) +{ + __builtin_ia32_storehps ((__v2sf *)__P, (__v4sf)__A); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48084-2.c b/gcc/testsuite/gcc.target/i386/pr48084-2.c new file mode 100644 index 0000000000..2b41c0bba2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48084-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef char __v8qi __attribute__ ((__vector_size__ (8))); +void +_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P) +{ + __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48084-3.c b/gcc/testsuite/gcc.target/i386/pr48084-3.c new file mode 100644 index 0000000000..423c598042 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48084-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3" } */ + +void +_mm_monitor (void const * __P, unsigned int __E, unsigned int __H) +{ + __builtin_ia32_monitor (__P, __E, __H); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48084-4.c b/gcc/testsuite/gcc.target/i386/pr48084-4.c new file mode 100644 index 0000000000..df465a313a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48084-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse2" } */ + +void +_mm_clflush (void const *__A) +{ + __builtin_ia32_clflush (__A); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48084-5.c b/gcc/testsuite/gcc.target/i386/pr48084-5.c new file mode 100644 index 0000000000..d6ed8e5fc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48084-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mrdrnd" } */ + +int +_rdrand16_step (unsigned short *__P) +{ + return __builtin_ia32_rdrand16_step (__P); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48389.c b/gcc/testsuite/gcc.target/i386/pr48389.c new file mode 100644 index 0000000000..2ac18cdbe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48389.c @@ -0,0 +1,13 @@ +/* PR middle-end/48389 */ +/* { dg-do compile } */ +/* { dg-options "-O -mtune=pentiumpro -Wno-abi" } */ +/* { dg-require-effective-target ia32 } */ +typedef float V2SF __attribute__ ((vector_size (128))); +V2SF foo (int x, V2SF a) +{ + V2SF b = {}; + if (x & 42) + b = a; + a += b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr48688.c b/gcc/testsuite/gcc.target/i386/pr48688.c new file mode 100644 index 0000000000..f4d663a210 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48688.c @@ -0,0 +1,24 @@ +/* PR target/48688 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int fn1 (int x) { return (x << 3) | 5; } +int fn2 (int x) { return (x * 8) | 5; } +int fn3 (int x) { return (x << 3) + 5; } +int fn4 (int x) { return (x * 8) + 5; } +int fn5 (int x) { return (x << 3) ^ 5; } +int fn6 (int x) { return (x * 8) ^ 5; } +long fn7 (long x) { return (x << 3) | 5; } +long fn8 (long x) { return (x * 8) | 5; } +long fn9 (long x) { return (x << 3) + 5; } +long fn10 (long x) { return (x * 8) + 5; } +long fn11 (long x) { return (x << 3) ^ 5; } +long fn12 (long x) { return (x * 8) ^ 5; } +long fn13 (unsigned x) { return (x << 3) | 5; } +long fn14 (unsigned x) { return (x * 8) | 5; } +long fn15 (unsigned x) { return (x << 3) + 5; } +long fn16 (unsigned x) { return (x * 8) + 5; } +long fn17 (unsigned x) { return (x << 3) ^ 5; } +long fn18 (unsigned x) { return (x * 8) ^ 5; } + +/* { dg-final { scan-assembler-not "\[ \t\]x?or\[bwlq\]\[ \t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr48721.c b/gcc/testsuite/gcc.target/i386/pr48721.c new file mode 100644 index 0000000000..f37a16949a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48721.c @@ -0,0 +1,51 @@ +/* PR rtl-optimization/48721 */ +/* { dg-do compile } */ +/* { dg-options "-O -foptimize-sibling-calls -fsched2-use-superblocks -fschedule-insns2 -mtune=core2" } */ + +extern unsigned char a[]; +extern int b[], d[], e[], f[], g[], *h[], m[], *n[], o[]; +extern char c[]; + +struct S +{ + unsigned char s1; + int s2, s3, s4, s5, s6, s7, s8; +}; + +__attribute__((noinline, noclone)) int +foo (int x) +{ + return 0; +} + +int +bar (int x, struct S *y) +{ + int z; + switch (x) + { + case 1: + case 2: + { + int t2, t4, t5, t6, t7, t8; + z = o[y->s8 * 6]; + t8 = *n[m[x] * 5]; + t4 = *h[y->s7]; + t7 = z; + z = g[f[x] + y->s6]; + t6 = e[y->s5]; + t5 = d[c[x] + y->s3 * 17]; + if (z) + t2 = b[z]; + if (a[z] != y->s1) + return foo (x); + y->s8 = t8; + y->s4 = t4; + y->s7 = t7; + y->s6 = t6; + y->s5 = t5; + y->s2 = t2; + } + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr48722.c b/gcc/testsuite/gcc.target/i386/pr48722.c new file mode 100644 index 0000000000..a35fe7e22a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr48722.c @@ -0,0 +1,13 @@ +/* PR middle-end/48722 */ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-push-args" } */ + +extern long long a; +extern int b; +void bar (int, long long); + +void +foo (void) +{ + bar (a > 0x85, b); +} diff --git a/gcc/testsuite/gcc.target/i386/pr49095.c b/gcc/testsuite/gcc.target/i386/pr49095.c new file mode 100644 index 0000000000..b7d1fb2804 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49095.c @@ -0,0 +1,73 @@ +/* PR rtl-optimization/49095 */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-options "-Os -mregparm=2" { target ia32 } } */ + +void foo (void *); + +int * +f1 (int *x) +{ + if (!--*x) + foo (x); + return x; +} + +int +g1 (int x) +{ + if (!--x) + foo ((void *) 0); + return x; +} + +#define F(T, OP, OPN) \ +T * \ +f##T##OPN (T *x, T y) \ +{ \ + *x OP y; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +g##T##OPN (T x, T y) \ +{ \ + x OP y; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} \ + \ +T * \ +h##T##OPN (T *x) \ +{ \ + *x OP 24; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +i##T##OPN (T x, T y) \ +{ \ + x OP 24; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} + +#define G(T) \ +F (T, +=, plus) \ +F (T, -=, minus) \ +F (T, &=, and) \ +F (T, |=, or) \ +F (T, ^=, xor) + +G (char) +G (short) +G (int) +G (long) + +/* { dg-final { scan-assembler-not "test\[lq\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr49168-1.c b/gcc/testsuite/gcc.target/i386/pr49168-1.c new file mode 100644 index 0000000000..9676dc85a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49168-1.c @@ -0,0 +1,11 @@ +/* PR target/49168 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movdqa\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */ +/* { dg-final { scan-assembler "movdqu\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */ + +void +flt128_va (void *mem, __float128 d) +{ + __builtin_memcpy (mem, &d, sizeof (d)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr49504.c b/gcc/testsuite/gcc.target/i386/pr49504.c new file mode 100644 index 0000000000..503e6c238b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49504.c @@ -0,0 +1,18 @@ +/* PR target/49504 */ +/* { dg-do run { target { x32 } } } */ +/* { dg-options "-O" } */ + +unsigned long long +foo (const void* p, unsigned long long q) +{ + unsigned long long a = (((unsigned long long) ((unsigned long) p)) + q) >> 32; + return a; +} + +int +main () +{ + if (foo (foo, 0x100000000ULL) != 0x1) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr49567.c b/gcc/testsuite/gcc.target/i386/pr49567.c new file mode 100644 index 0000000000..309deb479e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49567.c @@ -0,0 +1,13 @@ +/* PR debug/49567 */ +/* { dg-do compile } */ +/* { dg-options "-g -O2 -msse4" } */ + +#include <x86intrin.h> + +__m128 +foo (__m128i x) +{ + __m128i y; + y = _mm_cvtepi16_epi32 (x); + return _mm_cvtepi32_ps (y); +} diff --git a/gcc/testsuite/gcc.target/i386/pr49715-1.c b/gcc/testsuite/gcc.target/i386/pr49715-1.c new file mode 100644 index 0000000000..d959f9e379 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49715-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -mfpmath=sse" } */ + +float func(unsigned x) +{ + return (x & 0xfffff) * 0.01f; +} + +/* { dg-final { scan-assembler-times "cvtsi2ss" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr49715-2.c b/gcc/testsuite/gcc.target/i386/pr49715-2.c new file mode 100644 index 0000000000..3fc8e4e8df --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49715-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +double func(unsigned long long x) +{ + if (x <= 0x7ffffffffffffffeULL) + return (x + 1) * 0.01; + return 0.0; +} + +/* { dg-final { scan-assembler-times "cvtsi2sdq" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr49781-1.c b/gcc/testsuite/gcc.target/i386/pr49781-1.c new file mode 100644 index 0000000000..60f9d50d86 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49781-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fpic -mtune=generic" } */ +/* { dg-require-effective-target fpic } */ + +static int heap[2*(256 +1+29)+1]; +static int heap_len; +static int heap_max; +void +foo (int elems) +{ + int n, m; + int max_code = -1; + int node = elems; + heap_len = 0, heap_max = (2*(256 +1+29)+1); + for (n = 0; n < elems; n++) + heap[++heap_len] = max_code = n; + do { + n = heap[1]; + heap[1] = heap[heap_len--]; + m = heap[1]; + heap[--heap_max] = n; + heap[--heap_max] = m; + } while (heap_len >= 2); +} + +/* { dg-final { scan-assembler-not "lea\[lq\]?\[ \t\]\\((%|)r\[a-z0-9\]*" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr49920.c b/gcc/testsuite/gcc.target/i386/pr49920.c index 416e7a4784..ef2a185122 100644 --- a/gcc/testsuite/gcc.target/i386/pr49920.c +++ b/gcc/testsuite/gcc.target/i386/pr49920.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ typedef __SIZE_TYPE__ size_t; extern void *malloc (size_t); diff --git a/gcc/testsuite/gcc.target/i386/pr49927.c b/gcc/testsuite/gcc.target/i386/pr49927.c new file mode 100644 index 0000000000..5850597d64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49927.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +char a[1][1]; +long long b; + +void +foo (void) +{ + --a[b][b]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr50038.c b/gcc/testsuite/gcc.target/i386/pr50038.c new file mode 100644 index 0000000000..e111574c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50038.c @@ -0,0 +1,20 @@ +/* PR target/50038 */ +/* { dg-options "-O2" } */ + +void +test (int len, unsigned char *in, unsigned char *out) +{ + int i; + unsigned char xr, xg; + unsigned char xy=0; + for (i = 0; i < len; i++) + { + xr = *in++; + xg = *in++; + xy = (unsigned char) ((19595 * xr + 38470 * xg) >> 16); + + *out++ = xy; + } +} + +/* { dg-final { scan-assembler-times "movzbl" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr50155.c b/gcc/testsuite/gcc.target/i386/pr50155.c new file mode 100644 index 0000000000..c641d4c47a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50155.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +void +foo (int x, double *a, double *b, double c) +{ + int i; + + for (i = 0; i < x; i++) + *a++ = *b++ * i / c; +} + +/* { dg-final { scan-assembler-not "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr50482.c b/gcc/testsuite/gcc.target/i386/pr50482.c new file mode 100644 index 0000000000..64c2686bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50482.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4" } */ + +void +test (int code, unsigned int * image, int * colors) +{ + int i; + + for (i = 0; i < code; ++i) + image[i] = (colors[i] < 0 ? ~(unsigned int) 0 : colors[i]); +} diff --git a/gcc/testsuite/gcc.target/i386/pr50603.c b/gcc/testsuite/gcc.target/i386/pr50603.c new file mode 100644 index 0000000000..101ef85484 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50603.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int *foo; + +int +bar (int x) +{ + return foo[x]; +} +/* { dg-final { scan-assembler-not "lea\[lq\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr50712.c b/gcc/testsuite/gcc.target/i386/pr50712.c index f08a94453d..90cc75db34 100644 --- a/gcc/testsuite/gcc.target/i386/pr50712.c +++ b/gcc/testsuite/gcc.target/i386/pr50712.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ typedef __builtin_va_list __va_list; diff --git a/gcc/testsuite/gcc.target/i386/pr50725.c b/gcc/testsuite/gcc.target/i386/pr50725.c new file mode 100644 index 0000000000..ef74ecb021 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50725.c @@ -0,0 +1,48 @@ +/* PR target/50725 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O2 -mavx" } */ + +extern void abort (void); + +typedef int __attribute__((vector_size (32))) m256i; + +__attribute__((noinline, noclone)) void +foo (int *x, m256i *y) +{ + asm volatile ("" : : "r" (x), "r" (y) : "memory"); +} + +__attribute__((noinline, noclone)) int +bar (int x) +{ + if (x > 20) + return 24; + m256i i; + foo (__builtin_alloca (x), &i); + return 128; +} + +__attribute__((noinline, noclone)) int +baz (int d0, int d1, int d2, int d3, int d4, int d5, int x) +{ + if (x > 20) + return 24; + m256i i; + d0 += d1 + d2 + d3 + d4 + d5; d1 += d0; + foo (__builtin_alloca (x), &i); + return 128; +} + +int +main () +{ + if (bar (22) != 24 || bar (20) != 128) + abort (); +#ifdef __x86_64__ + register long r10 __asm__ ("r10") = 0xdeadbeefdeadbeefUL; + asm volatile ("" : "+r" (r10)); +#endif + if (baz (0, 0, 0, 0, 0, 0, 22) != 24 || baz (0, 0, 0, 0, 0, 0, 20) != 128) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr50766.c b/gcc/testsuite/gcc.target/i386/pr50766.c new file mode 100644 index 0000000000..9923de4248 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr50766.c @@ -0,0 +1,17 @@ +/* PR target/50766 */ +/* { dg-do assemble } */ +/* { dg-options "-mbmi2" } */ +/* { dg-require-effective-target bmi2 } */ + +#include <x86intrin.h> + +unsigned z; + +void +foo () +{ + unsigned x = 0x23593464; + unsigned y = 0xF9494302; + z = _pext_u32(x, y); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr51235.c b/gcc/testsuite/gcc.target/i386/pr51235.c new file mode 100644 index 0000000000..c99d5c0e73 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr51235.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -mxop -mavx2" } */ + +void *foo (int count, void **list) +{ + void *minaddr = list[0]; + int i; + + for (i = 1; i < count; i++) + { + void *addr = list[i]; + if (addr < minaddr) + minaddr = addr; + } + + return minaddr; +} diff --git a/gcc/testsuite/gcc.target/i386/pr51236.c b/gcc/testsuite/gcc.target/i386/pr51236.c new file mode 100644 index 0000000000..63bfaeeb0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr51236.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -mavx2" } */ + +long foo (long *p, int i) +{ + long x = 0; + + while (--i) + x ^= p[i]; + + return x; +} diff --git a/gcc/testsuite/gcc.target/i386/pr51393.c b/gcc/testsuite/gcc.target/i386/pr51393.c new file mode 100644 index 0000000000..51175c87a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr51393.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O -mavx" } */ + +#include "avx-check.h" +#include <immintrin.h> + +static void +__attribute__((noinline)) +avx_test (void) +{ + long long in = 0x800000000ll; + long long out; + + __m256i zero = _mm256_setzero_si256(); + __m256i tmp = _mm256_insert_epi64 (zero, in, 0); + out = _mm256_extract_epi64(tmp, 0); + + if (in != out) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr51987.c b/gcc/testsuite/gcc.target/i386/pr51987.c new file mode 100644 index 0000000000..6ac2e6395d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr51987.c @@ -0,0 +1,33 @@ +/* PR tree-optimization/51987 */ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-options "-O3" } */ + +extern void abort (void); +union U { unsigned long long l; struct { unsigned int l, h; } i; }; + +__attribute__((noinline, noclone)) void +foo (char *x, char *y) +{ + int i; + for (i = 0; i < 64; i++) + { + union U u; + asm ("movl %1, %k0; salq $32, %0" : "=r" (u.l) : "r" (i)); + x[i] = u.i.h; + union U v; + asm ("movl %1, %k0; salq $32, %0" : "=r" (v.l) : "r" (i)); + y[i] = v.i.h; + } +} + +int +main () +{ + char a[64], b[64]; + int i; + foo (a, b); + for (i = 0; i < 64; i++) + if (a[i] != i || b[i] != i) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr52146.c b/gcc/testsuite/gcc.target/i386/pr52146.c new file mode 100644 index 0000000000..a4804e6779 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr52146.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32" } */ + +void +test1 (void) +{ + int* apic_tpr_addr = (int *) 0xfee00080; + *apic_tpr_addr += 4; +} + +void +test2 (void) +{ + int* apic_tpr_addr = (int *) 0xfee00080; + *apic_tpr_addr = 0; +} + +/* { dg-final { scan-assembler-not "-18874240" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr52330.c b/gcc/testsuite/gcc.target/i386/pr52330.c new file mode 100644 index 0000000000..22ba0b21ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr52330.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +void foo (int a) +{ + asm volatile ("# %H0" : : "r" (a)); /* { dg-error "not an offsettable" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr52736.c b/gcc/testsuite/gcc.target/i386/pr52736.c new file mode 100644 index 0000000000..f35c1fd6c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr52736.c @@ -0,0 +1,29 @@ +/* PR target/52736 */ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2" } */ +/* { dg-require-effective-target sse2_runtime } */ + +#include <x86intrin.h> + +typedef double D __attribute__((may_alias)); +__attribute__((aligned(16))) static const double r[4] = { 1., 5., 1., 3. }; + +__attribute__((noinline, noclone)) +void +foo (int x) +{ + asm volatile ("" : "+g" (x) : : "memory"); + if (x != 3) + __builtin_abort (); +} + +int +main () +{ + __m128d t = _mm_set1_pd (5.); + ((D *)(&t))[0] = 1.; + foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[0])))); + ((D *)(&t))[1] = 3.; + foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[2])))); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr52754.c b/gcc/testsuite/gcc.target/i386/pr52754.c new file mode 100644 index 0000000000..0f2dbff2dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr52754.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fpredictive-commoning -msse2 -std=c99" } */ +/* { dg-require-effective-target sse2 } */ + +#include <x86intrin.h> + +#include "isa-check.h" +#include "sse-os-support.h" + +int main() +{ + const float mem[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + + unsigned int indexes[8]; + for (unsigned int i = 0; i < 8; ++i) indexes[i] = i; + + check_isa (); + + if (!sse_os_support ()) + exit (0); + + __m128 x = _mm_setr_ps(0, 1, 2, 3); + for (unsigned int i = 0; i + 4 < 6; ++i) { + const unsigned int *ii = &indexes[i]; + const __m128 tmp = _mm_setr_ps(mem[ii[0]], mem[ii[1]], mem[ii[2]], mem[ii[3]]); + if (0xf != _mm_movemask_ps(_mm_cmpeq_ps(tmp, x))) { + __builtin_abort(); + } + x = _mm_add_ps(x, _mm_set1_ps(1)); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr53366-1.c b/gcc/testsuite/gcc.target/i386/pr53366-1.c new file mode 100644 index 0000000000..c24a594b8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53366-1.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/53366 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O3 -mavx" } */ + +#include "../../gcc.dg/torture/pr53366-1.c" diff --git a/gcc/testsuite/gcc.target/i386/pr53366-2.c b/gcc/testsuite/gcc.target/i386/pr53366-2.c new file mode 100644 index 0000000000..77270a0b0a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53366-2.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/53366 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O3 -mavx" } */ + +#include "../../gcc.dg/torture/pr53366-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr53416.c b/gcc/testsuite/gcc.target/i386/pr53416.c new file mode 100644 index 0000000000..68abe8bddb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53416.c @@ -0,0 +1,17 @@ +/* PR target/53416 */ +/* { dg-options "-O2 -mrdrnd" } */ + +int test (void) +{ + unsigned int number = 0; + int result0, result1, result2, result3; + + result0 = __builtin_ia32_rdrand32_step (&number); + result1 = __builtin_ia32_rdrand32_step (&number); + result2 = __builtin_ia32_rdrand32_step (&number); + result3 = __builtin_ia32_rdrand32_step (&number); + + return result0 + result1 +result2 + result3; +} + +/* { dg-final { scan-assembler-times "rdrand" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr53759.c b/gcc/testsuite/gcc.target/i386/pr53759.c new file mode 100644 index 0000000000..b824b98457 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53759.c @@ -0,0 +1,17 @@ +/* PR target/53759 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ +/* { dg-require-effective-target avx } */ + +#include <xmmintrin.h> + +void +foo (__m128 *x, __m64 *y) +{ + __m128 a = _mm_setzero_ps (); + __m128 b = _mm_loadl_pi (a, y); + *x = _mm_add_ps (b, b); +} + +/* { dg-final { scan-assembler "vmovlps\[ \\t\]" } } */ +/* { dg-final { scan-assembler-not "vshufps\[ \\t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr54157.c b/gcc/testsuite/gcc.target/i386/pr54157.c new file mode 100644 index 0000000000..59fcd792bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr54157.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -ftree-vectorize" } */ + +struct s2{ + int n[24 -1][24 -1][24 -1]; +}; + +struct test2{ + struct s2 e; +}; + +struct test2 tmp2[4]; + +void main1 () +{ + int i,j; + + for (i = 0; i < 24 -4; i++) + for (j = 0; j < 24 -4; j++) + tmp2[2].e.n[1][i][j] = 8; +} diff --git a/gcc/testsuite/gcc.target/i386/pr54703.c b/gcc/testsuite/gcc.target/i386/pr54703.c new file mode 100644 index 0000000000..e30c293c07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr54703.c @@ -0,0 +1,36 @@ +/* PR target/54703 */ +/* { dg-do run { target sse2_runtime } } */ +/* { dg-options "-O -msse2" } */ +/* { dg-additional-options "-mavx -mtune=bdver1" { target avx_runtime } } */ + +extern void abort (void); +typedef double V __attribute__((vector_size(16))); + +union { + unsigned long long m[2]; + V v; +} u = { { 0xffffffffff000000ULL, 0xffffffffff000000ULL } }; + +static inline V +foo (V x) +{ + V y = __builtin_ia32_andpd (x, u.v); + V z = __builtin_ia32_subpd (x, y); + return __builtin_ia32_mulpd (y, z); +} + +void +test (V *x) +{ + V a = { 2.1, 2.1 }; + *x = foo (foo (a)); +} + +int +main () +{ + test (&u.v); + if (u.m[0] != 0x3acbf487f0a30550ULL || u.m[1] != u.m[0]) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr55142-1.c b/gcc/testsuite/gcc.target/i386/pr55142-1.c new file mode 100644 index 0000000000..28375b5476 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr55142-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -mx32 -fpic" } */ + +typedef int int32_t; +typedef unsigned int uint32_t; +typedef int32_t Elf32_Sword; +typedef struct +{ + Elf32_Sword d_tag; +} Elf32_Dyn; +struct link_map +{ + Elf32_Dyn *l_ld; + Elf32_Dyn *l_info[34]; +}; +extern struct link_map _dl_rtld_map __attribute__ ((visibility ("hidden"))); +static void elf_get_dynamic_info (struct link_map *l) +{ + Elf32_Dyn *dyn = l->l_ld; + Elf32_Dyn **info; + info = l->l_info; + while (dyn->d_tag != 0) + { + if ((uint32_t) (0x6ffffeff - dyn->d_tag) < 11) + info[0x6ffffeff - dyn->d_tag + 12] = dyn; + ++dyn; + } +} +void +foo (void) +{ + elf_get_dynamic_info (&_dl_rtld_map); +} diff --git a/gcc/testsuite/gcc.target/i386/pr55142-2.c b/gcc/testsuite/gcc.target/i386/pr55142-2.c new file mode 100644 index 0000000000..9daae9dca9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr55142-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O3 -mx32 -fpic" } */ +/* { dg-final { scan-assembler-not "movl\[\\t \]*%.*,\[\\t \]*-1073742592\\(%r(.x|.i|.p|\[1-9\]*)\\)" } } */ + +typedef int int32_t; +typedef unsigned int uint32_t; +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint32_t Elf32_Addr; +typedef struct { + Elf32_Sword d_tag; + union { + Elf32_Word d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; +struct link_map { + Elf32_Dyn *l_ld; + Elf32_Dyn *l_info[34 + 16 + 3 + 12 + 11]; +}; +void +elf_get_dynamic_info (struct link_map *l) +{ + Elf32_Dyn *dyn = l->l_ld; + Elf32_Dyn **info = l->l_info; + typedef Elf32_Word d_tag_utype; + while (dyn->d_tag != 0) { + if ((d_tag_utype) (0x6ffffeff - dyn->d_tag) < 11) + info[(0x6ffffeff - dyn->d_tag) + 34 + 16 + 3 + 12] = dyn; + ++dyn; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr55597.c b/gcc/testsuite/gcc.target/i386/pr55597.c new file mode 100644 index 0000000000..cafe194c1b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr55597.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fPIC -mx32" } */ + +struct initial_sp +{ + void *sp; + int mask; +}; + +__thread struct initial_sp __morestack_initial_sp; + +void foo (int *); + +void __morestack_release_segments (void) +{ + foo (&__morestack_initial_sp.mask); +} diff --git a/gcc/testsuite/gcc.target/i386/pr56028.c b/gcc/testsuite/gcc.target/i386/pr56028.c new file mode 100644 index 0000000000..18ae25398b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr56028.c @@ -0,0 +1,54 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + +volatile long long y; + +void +test () +{ + int a_ = a; + int b_ = b; + int c_ = c; + int d_ = d; + int e_ = e; + int f_ = f; + int g_ = g; + int h_ = h; + int i_ = i; + int j_ = j; + int k_ = k; + int l_ = l; + int m_ = m; + int n_ = n; + int o_ = o; + int p_ = p; + + int z; + + for (z = 0; z < 1000; z++) + { + y = 0x100000002ll; + y = 0x300000004ll; + } + + a = a_; + b = b_; + c = c_; + d = d_; + e = e_; + f = f_; + g = g_; + h = h_; + i = i_; + j = j_; + k = k_; + l = l_; + m = m_; + n = n_; + o = o_; + p = p_; +} + +/* { dg-final { scan-assembler-times "movabs" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr56560.c b/gcc/testsuite/gcc.target/i386/pr56560.c new file mode 100644 index 0000000000..5417cbdded --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr56560.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mvzeroupper -dp" } */ + +extern void abort (void); + +typedef double vec_t __attribute__((vector_size(32))); + +struct S { int i1; int i2; int i3; }; + +extern int bar (vec_t, int, int, int, int, int, struct S); + +void foo (vec_t v, struct S s) +{ + int i = bar (v, 1, 2, 3, 4, 5, s); + if (i == 0) + abort (); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr9771-1.c b/gcc/testsuite/gcc.target/i386/pr9771-1.c index 37ec490220..38586fe972 100644 --- a/gcc/testsuite/gcc.target/i386/pr9771-1.c +++ b/gcc/testsuite/gcc.target/i386/pr9771-1.c @@ -1,6 +1,6 @@ /* PR rtl-optimization/9771 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer -ffixed-ebp" } */ extern void abort(void); diff --git a/gcc/testsuite/gcc.target/i386/rdfsbase-1.c b/gcc/testsuite/gcc.target/i386/rdfsbase-1.c index c4808e9683..2ed33cd475 100644 --- a/gcc/testsuite/gcc.target/i386/rdfsbase-1.c +++ b/gcc/testsuite/gcc.target/i386/rdfsbase-1.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ /* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)eax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/rdfsbase-2.c b/gcc/testsuite/gcc.target/i386/rdfsbase-2.c index 40b8f4a999..f319cea57f 100644 --- a/gcc/testsuite/gcc.target/i386/rdfsbase-2.c +++ b/gcc/testsuite/gcc.target/i386/rdfsbase-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ /* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/rdgsbase-1.c b/gcc/testsuite/gcc.target/i386/rdgsbase-1.c index 1e5a302085..cb2a3d5811 100644 --- a/gcc/testsuite/gcc.target/i386/rdgsbase-1.c +++ b/gcc/testsuite/gcc.target/i386/rdgsbase-1.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ /* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)eax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/rdgsbase-2.c b/gcc/testsuite/gcc.target/i386/rdgsbase-2.c index 1321582506..d514cd9612 100644 --- a/gcc/testsuite/gcc.target/i386/rdgsbase-2.c +++ b/gcc/testsuite/gcc.target/i386/rdgsbase-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ /* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/rdrand-3.c b/gcc/testsuite/gcc.target/i386/rdrand-3.c index c494d3bf9a..de0e730ad1 100644 --- a/gcc/testsuite/gcc.target/i386/rdrand-3.c +++ b/gcc/testsuite/gcc.target/i386/rdrand-3.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mrdrnd -dp" } */ /* { dg-final { scan-assembler-times "rdranddi_1" 1 } } */ /* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c b/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c index dfc4c73dfd..8aeec20d5c 100644 --- a/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c +++ b/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c @@ -1,15 +1,15 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */ -float a[16]; -float b[16]; -float r[16]; +float a[32]; +float b[32]; +float r[32]; void t1(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 32; i++) r[i] = a[i] / b[i]; } diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-divf.c b/gcc/testsuite/gcc.target/i386/recip-vec-divf.c index 4bdbba79f3..0c0cd42ae8 100644 --- a/gcc/testsuite/gcc.target/i386/recip-vec-divf.c +++ b/gcc/testsuite/gcc.target/i386/recip-vec-divf.c @@ -1,15 +1,15 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */ -float a[16]; -float b[16]; -float r[16]; +float a[4]; +float b[4]; +float r[4]; void t1(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 4; i++) r[i] = a[i] / b[i]; } diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c b/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c index 5a8e6967b4..9cf3cc81be 100644 --- a/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c +++ b/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */ -float a[16]; -float b[16]; -float r[16]; +float a[32]; +float b[32]; +float r[32]; extern float sqrtf (float); @@ -11,7 +11,7 @@ void t1(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 32; i++) r[i] = a[i] / sqrtf (b[i]); } @@ -19,7 +19,7 @@ void t2(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 32; i++) r[i] = sqrtf (a[i] / b[i]); } @@ -27,9 +27,8 @@ void t3(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 32; i++) r[i] = sqrtf (a[i]); } -/* Last loop is small enough to be fully unrolled. */ -/* { dg-final { scan-assembler-times "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" 6 } } */ +/* { dg-final { scan-assembler-times "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" 3 } } */ diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c b/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c index bcef700ec6..9ac9bd76ce 100644 --- a/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c +++ b/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */ -float a[16]; -float b[16]; -float r[16]; +float a[4]; +float b[4]; +float r[4]; extern float sqrtf (float); @@ -11,7 +11,7 @@ void t1(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 4; i++) r[i] = a[i] / sqrtf (b[i]); } @@ -19,7 +19,7 @@ void t2(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 4; i++) r[i] = sqrtf (a[i] / b[i]); } @@ -27,7 +27,7 @@ void t3(void) { int i; - for (i = 0; i < 16; i++) + for (i = 0; i < 4; i++) r[i] = sqrtf (a[i]); } diff --git a/gcc/testsuite/gcc.target/i386/regparm-stdcall.c b/gcc/testsuite/gcc.target/i386/regparm-stdcall.c index 144f5f99e3..fbb3be5495 100644 --- a/gcc/testsuite/gcc.target/i386/regparm-stdcall.c +++ b/gcc/testsuite/gcc.target/i386/regparm-stdcall.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options -mpreferred-stack-boundary=4 } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ extern void abort(void); diff --git a/gcc/testsuite/gcc.target/i386/regparm.c b/gcc/testsuite/gcc.target/i386/regparm.c index 9db191c727..4cfd110206 100644 --- a/gcc/testsuite/gcc.target/i386/regparm.c +++ b/gcc/testsuite/gcc.target/i386/regparm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-W -Wall" } */ /* Verify that GCC correctly detects non-matching regparm attributes. */ diff --git a/gcc/testsuite/gcc.target/i386/reload-1.c b/gcc/testsuite/gcc.target/i386/reload-1.c index f8075acaed..9c6cd32227 100644 --- a/gcc/testsuite/gcc.target/i386/reload-1.c +++ b/gcc/testsuite/gcc.target/i386/reload-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O3 -msse2 -fdump-rtl-csa" } */ /* { dg-skip-if "no stdint" { vxworks_kernel } } */ diff --git a/gcc/testsuite/gcc.target/i386/rotate-2.c b/gcc/testsuite/gcc.target/i386/rotate-2.c index 69a062527a..71fd7edbd6 100644 --- a/gcc/testsuite/gcc.target/i386/rotate-2.c +++ b/gcc/testsuite/gcc.target/i386/rotate-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2" } */ typedef unsigned int UTItype __attribute__ ((mode (TI))); diff --git a/gcc/testsuite/gcc.target/i386/sibcall-5.c b/gcc/testsuite/gcc.target/i386/sibcall-5.c index f4127b9751..7cf67dbe16 100644 --- a/gcc/testsuite/gcc.target/i386/sibcall-5.c +++ b/gcc/testsuite/gcc.target/i386/sibcall-5.c @@ -1,6 +1,6 @@ /* Check that indirect sibcalls understand regparm. */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/signbit-1.c b/gcc/testsuite/gcc.target/i386/signbit-1.c index 745796d706..3f31f5e2df 100644 --- a/gcc/testsuite/gcc.target/i386/signbit-1.c +++ b/gcc/testsuite/gcc.target/i386/signbit-1.c @@ -1,6 +1,6 @@ /* PR optimization/8746 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -mtune=i586" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/signbit-2.c b/gcc/testsuite/gcc.target/i386/signbit-2.c index c09bba3b8b..bc8e4f8246 100644 --- a/gcc/testsuite/gcc.target/i386/signbit-2.c +++ b/gcc/testsuite/gcc.target/i386/signbit-2.c @@ -1,6 +1,6 @@ /* PR optimization/8746 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -mtune=i586" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/signbit-3.c b/gcc/testsuite/gcc.target/i386/signbit-3.c index dcd56b636d..8f1de51298 100644 --- a/gcc/testsuite/gcc.target/i386/signbit-3.c +++ b/gcc/testsuite/gcc.target/i386/signbit-3.c @@ -1,6 +1,6 @@ /* PR optimization/8746 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O1 -mtune=i586" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 4f8aaec6d3..66a36c68cb 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mbmi -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 188b2e6dc0..4bc0a2ef0e 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,13 +1,13 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mbmi -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */ #include <mm_malloc.h> /* Test that the intrinsics compile with optimization. All of them are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, - tbmintrin.h, lwpintrin.h, popcntintrin.h and mm_malloc.h that - reference the proper builtin functions. + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ @@ -147,5 +147,37 @@ #define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextri_u32 (X, 1) #define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextri_u64 (X, 1) +/* avx2intrin.h */ +#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1) +#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1) +#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1) +#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1) +#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1) #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 22ea61f68b..6451166ca1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,12 +1,13 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mbmi -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */ #include <mm_malloc.h> /* Test that the intrinsics compile without optimization. All of them are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, - fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, - lwpintrin.h and mm_malloc.h that reference the proper builtin functions. + fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, + lwpintrin.h, fmaintrin.h and mm_malloc.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ diff --git a/gcc/testsuite/gcc.target/i386/sse-19.c b/gcc/testsuite/gcc.target/i386/sse-19.c index 7a49a98fea..3025567fd8 100644 --- a/gcc/testsuite/gcc.target/i386/sse-19.c +++ b/gcc/testsuite/gcc.target/i386/sse-19.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=x86-64" } } */ -/* { dg-options "-O3 -march=x86-64 -msse2" } */ +/* { dg-options "-O3 -march=x86-64 -msse2 -mno-ssse3" } */ /* { dg-final { scan-assembler "punpcklbw" } } */ extern void abort(); #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-21.c b/gcc/testsuite/gcc.target/i386/sse-21.c index ca4c114d8b..d006cdc0a4 100644 --- a/gcc/testsuite/gcc.target/i386/sse-21.c +++ b/gcc/testsuite/gcc.target/i386/sse-21.c @@ -1,6 +1,6 @@ /* Test that we don't generate a fisttp instruction when -mno-sse3. */ /* { dg-do compile } */ -/* { dg-options "-O -mfpmath=387 -march=nocona -mno-sse3" } */ +/* { dg-options "-O -mfpmath=387 -march=nocona -mno-sse3 -mno-avx" } */ /* { dg-final { scan-assembler-not "fisttp" } } */ struct foo { diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index e28164d080..9ccb92d1b6 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1,15 +1,17 @@ /* Same as sse-14, except converted to use #pragma GCC option. */ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */ #include <mm_malloc.h> -/* Test that the intrinsics compile without optimization. All of them - are defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, - xopintrin.h, tbmintrin.h, lwpintrin.h, popcntintrin.h and - mm3dnow.h that reference the proper builtin functions. Defining - away "extern" and "__inline" results in all of them being compiled as - proper functions. */ +/* Test that the intrinsics compile with optimization. All of them + are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, + mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. + + Defining away "extern" and "__inline" results in all of them being + compiled as proper functions. */ #define extern #define __inline @@ -32,6 +34,11 @@ type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \ { return func (A, B, imm1, imm2); } +#define test_3(func, type, op1_type, op2_type, op3_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, int const I) \ + { return func (A, B, C, imm); } + #define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \ type _CONCAT(_,func) (op1_type A, op2_type B, \ op3_type C, op4_type D, int const I) \ @@ -39,7 +46,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp,fsgsbase,rdrnd,f16c,tbm") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c") #endif /* Following intrinsics require immediate arguments. They @@ -107,14 +114,18 @@ test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1) test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1) test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1) -/* smmintrin.h (SSE4.1). */ -/* nmmintrin.h (SSE4.2). */ -/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h checks for the - #ifdef. So just set the option to SSE4.2. */ +/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h + checks for the #ifdef. So just set the option to SSE4.2. */ #ifdef DIFFERENT_PRAGMAS #pragma GCC target ("sse4.2") #endif #include <nmmintrin.h> +/* smmintrin.h (SSE4.2). */ +test_1 (_mm_round_pd, __m128d, __m128d, 1) +test_1 (_mm_round_ps, __m128, __m128, 1) +test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_round_ss, __m128, __m128, __m128, 1) + test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1) test_2 (_mm_blend_ps, __m128, __m128, __m128, 1) test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1) @@ -148,6 +159,88 @@ test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1) test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1) test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) +/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C) */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c") +#endif +#include <immintrin.h> +test_1 (_cvtss_sh, unsigned short, float, 1) +test_1 (_mm_cvtps_ph, __m128i, __m128, 1) +test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) + +/* avxintrin.h */ +test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1) +test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1) +test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1) +test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1) +test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1) +test_1 (_mm256_extractf128_ps, __m128, __m256, 1) +test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1) +test_1 (_mm256_extract_epi8, int, __m256i, 20) +test_1 (_mm256_extract_epi16, int, __m256i, 13) +test_1 (_mm256_extract_epi32, int, __m256i, 6) +#ifdef __x86_64__ +test_1 (_mm256_extract_epi64, long long, __m256i, 2) +#endif +test_1 (_mm_permute_pd, __m128d, __m128d, 1) +test_1 (_mm256_permute_pd, __m256d, __m256d, 1) +test_1 (_mm_permute_ps, __m128, __m128, 1) +test_1 (_mm256_permute_ps, __m256, __m256, 1) +test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1) +test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1) +test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1) +test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1) +test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30) +test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7) +test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3) +#ifdef __x86_64__ +test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1) +#endif +test_1 (_mm256_round_pd, __m256d, __m256d, 1) +test_1 (_mm256_round_ps, __m256, __m256, 1) + +/* avx2intrin.h */ +test_2 ( _mm256_mpsadbw_epu8, __m256i, __m256i, __m256i, 1) +test_2 ( _mm256_alignr_epi8, __m256i, __m256i, __m256i, 1) +test_2 ( _mm256_blend_epi16, __m256i, __m256i, __m256i, 1) +test_1 ( _mm256_shuffle_epi32, __m256i, __m256i, 1) +test_1 ( _mm256_shufflehi_epi16, __m256i, __m256i, 1) +test_1 ( _mm256_shufflelo_epi16, __m256i, __m256i, 1) +test_1 ( _mm256_slli_si256, __m256i, __m256i, 8) +test_1 ( _mm256_srli_si256, __m256i, __m256i, 8) +test_2 ( _mm_blend_epi32, __m128i, __m128i, __m128i, 1) +test_2 ( _mm256_blend_epi32, __m256i, __m256i, __m256, 1) +test_1 ( _mm256_permute4x64_pd, __m256d, __m256d, 1) +test_1 ( _mm256_permute4x64_epi64, __m256i, __m256i, 1) +test_2 ( _mm256_permute2x128_si256, __m256i, __m256i, __m256i, 1) +test_1 ( _mm256_extracti128_si256, __m128i, __m256i, 1) +test_2 ( _mm256_inserti128_si256, __m256i, __m256i, __m128i, 1) +test_2 ( _mm_i32gather_pd, __m128d, double const *, __m128i, 1) +test_2 ( _mm256_i32gather_pd, __m256d, double const *, __m128i, 1) +test_2 ( _mm_i64gather_pd, __m128d, double const *, __m128i, 1) +test_2 ( _mm256_i64gather_pd, __m256d, double const *, __m256i, 1) +test_2 ( _mm_i32gather_ps, __m128, float const *, __m128i, 1) +test_2 ( _mm256_i32gather_ps, __m256, float const *, __m256i, 1) +test_2 ( _mm_i64gather_ps, __m128, float const *, __m128i, 1) +test_2 ( _mm256_i64gather_ps, __m128, float const *, __m256i, 1) +test_2 ( _mm_i32gather_epi64, __m128i, long long int const *, __m128i, 1) +test_2 ( _mm256_i32gather_epi64, __m256i, long long int const *, __m128i, 1) +test_2 ( _mm_i64gather_epi64, __m128i, long long int const *, __m128i, 1) +test_2 ( _mm256_i64gather_epi64, __m256i, long long int const *, __m256i, 1) +test_2 ( _mm_i32gather_epi32, __m128i, int const *, __m128i, 1) +test_2 ( _mm256_i32gather_epi32, __m256i, int const *, __m256i, 1) +test_2 ( _mm_i64gather_epi32, __m128i, int const *, __m128i, 1) +test_2 ( _mm256_i64gather_epi32, __m128i, int const *, __m256i, 1) + /* wmmintrin.h (AES/PCLMUL). */ #ifdef DIFFERENT_PRAGMAS #pragma GCC target ("aes,pclmul") @@ -156,23 +249,28 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1) test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) -/* smmintrin.h (SSE4.1). */ -test_1 (_mm_round_pd, __m128d, __m128d, 1) -test_1 (_mm_round_ps, __m128, __m128, 1) -test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) -test_2 (_mm_round_ss, __m128, __m128, __m128, 1) +/* popcnintrin.h (POPCNT). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("popcnt") +#endif +#include <popcntintrin.h> -/* xopintrin.h (XOP). */ +/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("xop,lwp") +#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma") #endif #include <x86intrin.h> +/* xopintrin.h */ test_1 ( _mm_roti_epi8, __m128i, __m128i, 1) test_1 ( _mm_roti_epi16, __m128i, __m128i, 1) test_1 ( _mm_roti_epi32, __m128i, __m128i, 1) test_1 ( _mm_roti_epi64, __m128i, __m128i, 1) +test_3 (_mm_permute2_pd, __m128d, __m128d, __m128d, __m128d, 1) +test_3 (_mm256_permute2_pd, __m256d, __m256d, __m256d, __m256d, 1) +test_3 (_mm_permute2_ps, __m128, __m128, __m128, __m128, 1) +test_3 (_mm256_permute2_ps, __m256, __m256, __m256, __m256, 1) -/* lwpintrin.h (LWP). */ +/* lwpintrin.h */ test_2 ( __lwpval32, void, unsigned int, unsigned int, 1) test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1) #ifdef __x86_64__ @@ -180,20 +278,7 @@ test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1) test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1) #endif -/* immintrin.h (F16C). */ -#ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("f16c") -#endif -#include <x86intrin.h> -test_1 (_cvtss_sh, unsigned short, float, 1) -test_1 (_mm_cvtps_ph, __m128i, __m128, 1) -test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) - -/* tbmintrin.h (TBM). */ -#ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("tbm") -#endif -#include <x86intrin.h> +/* tbmintrin.h */ test_1 ( __bextri_u32, unsigned int, unsigned int, 1) #ifdef __x86_64__ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22a.c b/gcc/testsuite/gcc.target/i386/sse-22a.c new file mode 100644 index 0000000000..688908f9ec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-22a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */ + +#define DIFFERENT_PRAGMAS + +#include "sse-22.c" diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 3d932e16bb..462f8c9acd 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -4,11 +4,13 @@ #include <mm_malloc.h> /* Test that the intrinsics compile with optimization. All of them - are defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, - xopintrin.h, lwpintrin.h, tbmintrin.h, popcntintrin.h and mm3dnow.h - that reference the proper builtin functions. Defining away "extern" - and "__inline" results in all of them being compiled as proper - functions. */ + are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, + mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. + + Defining away "extern" and "__inline" results in all of them being + compiled as proper functions. */ #define extern #define __inline @@ -145,7 +147,40 @@ #define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextr_u32 (X, 1) #define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextr_u64 (X, 1) -#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp,tbm,fsgsbase,rdrnd,f16c") +/* avx2intrin.h */ +#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1) +#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1) +#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1) +#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1) +#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1) + +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma") #include <wmmintrin.h> #include <smmintrin.h> #include <mm3dnow.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-5.c b/gcc/testsuite/gcc.target/i386/sse-5.c index 934fad51b9..af935c2f00 100644 --- a/gcc/testsuite/gcc.target/i386/sse-5.c +++ b/gcc/testsuite/gcc.target/i386/sse-5.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ -/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ -/* { dg-options "-Winline -Wno-psabi -O2 -march=i386" } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-Winline -Wno-psabi -O2 -mno-sse" } */ typedef double v2df __attribute__ ((vector_size (16))); v2df p; diff --git a/gcc/testsuite/gcc.target/i386/sse-8.c b/gcc/testsuite/gcc.target/i386/sse-8.c index b6cb5c8241..31e8c32fbd 100644 --- a/gcc/testsuite/gcc.target/i386/sse-8.c +++ b/gcc/testsuite/gcc.target/i386/sse-8.c @@ -2,7 +2,7 @@ /* Origin: <Pawe Sikora <pluto@ds14.agh.edu.pl> */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-march=pentium3" } */ int main() diff --git a/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c b/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c index bd85889503..5b1cfe795f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c @@ -2,7 +2,15 @@ /* { dg-options "-O2 -ftree-vectorize -msse" } */ /* { dg-require-effective-target sse } */ -#include "sse-check.h" +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H extern float copysignf (float, float); @@ -13,7 +21,7 @@ float b[N] = {-1.2f,3.4f,-5.6f,7.8f,-9.0f,1.0f,-2.0f,3.0f,-4.0f,-5.0f,6.0f,7.0f, float r[N]; static void -sse_test (void) +TEST (void) { int i; diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c index 6abc4d5afe..76ce912a45 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c index 44a5fafc31..909c3880ed 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c index eb85223450..cbfdddd405 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-recip-vec.c b/gcc/testsuite/gcc.target/i386/sse-recip-vec.c index bb1e458f92..de2f3d2977 100644 --- a/gcc/testsuite/gcc.target/i386/sse-recip-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse-recip-vec.c @@ -2,7 +2,15 @@ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */ /* { dg-require-effective-target sse } */ -#include "sse-check.h" +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H extern float sqrtf (float); extern float fabsf (float); @@ -16,7 +24,7 @@ float r[N]; float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f }; static void -sse_test (void) +TEST (void) { int i; diff --git a/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c b/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c index 5726448d76..b336b3284d 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c @@ -2,7 +2,15 @@ /* { dg-options "-O2 -ftree-vectorize -msse2" } */ /* { dg-require-effective-target sse2 } */ -#include "sse2-check.h" +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H extern double copysign (double, double); @@ -13,7 +21,7 @@ double b[N] = {-1.2,3.4,-5.6,7.8,-9.0,1.0,-2.0,3.0,-4.0,-5.0,6.0,7.0,-8.0,-9.0,1 double r[N]; static void -sse2_test (void) +TEST (void) { int i; diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c b/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c new file mode 100644 index 0000000000..4d5683108d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c @@ -0,0 +1,111 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -msse2 -mno-avx" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#define N 16 +float f[N]; +double d[N]; +int n[N]; + +__attribute__((noinline)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = d[i]; +} + +__attribute__((noinline)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + f[i] = n[i]; +} + +__attribute__((noinline)) void +f3 (void) +{ + int i; + for (i = 0; i < N; i++) + d[i] = f[i]; +} + +__attribute__((noinline)) void +f4 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = f[i]; +} + +__attribute__((noinline)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + d[i] = n[i]; +} + +__attribute__((noinline)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + f[i] = d[i]; +} + +static void +TEST () +{ + int i; + for (i = 0; i < N; i++) + { + asm (""); + d[i] = i + 2.5; + } + f1 (); + for (i = 0; i < N; i++) + if (n[i] != i + 2) + abort (); + else + n[i] = i + 7; + f2 (); + for (i = 0; i < N; i++) + if (f[i] != i + 7) + abort (); + else + f[i] = i - 2.25f; + f3 (); + for (i = 0; i < N; i++) + if (d[i] != i - 2.25) + abort (); + else + f[i] = i + 3.5; + f4 (); + for (i = 0; i < N; i++) + if (n[i] != i + 3) + abort (); + else + n[i] = i + 9; + f5 (); + for (i = 0; i < N; i++) + if (d[i] != i + 9) + abort (); + else + d[i] = i - 7.25; + f6 (); + for (i = 0; i < N; i++) + if (f[i] != i - 7.25) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c b/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c new file mode 100644 index 0000000000..00f13254c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mno-sse3 -mtune=generic -fdump-tree-vect-details" } */ + +#include "sse2-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "cvttpd2dq" } } */ +/* { dg-final { scan-assembler "cvtdq2ps" } } */ +/* { dg-final { scan-assembler "cvtps2pd" } } */ +/* { dg-final { scan-assembler "cvttps2dq" } } */ +/* { dg-final { scan-assembler "cvtdq2pd" } } */ +/* { dg-final { scan-assembler "cvtpd2ps" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c b/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c new file mode 100644 index 0000000000..8a811a3def --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <math.h> + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=sse"))) +TEST (void) +{ + double a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (float) a[i]; + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (float) a[i]) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c b/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c index 908e82f43e..a79a258367 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c b/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c index 7035c4e6de..ee047baa9c 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c b/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c index 0284a731b0..cd913a19f8 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-extract-1.c b/gcc/testsuite/gcc.target/i386/sse2-extract-1.c new file mode 100644 index 0000000000..f701cee8c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-extract-1.c @@ -0,0 +1,102 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2_runtime } */ + +extern void abort (void); +typedef unsigned long long uint64_t; + +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +#define FN(elcount, type, idx) \ +__attribute__((noinline, noclone)) \ +type f##type##elcount##_##idx (vector (elcount, type) x) { return x[idx] + 1; } +#define T2(elcount, type) \ + H (elcount, type) \ + F (elcount, type, 0) \ + F (elcount, type, 1) +#define T4(elcount, type) \ + T2 (elcount, type) \ + F (elcount, type, 2) \ + F (elcount, type, 3) +#define T8(elcount, type) \ + T4 (elcount, type) \ + F (elcount, type, 4) \ + F (elcount, type, 5) \ + F (elcount, type, 6) \ + F (elcount, type, 7) +#define T16(elcount, type) \ + T8 (elcount, type) \ + F (elcount, type, 8) \ + F (elcount, type, 9) \ + F (elcount, type, 10) \ + F (elcount, type, 11) \ + F (elcount, type, 12) \ + F (elcount, type, 13) \ + F (elcount, type, 14) \ + F (elcount, type, 15) +#define T32(elcount, type) \ + T16 (elcount, type) \ + F (elcount, type, 16) \ + F (elcount, type, 17) \ + F (elcount, type, 18) \ + F (elcount, type, 19) \ + F (elcount, type, 20) \ + F (elcount, type, 21) \ + F (elcount, type, 22) \ + F (elcount, type, 23) \ + F (elcount, type, 24) \ + F (elcount, type, 25) \ + F (elcount, type, 26) \ + F (elcount, type, 27) \ + F (elcount, type, 28) \ + F (elcount, type, 29) \ + F (elcount, type, 30) \ + F (elcount, type, 31) +#define TESTS_SSE2 \ +T2 (2, double) E \ +T2 (2, uint64_t) E \ +T4 (4, float) E \ +T4 (4, int) E \ +T8 (8, short) E \ +T16 (16, char) E +#define TESTS_AVX \ +T4 (4, double) E \ +T4 (4, uint64_t) E \ +T8 (8, float) E \ +T8 (8, int) E \ +T16 (16, short) E \ +T32 (32, char) E +#ifdef __AVX__ +#define TESTS TESTS_SSE2 TESTS_AVX +#else +#define TESTS TESTS_SSE2 +#endif + +#define F FN +#define H(elcount, type) +#define E +TESTS + +int +main () +{ +#undef F +#undef H +#undef E +#define H(elcount, type) \ + vector (elcount, type) v##type##elcount = { +#define E }; +#define F(elcount, type, idx) idx + 1, + TESTS +#undef F +#undef H +#undef E +#define H(elcount, type) +#define E +#define F(elcount, type, idx) \ + if (f##type##elcount##_##idx (v##type##elcount) != idx + 2) \ + abort (); + TESTS + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c index db1fbd0a36..f4d3a9a8f2 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -msse4 -march=core2 -dp" } */ #include <emmintrin.h> @@ -10,4 +9,4 @@ test (long long b) return _mm_cvtsi64_si128 (b); } -/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64_sse4_1/3" 1 } } */ +/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64/4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-insvhi.c b/gcc/testsuite/gcc.target/i386/sse2-insvhi.c new file mode 100644 index 0000000000..03a287042f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-insvhi.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> +#include <string.h> + +typedef short T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, short x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned short s[8]; + } res, val, tmp; + unsigned short ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.s[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c b/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c index 43797f7078..111e9b2740 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c @@ -2,7 +2,15 @@ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ /* { dg-require-effective-target sse2 } */ -#include "sse2-check.h" +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H extern long lrint (double); @@ -12,7 +20,7 @@ double a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5 long r[N]; static void -sse2_test (void) +TEST (void) { int i; diff --git a/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c b/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c index eaec22cb3a..ee917623cb 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c @@ -2,7 +2,15 @@ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ /* { dg-require-effective-target sse2 } */ -#include "sse2-check.h" +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H extern long lrintf (float); @@ -12,7 +20,7 @@ float a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5, long r[N]; static void -sse2_test (void) +TEST (void) { int i; diff --git a/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c b/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c new file mode 100644 index 0000000000..b401c85b3b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +#ifndef MASK +#define MASK 0x7986 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 7) + +void static +TEST (void) +{ + __m128i src, mask; + char s[16] = { 1,-2,3,-4,5,-6,7,-8,9,-10,11,-12,13,-14,15,-16 }; + char m[16]; + + char u[20] = { 0 }; + int i; + + for (i = 0; i < 16; i++) + m[i] = mask_v (i); + + src = _mm_loadu_si128 ((__m128i *)s); + mask = _mm_loadu_si128 ((__m128i *)m); + + _mm_maskmoveu_si128 (src, mask, u+3); + + for (i = 0; i < 16; i++) + if (u[i+3] != (m[i] ? s[i] : 0)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-movq-2.c b/gcc/testsuite/gcc.target/i386/sse2-movq-2.c index edf16f4a89..e1e9b14cf4 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-movq-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-movq-2.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-movq-3.c b/gcc/testsuite/gcc.target/i386/sse2-movq-3.c index 571fd6db0f..0a17e3e709 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-movq-3.c +++ b/gcc/testsuite/gcc.target/i386/sse2-movq-3.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-mul-1.c b/gcc/testsuite/gcc.target/i386/sse2-mul-1.c new file mode 100644 index 0000000000..9cdc12763b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mul-1.c @@ -0,0 +1,214 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O3 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +#define N 512 +static short a1[N], a2[N], a3[N]; +static unsigned short b1[N], b2[N], b3[N]; +static int c1[N], c2[N], c3[N]; +static unsigned int d1[N], d2[N], d3[N]; +static long long e1[N], e2[N], e3[N]; +static unsigned long long g1[N], g2[N], g3[N]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; ++i) + a1[i] = a2[i] * a3[i]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; ++i) + b1[i] = b2[i] * b3[i]; +} + +__attribute__((noinline, noclone)) void +f3 (void) +{ + int i; + for (i = 0; i < N; ++i) + c1[i] = c2[i] * c3[i]; +} + +__attribute__((noinline, noclone)) void +f4 (void) +{ + int i; + for (i = 0; i < N; ++i) + d1[i] = d2[i] * d3[i]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; ++i) + e1[i] = e2[i] * e3[i]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; ++i) + g1[i] = g2[i] * g3[i]; +} + +__attribute__((noinline, noclone)) void +f7 (void) +{ + int i; + for (i = 0; i < N; ++i) + c1[i] = a2[i] * a3[i]; +} + +__attribute__((noinline, noclone)) void +f8 (void) +{ + int i; + for (i = 0; i < N; ++i) + d1[i] = (unsigned int) b2[i] * b3[i]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; ++i) + e1[i] = (long long) c2[i] * (long long) c3[i]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; ++i) + g1[i] = (unsigned long long) d2[i] * (unsigned long long) d3[i]; +} + +__attribute__((noinline, noclone)) int +f11 (void) +{ + int i, r = 0; + for (i = 0; i < N; ++i) + r += a2[i] * a3[i]; + return r; +} + +__attribute__((noinline, noclone)) unsigned int +f12 (void) +{ + int i; + unsigned r = 0; + for (i = 0; i < N; ++i) + r += (unsigned int) b2[i] * b3[i]; + return r; +} + +__attribute__((noinline, noclone)) long long +f13 (void) +{ + int i; + long long r = 0; + for (i = 0; i < N; ++i) + r += (long long) c2[i] * (long long) c3[i]; + return r; +} + +__attribute__((noinline, noclone)) unsigned long long +f14 (void) +{ + int i; + unsigned long long r = 0; + for (i = 0; i < N; ++i) + r += (unsigned long long) d2[i] * (unsigned long long) d3[i]; + return r; +} + +static void +TEST (void) +{ + int i; + int s1 = 0; + unsigned int s2 = 0; + long long s3 = 0; + unsigned long long s4 = 0; + for (i = 0; i < N; ++i) + { + asm volatile ("" : : "r" (&s1) : "memory"); + asm volatile ("" : : "r" (&s2) : "memory"); + asm volatile ("" : : "r" (&s3) : "memory"); + asm volatile ("" : : "r" (&s4) : "memory"); + b2[i] = (int) random (); + b3[i] = (int) random (); + a2[i] = b2[i]; + a3[i] = b3[i]; + d2[i] = (((int) random ()) << 16) | b2[i]; + d3[i] = (((int) random ()) << 16) | b3[i]; + c2[i] = d2[i]; + c3[i] = d3[i]; + s1 += a2[i] * a3[i]; + s2 += (unsigned int) b2[i] * b3[i]; + s3 += (long long) c2[i] * (long long) c3[i]; + s4 += (unsigned long long) d2[i] * (unsigned long long) d3[i]; + } + f1 (); + f2 (); + f3 (); + f4 (); + f5 (); + f6 (); + for (i = 0; i < N; ++i) + { + if (a1[i] != (short) (a2[i] * a3[i])) + abort (); + if (b1[i] != (unsigned short) (b2[i] * b3[i])) + abort (); + if (c1[i] != c2[i] * c3[i]) + abort (); + if (d1[i] != d2[i] * d3[i]) + abort (); + if (e1[i] != e2[i] * e3[i]) + abort (); + if (g1[i] != g2[i] * g3[i]) + abort (); + } + f7 (); + f8 (); + f9 (); + f10 (); + for (i = 0; i < N; ++i) + { + if (c1[i] != a2[i] * a3[i]) + abort (); + if (d1[i] != b2[i] * b3[i]) + abort (); + if (e1[i] != (long long) c2[i] * (long long) c3[i]) + abort (); + if (g1[i] != (unsigned long long) d2[i] * (unsigned long long) d3[i]) + abort (); + } + if (f11 () != s1 || f12 () != s2 || f13 () != s3 || f14 () != s4) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c b/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c new file mode 100644 index 0000000000..16167437c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> +#include <string.h> + +#define msk0 0x00 +#define msk1 0x01 +#define msk2 0x02 +#define msk3 0x03 +#define msk4 0x04 +#define msk5 0x05 +#define msk6 0x06 +#define msk7 0x07 + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned short s[8]; + } res [8], val, tmp; + int masks[8]; + unsigned short ins[4] = { 3, 4, 5, 6 }; + int i; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + /* Check pinsrw imm8, r32, xmm. */ + res[0].x = _mm_insert_epi16 (val.x, ins[0], msk0); + res[1].x = _mm_insert_epi16 (val.x, ins[0], msk1); + res[2].x = _mm_insert_epi16 (val.x, ins[0], msk2); + res[3].x = _mm_insert_epi16 (val.x, ins[0], msk3); + res[4].x = _mm_insert_epi16 (val.x, ins[0], msk4); + res[5].x = _mm_insert_epi16 (val.x, ins[0], msk5); + res[6].x = _mm_insert_epi16 (val.x, ins[0], msk6); + res[7].x = _mm_insert_epi16 (val.x, ins[0], msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i = 0; i < 8; i++) + { + tmp.x = val.x; + tmp.s[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check pinsrw imm8, m16, xmm. */ + for (i = 0; i < 8; i++) + { + res[i].x = _mm_insert_epi16 (val.x, ins[i % 2], msk0); + masks[i] = msk0; + } + + for (i = 0; i < 8; i++) + { + tmp.x = val.x; + tmp.s[masks[i]] = ins[i % 2]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c b/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c index b66bbfd3b8..8fe71b71c5 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c +++ b/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c @@ -6,6 +6,12 @@ #include <smmintrin.h> #include <string.h> +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif #define NUM 20 @@ -57,6 +63,9 @@ sse4_1_test (void) init_blendps (src1.f, src2.f); + for (i = 0; i < 4; i++) + src3.f[i] = (int) random (); + /* Check blendps imm8, m128, xmm */ for (i = 0; i < NUM; i++) { diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c b/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c index b4d8e8ee16..3f4b335aca 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c +++ b/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c @@ -14,6 +14,12 @@ #include <smmintrin.h> #include <string.h> +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif #define NUM 20 @@ -66,6 +72,9 @@ TEST (void) init_blendps (src1.f, src2.f); + for (i = 0; i < 4; i++) + src3.f[i] = (int) random (); + /* Check blendps imm8, m128, xmm */ for (i = 0; i < NUM; i++) { diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c new file mode 100644 index 0000000000..ca07d9c003 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceil (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c new file mode 100644 index 0000000000..20bb2641fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceil (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c new file mode 100644 index 0000000000..b0559bf399 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float ceilf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c new file mode 100644 index 0000000000..314be91fa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float ceilf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c new file mode 100644 index 0000000000..41e69e59f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +extern void abort (void); +double ad[64], bd[64], cd[64], dd[64], ed[64]; +float af[64], bf[64], cf[64], df[64], ef[64]; +signed char ac[64], bc[64], cc[64], dc[64], ec[64]; +short as[64], bs[64], cs[64], ds[64], es[64]; +int ai[64], bi[64], ci[64], di[64], ei[64]; +long long all[64], bll[64], cll[64], dll[64], ell[64]; +unsigned char auc[64], buc[64], cuc[64], duc[64], euc[64]; +unsigned short aus[64], bus[64], cus[64], dus[64], eus[64]; +unsigned int au[64], bu[64], cu[64], du[64], eu[64]; +unsigned long long aull[64], bull[64], cull[64], dull[64], eull[64]; + +#define F(var) \ +__attribute__((noinline, noclone)) void \ +f##var (void) \ +{ \ + int i; \ + for (i = 0; i < 64; i++) \ + { \ + __typeof (a##var[0]) d = d##var[i], e = e##var[i]; \ + a##var[i] = b##var[i] > c##var[i] ? d : e; \ + } \ +} + +#define TESTS \ +F (d) F (f) F (c) F (s) F (i) F (ll) F (uc) F (us) F (u) F (ull) + +TESTS + +void +TEST () +{ + int i; + for (i = 0; i < 64; i++) + { +#undef F +#define F(var) \ + b##var[i] = i + 64; \ + switch (i % 3) \ + { \ + case 0: c##var[i] = i + 64; break; \ + case 1: c##var[i] = 127 - i; break; \ + case 2: c##var[i] = i; break; \ + } \ + d##var[i] = i / 2; \ + e##var[i] = i * 2; + TESTS + } +#undef F +#define F(var) f##var (); + TESTS + for (i = 0; i < 64; i++) + { + asm volatile ("" : : : "memory"); +#undef F +#define F(var) \ + if (a##var[i] != (b##var[i] > c##var[i] ? d##var[i] : e##var[i])) \ + abort (); + TESTS + } +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c new file mode 100644 index 0000000000..2083a60e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floor (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c new file mode 100644 index 0000000000..d250413c1b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floor (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c new file mode 100644 index 0000000000..aa2976d5b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float floorf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c new file mode 100644 index 0000000000..2f339f3b50 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float floorf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c b/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c index 75a8073354..7c71664a75 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c +++ b/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target ilp32 } } */ +/* { dg-do run { target ia32 } } */ /* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.1 -mtune=geode" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c b/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c new file mode 100644 index 0000000000..da090ba158 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef long T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, long x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned long l[2]; + } res, val, tmp; + unsigned long ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.l[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c b/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c new file mode 100644 index 0000000000..784201e2d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef char T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, char x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned char c[16]; + } res, val, tmp; + unsigned char ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.c[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c b/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c new file mode 100644 index 0000000000..569b8f269c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef int T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, int x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } res, val, tmp; + unsigned int ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.i[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c new file mode 100644 index 0000000000..20d03a515d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c b/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c index b90f4e2f12..112dd37fd9 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c +++ b/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.1" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c b/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c new file mode 100644 index 0000000000..c9f9c1cdf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1 -mno-avx2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +extern void abort (void); + +#define N 1024 +short a[N], c, e; +unsigned short b[N], d, f; + +__attribute__((noinline)) short +vecsmax (void) +{ + int i; + short r = -32768; + for (i = 0; i < N; ++i) + if (r < a[i]) r = a[i]; + return r; +} + +__attribute__((noinline)) unsigned short +vecumax (void) +{ + int i; + unsigned short r = 0; + for (i = 0; i < N; ++i) + if (r < b[i]) r = b[i]; + return r; +} + +__attribute__((noinline)) short +vecsmin (void) +{ + int i; + short r = 32767; + for (i = 0; i < N; ++i) + if (r > a[i]) r = a[i]; + return r; +} + +__attribute__((noinline)) unsigned short +vecumin (void) +{ + int i; + unsigned short r = 65535; + for (i = 0; i < N; ++i) + if (r > b[i]) r = b[i]; + return r; +} + +static void +TEST (void) +{ + int i; + for (i = 0; i < N; ++i) + { + a[i] = i - N / 2; + b[i] = i + 32768 - N / 2; + } + a[N / 3] = N; + a[2 * N / 3] = -N; + b[N / 5] = 32768 + N; + b[4 * N / 5] = 32768 - N; + if (vecsmax () != N || vecsmin () != -N) + abort (); + if (vecumax () != 32768 + N || vecumin () != 32768 - N) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c b/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c new file mode 100644 index 0000000000..95c5f059d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4.1 -mno-avx2" } */ + +#include "sse4_1-phminposuw-2.c" + +/* { dg-final { scan-assembler "phminposuw\[^\n\r\]*xmm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c b/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c index 1640439e59..1ed0987bd7 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c +++ b/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.1" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c new file mode 100644 index 0000000000..d9c2fbf2d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c new file mode 100644 index 0000000000..f20359a1ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != rint (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c new file mode 100644 index 0000000000..1d25f7669d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float rintf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rintf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c new file mode 100644 index 0000000000..716cad1e3f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float rintf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != rintf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c new file mode 100644 index 0000000000..9abbe55b7d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c new file mode 100644 index 0000000000..bb912cef95 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != round (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c new file mode 100644 index 0000000000..5384e5c62c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float roundf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) roundf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c new file mode 100644 index 0000000000..d254aa66b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float roundf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != roundf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c new file mode 100644 index 0000000000..9cbcd9b398 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double trunc (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = trunc (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != trunc (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c b/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c new file mode 100644 index 0000000000..815b508143 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float truncf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = truncf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != truncf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c b/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c index 8209e99359..f1f75d916f 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c +++ b/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.2" } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c b/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c index aa4d8a9173..47cdf35629 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c +++ b/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do run { target { ! { ia32 } } } } */ /* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.2" } */ diff --git a/gcc/testsuite/gcc.target/i386/ssefn-1.c b/gcc/testsuite/gcc.target/i386/ssefn-1.c index bea6cb2bf0..4c72fa4d1a 100644 --- a/gcc/testsuite/gcc.target/i386/ssefn-1.c +++ b/gcc/testsuite/gcc.target/i386/ssefn-1.c @@ -2,13 +2,13 @@ Written by Paolo Bonzini, 25 January 2005 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-final { scan-assembler "movss" } } */ /* { dg-final { scan-assembler "mulss" } } */ /* { dg-final { scan-assembler-not "movsd" } } */ /* { dg-final { scan-assembler-not "mulsd" } } */ /* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ -/* { dg-options "-O2 -march=i386 -msse -mfpmath=sse -fno-inline" } */ +/* { dg-options "-O2 -march=i386 -msse -mno-sse2 -mfpmath=sse -fno-inline" } */ static float xs (void) { diff --git a/gcc/testsuite/gcc.target/i386/ssefn-2.c b/gcc/testsuite/gcc.target/i386/ssefn-2.c index 09b920ea7c..2549855cf4 100644 --- a/gcc/testsuite/gcc.target/i386/ssefn-2.c +++ b/gcc/testsuite/gcc.target/i386/ssefn-2.c @@ -2,7 +2,7 @@ Written by Paolo Bonzini, 25 January 2005 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-final { scan-assembler "movss" } } */ /* { dg-final { scan-assembler "mulss" } } */ /* { dg-final { scan-assembler "movsd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-1.c b/gcc/testsuite/gcc.target/i386/sseregparm-1.c index 9d426b8427..63bad7e471 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-1.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ float essef(float) __attribute__((sseregparm)); double essed(double) __attribute__((sseregparm)); diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-2.c b/gcc/testsuite/gcc.target/i386/sseregparm-2.c index cca98ca82b..b5e521a11e 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-2.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mno-sse" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ float essef(float) __attribute__((sseregparm)); double essed(double) __attribute__((sseregparm)); diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-3.c b/gcc/testsuite/gcc.target/i386/sseregparm-3.c index 9ee82af44a..5c16f43548 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-3.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-4.c b/gcc/testsuite/gcc.target/i386/sseregparm-4.c index a29cf06bf5..47d66e3ab1 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-4.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-5.c b/gcc/testsuite/gcc.target/i386/sseregparm-5.c index 7423722d69..d0f4757b54 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-5.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-6.c b/gcc/testsuite/gcc.target/i386/sseregparm-6.c index 6203b6b597..a4a836386f 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-6.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-7.c b/gcc/testsuite/gcc.target/i386/sseregparm-7.c index 61267df985..54b2573cf3 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-7.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-8.c b/gcc/testsuite/gcc.target/i386/sseregparm-8.c index 3a9d345a96..a7068dfe00 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-8.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mno-sse" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ float essef(float) __attribute__((sseregparm)); double essed(double) __attribute__((sseregparm)); diff --git a/gcc/testsuite/gcc.target/i386/stack-realign.c b/gcc/testsuite/gcc.target/i386/stack-realign.c index ab9360f49f..a45441845f 100644 --- a/gcc/testsuite/gcc.target/i386/stack-realign.c +++ b/gcc/testsuite/gcc.target/i386/stack-realign.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mstackrealign -O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/stack-usage-realign.c b/gcc/testsuite/gcc.target/i386/stack-usage-realign.c index 03d9d41748..c899606d64 100644 --- a/gcc/testsuite/gcc.target/i386/stack-usage-realign.c +++ b/gcc/testsuite/gcc.target/i386/stack-usage-realign.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-skip-if "no stack realignment" { *-*-darwin* } { "*" } { "" } } */ /* { dg-options "-fstack-usage -msse2 -mforce-drap" } */ diff --git a/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c b/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c index e4d4f20bb1..dfe3968f5a 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mpreferred-stack-boundary=2" } */ /* This case is to detect a compile time regression introduced in stack diff --git a/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c b/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c index 225d0c5e55..161d2292d4 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c @@ -1,6 +1,6 @@ /* PR target/39137 */ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mpreferred-stack-boundary=2" } */ /* Make sure dynamic stack realignment isn't performed just because there are long long variables. */ diff --git a/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c b/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c index ae7f3ee333..6ea83f98fb 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! *-*-darwin* } } } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -mpreferred-stack-boundary=2" } */ /* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" 2 } } */ /* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-16,\[^\\n\]*sp" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/stackalign/return-1.c b/gcc/testsuite/gcc.target/i386/stackalign/return-1.c index c5b32e5c42..c9fcc12138 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/return-1.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/return-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mpreferred-stack-boundary=2" } */ /* This compile only test is to detect an assertion failure in stack branch diff --git a/gcc/testsuite/gcc.target/i386/stackalign/return-2.c b/gcc/testsuite/gcc.target/i386/stackalign/return-2.c index 113e71b80d..d393913ae7 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/return-2.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/return-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mpreferred-stack-boundary=2" } */ /* This compile only test is to detect an assertion failure in stack branch diff --git a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c index dd2c2e8b45..e32547e01b 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! { ilp32 && dfp } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ /* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */ /* { dg-require-effective-target sse } */ diff --git a/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc/testsuite/gcc.target/i386/sw-1.c new file mode 100644 index 0000000000..fcb1bbd80b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sw-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */ +/* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */ + +#include <string.h> + +int c; +int x[2000]; +__attribute__((regparm(1))) void foo (int a, int b) + { + int t[200]; + if (a == 0 || c == 0) + return; + memcpy (t, x + b, sizeof t); + c = t[a]; + } + +/* { dg-final { scan-rtl-dump "Performing shrink-wrapping" "pro_and_epilogue" } } */ +/* { dg-final { cleanup-rtl-dump "pro_and_epilogue" } } */ diff --git a/gcc/testsuite/gcc.target/i386/tailcall-1.c b/gcc/testsuite/gcc.target/i386/tailcall-1.c index e6ae990a5c..9aae9d45ed 100644 --- a/gcc/testsuite/gcc.target/i386/tailcall-1.c +++ b/gcc/testsuite/gcc.target/i386/tailcall-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target nonpic } */ /* { dg-options "-O2" } */ diff --git a/gcc/testsuite/gcc.target/i386/tbm-2.c b/gcc/testsuite/gcc.target/i386/tbm-2.c index 447e0ab66c..fa3870a5e3 100644 --- a/gcc/testsuite/gcc.target/i386/tbm-2.c +++ b/gcc/testsuite/gcc.target/i386/tbm-2.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mtbm" } */ /* { dg-final { scan-assembler "bextr\[^\\n]*(%|)rax" } } */ /* { dg-final { scan-assembler "blcfill\[^\\n]*(%|)rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/testimm-9.c b/gcc/testsuite/gcc.target/i386/testimm-9.c new file mode 100644 index 0000000000..a9b4fe9e3b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testimm-9.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx2" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m256i l1, l2, l3, l4; +__m256d e1, e2, e3, e4; + +void +test8bit (void) +{ + l1 = _mm256_mpsadbw_epu8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_alignr_epi8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_blend_epi32 (i1, i1, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_blend_epi32 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_blend_epi16(l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute2x128_si256 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + e1 = _mm256_permute4x64_pd (e2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute4x64_epi64 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shuffle_epi32 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shufflehi_epi16 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shufflelo_epi16 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_slli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_srli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} + +void +test1bit (void) +{ + i1 = _mm256_extracti128_si256 (l1, 2); /* { dg-error "the last argument must be an 1-bit immediate" } */ + l1 = _mm256_inserti128_si256 (l1, i2, 2); /* { dg-error "the last argument must be an 1-bit immediate" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/udivmod-7.c b/gcc/testsuite/gcc.target/i386/udivmod-7.c index 14a065f68e..4a68a75f23 100644 --- a/gcc/testsuite/gcc.target/i386/udivmod-7.c +++ b/gcc/testsuite/gcc.target/i386/udivmod-7.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -m8bit-idiv" } */ -/* { dg-require-effective-target lp64 } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/udivmod-8.c b/gcc/testsuite/gcc.target/i386/udivmod-8.c index 16459fca58..bef496490a 100644 --- a/gcc/testsuite/gcc.target/i386/udivmod-8.c +++ b/gcc/testsuite/gcc.target/i386/udivmod-8.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -m8bit-idiv" } */ extern void foo (unsigned long long, unsigned long long, diff --git a/gcc/testsuite/gcc.target/i386/unroll-1.c b/gcc/testsuite/gcc.target/i386/unroll-1.c index 8cf19c4bea..cc8132e207 100644 --- a/gcc/testsuite/gcc.target/i386/unroll-1.c +++ b/gcc/testsuite/gcc.target/i386/unroll-1.c @@ -1,6 +1,6 @@ /* PR optimization/8599 */ /* { dg-do run } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-mtune=k6 -O2 -funroll-loops" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/vararg-1.c b/gcc/testsuite/gcc.target/i386/vararg-1.c index 9ed9ab087d..a2db4b9f77 100644 --- a/gcc/testsuite/gcc.target/i386/vararg-1.c +++ b/gcc/testsuite/gcc.target/i386/vararg-1.c @@ -1,8 +1,8 @@ /* PR middle-end/36858 */ /* { dg-do run } */ -/* { dg-options "-w" { target { lp64 } } } */ +/* { dg-options "-w" { target { ! { ia32 } } } } */ /* { dg-options "-w" { target { llp64 } } } */ -/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ilp32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */ /* { dg-require-effective-target sse2 } */ #include "sse2-check.h" diff --git a/gcc/testsuite/gcc.target/i386/vararg-2.c b/gcc/testsuite/gcc.target/i386/vararg-2.c index 804801256f..bd5ad54463 100644 --- a/gcc/testsuite/gcc.target/i386/vararg-2.c +++ b/gcc/testsuite/gcc.target/i386/vararg-2.c @@ -1,8 +1,8 @@ /* PR middle-end/36859 */ /* { dg-do run } */ -/* { dg-options "-w" { target { lp64 } } } */ +/* { dg-options "-w" { target { ! { ia32 } } } } */ /* { dg-options "-w" { target { llp64 } } } */ -/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ilp32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */ /* { dg-require-effective-target sse2 } */ #include "sse2-check.h" diff --git a/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc/testsuite/gcc.target/i386/vecinit-1.c index a5091cd85f..17e2959851 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-1.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=k8 -msse2" } */ +/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */ #define vector __attribute__((vector_size(16))) diff --git a/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc/testsuite/gcc.target/i386/vecinit-2.c index 52998a6bfc..d7b910062d 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-2.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=k8 -msse2" } */ +/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */ #define vector __attribute__((vector_size(16))) diff --git a/gcc/testsuite/gcc.target/i386/vect-double-1.c b/gcc/testsuite/gcc.target/i386/vect-double-1.c index 87e5fe94b2..0b691bcbba 100644 --- a/gcc/testsuite/gcc.target/i386/vect-double-1.c +++ b/gcc/testsuite/gcc.target/i386/vect-double-1.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=core2" } } */ /* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -march=core2 -fdump-tree-vect-stats" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/vect8-ret.c b/gcc/testsuite/gcc.target/i386/vect8-ret.c index f2eb81b386..c2e21068a0 100644 --- a/gcc/testsuite/gcc.target/i386/vect8-ret.c +++ b/gcc/testsuite/gcc.target/i386/vect8-ret.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target ilp32 } } */ +/* { dg-do compile { target ia32 } } */ /* { dg-options "-mmmx" { target i?86-*-solaris2.[89] *-*-vxworks* } } */ /* { dg-options "-mmmx -mvect8-ret-in-mem" } */ diff --git a/gcc/testsuite/gcc.target/i386/vectorize4-avx.c b/gcc/testsuite/gcc.target/i386/vectorize4-avx.c index 8e4a747a64..33e9918937 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize4-avx.c +++ b/gcc/testsuite/gcc.target/i386/vectorize4-avx.c @@ -11,4 +11,4 @@ calc_freq (int *dest) dest[i] = sqrt (tmp_out[i]); } -/* { dg-final { scan-assembler "vsqrtpd\[ \\t\]+\[^\n\]*%ymm" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "vsqrtpd\[ \\t\]+\[^\n\]*%ymm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vectorize5.c b/gcc/testsuite/gcc.target/i386/vectorize5.c index 04f044f621..2065e5d157 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize5.c +++ b/gcc/testsuite/gcc.target/i386/vectorize5.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -ftree-vectorize -mveclibabi=acml -ffast-math -mtune=generic" } */ double x[256]; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v2df.c b/gcc/testsuite/gcc.target/i386/vperm-v2df.c index 40a51306fd..5aefc05f47 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v2df.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v2df.c @@ -16,7 +16,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1) \ - b.v = __builtin_ia32_vec_perm_v2df (i[0].v, i[1].v, (IV){E0, E1}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ __asm__("" : : : "memory"); \ diff --git a/gcc/testsuite/gcc.target/i386/vperm-v2di.c b/gcc/testsuite/gcc.target/i386/vperm-v2di.c index 8e300837da..282cce6e9b 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v2di.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v2di.c @@ -16,7 +16,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1) \ - b.v = __builtin_ia32_vec_perm_v2di (i[0].v, i[1].v, (IV){E0, E1}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ __asm__("" : : : "memory"); \ diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c b/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c index 23608b3cf0..f16c34bc2b 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c @@ -16,7 +16,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1, E2, E3) \ - b.v = __builtin_ia32_vec_perm_v4sf (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ c.s[2] = i[0].s[E2]; \ diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c b/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c index a0d49874f9..12a4623700 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c @@ -15,7 +15,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1, E2, E3) \ - b.v = __builtin_ia32_vec_perm_v4sf (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ c.s[2] = i[0].s[E2]; \ diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c b/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c index 01b7c6fdab..4667f9556b 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c @@ -16,7 +16,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1, E2, E3) \ - b.v = __builtin_ia32_vec_perm_v4si (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ c.s[2] = i[0].s[E2]; \ diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c b/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c index 43f88ee093..9304345559 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c @@ -15,7 +15,7 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); #define assert(T) ((T) || (__builtin_trap (), 0)) #define TEST(E0, E1, E2, E3) \ - b.v = __builtin_ia32_vec_perm_v4si (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ c.s[0] = i[0].s[E0]; \ c.s[1] = i[0].s[E1]; \ c.s[2] = i[0].s[E2]; \ diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c new file mode 100644 index 0000000000..6fecf92620 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (4, int) v0 = {argc, 1, 15, 38}; + vector (4, int) v1 = {-4, argc, 2, 11}; + vector (4, int) res[] = + { + v0 + v1, /* { dg-warning "expanded piecewise" } */ + v0 - v1, /* { dg-warning "expanded piecewise" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c new file mode 100644 index 0000000000..6e63119244 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (16, signed char) v0 = {argc, 1, 15, 38, 12, -1, argc, 2, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) v1 = {-4, argc, 2, 11, 1, 17, -8, argc, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c b/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c new file mode 100644 index 0000000000..bdbd8b520b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (8, short) v0 = {argc, 1, 15, 38, 12, -1, argc, 2}; + vector (8, short) v1 = {-4, argc, 2, 11, 1, 17, -8, argc}; + vector (8, short) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc/testsuite/gcc.target/i386/wmul-1.c b/gcc/testsuite/gcc.target/i386/wmul-1.c index 3497f71ce5..4ef8385ef8 100644 --- a/gcc/testsuite/gcc.target/i386/wmul-1.c +++ b/gcc/testsuite/gcc.target/i386/wmul-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ long long mac(const int *a, const int *b, long long sqr, long long *sum) { diff --git a/gcc/testsuite/gcc.target/i386/wmul-2.c b/gcc/testsuite/gcc.target/i386/wmul-2.c index 51de26960d..0a82654450 100644 --- a/gcc/testsuite/gcc.target/i386/wmul-2.c +++ b/gcc/testsuite/gcc.target/i386/wmul-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ void vec_mpy(int y[], const int x[], int scaler) { diff --git a/gcc/testsuite/gcc.target/i386/wrfsbase-1.c b/gcc/testsuite/gcc.target/i386/wrfsbase-1.c index 4b849269bb..dc1503817b 100644 --- a/gcc/testsuite/gcc.target/i386/wrfsbase-1.c +++ b/gcc/testsuite/gcc.target/i386/wrfsbase-1.c @@ -1,7 +1,6 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ -/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)edi" } } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(edi|ecx)" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/wrfsbase-2.c b/gcc/testsuite/gcc.target/i386/wrfsbase-2.c index 5e1762dfa3..fc4a7b5fff 100644 --- a/gcc/testsuite/gcc.target/i386/wrfsbase-2.c +++ b/gcc/testsuite/gcc.target/i386/wrfsbase-2.c @@ -1,7 +1,6 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ -/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)rdi" } } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(rdi|rcx)" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/wrgsbase-1.c b/gcc/testsuite/gcc.target/i386/wrgsbase-1.c index 15d2d7ffb9..5474288be0 100644 --- a/gcc/testsuite/gcc.target/i386/wrgsbase-1.c +++ b/gcc/testsuite/gcc.target/i386/wrgsbase-1.c @@ -1,7 +1,6 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ -/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)edi" } } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(edi|ecx)" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/wrgsbase-2.c b/gcc/testsuite/gcc.target/i386/wrgsbase-2.c index 0a33d77071..cf94750842 100644 --- a/gcc/testsuite/gcc.target/i386/wrgsbase-2.c +++ b/gcc/testsuite/gcc.target/i386/wrgsbase-2.c @@ -1,7 +1,6 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mfsgsbase" } */ -/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)rdi" } } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(rdi|rcx)" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/xop-check.h b/gcc/testsuite/gcc.target/i386/xop-check.h index 7e8e665c79..395abe8766 100644 --- a/gcc/testsuite/gcc.target/i386/xop-check.h +++ b/gcc/testsuite/gcc.target/i386/xop-check.h @@ -24,5 +24,5 @@ main () if (ecx & bit_XOP) do_test (); - exit (0); + return 0; } diff --git a/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c index 0406d023df..0730987e1a 100644 --- a/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c @@ -32,5 +32,5 @@ int main () exit (0); } -/* { dg-final { scan-assembler "vpmacsdql" } } */ +/* { dg-final { scan-assembler "vpmuldq" } } */ /* { dg-final { scan-assembler "vpmacsdqh" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-mul-1.c b/gcc/testsuite/gcc.target/i386/xop-mul-1.c new file mode 100644 index 0000000000..47ef1bc02b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O3 -mxop" } */ + +#ifndef CHECK_H +#define CHECK_H "xop-check.h" +#endif + +#ifndef TEST +#define TEST xop_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc/testsuite/gcc.target/i386/xop-pcmov.c b/gcc/testsuite/gcc.target/i386/xop-pcmov.c index d6375b1fd5..75ed433cf0 100644 --- a/gcc/testsuite/gcc.target/i386/xop-pcmov.c +++ b/gcc/testsuite/gcc.target/i386/xop-pcmov.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes conditional floating point moves into the pcmov instruction on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-pcmov2.c b/gcc/testsuite/gcc.target/i386/xop-pcmov2.c index 617da39da9..6b6bd21691 100644 --- a/gcc/testsuite/gcc.target/i386/xop-pcmov2.c +++ b/gcc/testsuite/gcc.target/i386/xop-pcmov2.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes conditional floating point moves into the pcmov instruction on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c index e3ae644d0b..f2b9eb8455 100644 --- a/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector rotate instructions vector into prot on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c index 9996279bc0..11d40023f8 100644 --- a/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector rotate instructions vector into prot on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c index 73d52f5f3f..eb3c614315 100644 --- a/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector rotate instructions vector into prot on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c index eb84439c49..16b3a6b755 100644 --- a/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector shift instructions into psha/pshl on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c index e59c30d021..1f1ed630ee 100644 --- a/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector shift instructions into psha/pshl on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c index 2b9302db52..de6417876e 100644 --- a/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c @@ -1,8 +1,7 @@ /* Test that the compiler properly optimizes vector shift instructions into psha/pshl on XOP systems. */ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mxop -ftree-vectorize" } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/xop-vshift-1.c b/gcc/testsuite/gcc.target/i386/xop-vshift-1.c new file mode 100644 index 0000000000..ee3d299039 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-vshift-1.c @@ -0,0 +1,145 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#ifndef CHECK_H +#define CHECK_H "xop-check.h" +#endif + +#ifndef TEST +#define TEST xop_test +#endif + +#include CHECK_H + +#define N 64 + +#ifndef TYPE1 +#define TYPE1 int +#define TYPE2 long long +#endif + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +signed TYPE1 a[N], b[N], g[N]; +unsigned TYPE1 c[N], h[N]; +signed TYPE2 d[N], e[N], j[N]; +unsigned TYPE2 f[N], k[N]; + +__attribute__((noinline)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + g[i] = a[i] << b[i]; +} + +__attribute__((noinline)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + g[i] = a[i] >> b[i]; +} + +__attribute__((noinline)) void +f3 (void) +{ + int i; + for (i = 0; i < N; i++) + h[i] = c[i] >> b[i]; +} + +__attribute__((noinline)) void +f4 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] << e[i]; +} + +__attribute__((noinline)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] >> e[i]; +} + +__attribute__((noinline)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + k[i] = f[i] >> e[i]; +} + +__attribute__((noinline)) void +f7 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] << b[i]; +} + +__attribute__((noinline)) void +f8 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] >> b[i]; +} + +__attribute__((noinline)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + k[i] = f[i] >> b[i]; +} + +static void +TEST () +{ + int i; + for (i = 0; i < N; i++) + { + asm (""); + c[i] = (random () << 1) | (random () & 1); + b[i] = (i * 85) & (sizeof (TYPE1) * __CHAR_BIT__ - 1); + a[i] = c[i]; + d[i] = (random () << 1) | (random () & 1); + d[i] |= (unsigned long long) c[i] << 32; + e[i] = (i * 85) & (sizeof (TYPE2) * __CHAR_BIT__ - 1); + f[i] = d[i]; + } + f1 (); + f3 (); + f4 (); + f6 (); + for (i = 0; i < N; i++) + if (g[i] != (signed TYPE1) (a[i] << b[i]) + || h[i] != (unsigned TYPE1) (c[i] >> b[i]) + || j[i] != (signed TYPE2) (d[i] << e[i]) + || k[i] != (unsigned TYPE2) (f[i] >> e[i])) + abort (); + f2 (); + f5 (); + f9 (); + for (i = 0; i < N; i++) + if (g[i] != (signed TYPE1) (a[i] >> b[i]) + || j[i] != (signed TYPE2) (d[i] >> e[i]) + || k[i] != (unsigned TYPE2) (f[i] >> b[i])) + abort (); + f7 (); + for (i = 0; i < N; i++) + if (j[i] != (signed TYPE2) (d[i] << b[i])) + abort (); + f8 (); + for (i = 0; i < N; i++) + if (j[i] != (signed TYPE2) (d[i] >> b[i])) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/xop-vshift-2.c b/gcc/testsuite/gcc.target/i386/xop-vshift-2.c new file mode 100644 index 0000000000..81e86d098e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-vshift-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#define TYPE1 char +#define TYPE2 short + +#include "xop-vshift-1.c" diff --git a/gcc/testsuite/gcc.target/i386/zee.c b/gcc/testsuite/gcc.target/i386/zee.c index b46e890e2b..1975b02b2f 100644 --- a/gcc/testsuite/gcc.target/i386/zee.c +++ b/gcc/testsuite/gcc.target/i386/zee.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target lp64 } */ +/* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -fzee" } */ /* { dg-final { scan-assembler-not "mov\[\\t \]+\(%\[\^,\]+\),\[\\t \]*\\1" } } */ int mask[100]; diff --git a/gcc/testsuite/gcc.target/ia64/pr48496.c b/gcc/testsuite/gcc.target/ia64/pr48496.c new file mode 100644 index 0000000000..6e604336ad --- /dev/null +++ b/gcc/testsuite/gcc.target/ia64/pr48496.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int UINT64 __attribute__((__mode__(__DI__))); + +typedef struct +{ + UINT64 x[2] __attribute__((aligned(16))); +} fpreg; + +struct ia64_args +{ + fpreg fp_regs[8]; + UINT64 gp_regs[8]; +}; + +ffi_call(long i, long gpcount, long fpcount, void **avalue) +{ + struct ia64_args *stack; + stack = __builtin_alloca (64); + asm ("stf.spill %0 = %1%P0" : "=m" (*&stack->fp_regs[fpcount++]) + : "f"(*(double *)avalue[i])); + stack->gp_regs[gpcount++] = *(UINT64 *)avalue[i]; +} diff --git a/gcc/testsuite/gcc.target/ia64/pr49303.c b/gcc/testsuite/gcc.target/ia64/pr49303.c new file mode 100644 index 0000000000..2d88304f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/ia64/pr49303.c @@ -0,0 +1,185 @@ +/* { dg-do compile } */ +/* { dg-options "-w -O2 -fselective-scheduling2 -fsel-sched-pipelining" } */ + +typedef struct rtx_def *rtx; +typedef const struct rtx_def *const_rtx; +typedef struct basic_block_def *basic_block; +enum machine_mode { + VOIDmode, BLKmode, CCmode, CCImode, BImode, QImode, HImode, SImode, DImode, TImode, OImode, QQmode, HQmode, SQmode, DQmode, TQmode, UQQmode, UHQmode, USQmode, UDQmode, UTQmode, HAmode, SAmode, DAmode, TAmode, UHAmode, USAmode, UDAmode, UTAmode, SFmode, DFmode, XFmode, RFmode, TFmode, SDmode, DDmode, TDmode, CQImode, CHImode, CSImode, CDImode, CTImode, COImode, SCmode, DCmode, XCmode, RCmode, TCmode, V4QImode, V2HImode, V8QImode, V4HImode, V2SImode, V16QImode, V8HImode, V4SImode, V2SFmode, V4SFmode, MAX_MACHINE_MODE, MIN_MODE_RANDOM = VOIDmode, MAX_MODE_RANDOM = BLKmode, MIN_MODE_CC = CCmode, MAX_MODE_CC = CCImode, MIN_MODE_INT = QImode, MAX_MODE_INT = OImode, MIN_MODE_PARTIAL_INT = VOIDmode, MAX_MODE_PARTIAL_INT = VOIDmode, MIN_MODE_FRACT = QQmode, MAX_MODE_FRACT = TQmode, MIN_MODE_UFRACT = UQQmode, MAX_MODE_UFRACT = UTQmode, MIN_MODE_ACCUM = HAmode, MAX_MODE_ACCUM = TAmode, MIN_MODE_UACCUM = UHAmode, MAX_MODE_UACCUM = UTAmode, MIN_MODE_FLOAT = SFmode, MAX_MODE_FLOAT = TFmode, MIN_MODE_DECIMAL_FLOAT = SDmode, MAX_MODE_DECIMAL_FLOAT = TDmode, MIN_MODE_COMPLEX_INT = CQImode, MAX_MODE_COMPLEX_INT = COImode, MIN_MODE_COMPLEX_FLOAT = SCmode, MAX_MODE_COMPLEX_FLOAT = TCmode, MIN_MODE_VECTOR_INT = V4QImode, MAX_MODE_VECTOR_INT = V4SImode, MIN_MODE_VECTOR_FRACT = VOIDmode, MAX_MODE_VECTOR_FRACT = VOIDmode, MIN_MODE_VECTOR_UFRACT = VOIDmode, MAX_MODE_VECTOR_UFRACT = VOIDmode, MIN_MODE_VECTOR_ACCUM = VOIDmode, MAX_MODE_VECTOR_ACCUM = VOIDmode, MIN_MODE_VECTOR_UACCUM = VOIDmode, MAX_MODE_VECTOR_UACCUM = VOIDmode, MIN_MODE_VECTOR_FLOAT = V2SFmode, MAX_MODE_VECTOR_FLOAT = V4SFmode, NUM_MACHINE_MODES = MAX_MACHINE_MODE }; +struct real_value { +}; +extern void vec_assert_fail (const char *, const char * ,const char *file_,unsigned line_,const char *function_) __attribute__ ((__noreturn__)); +typedef struct vec_prefix { + unsigned num; +}; +enum rtx_code { + UNKNOWN , VALUE , DEBUG_EXPR , EXPR_LIST , INSN_LIST , SEQUENCE , ADDRESS , DEBUG_INSN , INSN , JUMP_INSN , CALL_INSN , BARRIER , CODE_LABEL , NOTE , COND_EXEC , PARALLEL , ASM_INPUT , ASM_OPERANDS , UNSPEC , UNSPEC_VOLATILE , ADDR_VEC , ADDR_DIFF_VEC , PREFETCH , SET , USE , CLOBBER , CALL , RETURN , EH_RETURN , TRAP_IF , CONST_INT , CONST_FIXED , CONST_DOUBLE , CONST_VECTOR , CONST_STRING , CONST , PC , REG , SCRATCH , SUBREG , STRICT_LOW_PART , CONCAT , CONCATN , MEM , LABEL_REF , SYMBOL_REF , CC0 , IF_THEN_ELSE , COMPARE , PLUS , MINUS , NEG , MULT , SS_MULT , US_MULT , DIV , SS_DIV , US_DIV , MOD , UDIV , UMOD , AND , IOR , XOR , NOT , ASHIFT , ROTATE , ASHIFTRT , LSHIFTRT , ROTATERT , SMIN , SMAX , UMIN , UMAX , PRE_DEC , PRE_INC , POST_DEC , POST_INC , PRE_MODIFY , POST_MODIFY , NE , EQ , GE , GT , LE , LT , GEU , GTU , LEU , LTU , UNORDERED , ORDERED , UNEQ , UNGE , UNGT , UNLE , UNLT , LTGT , SIGN_EXTEND , ZERO_EXTEND , TRUNCATE , FLOAT_EXTEND , FLOAT_TRUNCATE , FLOAT , FIX , UNSIGNED_FLOAT , UNSIGNED_FIX , FRACT_CONVERT , UNSIGNED_FRACT_CONVERT , SAT_FRACT , UNSIGNED_SAT_FRACT , ABS , SQRT , BSWAP , FFS , CLZ , CTZ , POPCOUNT , PARITY , SIGN_EXTRACT , ZERO_EXTRACT , HIGH , LO_SUM , VEC_MERGE , VEC_SELECT , VEC_CONCAT , VEC_DUPLICATE , SS_PLUS , US_PLUS , SS_MINUS , SS_NEG , US_NEG , SS_ABS , SS_ASHIFT , US_ASHIFT , US_MINUS , SS_TRUNCATE , US_TRUNCATE , FMA , VAR_LOCATION , DEBUG_IMPLICIT_PTR , ENTRY_VALUE , LAST_AND_UNUSED_RTX_CODE}; +enum rtx_class { + RTX_COMPARE, RTX_COMM_COMPARE, RTX_BIN_ARITH, RTX_COMM_ARITH, RTX_UNARY, RTX_EXTRA, RTX_MATCH, RTX_INSN, RTX_OBJ, RTX_CONST_OBJ, RTX_TERNARY, RTX_BITFIELD_OPS, RTX_AUTOINC }; +extern const enum rtx_class rtx_class[((int) LAST_AND_UNUSED_RTX_CODE)]; +union rtunion_def { + int rt_int; + unsigned int rt_uint; + rtx rt_rtx; +}; +typedef union rtunion_def rtunion; +struct rtx_def { + __extension__ enum rtx_code code: 16; + __extension__ enum machine_mode mode : 8; + unsigned int unchanging : 1; + union u { + rtunion fld[1]; + } + u; +}; +static __inline__ unsigned int rhs_regno (const_rtx x) { + return (((x)->u.fld[0]).rt_uint); +} +struct regstat_n_sets_and_refs_t { + int sets; +}; +extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs; +static __inline__ int REG_N_SETS (int regno) { + return regstat_n_sets_and_refs[regno].sets; +} +struct target_regs { + unsigned char x_hard_regno_nregs[334][MAX_MACHINE_MODE]; +}; +extern struct target_regs default_target_regs; +static __inline__ unsigned int end_hard_regno (enum machine_mode mode, unsigned int regno) { + return regno + ((&default_target_regs)->x_hard_regno_nregs)[regno][(int) mode]; +} +struct function { + struct eh_status *eh; + struct control_flow_graph *cfg; +}; +extern struct function *cfun; +typedef struct VEC_edge_gc { +} +VEC_edge_gc; +struct basic_block_def { + VEC_edge_gc *preds; + struct basic_block_def *next_bb; + int index; +} +VEC_basic_block_gc; +struct control_flow_graph { + basic_block x_entry_block_ptr; +} +bitmap_obstack; +typedef struct bitmap_element_def { +} +bitmap_element; +typedef struct bitmap_head_def { + bitmap_element *first; + bitmap_element *current; +} +bitmap_head; +struct dataflow { + struct df_problem *problem; + void *block_info; + unsigned int block_info_size; +}; +struct df_insn_info { + int luid; +}; +struct df_d { + struct dataflow *problems_by_index[(7 + 1)]; + struct df_insn_info **insns; +}; +struct df_lr_bb_info { + bitmap_head def; + bitmap_head in; +}; +extern struct df_d *df; +static __inline__ struct df_lr_bb_info * df_lr_get_bb_info (unsigned int index) { + if (index < (df->problems_by_index[1])->block_info_size) return &((struct df_lr_bb_info *) (df->problems_by_index[1])->block_info)[index]; + else return ((void *)0); +} +typedef struct reg_stat_struct { + int last_set_label; + unsigned long last_set_nonzero_bits; + char last_set_invalid; +} +reg_stat_type; +typedef struct VEC_reg_stat_type_base { + struct vec_prefix prefix; + reg_stat_type vec[1]; +} +VEC_reg_stat_type_base; +static __inline__ reg_stat_type *VEC_reg_stat_type_base_index (VEC_reg_stat_type_base *vec_, unsigned ix_ ,const char *file_,unsigned line_,const char *function_) { + (void)((vec_ && ix_ < vec_->prefix.num) ? 0 : (vec_assert_fail ("index","VEC(reg_stat_type,base)" ,file_,line_,function_), 0)); + return &vec_->vec[ix_]; +} +typedef struct VEC_reg_stat_type_heap { + VEC_reg_stat_type_base base; +} +VEC_reg_stat_type_heap; +static VEC_reg_stat_type_heap *reg_stat; +static int mem_last_set; +static int label_tick; +int get_last_value_validate (rtx *loc, rtx insn, int tick, int replace) +{ + rtx x = *loc; + int i, j; + if ((((enum rtx_code) (x)->code) == REG)) + { + unsigned int regno = (rhs_regno(x)); + unsigned int endregno = (((((rhs_regno(x))) < 334)) ? end_hard_regno (((enum machine_mode) (x)->mode), (rhs_regno(x))) : (rhs_regno(x)) + 1); + for (j = regno; + j < endregno; + j++) + { + reg_stat_type *rsp = (VEC_reg_stat_type_base_index(((reg_stat) ? &(reg_stat)->base : 0),j ,"/gcc/combine.c",12640,__FUNCTION__)); + if ( + rsp->last_set_invalid + || + ( + ( + regno >= 334 + && REG_N_SETS (regno) == 1 + && (!bitmap_bit_p ((&(df_lr_get_bb_info((((cfun + 0)->cfg->x_entry_block_ptr)->next_bb)->index))->in), regno) ) + ) + && rsp->last_set_label > tick + ) + ) + { + return replace; + } + } + } + else if ((((enum rtx_code) (x)->code) == MEM) + && + ( + ( + { + __typeof ((x)) const _rtx = ((x)); + _rtx; + } + )->unchanging + ) + && + ( + tick != label_tick + || ((((df->insns[((((insn)->u.fld[0]).rt_int))]))->luid)) <= mem_last_set + ) + ) + { + { + if ( + i == 1 + ) + { + rtx x0 = (((x)->u.fld[0]).rt_rtx); + rtx x1 = (((x)->u.fld[1]).rt_rtx); + if ((((rtx_class[(int) (((enum rtx_code) (x1)->code))]) & (~1)) == (RTX_COMM_ARITH & (~1))) + && + ( + x0 == (((x1)->u.fld[0]).rt_rtx) + ) + ) + return get_last_value_validate (&(((x1)->u.fld[x0 == (((x1)->u.fld[0]).rt_rtx) ? 1 : 0]).rt_rtx) , insn, tick, replace); + } + } + } +} diff --git a/gcc/testsuite/gcc.target/ia64/pr52657.c b/gcc/testsuite/gcc.target/ia64/pr52657.c new file mode 100644 index 0000000000..8db5881985 --- /dev/null +++ b/gcc/testsuite/gcc.target/ia64/pr52657.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +typedef unsigned long int mp_limb_t; + +typedef struct +{ + int _mp_alloc; + int _mp_size; + mp_limb_t *_mp_d; +} __mpz_struct; + +typedef __mpz_struct mpz_t[1]; +typedef mp_limb_t * mp_ptr; +typedef const mp_limb_t * mp_srcptr; +typedef long int mp_size_t; + +extern mp_limb_t __gmpn_addmul_2 (mp_ptr, mp_srcptr, mp_size_t, mp_srcptr); + +void +__gmpn_redc_2 (mp_ptr rp, mp_ptr up, mp_srcptr mp, mp_size_t n, mp_srcptr mip) +{ + mp_limb_t q[2]; + mp_size_t j; + mp_limb_t upn; + + for (j = n - 2; j >= 0; j -= 2) + { + mp_limb_t _ph, _pl; + __asm__ ("xma.hu %0 = %3, %5, f0\n\t" + "xma.l %1 = %3, %5, f0\n\t" + ";;\n\t" + "xma.l %0 = %3, %4, %0\n\t" + ";;\n\t" + "xma.l %0 = %2, %5, %0" + : "=&f" (q[1]), "=&f" (q[0]) + : "f" (mip[1]), "f" (mip[0]), "f" (up[1]), "f" (up[0])); + upn = up[n]; + up[1] = __gmpn_addmul_2 (up, mp, n, q); + up[0] = up[n]; + up[n] = upn; + up += 2; + } +} diff --git a/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c b/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c new file mode 100644 index 0000000000..ebc5dd6724 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp32 -mlong32 -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c b/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c new file mode 100644 index 0000000000..5a776eca98 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp32 -mlong64 -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c b/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c new file mode 100644 index 0000000000..3882e48fa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp64 -mlong32 -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c b/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c new file mode 100644 index 0000000000..5569bf521e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp64 -mlong64 -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-main.h b/gcc/testsuite/gcc.target/mips/abi-main.h new file mode 100644 index 0000000000..f47a2e3049 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-main.h @@ -0,0 +1,74 @@ +#define FOR_EACH_SCALAR(F) \ + F(sc, signed char) \ + F(uc, unsigned char) \ + F(ss, short) \ + F(us, unsigned short) \ + F(si, int) \ + F(ui, unsigned int) \ + F(sl, long) \ + F(ul, unsigned long) \ + F(sll, long long) \ + F(ull, unsigned long long) \ + F(f, float) \ + F(d, double) \ + F(ld, long double) \ + F(ptr, void *) + +#define EXTERN(SUFFIX, TYPE) extern TYPE x##SUFFIX; +#define STATIC(SUFFIX, TYPE) static TYPE s##SUFFIX; +#define COMMON(SUFFIX, TYPE) TYPE c##SUFFIX; + +#define GETADDR(SUFFIX, TYPE) \ + TYPE *get##SUFFIX (int which) \ + { \ + return (which == 0 ? &c##SUFFIX \ + : which == 1 ? &s##SUFFIX \ + : &x##SUFFIX); \ + } + +#define COPY(SUFFIX, TYPE) c##SUFFIX = s##SUFFIX; s##SUFFIX = x##SUFFIX; + +FOR_EACH_SCALAR (EXTERN) +FOR_EACH_SCALAR (STATIC) +FOR_EACH_SCALAR (COMMON) + +FOR_EACH_SCALAR (GETADDR) + +void +copy (void) +{ + FOR_EACH_SCALAR (COPY); +} + +extern void foo (int); + +void +sibcall1 (void) +{ + foo (1); +} + +void +sibcall2 (void) +{ + foo (csi + ssi + xsi); +} + +static void +sibcall3 (void) +{ + foo (1); + foo (2); + foo (3); +} + +extern void bar (void (*) (void)); + +int +nested (int x) +{ + void sub (void) { foo (x); } + bar (sub); + bar (sibcall3); + return 1; +} diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c new file mode 100644 index 0000000000..5cab4c97a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 -mabicalls -mno-shared -mno-plt -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c b/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c new file mode 100644 index 0000000000..eb455da96a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 -fpic -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long32.c b/gcc/testsuite/gcc.target/mips/abi-n32-long32.c new file mode 100644 index 0000000000..6a0f7023c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 addressing=absolute -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c new file mode 100644 index 0000000000..3edf86787c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 -mabicalls -mno-shared -mno-plt -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c b/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c new file mode 100644 index 0000000000..b444209e3b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 -fpic -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n32-long64.c b/gcc/testsuite/gcc.target/mips/abi-n32-long64.c new file mode 100644 index 0000000000..868719c445 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n32-long64.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 addressing=absolute -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c new file mode 100644 index 0000000000..b268d888a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 -mabicalls -mno-shared -mno-plt -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c b/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c new file mode 100644 index 0000000000..5a0d917265 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 -fpic -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long32.c b/gcc/testsuite/gcc.target/mips/abi-n64-long32.c new file mode 100644 index 0000000000..4227169ec7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long32.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 addressing=absolute -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c new file mode 100644 index 0000000000..5301cfc5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 -mabicalls -mno-shared -mno-plt -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c b/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c new file mode 100644 index 0000000000..f43e9157ba --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 -fpic -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-n64-long64.c b/gcc/testsuite/gcc.target/mips/abi-n64-long64.c new file mode 100644 index 0000000000..a670fe5af9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-n64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 addressing=absolute -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c new file mode 100644 index 0000000000..2032b36d9d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 -mabicalls -mno-shared -mno-plt -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c b/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c new file mode 100644 index 0000000000..5a3e93effa --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 -fpic -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long32.c b/gcc/testsuite/gcc.target/mips/abi-o32-long32.c new file mode 100644 index 0000000000..bdb9464c74 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 addressing=absolute -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c new file mode 100644 index 0000000000..6340b63252 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 -mabicalls -mno-shared -mno-plt -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c b/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c new file mode 100644 index 0000000000..1583034b2a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 -fpic -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o32-long64.c b/gcc/testsuite/gcc.target/mips/abi-o32-long64.c new file mode 100644 index 0000000000..4a88739b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o32-long64.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 addressing=absolute -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c new file mode 100644 index 0000000000..548ae0d4a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 -mabicalls -mno-shared -mno-plt -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c b/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c new file mode 100644 index 0000000000..89d03ab674 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 -fpic -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long32.c b/gcc/testsuite/gcc.target/mips/abi-o64-long32.c new file mode 100644 index 0000000000..db5893e452 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 addressing=absolute -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c b/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c new file mode 100644 index 0000000000..df164b22f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=o64 -mlong64 -mabicalls -mno-shared -mno-plt -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c b/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c new file mode 100644 index 0000000000..df58d1f028 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=o64 -mlong64 -fpic -O2" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/abi-o64-long64.c b/gcc/testsuite/gcc.target/mips/abi-o64-long64.c new file mode 100644 index 0000000000..43078f6809 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/abi-o64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong64 -mno-abicalls -O2" } */ +#include "abi-main.h" diff --git a/gcc/testsuite/gcc.target/mips/atomic-memory-1.c b/gcc/testsuite/gcc.target/mips/atomic-memory-1.c index b2316ee646..839d75c2b2 100644 --- a/gcc/testsuite/gcc.target/mips/atomic-memory-1.c +++ b/gcc/testsuite/gcc.target/mips/atomic-memory-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */ +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target mips_llsc } 0 } */ extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc/testsuite/gcc.target/mips/branch-1.c index 62d6bbb619..2f4510f8dd 100644 --- a/gcc/testsuite/gcc.target/mips/branch-1.c +++ b/gcc/testsuite/gcc.target/mips/branch-1.c @@ -2,7 +2,7 @@ but we test for "bbit" elsewhere. On other targets, we should implement the "if" statements using an "andi" instruction followed by a branch on zero. */ -/* { dg-options "-O2 forbid_cpu=octeon" } */ +/* { dg-options "-O2 forbid_cpu=octeon.*" } */ void bar (void); NOMIPS16 void f1 (int x) { if (x & 4) bar (); } diff --git a/gcc/testsuite/gcc.target/mips/branch-10.c b/gcc/testsuite/gcc.target/mips/branch-10.c index 7fdebfcc3f..8186030e6e 100644 --- a/gcc/testsuite/gcc.target/mips/branch-10.c +++ b/gcc/testsuite/gcc.target/mips/branch-10.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-11.c b/gcc/testsuite/gcc.target/mips/branch-11.c index 1c57f82f53..a314740655 100644 --- a/gcc/testsuite/gcc.target/mips/branch-11.c +++ b/gcc/testsuite/gcc.target/mips/branch-11.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler "\tsd\t\\\$28," } } */ /* { dg-final { scan-assembler "\tld\t\\\$28," } } */ /* { dg-final { scan-assembler "\taddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-12.c b/gcc/testsuite/gcc.target/mips/branch-12.c index f1b6f1e824..3e5b421cf8 100644 --- a/gcc/testsuite/gcc.target/mips/branch-12.c +++ b/gcc/testsuite/gcc.target/mips/branch-12.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-13.c b/gcc/testsuite/gcc.target/mips/branch-13.c index cc0b607d72..9bd94146a6 100644 --- a/gcc/testsuite/gcc.target/mips/branch-13.c +++ b/gcc/testsuite/gcc.target/mips/branch-13.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler "\tsd\t\\\$28," } } */ /* { dg-final { scan-assembler "\tld\t\\\$28," } } */ /* { dg-final { scan-assembler "\tdaddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-2.c b/gcc/testsuite/gcc.target/mips/branch-2.c index 845e748172..f6642cb874 100644 --- a/gcc/testsuite/gcc.target/mips/branch-2.c +++ b/gcc/testsuite/gcc.target/mips/branch-2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|cpload)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "cprestore" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-3.c b/gcc/testsuite/gcc.target/mips/branch-3.c index 0a4ffbba60..198d6ec648 100644 --- a/gcc/testsuite/gcc.target/mips/branch-3.c +++ b/gcc/testsuite/gcc.target/mips/branch-3.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */ /* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "cprestore" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-4.c b/gcc/testsuite/gcc.target/mips/branch-4.c index 277bd0af76..31e4909e58 100644 --- a/gcc/testsuite/gcc.target/mips/branch-4.c +++ b/gcc/testsuite/gcc.target/mips/branch-4.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-5.c b/gcc/testsuite/gcc.target/mips/branch-5.c index 3d151d824e..1e9c120c83 100644 --- a/gcc/testsuite/gcc.target/mips/branch-5.c +++ b/gcc/testsuite/gcc.target/mips/branch-5.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler "\taddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ /* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-6.c b/gcc/testsuite/gcc.target/mips/branch-6.c index 9bf73f01c9..77e0340eb2 100644 --- a/gcc/testsuite/gcc.target/mips/branch-6.c +++ b/gcc/testsuite/gcc.target/mips/branch-6.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-7.c b/gcc/testsuite/gcc.target/mips/branch-7.c index 053ec610c3..8ad6808c8d 100644 --- a/gcc/testsuite/gcc.target/mips/branch-7.c +++ b/gcc/testsuite/gcc.target/mips/branch-7.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler "\tdaddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ /* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-8.c b/gcc/testsuite/gcc.target/mips/branch-8.c index c2cbae3690..4595feafa6 100644 --- a/gcc/testsuite/gcc.target/mips/branch-8.c +++ b/gcc/testsuite/gcc.target/mips/branch-8.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-9.c b/gcc/testsuite/gcc.target/mips/branch-9.c index 2b83ea5b59..417507cc48 100644 --- a/gcc/testsuite/gcc.target/mips/branch-9.c +++ b/gcc/testsuite/gcc.target/mips/branch-9.c @@ -1,4 +1,4 @@ -/* { dg-options "-mabicalls -mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */ /* { dg-final { scan-assembler "\t\\.cprestore\t16\n" } } */ /* { dg-final { scan-assembler "\tlw\t\\\$1,16\\(\\\$fp\\)\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/code-readable-2.c b/gcc/testsuite/gcc.target/mips/code-readable-2.c index 8b87ff6582..e0176c3dbd 100644 --- a/gcc/testsuite/gcc.target/mips/code-readable-2.c +++ b/gcc/testsuite/gcc.target/mips/code-readable-2.c @@ -26,8 +26,7 @@ bar (void) /* { dg-final { scan-assembler-not "\tla\t" } } */ /* { dg-final { scan-assembler-not "\t\\.half\t" } } */ -/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */ -/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */ +/* { dg-final { scan-assembler "\t\\.word\t\[^\n\]*L" } } */ /* { dg-final { scan-assembler "\t\\.word\tk\n" } } */ /* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */ diff --git a/gcc/testsuite/gcc.target/mips/div-1.c b/gcc/testsuite/gcc.target/mips/div-1.c new file mode 100644 index 0000000000..e1976c25e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-1.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-10.c b/gcc/testsuite/gcc.target/mips/div-10.c new file mode 100644 index 0000000000..23075da2c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-10.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-11.c b/gcc/testsuite/gcc.target/mips/div-11.c new file mode 100644 index 0000000000..68f1658484 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-11.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-12.c b/gcc/testsuite/gcc.target/mips/div-12.c new file mode 100644 index 0000000000..c2384b20a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-12.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-2.c b/gcc/testsuite/gcc.target/mips/div-2.c new file mode 100644 index 0000000000..af6e2fa8e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-2.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-3.c b/gcc/testsuite/gcc.target/mips/div-3.c new file mode 100644 index 0000000000..684b6a8e44 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-3.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-4.c b/gcc/testsuite/gcc.target/mips/div-4.c new file mode 100644 index 0000000000..251b88f816 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-4.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-5.c b/gcc/testsuite/gcc.target/mips/div-5.c new file mode 100644 index 0000000000..a08f3e6f4b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-5.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-6.c b/gcc/testsuite/gcc.target/mips/div-6.c new file mode 100644 index 0000000000..23075da2c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-6.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-7.c b/gcc/testsuite/gcc.target/mips/div-7.c new file mode 100644 index 0000000000..68f1658484 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-7.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-8.c b/gcc/testsuite/gcc.target/mips/div-8.c new file mode 100644 index 0000000000..c2384b20a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-8.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc/testsuite/gcc.target/mips/div-9.c b/gcc/testsuite/gcc.target/mips/div-9.c new file mode 100644 index 0000000000..a08f3e6f4b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/div-9.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc/testsuite/gcc.target/mips/dmult-1.c index 517e43ed54..f8c0b8b44f 100644 --- a/gcc/testsuite/gcc.target/mips/dmult-1.c +++ b/gcc/testsuite/gcc.target/mips/dmult-1.c @@ -1,4 +1,4 @@ -/* { dg-options "forbid_cpu=octeon -mgp64" } */ +/* { dg-options "forbid_cpu=octeon.* -mgp64" } */ /* { dg-final { scan-assembler "\tdmult\t" } } */ /* { dg-final { scan-assembler "\tmflo\t" } } */ /* { dg-final { scan-assembler-not "\tdmul\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/dspr2-MULT.c b/gcc/testsuite/gcc.target/mips/dspr2-MULT.c index 8b815e5acb..c685974895 100644 --- a/gcc/testsuite/gcc.target/mips/dspr2-MULT.c +++ b/gcc/testsuite/gcc.target/mips/dspr2-MULT.c @@ -1,11 +1,12 @@ /* Test MIPS32 DSP REV 2 MULT instruction. Tune for a CPU that has pipelined mult. */ /* { dg-do compile } */ -/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo -mtune=74kc" } */ +/* { dg-options "-mgp32 -mdspr2 -O2 -mtune=74kc" } */ +/* See PR target/51729 for the reason behind the XFAILs. */ /* { dg-final { scan-assembler "\tmult\t" } } */ -/* { dg-final { scan-assembler "ac1" } } */ -/* { dg-final { scan-assembler "ac2" } } */ +/* { dg-final { scan-assembler "ac1" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "ac2" { xfail *-*-* } } } */ typedef long long a64; diff --git a/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c b/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c index c457d245a3..7f04315efe 100644 --- a/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c +++ b/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c @@ -1,11 +1,12 @@ /* Test MIPS32 DSP REV 2 MULTU instruction. Tune for a CPU that has pipelined multu. */ /* { dg-do compile } */ -/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo -mtune=74kc" } */ +/* { dg-options "-mgp32 -mdspr2 -O2 -mtune=74kc" } */ +/* See PR target/51729 for the reason behind the XFAILs. */ /* { dg-final { scan-assembler "\tmultu\t" } } */ -/* { dg-final { scan-assembler "ac1" } } */ -/* { dg-final { scan-assembler "ac2" } } */ +/* { dg-final { scan-assembler "ac1" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "ac2" { xfail *-*-* } } } */ typedef unsigned long long a64; diff --git a/gcc/testsuite/gcc.target/mips/ext-2.c b/gcc/testsuite/gcc.target/mips/ext-2.c index 8d502b21b1..d6ccce29e0 100644 --- a/gcc/testsuite/gcc.target/mips/ext-2.c +++ b/gcc/testsuite/gcc.target/mips/ext-2.c @@ -7,7 +7,7 @@ /* { dg-final { scan-assembler-not "and" } } */ /* { dg-final { scan-assembler-not "srl" } } */ -void +NOMIPS16 void f (unsigned char x, unsigned char *r) { *r = 0x50 | (x >> 4); diff --git a/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc/testsuite/gcc.target/mips/extend-1.c index 4295106866..94d199f887 100644 --- a/gcc/testsuite/gcc.target/mips/extend-1.c +++ b/gcc/testsuite/gcc.target/mips/extend-1.c @@ -1,12 +1,20 @@ -/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */ +/* { dg-options "-O -mgp64 forbid_cpu=octeon.*" } */ /* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */ /* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */ /* { dg-final { scan-assembler-not "\tsll\t" } } */ -#define TEST_CHAR(T, N) \ - NOMIPS16 T f##N (long long d, T *a, T *r) { T b = (char) d; *r = b + *a; } -#define TEST_SHORT(T, N) \ - NOMIPS16 T g##N (long long d, T *a, T *r) { T b = (short) d; *r = b + *a; } +#define TEST_CHAR(T, N) \ + NOMIPS16 T \ + f##N (long long d, T *a, T *r) \ + { \ + T b = (signed char) d; *r = b + *a; \ + } +#define TEST_SHORT(T, N) \ + NOMIPS16 T \ + g##N (long long d, T *a, T *r) \ + { \ + T b = (short) d; *r = b + *a; \ + } #define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N) TEST (int, 1); diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-1.c b/gcc/testsuite/gcc.target/mips/fix-r4000-1.c index 513fc6130a..551d3549d8 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-1.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-1.c @@ -1,6 +1,6 @@ /* { dg-options "-march=r4000 -mfix-r4000 -O2 -dp" } */ typedef int int32_t; typedef int uint32_t; -int32_t foo (int32_t x, int32_t y) { return x * y; } -uint32_t bar (uint32_t x, uint32_t y) { return x * y; } +NOMIPS16 int32_t foo (int32_t x, int32_t y) { return x * y; } +NOMIPS16 uint32_t bar (uint32_t x, uint32_t y) { return x * y; } /* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-10.c b/gcc/testsuite/gcc.target/mips/fix-r4000-10.c index ebf3ca3056..8c938b7d21 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-10.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-10.c @@ -4,5 +4,5 @@ /* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ typedef unsigned long long uint64_t; typedef unsigned int uint128_t __attribute__((mode(TI))); -uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } +NOMIPS16 uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } /* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-11.c b/gcc/testsuite/gcc.target/mips/fix-r4000-11.c index 93f78134e4..7cfad3d2f7 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-11.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-11.c @@ -1,4 +1,4 @@ /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ typedef long long int64_t; -int64_t foo (int64_t x) { return x / 11993; } +NOMIPS16 int64_t foo (int64_t x) { return x / 11993; } /* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-12.c b/gcc/testsuite/gcc.target/mips/fix-r4000-12.c index 554975ccca..d449283ddf 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-12.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-12.c @@ -1,4 +1,4 @@ /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ typedef unsigned long long uint64_t; -uint64_t foo (uint64_t x) { return x / 11993; } +NOMIPS16 uint64_t foo (uint64_t x) { return x / 11993; } /* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-2.c b/gcc/testsuite/gcc.target/mips/fix-r4000-2.c index 4f27041bed..6cb7d3594e 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-2.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-2.c @@ -1,7 +1,7 @@ /* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ typedef int int32_t; typedef long long int64_t; -int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } +NOMIPS16 int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } /* ??? A highpart pattern would be a better choice, but we currently don't use them. */ /* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-3.c b/gcc/testsuite/gcc.target/mips/fix-r4000-3.c index 207fc66b06..bd12509d1b 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-3.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-3.c @@ -1,7 +1,7 @@ /* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ typedef unsigned int uint32_t; typedef unsigned long long uint64_t; -uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } +NOMIPS16 uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } /* ??? A highpart pattern would be a better choice, but we currently don't use them. */ /* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-4.c b/gcc/testsuite/gcc.target/mips/fix-r4000-4.c index be32b57ae4..3854db8967 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-4.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-4.c @@ -4,5 +4,5 @@ /* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ typedef int int32_t; typedef long long int64_t; -int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } +NOMIPS16 int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } /* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-5.c b/gcc/testsuite/gcc.target/mips/fix-r4000-5.c index c14e949f22..c46300f62d 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-5.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-5.c @@ -4,5 +4,5 @@ /* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ typedef unsigned int uint32_t; typedef unsigned long long uint64_t; -uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } +NOMIPS16 uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } /* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-6.c b/gcc/testsuite/gcc.target/mips/fix-r4000-6.c index 32861f9750..1e33cc4f76 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-6.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-6.c @@ -1,6 +1,6 @@ /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ typedef long long int64_t; typedef unsigned long long uint64_t; -int64_t foo (int64_t x, int64_t y) { return x * y; } -uint64_t bar (uint64_t x, uint64_t y) { return x * y; } +NOMIPS16 int64_t foo (int64_t x, int64_t y) { return x * y; } +NOMIPS16 uint64_t bar (uint64_t x, uint64_t y) { return x * y; } /* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-7.c b/gcc/testsuite/gcc.target/mips/fix-r4000-7.c index 2555d5306d..118ba99dfe 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-7.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-7.c @@ -1,7 +1,7 @@ /* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ typedef long long int64_t; typedef int int128_t __attribute__((mode(TI))); -int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } +NOMIPS16 int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } /* ??? A highpart pattern would be a better choice, but we currently don't use them. */ /* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-8.c b/gcc/testsuite/gcc.target/mips/fix-r4000-8.c index 964dc22229..f2c71c1ef1 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-8.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-8.c @@ -1,7 +1,7 @@ /* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ typedef unsigned long long uint64_t; typedef unsigned int uint128_t __attribute__((mode(TI))); -uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } +NOMIPS16 uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } /* ??? A highpart pattern would be a better choice, but we currently don't use them. */ /* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-9.c b/gcc/testsuite/gcc.target/mips/fix-r4000-9.c index 68724eb376..da9c11364d 100644 --- a/gcc/testsuite/gcc.target/mips/fix-r4000-9.c +++ b/gcc/testsuite/gcc.target/mips/fix-r4000-9.c @@ -4,5 +4,5 @@ /* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ typedef long long int64_t; typedef int int128_t __attribute__((mode(TI))); -int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } +NOMIPS16 int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } /* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c b/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c index 076b399a38..38339cad89 100644 --- a/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c +++ b/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c @@ -89,7 +89,7 @@ extern _Complex double (*pcd10) (double, double); #define CHECK_RESULT(x, y) if ((x) != (y)) abort () #define CHECK_VOID_RESULT(x, y) CHECK_RESULT (((x), the_result), y) -/* Call functions through pointers and and check against expected results. */ +/* Call functions through pointers and check against expected results. */ void test (void) { diff --git a/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c new file mode 100644 index 0000000000..0ab2dc3348 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c @@ -0,0 +1,15 @@ +/* Make sure that we emit .cfa_restore notes for LO and HI. */ +/* { dg-options "-mips32r2 -msoft-float -O -g" } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */ +/* { dg-skip-if "PR target/50580" { mips-sgi-irix6* } } */ + +extern void f (void); + +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) +v1 (void) +{ + f (); +} diff --git a/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c new file mode 100644 index 0000000000..3fd49a322f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c @@ -0,0 +1,34 @@ +/* Make sure that we emit .cfa_restore notes for LO, HI and GPRs. */ +/* { dg-options "-mips32r2 -msoft-float -O -g" } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 1\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 2\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 3\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 4\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 5\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 6\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 7\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 8\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 9\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 10\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 11\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 12\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 13\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 14\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 15\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 24\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 25\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 31\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_def_cfa_offset 0\n" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */ +/* { dg-skip-if "PR target/50580" { mips-sgi-irix6* } } */ + +extern void f (void); + +NOMIPS16 void __attribute__ ((interrupt)) +v1 (void) +{ + f (); +} diff --git a/gcc/testsuite/gcc.target/mips/lazy-binding-1.c b/gcc/testsuite/gcc.target/mips/lazy-binding-1.c index e85727c42d..e281a270a6 100644 --- a/gcc/testsuite/gcc.target/mips/lazy-binding-1.c +++ b/gcc/testsuite/gcc.target/mips/lazy-binding-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabicalls -mshared -mexplicit-relocs -O2 -fno-delayed-branch" } */ +/* { dg-options "-mshared -mexplicit-relocs -O2 -fno-delayed-branch" } */ void bar (void); diff --git a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c index be52cf7ded..1c892d8062 100644 --- a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c +++ b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c @@ -5,6 +5,8 @@ seem any good reason for it to, given that the Loongson processors do not support MIPS16. */ /* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1" } */ +/* See PR 52155. */ +/* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1 -mlong64" { mips*-*-elf* && ilp32 } } */ #include "loongson.h" #include <assert.h> diff --git a/gcc/testsuite/gcc.target/mips/madd-7.c b/gcc/testsuite/gcc.target/mips/madd-7.c index 93ed0fc6f0..b43d720742 100644 --- a/gcc/testsuite/gcc.target/mips/madd-7.c +++ b/gcc/testsuite/gcc.target/mips/madd-7.c @@ -1,5 +1,4 @@ -/* -mlong32 added because of PR target/38598. */ -/* { dg-options "-O2 -march=5kc -mlong32" } */ +/* { dg-options "-O2 -march=5kc" } */ /* { dg-final { scan-assembler-not "\tmul\t" } } */ /* { dg-final { scan-assembler "\tmadd\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips-prepend-1.c b/gcc/testsuite/gcc.target/mips/mips-prepend-1.c new file mode 100644 index 0000000000..126dbebcba --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips-prepend-1.c @@ -0,0 +1,8 @@ +/* { dg-options "-mdspr2" } */ +/* { dg-final { scan-assembler "prepend\[^\n\]*,10" } } */ + +NOMIPS16 int +foo (int x, int y) +{ + return __builtin_mips_prepend (x, y, 42); +} diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 0535c48f54..1be2f1e372 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -226,6 +226,7 @@ set mips_option_groups { abi "-mabi=.*" addressing "addressing=.*" arch "-mips([1-5]|32.*|64.*)|-march=.*|isa(|_rev)(=|<=|>=).*" + debug "-g.*" dump_pattern "-dp" endianness "-E(L|B)|-me(l|b)" float "-m(hard|soft)-float" @@ -240,6 +241,7 @@ set mips_option_groups { profiling "-pg" small-data "-G[0-9]+" warnings "-w" + dump "-fdump-.*" } # Add -mfoo/-mno-foo options to mips_option_groups. @@ -587,6 +589,30 @@ proc mips_64bit_abi_p { option } { return 0 } +# Return true if the given abi-group option implicitly requires -mlong32. +# o64 requires this for -mabicalls, but not otherwise; pick the conservative +# case for simplicity. +proc mips_long32_abi_p { option } { + switch -glob -- $option { + -mabi=o64 - + -mabi=n32 - + -mabi=32 { + return 1 + } + } + return 0 +} + +# Return true if the given abi-group option implicitly requires -mlong64. +proc mips_long64_abi_p { option } { + switch -glob -- $option { + -mabi=64 { + return 1 + } + } + return 0 +} + # Check whether the current target supports all the options that the # current test requires. Return "" if so, otherwise return one of # the incompatible options. UPSTATUS describes the option status. @@ -809,6 +835,10 @@ proc mips-dg-finish {} { # | | # -mexplicit-relocs -mno-explicit-relocs # | | +# -mdspr2 -mno-dspr2 +# | | +# -mdsp -mno-dsp +# | | # +-- gp, abi & arch ---------+ # # For these purposes, the "gp", "abi" & "arch" option groups are treated @@ -825,6 +855,15 @@ proc mips-dg-options { args } { # Information about this run. global mips_base_options + if { [llength $args] >= 3 } { + switch { [dg-process-target [lindex $args 2]] } { + "S" { } + "N" { return } + "F" { error "[lindex $args 0]: `xfail' not allowed here" } + "P" { error "[lindex $args 0]: `xfail' not allowed here" } + } + } + # Start out with the default option state. array set options [array get mips_base_options] @@ -850,6 +889,7 @@ proc mips-dg-options { args } { mips_option_dependency options "-mrelax-pic-calls" "-mexplicit-relocs" mips_option_dependency options "-fpic" "-mshared" mips_option_dependency options "-mshared" "-mno-plt" + mips_option_dependency options "-mshared" "-mabicalls" mips_option_dependency options "-mno-plt" "addressing=unknown" mips_option_dependency options "-mabicalls" "-G0" mips_option_dependency options "-mno-gpopt" "-mexplicit-relocs" @@ -1027,24 +1067,41 @@ proc mips-dg-options { args } { # -mips16 -mhard-float requires o32 or o64. # -mips16 PIC requires o32 or o64. set force_abi 1 + } elseif { [mips_have_test_option_p options "-mlong32"] + && [mips_long64_abi_p $abi] } { + set force_abi 1 + } elseif { [mips_have_test_option_p options "-mlong64"] + && [mips_long32_abi_p $abi] } { + set force_abi 1 } else { set force_abi 0 } if { $gp_size == 32 } { if { $force_abi || [mips_64bit_abi_p $abi] } { - mips_make_test_option options "-mabi=32" + if { [mips_have_test_option_p options "-mlong64"] } { + mips_make_test_option options "-mabi=eabi" + mips_make_test_option options "-mgp32" + } else { + mips_make_test_option options "-mabi=32" + } } } else { if { $force_abi || [mips_32bit_abi_p $abi] } { - # All configurations should have an assembler that - # supports o64, since it requires the same BFD target - # vector as o32. In contrast, many assembler - # configurations do not have n32 or n64 support. - mips_make_test_option options "-mabi=o64" + if { [mips_have_test_option_p options "-mlong64"] } { + mips_make_test_option options "-mabi=eabi" + mips_make_test_option options "-mgp64" + } else { + # All configurations should have an assembler that + # supports o64, since it requires the same BFD target + # vector as o32. In contrast, many assembler + # configurations do not have n32 or n64 support. + mips_make_test_option options "-mabi=o64" + } } } - unset abi - unset eabi_p + set abi_test_option_p [mips_test_option_p options abi] + set abi [mips_option options abi] + set eabi_p [mips_same_option_p $abi "-mabi=eabi"] } # Handle dependencies between the abi options and the post-abi options. @@ -1068,8 +1125,11 @@ proc mips-dg-options { args } { mips_make_test_option options "-mno-mips16" } } - unset abi - unset eabi_p + if { [mips_long32_abi_p $abi] } { + mips_make_test_option options "-mlong32" + } elseif { [mips_long64_abi_p $abi] } { + mips_make_test_option options "-mlong64" + } } # Handle dependencies between the arch option and the post-arch options. @@ -1090,7 +1150,6 @@ proc mips-dg-options { args } { mips_make_test_option options "-mfp32" } mips_make_test_option options "-mno-dsp" - mips_make_test_option options "-mno-dspr2" } unset arch unset isa @@ -1098,6 +1157,7 @@ proc mips-dg-options { args } { } # Handle dependencies between options on the right of the diagram. + mips_option_dependency options "-mno-dsp" "-mno-dspr2" mips_option_dependency options "-mno-explicit-relocs" "-mgpopt" switch -- [mips_test_option options small-data] { "" - diff --git a/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c b/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c new file mode 100644 index 0000000000..d136676190 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c @@ -0,0 +1,10 @@ +/* Test MIPS64 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mgp64 -mdsp -O" } */ + +/* { dg-final { scan-assembler "\tldx\t" } } */ + +NOMIPS16 signed long long test (signed long long *a, int index) +{ + return a[index]; +} diff --git a/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c b/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c new file mode 100644 index 0000000000..b7f3bc8f81 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c @@ -0,0 +1,10 @@ +/* Test MIPS64 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mgp64 -mdsp" } */ + +/* { dg-final { scan-assembler "\tldx\t" } } */ + +NOMIPS16 signed long long test (signed long long *a, int index) +{ + return __builtin_mips_ldx (a, index); +} diff --git a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c index cf5b044d63..8514ed8cb4 100644 --- a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c +++ b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -pg -mmcount-ra-address -mabi=64" } */ /* { dg-final { scan-assembler "\tmove\t\\\$12,\\\$0" } } */ -int bazl(int i) +NOMIPS16 int bazl(int i) { return i + 2; } diff --git a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c index bef9dd93d8..bb59a1828c 100644 --- a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c +++ b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O2 -pg -mmcount-ra-address -mabi=64" } */ /* { dg-final { scan-assembler "\tdla\t\\\$12,8\\(\\\$sp\\)" } } */ int foo (int); -int bar (int i) +NOMIPS16 int bar (int i) { return foo (i) + 2; } diff --git a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c index 59007e6ef3..8c94c8345e 100644 --- a/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c +++ b/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c @@ -2,7 +2,7 @@ /* { dg-options "-O2 -pg -mmcount-ra-address -mabi=64" } */ /* { dg-final { scan-assembler "\tdla\t\\\$12,200008\\(\\\$sp\\)" } } */ int foo (int *); -int bar(int i) +NOMIPS16 int bar(int i) { int big[50000]; return foo (big) + 2; diff --git a/gcc/testsuite/gcc.target/mips/msub-7.c b/gcc/testsuite/gcc.target/mips/msub-7.c index ca90cee9ea..7ae96acb42 100644 --- a/gcc/testsuite/gcc.target/mips/msub-7.c +++ b/gcc/testsuite/gcc.target/mips/msub-7.c @@ -1,5 +1,4 @@ -/* -mlong32 added because of PR target/38598. */ -/* { dg-options "-O2 -march=5kc -mlong32" } */ +/* { dg-options "-O2 -march=5kc" } */ /* { dg-final { scan-assembler-not "\tmul\t" } } */ /* { dg-final { scan-assembler "\tmsub\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc/testsuite/gcc.target/mips/mult-1.c index 43dd08c0b5..8630ec95d5 100644 --- a/gcc/testsuite/gcc.target/mips/mult-1.c +++ b/gcc/testsuite/gcc.target/mips/mult-1.c @@ -1,6 +1,6 @@ /* For SI->DI widening multiplication we should use DINS to combine the two halves. For Octeon use DMUL with explicit widening. */ -/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */ +/* { dg-options "-O2 -mgp64 isa_rev>=2 forbid_cpu=octeon.*" } */ /* { dg-final { scan-assembler "\tdins\t" } } */ /* { dg-final { scan-assembler-not "\tdsll\t" } } */ /* { dg-final { scan-assembler-not "\tdsrl\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mult-10.c b/gcc/testsuite/gcc.target/mips/mult-10.c new file mode 100644 index 0000000000..0b990c3641 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-10.c @@ -0,0 +1,13 @@ +/* { dg-options "-O2 -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-11.c b/gcc/testsuite/gcc.target/mips/mult-11.c new file mode 100644 index 0000000000..d2ba695f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-11.c @@ -0,0 +1,13 @@ +/* { dg-options "-O2 -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-12.c b/gcc/testsuite/gcc.target/mips/mult-12.c new file mode 100644 index 0000000000..bd772d2cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-12.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-13.c b/gcc/testsuite/gcc.target/mips/mult-13.c new file mode 100644 index 0000000000..e0859f629f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-13.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-14.c b/gcc/testsuite/gcc.target/mips/mult-14.c new file mode 100644 index 0000000000..c4b54b7ec4 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-14.c @@ -0,0 +1,15 @@ +/* { dg-options "-O -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-15.c b/gcc/testsuite/gcc.target/mips/mult-15.c new file mode 100644 index 0000000000..a96049e04e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-15.c @@ -0,0 +1,15 @@ +/* { dg-options "-O -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-16.c b/gcc/testsuite/gcc.target/mips/mult-16.c new file mode 100644 index 0000000000..cb1707d912 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-16.c @@ -0,0 +1,13 @@ +/* { dg-options "-O2 -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-17.c b/gcc/testsuite/gcc.target/mips/mult-17.c new file mode 100644 index 0000000000..3539f63d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-17.c @@ -0,0 +1,13 @@ +/* { dg-options "-O -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-18.c b/gcc/testsuite/gcc.target/mips/mult-18.c new file mode 100644 index 0000000000..cfdac8b0de --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-18.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-19.c b/gcc/testsuite/gcc.target/mips/mult-19.c new file mode 100644 index 0000000000..47cdd5c23c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-19.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp32 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-2.c b/gcc/testsuite/gcc.target/mips/mult-2.c new file mode 100644 index 0000000000..8494e14c35 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-2.c @@ -0,0 +1,13 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmult\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ + +typedef int TI __attribute__((mode(TI))); +typedef int DI __attribute__((mode(DI))); + +MIPS16 TI +f (DI x, DI y) +{ + return (TI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-3.c b/gcc/testsuite/gcc.target/mips/mult-3.c new file mode 100644 index 0000000000..fa7cfa34e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-3.c @@ -0,0 +1,13 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmultu\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ + +typedef unsigned int TI __attribute__((mode(TI))); +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 TI +f (DI x, DI y) +{ + return (TI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-4.c b/gcc/testsuite/gcc.target/mips/mult-4.c new file mode 100644 index 0000000000..d579f0023d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-4.c @@ -0,0 +1,13 @@ +/* { dg-options "-O2 -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmult\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +typedef int TI __attribute__((mode(TI))); +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return ((TI) x * y) >> 64; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-5.c b/gcc/testsuite/gcc.target/mips/mult-5.c new file mode 100644 index 0000000000..6df86a1163 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-5.c @@ -0,0 +1,13 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmultu\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +typedef unsigned int TI __attribute__((mode(TI))); +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return ((TI) x * y) >> 64; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-6.c b/gcc/testsuite/gcc.target/mips/mult-6.c new file mode 100644 index 0000000000..a6b910ec40 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-6.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-7.c b/gcc/testsuite/gcc.target/mips/mult-7.c new file mode 100644 index 0000000000..7c2989baa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-7.c @@ -0,0 +1,12 @@ +/* { dg-options "-O -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-8.c b/gcc/testsuite/gcc.target/mips/mult-8.c new file mode 100644 index 0000000000..3e3acde81e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-8.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2 -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */ +/* { dg-final { scan-assembler "\tdsrl\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/mult-9.c b/gcc/testsuite/gcc.target/mips/mult-9.c new file mode 100644 index 0000000000..aa2ededa67 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mult-9.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2 -mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */ +/* { dg-final { scan-assembler "\tdsrl\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc/testsuite/gcc.target/mips/no-dsp-1.c b/gcc/testsuite/gcc.target/mips/no-dsp-1.c new file mode 100644 index 0000000000..093037579b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/no-dsp-1.c @@ -0,0 +1,7 @@ +/* { dg-options "-mno-dsp" } */ + +void +foo (void) +{ + register int x asm ("$ac1hi"); /* { dg-error "cannot be accessed" } */ +} diff --git a/gcc/testsuite/gcc.target/mips/octeon-exts-6.c b/gcc/testsuite/gcc.target/mips/octeon-exts-6.c index d04e27331d..d37ed95559 100644 --- a/gcc/testsuite/gcc.target/mips/octeon-exts-6.c +++ b/gcc/testsuite/gcc.target/mips/octeon-exts-6.c @@ -3,10 +3,18 @@ /* { dg-final { scan-assembler-not "\t(dsll|dsra)\t" } } */ /* { dg-final { scan-assembler-not "\tsll\t" } } */ -#define TEST_CHAR(T, N) \ - NOMIPS16 T f##N (long long d, T *a, T *r) { T b = (char) d; *r = b + *a; } -#define TEST_SHORT(T, N) \ - NOMIPS16 T g##N (long long d, T *a, T *r) { T b = (short) d; *r = b + *a; } +#define TEST_CHAR(T, N) \ + NOMIPS16 T \ + f##N (long long d, T *a, T *r) \ + { \ + T b = (signed char) d; *r = b + *a; \ + } +#define TEST_SHORT(T, N) \ + NOMIPS16 T \ + g##N (long long d, T *a, T *r) \ + { \ + T b = (short) d; *r = b + *a; \ + } #define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N) TEST (int, 1); diff --git a/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c b/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c new file mode 100644 index 0000000000..bbcf7c8fcb --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c @@ -0,0 +1,11 @@ +/* Check that we use the octeon pipeline description. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=octeon -fdump-rtl-sched2" } */ + +NOMIPS16 int f (int a, int b) +{ + return a / b; +} + +/* { dg-final { scan-rtl-dump "octeon_mult\\*71" "sched2" } } */ +/* { dg-final { cleanup-tree-dump "sched2" } } */ diff --git a/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c b/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c new file mode 100644 index 0000000000..34d8af8521 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -O -mgp64" } */ + +#define TEST(N, R, T) \ + T fll##N (T j, signed R *b, long long i) { return j + b[i]; } \ + T gll##N (T j, unsigned R *b, long long i) { return j + b[i]; } \ + T fi##N (T j, signed R *b, int i) { return j + b[i]; } \ + T gi##N (T j, unsigned R *b, int i) { return j + b[i]; } \ + +TEST (1, char, int) +TEST (2, char, long long) +/* { dg-final { scan-assembler-times "\tlbx\t" 4 } } */ +/* { dg-final { scan-assembler-times "\tlbux\t" 4 } } */ +TEST (3, short, int) +TEST (4, short, long long) +/* { dg-final { scan-assembler-times "\tlhx\t" 4 } } */ +/* { dg-final { scan-assembler-times "\tlhux\t" 4 } } */ +TEST (5, int, long long) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tlwux\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c b/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c new file mode 100644 index 0000000000..521a71f961 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -O -mgp64" } */ + +#define TEST(N, T) \ + T f##N (T *p, int i) { return p[i]; } \ + unsigned T g##N (unsigned T *p, int i) { return p[i]; } + +TEST (1, char) +/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */ +TEST (2, short) +/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */ +TEST (3, int) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ +TEST (4, long long) +/* { dg-final { scan-assembler-times "\tldx\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c b/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c new file mode 100644 index 0000000000..51d2e1031c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -O -mgp32" } */ + +#define TEST(N, T) \ + T f##N (T *p, int i) { return p[i]; } \ + unsigned T g##N (unsigned T *p, int i) { return p[i]; } + +TEST (1, char) +/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */ +TEST (2, short) +/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */ +TEST (3, int) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c b/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c new file mode 100644 index 0000000000..da4f6321c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c @@ -0,0 +1,11 @@ +/* Check that we use the octeon2 pipeline description. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-sched2 -march=octeon2" } */ + +NOMIPS16 int f (int a, int b) +{ + return a / b; +} + +/* { dg-final { scan-rtl-dump "octeon_mult\\*17" "sched2" } } */ +/* { dg-final { cleanup-tree-dump "sched2" } } */ diff --git a/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc/testsuite/gcc.target/mips/pr37362.c index 14e3a75f1b..a37836640d 100644 --- a/gcc/testsuite/gcc.target/mips/pr37362.c +++ b/gcc/testsuite/gcc.target/mips/pr37362.c @@ -1,4 +1,5 @@ -/* { dg-do compile } */ +/* mips*-sde-elf doesn't have 128-bit long doubles. */ +/* { dg-do compile { target { ! mips*-sde-elf } } } */ /* { dg-options "-march=mips64r2 -mabi=n32" } */ typedef float TFtype __attribute__((mode(TF))); diff --git a/gcc/testsuite/gcc.target/mips/pr45074.c b/gcc/testsuite/gcc.target/mips/pr45074.c new file mode 100644 index 0000000000..ba578c838c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr45074.c @@ -0,0 +1,8 @@ +/* { dg-options "-mhard-float -mgp32 -O" } */ +register double g __asm__("$f20"); + +NOMIPS16 void +test (double a) +{ + g = -a; +} diff --git a/gcc/testsuite/gcc.target/mips/soft-float-1.c b/gcc/testsuite/gcc.target/mips/soft-float-1.c new file mode 100644 index 0000000000..4c45646279 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/soft-float-1.c @@ -0,0 +1,7 @@ +/* { dg-options "-msoft-float" } */ + +void +foo (void) +{ + register float x asm ("$f0"); /* { dg-error "cannot be accessed" } */ +} diff --git a/gcc/testsuite/gcc.target/mips/stack-1.c b/gcc/testsuite/gcc.target/mips/stack-1.c new file mode 100644 index 0000000000..3d495453dd --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/stack-1.c @@ -0,0 +1,11 @@ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "addiu\t(\\\$sp,)?\\\$sp,\[1-9\]" } } */ +/* { dg-final { scan-assembler "\tlw\t" } } */ +/* { dg-final { scan-assembler-not "addiu\t(\\\$sp,)?\\\$sp,\[1-9\].*\tlw\t" } } */ + +int foo (int y) +{ + volatile int a = y; + volatile int *volatile b = &a; + return *b; +} diff --git a/gcc/testsuite/gcc.target/mips/va-arg-1.c b/gcc/testsuite/gcc.target/mips/va-arg-1.c new file mode 100644 index 0000000000..87c95f525f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/va-arg-1.c @@ -0,0 +1,48 @@ +/* See PR 52154 for the xfail. */ +/* { dg-do run { xfail { mips_eabi && { hard_float && ilp32 } } } } */ + +#include <stdarg.h> + +extern void abort (void); + +struct __attribute__((aligned(16))) empty {}; + +static void __attribute__((noinline)) +check_args (int count, ...) +{ + va_list va; + int i; + + va_start (va, count); + for (i = 0; i < count; i++) + if (va_arg (va, int) != 1000 + i) + abort (); + + va_arg (va, struct empty); + if (va_arg (va, int) != 2000 + count) + abort (); + + va_end (va); +} + +int +main (void) +{ + struct empty e; + + check_args (1, 1000, e, 2001); + check_args (2, 1000, 1001, e, 2002); + check_args (3, 1000, 1001, 1002, e, 2003); + check_args (4, 1000, 1001, 1002, 1003, e, 2004); + check_args (5, 1000, 1001, 1002, 1003, 1004, e, 2005); + check_args (6, 1000, 1001, 1002, 1003, 1004, 1005, e, 2006); + check_args (7, 1000, 1001, 1002, 1003, 1004, 1005, 1006, e, 2007); + check_args (8, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, e, 2008); + check_args (9, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, e, 2009); + check_args (10, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, e, 2010); + check_args (11, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, e, 2011); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-34.c b/gcc/testsuite/gcc.target/powerpc/altivec-34.c index 8e6372bfb4..98fa5d2d41 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-34.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-34.c @@ -1,6 +1,7 @@ /* PR target/49621 */ /* { dg-do compile } */ -/* { dg-options "-O2 -maltivec" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mno-vsx" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c new file mode 100644 index 0000000000..ee5c5eee90 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c @@ -0,0 +1,76 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ + +typedef unsigned char V __attribute__((vector_size(16))); + +V b1(V x) +{ + return __builtin_shuffle(x, (V){ 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, }); +} + +V b2(V x) +{ + return __builtin_shuffle(x, (V){ 2,3,2,3, 2,3,2,3, 2,3,2,3, 2,3,2,3, }); +} + +V b4(V x) +{ + return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, }); +} + +V p2(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 }); + +} + +V p4(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 }); +} + +V h1(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 }); +} + +V h2(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 }); +} + +V h4(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 }); +} + +V l1(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 }); +} + +V l2(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 }); +} + +V l4(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 }); +} + +/* { dg-final { scan-assembler-not "vperm" } } */ +/* { dg-final { scan-assembler "vspltb" } } */ +/* { dg-final { scan-assembler "vsplth" } } */ +/* { dg-final { scan-assembler "vspltw" } } */ +/* { dg-final { scan-assembler "vpkuhum" } } */ +/* { dg-final { scan-assembler "vpkuwum" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c new file mode 100644 index 0000000000..1b90bb9567 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ + +typedef unsigned short V __attribute__((vector_size(16))); + +V f2(V x) +{ + return __builtin_shuffle(x, (V){ 1,1,1,1, 1,1,1,1, }); +} + +V f4(V x) +{ + return __builtin_shuffle(x, (V){ 2,3,2,3, 2,3,2,3, }); +} + +/* { dg-final { scan-assembler-not "vperm" } } */ +/* { dg-final { scan-assembler "vsplth" } } */ +/* { dg-final { scan-assembler "vspltw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c new file mode 100644 index 0000000000..9598edfb01 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ + +typedef unsigned int V __attribute__((vector_size(16))); + +V f4(V x) +{ + return __builtin_shuffle(x, (V){ 1,1,1,1, }); +} + +/* { dg-final { scan-assembler-not "vperm" } } */ +/* { dg-final { scan-assembler "vspltw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c new file mode 100644 index 0000000000..f2bc7ffb3c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c new file mode 100644 index 0000000000..220be57165 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c new file mode 100644 index 0000000000..4b437291ea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c new file mode 100644 index 0000000000..d73328ac43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c new file mode 100644 index 0000000000..cc6adba805 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c new file mode 100644 index 0000000000..9c748d973d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c new file mode 100644 index 0000000000..abdb3b0caf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c new file mode 100644 index 0000000000..ec7fc3031b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/ehreturn.c b/gcc/testsuite/gcc.target/powerpc/ehreturn.c index abada8300e..558db42381 100644 --- a/gcc/testsuite/gcc.target/powerpc/ehreturn.c +++ b/gcc/testsuite/gcc.target/powerpc/ehreturn.c @@ -12,4 +12,4 @@ void foo () __builtin_eh_return (l, p); } -/* { dg-final { scan-assembler "st\[wd\] 30," } } */ +/* { dg-final { scan-assembler "(st\[wd\]|evstdd) 30," } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-1.c b/gcc/testsuite/gcc.target/powerpc/lhs-1.c new file mode 100644 index 0000000000..000ebcadfb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/lhs-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5" } */ +/* { dg-final { scan-assembler-times "nop" 3 } } */ + +/* Test generation of nops in load hit store situation. */ + +typedef union { + double val; + struct { + unsigned int w1; + unsigned int w2; + }; +} words; + +unsigned int f (double d, words *u) +{ + u->val = d; + return u->w2; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-2.c b/gcc/testsuite/gcc.target/powerpc/lhs-2.c new file mode 100644 index 0000000000..748011f8d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/lhs-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power6 -msched-groups" } */ +/* { dg-final { scan-assembler "ori 1,1,0" } } */ + +/* Test generation of group ending nop in load hit store situation. */ +typedef union { + double val; + struct { + unsigned int w1; + unsigned int w2; + }; +} words; + +unsigned int f (double d) +{ + words u; + u.val = d; + return u.w2; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-3.c b/gcc/testsuite/gcc.target/powerpc/lhs-3.c new file mode 100644 index 0000000000..31677ed667 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/lhs-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "ori 2,2,0" } } */ + +/* Test generation of group ending nop in load hit store situation. */ +typedef union { + double val; + struct { + unsigned int w1; + unsigned int w2; + }; +} words; + +unsigned int f (double d) +{ + words u; + u.val = d; + return u.w2; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-1.c b/gcc/testsuite/gcc.target/powerpc/no-r11-1.c new file mode 100644 index 0000000000..57c01a3e25 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ + +int +call_ptr (int (func) (void)) +{ + return func () + 1; +} + +/* { dg-final { scan-assembler-not "ld 11,16(3)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-2.c b/gcc/testsuite/gcc.target/powerpc/no-r11-2.c new file mode 100644 index 0000000000..3e4a6ca0ff --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mpointers-to-nested-functions" } */ + +int +call_ptr (int (func) (void)) +{ + return func () + 1; +} + +/* { dg-final { scan-assembler "ld 11,16" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-3.c b/gcc/testsuite/gcc.target/powerpc/no-r11-3.c new file mode 100644 index 0000000000..c98797e7f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ + +extern void ext_call (int (func) (void)); + +int +outer_func (int init) /* { dg-error "-mno-pointers-to-nested-functions option" "" } */ +{ + int value = init; + + int inner (void) + { + return ++value; + } + + ext_call (inner); + return value; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c index 674115a285..a3d532485e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c @@ -3,16 +3,16 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math" } */ /* { dg-final { scan-assembler-times "xvmadd" 4 } } */ -/* { dg-final { scan-assembler-times "xsmadd" 2 } } */ +/* { dg-final { scan-assembler-times "xsmadd\|fmadd\ " 2 } } */ /* { dg-final { scan-assembler-times "fmadds" 2 } } */ /* { dg-final { scan-assembler-times "xvmsub" 2 } } */ -/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ +/* { dg-final { scan-assembler-times "xsmsub\|fmsub\ " 1 } } */ /* { dg-final { scan-assembler-times "fmsubs" 1 } } */ /* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ -/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ +/* { dg-final { scan-assembler-times "xsnmadd\|fnmadd " 1 } } */ /* { dg-final { scan-assembler-times "fnmadds" 1 } } */ /* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ -/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ +/* { dg-final { scan-assembler-times "xsnmsub\|fnmsub " 1 } } */ /* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ /* All functions should generate an appropriate (a * b) + c instruction diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c index 111b9cb098..f732b9fa41 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c @@ -3,16 +3,16 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -ffp-contract=off" } */ /* { dg-final { scan-assembler-times "xvmadd" 2 } } */ -/* { dg-final { scan-assembler-times "xsmadd" 1 } } */ +/* { dg-final { scan-assembler-times "xsmadd\|fmadd\ " 1 } } */ /* { dg-final { scan-assembler-times "fmadds" 1 } } */ /* { dg-final { scan-assembler-times "xvmsub" 2 } } */ -/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ +/* { dg-final { scan-assembler-times "xsmsub\|fmsub\ " 1 } } */ /* { dg-final { scan-assembler-times "fmsubs" 1 } } */ /* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ -/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ +/* { dg-final { scan-assembler-times "xsnmadd\|fnmadd\ " 1 } } */ /* { dg-final { scan-assembler-times "fnmadds" 1 } } */ /* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ -/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ +/* { dg-final { scan-assembler-times "xsnmsub\|fnmsub\ " 1 } } */ /* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ /* Only the functions calling the bulitin should generate an appropriate (a * diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c index c83c58298b..3203704be7 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math" } */ /* { dg-final { scan-assembler-times "vmaddfp" 2 } } */ /* { dg-final { scan-assembler-times "fmadd " 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c index 44da6e76bc..35836eec23 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math -ffp-contract=off" } */ /* { dg-final { scan-assembler-times "vmaddfp" 1 } } */ /* { dg-final { scan-assembler-times "fmadd " 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c index 97243afb7c..e5ba874e7e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c @@ -1,5 +1,6 @@ /* { dg-do run { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mcpu=power5 -std=c99" } */ #ifndef __FP_FAST_FMA diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c index ec0c3d7407..f6e7e4ce56 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -ffast-math" } */ /* { dg-final { scan-assembler-times "fmadd" 1 } } */ /* { dg-final { scan-assembler-times "fmsub " 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c index 2eebbb42cd..23b3d1e15e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */ /* { dg-final { scan-assembler-not "xsrdpiz" } } */ /* { dg-final { scan-assembler "friz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c index 6196162a2f..bf12113d28 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mcpu=power5 -ffast-math" } */ /* { dg-final { scan-assembler-not "lfiwax" } } */ /* { dg-final { scan-assembler-not "lfiwzx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c index 007c8644a0..808cbc3907 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -mcpu=power5 -ffast-math" } */ /* { dg-final { scan-assembler-times "fctiwz" 2 } } */ /* { dg-final { scan-assembler-not "fctiwuz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c index b5410f60ea..f841d7ee07 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -mcpu=750 -ffast-math" } */ /* { dg-final { scan-assembler-times "fctiwz" 6 } } */ /* { dg-final { scan-assembler-not "fctiwuz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-pow.c b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c index 1255d5c596..29614e8f51 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-pow.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c @@ -1,9 +1,13 @@ /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ -/* { dg-options "-O2 -ffast-math -mcpu=power6" } */ +/* Check for VSX here, even though we don't use VSX to eliminate SPE, PAIRED + and other ppc floating point varients. However, we need to also eliminate + Darwin, since it doesn't like -mcpu=power6. */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ffast-math -mcpu=power6 -mno-vsx -mno-altivec" } */ /* { dg-final { scan-assembler-times "fsqrt" 3 } } */ /* { dg-final { scan-assembler-times "fmul" 1 } } */ -/* { dg-final { scan-assembler-times "bl pow" 1 } } */ -/* { dg-final { scan-assembler-times "bl sqrt" 1 } } */ +/* { dg-final { scan-assembler-times "bl? pow" 1 } } */ +/* { dg-final { scan-assembler-times "bl? sqrt" 1 } } */ double do_pow_0_75_default (double a) diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c new file mode 100644 index 0000000000..ac1dac9faa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 --param case-values-threshold=2" } */ +/* { dg-final { scan-assembler "mtctr" } } */ +/* { dg-final { scan-assembler "bctr" } } */ + +/* Force using a dispatch table even though by default we would generate + ifs. */ + +extern long call (long); + +long +test_switch (long a, long b) +{ + long c; + + switch (a) + { + case 0: c = -b; break; + case 1: c = ~b; break; + case 2: c = b+1; break; + default: c = b & 9; break; + } + + return call (c) + 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c new file mode 100644 index 0000000000..4f2efccfbd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 --param case-values-threshold=20" } */ +/* { dg-final { scan-assembler-not "mtctr" } } */ +/* { dg-final { scan-assembler-not "bctr" } } */ + +/* Force using if tests, instead of a dispatch table. */ + +extern long call (long); + +long +test_switch (long a, long b) +{ + long c; + + switch (a) + { + case 0: c = -b; break; + case 1: c = ~b; break; + case 2: c = b+1; break; + case 3: c = b-2; break; + case 4: c = b*3; break; + case 5: c = b/4; break; + case 6: c = b<<5; break; + case 7: c = b>>6; break; + case 8: c = b|7; break; + case 9: c = b^8; break; + default: c = b&9; break; + } + + return call (c) + 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c new file mode 100644 index 0000000000..ac728334cd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c @@ -0,0 +1,84 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ffast-math -mcpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "vaddfp" 1 } } */ +/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */ +/* { dg-final { scan-assembler-times "fadds" 1 } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifdef __ALTIVEC__ +#error "__ALTIVEC__ should not be defined." +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined." +#endif + +#pragma GCC target("vsx") +#include <altivec.h> +#pragma GCC reset_options + +#pragma GCC push_options +#pragma GCC target("altivec,no-vsx") + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined." +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined." +#endif + +void +av_add (vector float *a, vector float *b, vector float *c) +{ + unsigned long i; + unsigned long n = SIZE / 4; + + for (i = 0; i < n; i++) + a[i] = vec_add (b[i], c[i]); +} + +#pragma GCC target("vsx") + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined." +#endif + +#ifndef __VSX__ +#error "__VSX__ should be defined." +#endif + +void +vsx_add (vector float *a, vector float *b, vector float *c) +{ + unsigned long i; + unsigned long n = SIZE / 4; + + for (i = 0; i < n; i++) + a[i] = vec_add (b[i], c[i]); +} + +#pragma GCC pop_options +#pragma GCC target("no-vsx,no-altivec") + +#ifdef __ALTIVEC__ +#error "__ALTIVEC__ should not be defined." +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined." +#endif + +void +norm_add (float *a, float *b, float *c) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c new file mode 100644 index 0000000000..16336243a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 0.5); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != sqrt (values[i])) + abort (); + + return 0; +} + + +/* { dg-final { scan-assembler-times "fsqrt" 2 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c new file mode 100644 index 0000000000..84833c84a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 0.25); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != sqrt (sqrt (values[i]))) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c new file mode 100644 index 0000000000..0dd0f7571a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 0.75); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + double PREC = 0.999999; + unsigned i; + + for (i = 0; i < NVALS; i++) + { + volatile double x, y; + x = sqrt (values[i]); + y = sqrt (sqrt (values[i])); + + if (fabs (convert_it (values[i]) / (x * y)) < PREC) + abort (); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c new file mode 100644 index 0000000000..71015a942c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 1.0 / 6.0); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != cbrt (sqrt (values[i]))) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c new file mode 100644 index 0000000000..d5fc83ba2d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it_1 (double x) +{ + return pow (x, 1.5); +} + +static double +convert_it_2 (double x) +{ + return pow (x, 2.5); +} + +static double +convert_it_3 (double x) +{ + return pow (x, -0.5); +} + +static double +convert_it_4 (double x) +{ + return pow (x, 10.5); +} + +static double +convert_it_5 (double x) +{ + return pow (x, -3.5); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + double PREC = .999999; + unsigned i; + + for (i = 0; i < NVALS; i++) + { + volatile double x, y; + + x = sqrt (values[i]); + y = __builtin_powi (values[i], 1); + if (fabs (convert_it_1 (values[i]) / (x * y)) < PREC) + abort (); + + x = sqrt (values[i]); + y = __builtin_powi (values[i], 2); + if (fabs (convert_it_2 (values[i]) / (x * y)) < PREC) + abort (); + + x = sqrt (values[i]); + y = __builtin_powi (values[i], -1); + if (fabs (convert_it_3 (values[i]) / (x * y)) < PREC) + abort (); + + x = sqrt (values[i]); + y = __builtin_powi (values[i], 10); + if (fabs (convert_it_4 (values[i]) / (x * y)) < PREC) + abort (); + + x = sqrt (values[i]); + y = __builtin_powi (values[i], -4); + if (fabs (convert_it_5 (values[i]) / (x * y)) < PREC) + abort (); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-15.c b/gcc/testsuite/gcc.target/powerpc/pr46728-15.c new file mode 100644 index 0000000000..0586e29013 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-15.c @@ -0,0 +1,67 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it_1 (double x) +{ + return pow (x, 10.0 / 3.0); +} + +static double +convert_it_2 (double x) +{ + return pow (x, 11.0 / 3.0); +} + +static double +convert_it_3 (double x) +{ + return pow (x, -7.0 / 3.0); +} + +static double +convert_it_4 (double x) +{ + return pow (x, -8.0 / 3.0); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + double PREC = .999999; + unsigned i; + + for (i = 0; i < NVALS; i++) + { + volatile double x, y; + + x = __builtin_powi (values[i], 3); + y = __builtin_powi (cbrt (values[i]), 1); + if (fabs (convert_it_1 (values[i]) / (x * y)) < PREC) + abort (); + + x = __builtin_powi (values[i], 3); + y = __builtin_powi (cbrt (values[i]), 2); + if (fabs (convert_it_2 (values[i]) / (x * y)) < PREC) + abort (); + + x = __builtin_powi (values[i], -3); + y = __builtin_powi (cbrt (values[i]), 2); + if (fabs (convert_it_3 (values[i]) / (x * y)) < PREC) + abort (); + + x = __builtin_powi (values[i], -3); + y = __builtin_powi (cbrt (values[i]), 1); + if (fabs (convert_it_4 (values[i]) / (x * y)) < PREC) + abort (); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-16.c b/gcc/testsuite/gcc.target/powerpc/pr46728-16.c new file mode 100644 index 0000000000..d9488e3b7a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -mcpu=power6" } */ + +double foo (double x, double y) +{ + return __builtin_pow (x, 0.75) + y; +} + + +/* { dg-final { scan-assembler "fmadd" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-2.c b/gcc/testsuite/gcc.target/powerpc/pr46728-2.c new file mode 100644 index 0000000000..abf92491f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 0.25); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != sqrt (sqrt (values[i]))) + abort (); + + return 0; +} + + +/* { dg-final { scan-assembler-times "fsqrt" 4 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-3.c b/gcc/testsuite/gcc.target/powerpc/pr46728-3.c new file mode 100644 index 0000000000..a00f7940a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-3.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 0.75); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != sqrt(values[i]) * sqrt (sqrt (values[i]))) + abort (); + + return 0; +} + + +/* { dg-final { scan-assembler-times "sqrt" 4 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-4.c b/gcc/testsuite/gcc.target/powerpc/pr46728-4.c new file mode 100644 index 0000000000..95d8fbe89e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 1.0 / 3.0); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != cbrt (values[i])) + abort (); + + return 0; +} + + +/* { dg-final { scan-assembler-times "cbrt" 2 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-5.c b/gcc/testsuite/gcc.target/powerpc/pr46728-5.c new file mode 100644 index 0000000000..a380d52252 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-5.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it (double x) +{ + return pow (x, 1.0 / 6.0); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + if (convert_it (values[i]) != cbrt (sqrt (values[i]))) + abort (); + + return 0; +} + + +/* { dg-final { scan-assembler-times "cbrt" 2 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not " pow " { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-7.c b/gcc/testsuite/gcc.target/powerpc/pr46728-7.c new file mode 100644 index 0000000000..873596cff3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-7.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it_1 (double x) +{ + return pow (x, 1.5); +} + +static double +convert_it_2 (double x) +{ + return pow (x, 2.5); +} + +static double +convert_it_3 (double x) +{ + return pow (x, -0.5); +} + +static double +convert_it_4 (double x) +{ + return pow (x, 10.5); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + { + if (convert_it_1 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 1)) + abort (); + if (convert_it_2 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 2)) + abort (); + if (convert_it_3 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], -1)) + abort (); + if (convert_it_4 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 10)) + abort (); + } + + return 0; +} + + +/* { dg-final { scan-assembler-times "sqrt" 5 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-8.c b/gcc/testsuite/gcc.target/powerpc/pr46728-8.c new file mode 100644 index 0000000000..6480c7df9b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr46728-8.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */ + +#include <math.h> + +extern void abort (void); + +#define NVALS 6 + +static double +convert_it_1 (double x) +{ + return pow (x, 10.0 / 3.0); +} + +static double +convert_it_2 (double x) +{ + return pow (x, 11.0 / 3.0); +} + +static double +convert_it_3 (double x) +{ + return pow (x, -7.0 / 3.0); +} + +static double +convert_it_4 (double x) +{ + return pow (x, -8.0 / 3.0); +} + +int +main (int argc, char *argv[]) +{ + double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 }; + unsigned i; + + for (i = 0; i < NVALS; i++) + { + if (convert_it_1 (values[i]) != + __builtin_powi (values[i], 3) * __builtin_powi (cbrt (values[i]), 1)) + abort (); + if (convert_it_2 (values[i]) != + __builtin_powi (values[i], 3) * __builtin_powi (cbrt (values[i]), 2)) + abort (); + if (convert_it_3 (values[i]) != + __builtin_powi (values[i], -3) * __builtin_powi (cbrt (values[i]), 2)) + abort (); + if (convert_it_4 (values[i]) != + __builtin_powi (values[i], -3) * __builtin_powi (cbrt (values[i]), 1)) + abort (); + } + + return 0; +} + + +/* { dg-final { scan-assembler-times "cbrt" 5 { target powerpc*-*-* } } } */ +/* { dg-final { scan-assembler-not "pow" { target powerpc*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755-2.c b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c index 2180efdbe4..5edcc118ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47755-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-require-effective-target vsx_hw } */ /* { dg-options "-O3 -mcpu=power7" } */ /* PR 47755: Make sure compiler generates correct code for various diff --git a/gcc/testsuite/gcc.target/powerpc/pr48053-3.c b/gcc/testsuite/gcc.target/powerpc/pr48053-3.c new file mode 100644 index 0000000000..399b3d3ea3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48053-3.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7" } */ + +/* Cut down example from s_scalbnl that aborted on 32-bit when the fix for + 48053 went in to allow creating DImode 0's in VSX registers. */ + +typedef union +{ + long double value; + struct + { + unsigned long long msw; + unsigned long long lsw; + } parts64; + struct + { + unsigned int w0, w1, w2, w3; + } parts32; +} ieee854_long_double_shape_type; + +static const long double twolm54 = 5.55111512312578270212e-17; + +long double foo (long double x, int n) +{ + long long k, hx, lx; + ieee854_long_double_shape_type qw_u; + + qw_u.value = x; + hx = qw_u.parts64.msw; + lx = qw_u.parts64.lsw; + + k = ((hx >> 52) & 0x7ff) + n + 54; + + qw_u.parts64.msw = ((hx & 0x800fffffffffffffULL) | (k << 52)); + qw_u.parts64.lsw = lx; + x = qw_u.value; + + return x*twolm54; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr48226.c b/gcc/testsuite/gcc.target/powerpc/pr48226.c new file mode 100644 index 0000000000..a436f1da5c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48226.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7" } */ + +/* The bug shows up if you compile with -maltivec or -mcpu=power7, due to one + of the vector's being eliminated due to rs6000_macro_to_expand being called + recursively. */ + +struct vector { + float v[4]; +}; + +struct vector vector = { 1.0, 2.0, 3.0, 4.0 }; diff --git a/gcc/testsuite/gcc.target/powerpc/pr48258-1.c b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c new file mode 100644 index 0000000000..4f37815d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "xvaddsp" 3 } } */ +/* { dg-final { scan-assembler-times "xvminsp" 3 } } */ +/* { dg-final { scan-assembler-times "xvmaxsp" 3 } } */ +/* { dg-final { scan-assembler-times "xxsldwi" 6 } } */ +/* { dg-final { scan-assembler-times "xscvspdp" 3 } } */ +/* { dg-final { scan-assembler-not "stvewx" } } */ +/* { dg-final { scan-assembler-not "stvx" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ + +#include <stddef.h> + +#ifndef SIZE +#define SIZE 1024 +#endif + +float values[SIZE] __attribute__((__aligned__(32))); + +float +vector_sum (void) +{ + size_t i; + float sum = 0.0f; + + for (i = 0; i < SIZE; i++) + sum += values[i]; + + return sum; +} + +float +vector_min (void) +{ + size_t i; + float min = values[0]; + + for (i = 0; i < SIZE; i++) + min = __builtin_fminf (min, values[i]); + + return min; +} + +float +vector_max (void) +{ + size_t i; + float max = values[0]; + + for (i = 0; i < SIZE; i++) + max = __builtin_fmaxf (max, values[i]); + + return max; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr48258-2.c b/gcc/testsuite/gcc.target/powerpc/pr48258-2.c new file mode 100644 index 0000000000..443fb624e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48258-2.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xsadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xsmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xsmaxdp" 1 } } */ +/* { dg-final { scan-assembler-not "xxsldwi" } } */ +/* { dg-final { scan-assembler-not "stvx" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ + +#include <stddef.h> + +#ifndef SIZE +#define SIZE 1024 +#endif + +double values[SIZE] __attribute__((__aligned__(32))); + +double +vector_sum (void) +{ + size_t i; + double sum = 0.0; + + for (i = 0; i < SIZE; i++) + sum += values[i]; + + return sum; +} + +double +vector_min (void) +{ + size_t i; + double min = values[0]; + + for (i = 0; i < SIZE; i++) + min = __builtin_fmin (min, values[i]); + + return min; +} + +double +vector_max (void) +{ + size_t i; + double max = values[0]; + + for (i = 0; i < SIZE; i++) + max = __builtin_fmax (max, values[i]); + + return max; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr51623.c b/gcc/testsuite/gcc.target/powerpc/pr51623.c new file mode 100644 index 0000000000..37b7d6557a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr51623.c @@ -0,0 +1,123 @@ +/* PR target/51623 */ +/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */ +/* { dg-options "-mrelocatable -ffreestanding" } */ + +/* This generated an error, since the compiler was calling + unlikely_text_section_p in a context where it wasn't valid. */ + +typedef long long loff_t; +typedef unsigned size_t; + + +struct mtd_info { + unsigned writesize; + unsigned oobsize; + const char *name; +}; + +extern int strcmp(const char *,const char *); +extern char * strchr(const char *,int); + +struct cmd_tbl_s { + char *name; +}; + + +int printf(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2))); +void* malloc(size_t); +void free(void*); + + +extern int nand_curr_device; +extern struct mtd_info nand_info[]; + +static int nand_dump(struct mtd_info *nand, unsigned long off, int only_oob) +{ + int i; + unsigned char *datbuf, *oobbuf, *p; + + datbuf = malloc(nand->writesize + nand->oobsize); + oobbuf = malloc(nand->oobsize); + off &= ~(nand->writesize - 1); + + printf("Page %08lx dump:\n", off); + i = nand->writesize >> 4; + p = datbuf; + + while (i--) { + if (!only_oob) + printf("\t%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], + p[8], p[9], p[10], p[11], p[12], p[13], p[14], + p[15]); + p += 16; + } + + i = nand->oobsize >> 3; + free(datbuf); + free(oobbuf); + + return 0; +} + +int do_nand(struct cmd_tbl_s * cmdtp, int flag, int argc, char *argv[]) +{ + int dev; + unsigned long off; + char *cmd, *s; + struct mtd_info *nand; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "info") == 0) { + putc('\n'); + return 0; + } + + if (strcmp(cmd, "device") == 0) { + if (argc < 3) { + putc('\n'); + } + dev = (int)simple_strtoul(argv[2], ((void *)0), 10); + nand_curr_device = dev; + return 0; + } + + if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 ) + goto usage; + + if (nand_curr_device < 0 ) { + return 1; + } + nand = &nand_info[nand_curr_device]; + + if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) { + int clean = argc > 2 && !strcmp("clean", argv[2]); + int scrub = !strcmp(cmd, "scrub"); + return 0; + } + + if (strncmp(cmd, "dump", 4) == 0) { + if (argc < 3) + goto usage; + + s = strchr(cmd, '.'); + off = (int)simple_strtoul(argv[2], ((void *)0), 16); + + if (s != ((void *)0) && strcmp(s, ".oob") == 0) + nand_dump(nand, off, 1); + else + nand_dump(nand, off, 0); + + return 0; + } +usage: + cmd_usage(cmdtp); + return 1; +} + +void *ptr = do_nand; diff --git a/gcc/testsuite/gcc.target/powerpc/pr52199.c b/gcc/testsuite/gcc.target/powerpc/pr52199.c new file mode 100644 index 0000000000..e223193883 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52199.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -fmerge-all-constants" } */ + +struct locale_time_t +{ + const char *abday[7]; + const unsigned int *wabday[7]; +}; + +static const unsigned int empty_wstr[1] = { 0 }; + +void +time_read (struct locale_time_t *time) +{ + int cnt; + + for (cnt=0; cnt < 7; cnt++) + { + time->abday[cnt] = ""; + time->wabday[cnt] = empty_wstr; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr52457.c b/gcc/testsuite/gcc.target/powerpc/pr52457.c new file mode 100644 index 0000000000..4470e55023 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52457.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target vsx_hw } */ +/* { dg-options "-O1 -mcpu=power7" } */ + +extern void abort (void); + +typedef long long T; +typedef T vl_t __attribute__((vector_size(2 * sizeof (T)))); + +vl_t +buggy_func (T x) +{ + vl_t w; + T *p = (T *)&w; + p[0] = p[1] = x; + return w; +} + +int +main(void) +{ + vl_t rval; + T *pl; + + pl = (T *) &rval; + rval = buggy_func (2); + + if (pl[0] != 2 || pl[1] != 2) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr52775.c b/gcc/testsuite/gcc.target/powerpc/pr52775.c new file mode 100644 index 0000000000..4027819ee6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52775.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O1 -mcpu=power4" } */ +/* { dg-final { scan-assembler-times "fcfid" 2 } } */ + +double +int_to_double (int *p) +{ + return (double)*p; +} + +double +long_long_to_double (long long *p) +{ + return (double)*p; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr53199.c b/gcc/testsuite/gcc.target/powerpc/pr53199.c new file mode 100644 index 0000000000..89a0cad06f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr53199.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power6 -mavoid-indexed-addresses" } */ +/* { dg-final { scan-assembler-times "lwbrx" 6 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 6 } } */ + +/* PR 51399: bswap gets an error if -mavoid-indexed-addresses was used in + creating the two lwbrx instructions. */ + +long long +load64_reverse_1 (long long *p) +{ + return __builtin_bswap64 (*p); +} + +long long +load64_reverse_2 (long long *p) +{ + return __builtin_bswap64 (p[1]); +} + +long long +load64_reverse_3 (long long *p, int i) +{ + return __builtin_bswap64 (p[i]); +} + +void +store64_reverse_1 (long long *p, long long x) +{ + *p = __builtin_bswap64 (x); +} + +void +store64_reverse_2 (long long *p, long long x) +{ + p[1] = __builtin_bswap64 (x); +} + +void +store64_reverse_3 (long long *p, long long x, int i) +{ + p[i] = __builtin_bswap64 (x); +} + +long long +reg_reverse (long long x) +{ + return __builtin_bswap64 (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-1.c b/gcc/testsuite/gcc.target/powerpc/recip-1.c index 590881bb89..4ae0c4f119 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-1.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-1.c @@ -1,4 +1,5 @@ /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */ /* { dg-final { scan-assembler-times "frsqrte" 2 } } */ /* { dg-final { scan-assembler-times "fmsub" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-2.c b/gcc/testsuite/gcc.target/powerpc/recip-2.c index 3e64c07578..5c9fbbda51 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-2.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-2.c @@ -1,4 +1,5 @@ /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power5" } */ /* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ /* { dg-final { scan-assembler-times "fmsubs" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-3.c b/gcc/testsuite/gcc.target/powerpc/recip-3.c index c5ce539bb4..905e793952 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-3.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-3.c @@ -1,9 +1,10 @@ /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */ /* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */ -/* { dg-final { scan-assembler-times "xsmsub.dp" 1 } } */ +/* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */ /* { dg-final { scan-assembler-times "xsmuldp" 4 } } */ -/* { dg-final { scan-assembler-times "xsnmsub.dp" 2 } } */ +/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */ /* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ /* { dg-final { scan-assembler-times "fmsubs" 1 } } */ /* { dg-final { scan-assembler-times "fmuls" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-4.c b/gcc/testsuite/gcc.target/powerpc/recip-4.c index bd496d70e2..35eef6f0f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-4.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-4.c @@ -1,4 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O3 -ftree-vectorize -mrecip -ffast-math -mcpu=power7 -fno-unroll-loops" } */ /* { dg-final { scan-assembler-times "xvrsqrtedp" 1 } } */ /* { dg-final { scan-assembler-times "xvmsub.dp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-5.c b/gcc/testsuite/gcc.target/powerpc/recip-5.c index 4a9c496201..3d7d691d5a 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-5.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-5.c @@ -1,4 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */ /* { dg-final { scan-assembler-times "xvredp" 4 } } */ /* { dg-final { scan-assembler-times "xvresp" 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c index 445dc1992d..8f4062be7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -mveclibabi=mass" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-1.c b/gcc/testsuite/gcc.target/powerpc/warn-1.c index c00aff08c6..f4cb4372fd 100644 --- a/gcc/testsuite/gcc.target/powerpc/warn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/warn-1.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O -mvsx -mno-altivec" } */ /* { dg-warning "-mvsx and -mno-altivec are incompatible" "" { target *-*-* } 1 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-2.c b/gcc/testsuite/gcc.target/powerpc/warn-2.c index 0a9fa1e3ff..e8c9096f77 100644 --- a/gcc/testsuite/gcc.target/powerpc/warn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/warn-2.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O -mcpu=power7 -mno-altivec" } */ /* { dg-warning "-mno-altivec disables vsx" "" { target *-*-* } 1 } */ diff --git a/gcc/testsuite/gcc.target/pr55981.c b/gcc/testsuite/gcc.target/pr55981.c new file mode 100644 index 0000000000..36498d63cf --- /dev/null +++ b/gcc/testsuite/gcc.target/pr55981.c @@ -0,0 +1,54 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + +volatile long long y; + +void +test () +{ + int a_ = a; + int b_ = b; + int c_ = c; + int d_ = d; + int e_ = e; + int f_ = f; + int g_ = g; + int h_ = h; + int i_ = i; + int j_ = j; + int k_ = k; + int l_ = l; + int m_ = m; + int n_ = n; + int o_ = o; + int p_ = p; + + int z; + + for (z = 0; z < 1000; z++) + { + __atomic_store_n (&y, 0x100000002ll, __ATOMIC_SEQ_CST); + __atomic_store_n (&y, 0x300000004ll, __ATOMIC_SEQ_CST); + } + + a = a_; + b = b_; + c = c_; + d = d_; + e = e_; + f = f_; + g = g_; + h = h_; + i = i_; + j = j_; + k = k_; + l = l_; + m = m_; + n = n_; + o = o_; + p = p_; +} + +/* { dg-final { scan-assembler-times "movabs" 2 } } */ diff --git a/gcc/testsuite/gcc.target/s390/20090223-1.c b/gcc/testsuite/gcc.target/s390/20090223-1.c index 443ccb9aa6..1bf0f2fe8f 100644 --- a/gcc/testsuite/gcc.target/s390/20090223-1.c +++ b/gcc/testsuite/gcc.target/s390/20090223-1.c @@ -3,7 +3,7 @@ register asm ("0"). */ /* { dg-do run } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -Wno-attributes" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/s390/addr-constraints-1.c b/gcc/testsuite/gcc.target/s390/addr-constraints-1.c new file mode 100644 index 0000000000..fbb48f282b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/addr-constraints-1.c @@ -0,0 +1,70 @@ +/* { dg-compile } */ +/* { dg-options "-O2" } */ + +static inline unsigned long +lay_uw(unsigned long addr) +{ + unsigned long result; + + __asm__ ("lay %[result],%a[addr]" + : [result] "=d" (result) + : [addr] "UW" (addr)); + return result; +} + +static inline unsigned long +la_u(unsigned long addr) +{ + unsigned long result; + + __asm__ ("la %[result],%a[addr]" + : [result] "=d" (result) + : [addr] "U" (addr)); + return result; +} + +static inline unsigned long +lay_zqzrzszt(unsigned long addr) +{ + unsigned long result; + + __asm__ ("lay %[result],%a[addr]" + : [result] "=d" (result) + : [addr] "ZQZRZSZT" (addr)); + return result; +} + +static inline unsigned long +la_zqzr(unsigned long addr) +{ + unsigned long result; + + __asm__ ("la %[result],%a[addr]" + : [result] "=d" (result) + : [addr] "ZQZR" (addr)); + return result; +} + + +extern unsigned long a[15]; + +int main(void) +{ + a[1] = lay_uw(3333); + a[2] = lay_uw(4444); + a[3] = lay_uw(1000000); + a[4] = lay_uw(a[0]); + + a[5] = la_u(2222); + a[6] = la_u(5555); + a[7] = la_u(a[0]); + + a[8] = lay_zqzrzszt(3333); + a[9] = lay_zqzrzszt(4444); + a[10] = lay_zqzrzszt(1000000); + a[11] = lay_zqzrzszt(a[0]); + + a[12] = la_zqzr(2222); + a[13] = la_zqzr(5555); + a[14] = la_zqzr(a[0]); +} diff --git a/gcc/testsuite/gcc.target/sh/20080410-1.c b/gcc/testsuite/gcc.target/sh/20080410-1.c index 0ba7792c07..63e517e94d 100644 --- a/gcc/testsuite/gcc.target/sh/20080410-1.c +++ b/gcc/testsuite/gcc.target/sh/20080410-1.c @@ -1,8 +1,9 @@ /* { dg-do compile { target "sh-*-*" } } */ -/* { dg-options "-O0 -m4 -ml" } */ +/* { dg-options "-O0" } */ +/* { dg-skip-if "" { "sh*-*-*" } "-mb" "" } */ /* { dg-final { scan-assembler-not "add\tr0,r0" } } */ -/* This test checks that chain reloads conflict. I they don't +/* This test checks chain reloads conflicts. If they don't conflict, the same hard register R0 is used for the both reloads but in this case the second reload needs an intermediate register (which is the reload register). As the result we have the diff --git a/gcc/testsuite/gcc.target/sh/mfmovd.c b/gcc/testsuite/gcc.target/sh/mfmovd.c index c8e0094f0c..b5653c7648 100644 --- a/gcc/testsuite/gcc.target/sh/mfmovd.c +++ b/gcc/testsuite/gcc.target/sh/mfmovd.c @@ -1,7 +1,9 @@ +/* Verify that we generate fmov.d instructions to move doubles when -mfmovd + option is enabled. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-mfmovd" } */ -/* { dg-skip-if "No double precision FPU support" { "sh*-*-*" } "-m2a-nofpu -m2a-single-only -m4-nofpu -m4-single-only -m4a-nofpu -m4a-single-only" { "" } } */ -/* { dg-final { scan-assembler "fmov.d"} } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a" "-m2a-single" "-m4" "-m4-single" "-m4-100" "-m4-100-single" "-m4-200" "-m4-200-single" "-m4-300" "-m4-300-single" "-m4a" "-m4a-single" } } */ +/* { dg-final { scan-assembler "fmov.d" } } */ extern double g; diff --git a/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c index c63a573ea9..570e7dd0b5 100644 --- a/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c +++ b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c @@ -1,5 +1,6 @@ /* { dg-do compile { target "sh*-*-*" } } */ -/* { dg-options "-ml -O2 -fomit-frame-pointer" } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-mb" && "-m5*"} { "" } } */ /* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */ double d; @@ -7,13 +8,6 @@ double f (void) { double r; - -/* If -mb from the target options is passed after -ml from dg-options, we - end up with th reverse endianness. */ -#if TARGET_SHMEDIA || defined (__BIG_ENDIAN__) - asm ("mov @(4,r1),r4; mov @r1,r3"); -#else asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d)); -#endif return r; } diff --git a/gcc/testsuite/gcc.target/sh/pr49263.c b/gcc/testsuite/gcc.target/sh/pr49263.c new file mode 100644 index 0000000000..b5ffe714fa --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49263.c @@ -0,0 +1,86 @@ +/* Verify that TST #imm, R0 instruction is generated if the constant + allows it. Under some circumstances another compare instruction might + be selected, which is also fine. Any AND instructions are considered + counter productive and fail the test. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "and" } } */ + +#define make_func(__valtype__, __valget__, __tstval__, __suff__)\ + int test_imm_##__tstval__##__suff__ (__valtype__ val) \ + {\ + return ((__valget__) & (0x##__tstval__ << 0)) ? -20 : -40;\ + } + +#define make_func_0_F(__valtype__, __valget__, __y__, __suff__)\ + make_func (__valtype__, __valget__, __y__##0, __suff__)\ + make_func (__valtype__, __valget__, __y__##1, __suff__)\ + make_func (__valtype__, __valget__, __y__##2, __suff__)\ + make_func (__valtype__, __valget__, __y__##3, __suff__)\ + make_func (__valtype__, __valget__, __y__##4, __suff__)\ + make_func (__valtype__, __valget__, __y__##5, __suff__)\ + make_func (__valtype__, __valget__, __y__##6, __suff__)\ + make_func (__valtype__, __valget__, __y__##7, __suff__)\ + make_func (__valtype__, __valget__, __y__##8, __suff__)\ + make_func (__valtype__, __valget__, __y__##9, __suff__)\ + make_func (__valtype__, __valget__, __y__##A, __suff__)\ + make_func (__valtype__, __valget__, __y__##B, __suff__)\ + make_func (__valtype__, __valget__, __y__##C, __suff__)\ + make_func (__valtype__, __valget__, __y__##D, __suff__)\ + make_func (__valtype__, __valget__, __y__##E, __suff__)\ + make_func (__valtype__, __valget__, __y__##F, __suff__)\ + +#define make_funcs_0_FF(__valtype__, __valget__, __suff__)\ + make_func_0_F (__valtype__, __valget__, 0, __suff__)\ + make_func_0_F (__valtype__, __valget__, 1, __suff__)\ + make_func_0_F (__valtype__, __valget__, 2, __suff__)\ + make_func_0_F (__valtype__, __valget__, 3, __suff__)\ + make_func_0_F (__valtype__, __valget__, 4, __suff__)\ + make_func_0_F (__valtype__, __valget__, 5, __suff__)\ + make_func_0_F (__valtype__, __valget__, 6, __suff__)\ + make_func_0_F (__valtype__, __valget__, 7, __suff__)\ + make_func_0_F (__valtype__, __valget__, 8, __suff__)\ + make_func_0_F (__valtype__, __valget__, 9, __suff__)\ + make_func_0_F (__valtype__, __valget__, A, __suff__)\ + make_func_0_F (__valtype__, __valget__, B, __suff__)\ + make_func_0_F (__valtype__, __valget__, C, __suff__)\ + make_func_0_F (__valtype__, __valget__, D, __suff__)\ + make_func_0_F (__valtype__, __valget__, E, __suff__)\ + make_func_0_F (__valtype__, __valget__, F, __suff__)\ + +make_funcs_0_FF (signed char*, *val, int8_mem) +make_funcs_0_FF (signed char, val, int8_reg) + +make_funcs_0_FF (unsigned char*, *val, uint8_mem) +make_funcs_0_FF (unsigned char, val, uint8_reg) + +make_funcs_0_FF (short*, *val, int16_mem) +make_funcs_0_FF (short, val, int16_reg) + +make_funcs_0_FF (unsigned short*, *val, uint16_mem) +make_funcs_0_FF (unsigned short, val, uint16_reg) + +make_funcs_0_FF (int*, *val, int32_mem) +make_funcs_0_FF (int, val, int32_reg) + +make_funcs_0_FF (unsigned int*, *val, uint32_mem) +make_funcs_0_FF (unsigned int, val, uint32_reg) + +make_funcs_0_FF (long long*, *val, int64_lowword_mem) +make_funcs_0_FF (long long, val, int64_lowword_reg) + +make_funcs_0_FF (unsigned long long*, *val, uint64_lowword_mem) +make_funcs_0_FF (unsigned long long, val, uint64_lowword_reg) + +make_funcs_0_FF (long long*, *val >> 32, int64_highword_mem) +make_funcs_0_FF (long long, val >> 32, int64_highword_reg) + +make_funcs_0_FF (unsigned long long*, *val >> 32, uint64_highword_mem) +make_funcs_0_FF (unsigned long long, val >> 32, uint64_highword_reg) + +make_funcs_0_FF (long long*, *val >> 16, int64_midword_mem) +make_funcs_0_FF (long long, val >> 16, int64_midword_reg) + +make_funcs_0_FF (unsigned long long*, *val >> 16, uint64_midword_mem) +make_funcs_0_FF (unsigned long long, val >> 16, uint64_midword_reg) + diff --git a/gcc/testsuite/gcc.target/sh/pr49468-si.c b/gcc/testsuite/gcc.target/sh/pr49468-si.c new file mode 100644 index 0000000000..69fbe230ef --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49468-si.c @@ -0,0 +1,22 @@ +/* Check that 32 bit integer abs is generated as neg instruction and + conditional branch instead of default branch-free code. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O1" } */ +/* { dg-final { scan-assembler-times "neg" 2 } } */ + + +/* Normal integer absolute value. */ +int +abs_0 (int i) +{ + return (i < 0) ? -i : i; +} + +/* Negated integer absolute value. + The generated code should be the same, except that the branch + condition is inverted. */ +int +abs_1 (int i) +{ + return (i > 0) ? -i : i; +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-1.c b/gcc/testsuite/gcc.target/sh/pr49880-1.c new file mode 100644 index 0000000000..e19f1bf38a --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-1.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-div1 works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-div1" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-2.c b/gcc/testsuite/gcc.target/sh/pr49880-2.c new file mode 100644 index 0000000000..eef832e30d --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-2.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-fp works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-3.c b/gcc/testsuite/gcc.target/sh/pr49880-3.c new file mode 100644 index 0000000000..80a7df548a --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-3.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-table works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-table" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-4.c b/gcc/testsuite/gcc.target/sh/pr49880-4.c new file mode 100644 index 0000000000..998a8b69fd --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-4.c @@ -0,0 +1,19 @@ +/* Check that the option -mdiv=call-fp does not produce calls to the + library function that uses FPU to implement integer division if FPU insns + are not supported or are disabled. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } } */ +/* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-5.c b/gcc/testsuite/gcc.target/sh/pr49880-5.c new file mode 100644 index 0000000000..09e99a85f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-5.c @@ -0,0 +1,19 @@ +/* Check that the option -mdiv=call-fp results in the corresponding library + function calls on targets that have a double precision FPU. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } } */ +/* { dg-final { scan-assembler "sdivsi3_i4\n" } } */ +/* { dg-final { scan-assembler "udivsi3_i4\n" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c index 761c7b0b5d..1c9ae6ee6b 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c @@ -1,9 +1,9 @@ -/* Verify that we generate movua to load unaligned 32-bit values. */ +/* Verify that we generate movua to load unaligned 32-bit values on SH4A. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O" } */ -/* { dg-final { scan-assembler-times "\tmovua\\.l\t" 6 } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" "-m4a-nofpu" } } */ +/* { dg-final { scan-assembler-times "movua.l" 6 } } */ -#ifdef __SH4A__ /* Aligned. */ struct s0 { long long d : 32; } x0; long long f0() { @@ -63,11 +63,5 @@ struct u4 { long long c : 32; unsigned long long d : 32; } y4; unsigned long long g4() { return y4.d; } -#else -asm ("movua.l\t"); -asm ("movua.l\t"); -asm ("movua.l\t"); -asm ("movua.l\t"); -asm ("movua.l\t"); -asm ("movua.l\t"); -#endif + + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-cos.c b/gcc/testsuite/gcc.target/sh/sh4a-cos.c index 198d41f867..c2e421c6a0 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-cos.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-cos.c @@ -1,13 +1,11 @@ /* Verify that we generate single-precision sine and cosine approximate - (fsca) in fast math mode. */ + (fsca) in fast math mode on SH4A with FPU. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler "\tfsca\t" } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler "fsca" } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> double test(double f) { return cos(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-cosf.c b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c index f78c140d50..68bb20f2c3 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-cosf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c @@ -1,13 +1,11 @@ /* Verify that we generate single-precision sine and cosine approximate - (fsca) in fast math mode. */ + (fsca) in fast math mode on SH4A with FPU. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler "\tfsca\t" } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler "fsca" } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> float test(float f) { return cosf(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c index c8f04e4d2e..4ce2e28e22 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c @@ -1,13 +1,11 @@ /* Verify that we generate single-precision square root reciprocal - approximate (fsrra) in fast math mode. */ + approximate (fsrra) in fast math mode on SH4A with FPU. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler "\tfsrra\t" } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler "fsrra" } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> float test(float f) { return 1 / sqrtf(f); } -#else -asm ("fsrra\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c index 359dd8feb9..7e817c4c12 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c @@ -1,17 +1,14 @@ /* Verify that we generate movua to copy unaligned memory regions to - 32-bit-aligned addresses. */ + 32-bit-aligned addresses on SH4A. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O" } */ -/* { dg-final { scan-assembler-times "\tmovua\\.l\t" 2 } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" "-m4a-nofpu" } } */ +/* { dg-final { scan-assembler-times "movua.l" 2 } } */ -#ifdef __SH4A__ #include <string.h> struct s { int i; char a[10], b[10]; } x; int f() { memcpy(x.a, x.b, 10); } -#else -asm ("movua.l\t+"); -asm ("movua.l\t+"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sin.c b/gcc/testsuite/gcc.target/sh/sh4a-sin.c index 9f46f60076..cd8f0783d7 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sin.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sin.c @@ -1,13 +1,11 @@ /* Verify that we generate single-precision sine and cosine approximate - (fsca) in fast math mode. */ + (fsca) in fast math mode on SH4A with FPU. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler "\tfsca\t" } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler "fsca" } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> double test(double f) { return sin(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sincos.c b/gcc/testsuite/gcc.target/sh/sh4a-sincos.c index f429379753..423dda1433 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sincos.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sincos.c @@ -3,12 +3,10 @@ sine and cosine. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler-times "fsca" 1 } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> double test(double f) { return sin(f) + cos(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c index 42913dbd59..0ca33e30a0 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c @@ -3,12 +3,10 @@ sine and cosine. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler-times "fsca" 1 } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> float test(float f) { return sinf(f) + cosf(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sinf.c b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c index 2a2343fd73..4d9abea045 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sinf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c @@ -1,13 +1,11 @@ /* Verify that we generate single-precision sine and cosine approximate - (fsca) in fast math mode. */ + (fsca) in fast math mode on SH4A with FPU. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-final { scan-assembler "\tfsca\t" } } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ +/* { dg-final { scan-assembler "fsca" } } */ -#if defined __SH4A__ && ! defined __SH4_NOFPU__ #include <math.h> float test(float f) { return sinf(f); } -#else -asm ("fsca\t"); -#endif + diff --git a/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c b/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c index effd13d19a..81f80df1e6 100644 --- a/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c +++ b/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c @@ -1,4 +1,4 @@ -/* Verify that we don't generate fame related insn against stack adjustment +/* Verify that we don't generate frame related insn against stack adjustment for the object sent partially in registers. */ /* { dg-do compile { target "sh*-*-*" } } */ /* { dg-options "-g" } */ diff --git a/gcc/testsuite/gcc.target/sparc/20111102-1.c b/gcc/testsuite/gcc.target/sparc/20111102-1.c new file mode 100644 index 0000000000..d33f103e37 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20111102-1.c @@ -0,0 +1,17 @@ +/* PR target/50945 */ +/* { dg-do compile } */ +/* { dg-options "-O -msoft-float" } */ + +double +__powidf2 (double x, int m) +{ + unsigned int n = m < 0 ? -m : m; + double y = n % 2 ? x : 1; + while (n >>= 1) + { + x = x * x; + if (n % 2) + y = y * x; + } + return m < 0 ? 1/y : y; +} diff --git a/gcc/testsuite/gcc.target/sparc/array.c b/gcc/testsuite/gcc.target/sparc/array.c new file mode 100644 index 0000000000..e382e22f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/array.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=ultrasparc -mvis" } */ + +long test_array8 (long a, long b) +{ + return __builtin_vis_array8 (a, b); +} + +long test_array16 (long a, long b) +{ + return __builtin_vis_array16 (a, b); +} + +long test_array32 (long a, long b) +{ + return __builtin_vis_array32 (a, b); +} + +/* { dg-final { scan-assembler "array8\t%" } } */ +/* { dg-final { scan-assembler "array16\t%" } } */ +/* { dg-final { scan-assembler "array32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c b/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c new file mode 100644 index 0000000000..7108a018e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */ +typedef long long int64_t; +typedef int vec32 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef unsigned char vec8 __attribute__((vector_size(8))); + +long test_bmask (long x, long y) +{ + return __builtin_vis_bmask (x, y); +} + +vec16 test_bshufv4hi (vec16 x, vec16 y) +{ + return __builtin_vis_bshufflev4hi (x, y); +} + +vec32 test_bshufv2si (vec32 x, vec32 y) +{ + return __builtin_vis_bshufflev2si (x, y); +} + +vec8 test_bshufv8qi (vec8 x, vec8 y) +{ + return __builtin_vis_bshufflev8qi (x, y); +} + +int64_t test_bshufdi (int64_t x, int64_t y) +{ + return __builtin_vis_bshuffledi (x, y); +} + +/* { dg-final { scan-assembler "bmask\t%" } } */ +/* { dg-final { scan-assembler "bshuffle\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c new file mode 100644 index 0000000000..d1be910f5e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/cmask.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ + +void test_cm8 (long x) +{ + __builtin_vis_cmask8 (x); +} + +void test_cm16 (long x) +{ + __builtin_vis_cmask16 (x); +} + +void test_cm32 (long x) +{ + __builtin_vis_cmask32 (x); +} + +/* { dg-final { scan-assembler "cmask8\t%" } } */ +/* { dg-final { scan-assembler "cmask16\t%" } } */ +/* { dg-final { scan-assembler "cmask32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/edge.c b/gcc/testsuite/gcc.target/sparc/edge.c new file mode 100644 index 0000000000..81d8d88563 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/edge.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +long test_edge8 (void *p1, void *p2) +{ + return __builtin_vis_edge8 (p1, p2); +} + +long test_edge8l (void *p1, void *p2) +{ + return __builtin_vis_edge8l (p1, p2); +} + +long test_edge16 (void *p1, void *p2) +{ + return __builtin_vis_edge16 (p1, p2); +} + +long test_edge16l (void *p1, void *p2) +{ + return __builtin_vis_edge16l (p1, p2); +} + +long test_edge32 (void *p1, void *p2) +{ + return __builtin_vis_edge32 (p1, p2); +} + +long test_edge32l (void *p1, void *p2) +{ + return __builtin_vis_edge32l (p1, p2); +} + +/* { dg-final { scan-assembler "edge8\t%" } } */ +/* { dg-final { scan-assembler "edge8l\t%" } } */ +/* { dg-final { scan-assembler "edge16\t%" } } */ +/* { dg-final { scan-assembler "edge16l\t%" } } */ +/* { dg-final { scan-assembler "edge32\t%" } } */ +/* { dg-final { scan-assembler "edge32l\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/edgen.c b/gcc/testsuite/gcc.target/sparc/edgen.c new file mode 100644 index 0000000000..11973b58c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/edgen.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc3 -mvis" } */ + +long test_edge8n (void *p1, void *p2) +{ + return __builtin_vis_edge8n (p1, p2); +} + +long test_edge8ln (void *p1, void *p2) +{ + return __builtin_vis_edge8ln (p1, p2); +} + +long test_edge16n (void *p1, void *p2) +{ + return __builtin_vis_edge16n (p1, p2); +} + +long test_edge16ln (void *p1, void *p2) +{ + return __builtin_vis_edge16ln (p1, p2); +} + +long test_edge32n (void *p1, void *p2) +{ + return __builtin_vis_edge32n (p1, p2); +} + +long test_edge32ln (void *p1, void *p2) +{ + return __builtin_vis_edge32ln (p1, p2); +} + +/* { dg-final { scan-assembler "edge8n\t%" } } */ +/* { dg-final { scan-assembler "edge8ln\t%" } } */ +/* { dg-final { scan-assembler "edge16n\t%" } } */ +/* { dg-final { scan-assembler "edge16ln\t%" } } */ +/* { dg-final { scan-assembler "edge32n\t%" } } */ +/* { dg-final { scan-assembler "edge32ln\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fand.c b/gcc/testsuite/gcc.target/sparc/fand.c index 3194c921cc..b0589bdbb3 100644 --- a/gcc/testsuite/gcc.target/sparc/fand.c +++ b/gcc/testsuite/gcc.target/sparc/fand.c @@ -12,13 +12,10 @@ vec8 fun8(void) return foo1_8 () & foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return a & b; } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return foo1_16 () & foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return a & b; } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,12 +38,9 @@ vec32 fun32(void) return foo1_32 () & foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return a & b; } -#endif -/* { dg-final { scan-assembler-times "fand\t%" 3 } } */ +/* { dg-final { scan-assembler-times "fand\t%" 6 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fandnot.c b/gcc/testsuite/gcc.target/sparc/fandnot.c index 41db849c23..005486385f 100644 --- a/gcc/testsuite/gcc.target/sparc/fandnot.c +++ b/gcc/testsuite/gcc.target/sparc/fandnot.c @@ -12,13 +12,10 @@ vec8 fun8(void) return ~foo1_8 () & foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return ~a & b; } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return ~foo1_16 () & foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return ~a & b; } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,13 +38,10 @@ vec32 fun32(void) return ~foo1_32 () & foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return ~a & b; } -#endif /* This should be transformed into ~b & a. */ @@ -59,38 +50,29 @@ vec8 fun8b(void) return foo1_8 () & ~foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2b(vec8 a, vec8 b) { return a & ~b; } -#endif vec16 fun16b(void) { return foo1_16 () & ~foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2b(vec16 a, vec16 b) { return a & ~b; } -#endif vec32 fun32b(void) { return foo1_32 () & ~foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2b(vec32 a, vec32 b) { return a & ~b; } -#endif -/* { dg-final { scan-assembler-times "fandnot1\t%" 6 } } */ +/* { dg-final { scan-assembler-times "fandnot1\t%" 12 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc/testsuite/gcc.target/sparc/fcmp.c new file mode 100644 index 0000000000..959a674e1e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fcmp.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=ultrasparc -mvis" } */ +typedef int vec32 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); + +long test_fcmple16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmple16 (a, b); +} + +long test_fcmple32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmple32 (a, b); +} + +long test_fcmpne16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpne16 (a, b); +} + +long test_fcmpne32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpne32 (a, b); +} + +long test_fcmpgt16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpgt16 (a, b); +} + +long test_fcmpgt32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpgt32 (a, b); +} + +long test_fcmpeq16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpeq16 (a, b); +} + +long test_fcmpeq32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpeq32 (a, b); +} + +/* { dg-final { scan-assembler "fcmple16\t%" } } */ +/* { dg-final { scan-assembler "fcmple32\t%" } } */ +/* { dg-final { scan-assembler "fcmpne16\t%" } } */ +/* { dg-final { scan-assembler "fcmpne32\t%" } } */ +/* { dg-final { scan-assembler "fcmpgt16\t%" } } */ +/* { dg-final { scan-assembler "fcmpgt32\t%" } } */ +/* { dg-final { scan-assembler "fcmpeq16\t%" } } */ +/* { dg-final { scan-assembler "fcmpeq32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c new file mode 100644 index 0000000000..b8f0745afc --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fhalve.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ + +float test_fhadds (float x, float y) +{ + return __builtin_vis_fhadds (x, y); +} + +double test_fhaddd (double x, double y) +{ + return __builtin_vis_fhaddd (x, y); +} + +float test_fhsubs (float x, float y) +{ + return __builtin_vis_fhsubs (x, y); +} + +double test_fhsubd (double x, double y) +{ + return __builtin_vis_fhsubd (x, y); +} + +float test_fnhadds (float x, float y) +{ + return __builtin_vis_fnhadds (x, y); +} + +double test_fnhaddd (double x, double y) +{ + return __builtin_vis_fnhaddd (x, y); +} + +/* { dg-final { scan-assembler "fhadds\t%" } } */ +/* { dg-final { scan-assembler "fhaddd\t%" } } */ +/* { dg-final { scan-assembler "fhsubs\t%" } } */ +/* { dg-final { scan-assembler "fhsubd\t%" } } */ +/* { dg-final { scan-assembler "fnhadds\t%" } } */ +/* { dg-final { scan-assembler "fnhaddd\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fmaf-1.c b/gcc/testsuite/gcc.target/sparc/fmaf-1.c new file mode 100644 index 0000000000..948b9269e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fmaf-1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfmaf" } */ + +float fmadds (float a, float b, float c) +{ + return a * b + c; +} + +float fmsubs (float a, float b, float c) +{ + return a * b - c; +} + +float fnmadds (float a, float b, float c) +{ + return -(a * b + c); +} + +float fnmsubs (float a, float b, float c) +{ + return -(a * b - c); +} + +double fmaddd (double a, double b, double c) +{ + return a * b + c; +} + +double fmsubd (double a, double b, double c) +{ + return a * b - c; +} + +double fnmaddd (double a, double b, double c) +{ + return -(a * b + c); +} + +double fnmsubd (double a, double b, double c) +{ + return -(a * b - c); +} + +/* { dg-final { scan-assembler "fmadds\t%" } } */ +/* { dg-final { scan-assembler "fmsubs\t%" } } */ +/* { dg-final { scan-assembler "fnmadds\t%" } } */ +/* { dg-final { scan-assembler "fnmsubs\t%" } } */ +/* { dg-final { scan-assembler "fmaddd\t%" } } */ +/* { dg-final { scan-assembler "fmsubd\t%" } } */ +/* { dg-final { scan-assembler "fnmaddd\t%" } } */ +/* { dg-final { scan-assembler "fnmsubd\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c new file mode 100644 index 0000000000..cbdf28f4c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fnegop.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mvis3" } */ + +float test_fnadds(float x, float y) +{ + return -(x + y); +} + +double test_fnaddd(double x, double y) +{ + return -(x + y); +} + +float test_fnmuls(float x, float y) +{ + return -(x * y); +} + +double test_fnmuld(double x, double y) +{ + return -(x * y); +} + +double test_fnsmuld(float x, float y) +{ + return -((double)x * (double)y); +} + +/* { dg-final { scan-assembler "fnadds\t%" } } */ +/* { dg-final { scan-assembler "fnaddd\t%" } } */ +/* { dg-final { scan-assembler "fnmuls\t%" } } */ +/* { dg-final { scan-assembler "fnmuld\t%" } } */ +/* { dg-final { scan-assembler "fnsmuld\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fnot.c b/gcc/testsuite/gcc.target/sparc/fnot.c index dceee52f7d..c0ddc931fb 100644 --- a/gcc/testsuite/gcc.target/sparc/fnot.c +++ b/gcc/testsuite/gcc.target/sparc/fnot.c @@ -12,13 +12,10 @@ vec8 fun8(void) return ~foo1_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a) { foo2_8 (~a); } -#endif extern vec16 foo1_16(void); extern void foo2_16(vec16); @@ -29,13 +26,10 @@ vec16 fun16(void) return ~foo1_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a) { foo2_16 (~a); } -#endif extern vec32 foo1_32(void); extern void foo2_32(vec32); @@ -45,12 +39,9 @@ vec32 fun32(void) return ~foo1_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a) { foo2_32 (~a); } -#endif -/* { dg-final { scan-assembler-times "fnot1\t%" 3 } } */ +/* { dg-final { scan-assembler-times "fnot1\t%" 6 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/for.c b/gcc/testsuite/gcc.target/sparc/for.c index 7348dce203..3da4bc2377 100644 --- a/gcc/testsuite/gcc.target/sparc/for.c +++ b/gcc/testsuite/gcc.target/sparc/for.c @@ -12,13 +12,10 @@ vec8 fun8(void) return foo1_8 () | foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return a | b; } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return foo1_16 () | foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return a | b; } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,12 +38,9 @@ vec32 fun32(void) return foo1_32 () | foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return a | b; } -#endif -/* { dg-final { scan-assembler-times "for\t%" 3 } } */ +/* { dg-final { scan-assembler-times "for\t%" 6 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fornot.c b/gcc/testsuite/gcc.target/sparc/fornot.c index 09fdb4f98f..2daa96e0a0 100644 --- a/gcc/testsuite/gcc.target/sparc/fornot.c +++ b/gcc/testsuite/gcc.target/sparc/fornot.c @@ -12,13 +12,10 @@ vec8 fun8(void) return ~foo1_8 () | foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return ~a | b; } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return ~foo1_16 () | foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return ~a | b; } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,14 +38,10 @@ vec32 fun32(void) return ~foo1_32 () | foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return ~a | b; } -#endif - /* This should be transformed into ~b | a. */ vec8 fun8b(void) @@ -59,38 +49,29 @@ vec8 fun8b(void) return foo1_8 () | ~foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2b(vec8 a, vec8 b) { return a | ~b; } -#endif vec16 fun16b(void) { return foo1_16 () | ~foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2b(vec16 a, vec16 b) { return a | ~b; } -#endif vec32 fun32b(void) { return foo1_32 () | ~foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2b(vec32 a, vec32 b) { return a | ~b; } -#endif -/* { dg-final { scan-assembler-times "fornot1\t%" 6 } } */ +/* { dg-final { scan-assembler-times "fornot1\t%" 12 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c new file mode 100644 index 0000000000..9b1027d5fc --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpadds.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef int __v1si __attribute__((vector_size(4))); +typedef short __v4hi __attribute__((vector_size(8))); +typedef short __v2hi __attribute__((vector_size(4))); + +__v4hi test_fpadds16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpadds16 (x, y); +} + +__v2hi test_fpadds16s (__v2hi x, __v2hi y) +{ + return __builtin_vis_fpadds16s (x, y); +} + +__v4hi test_fpsubs16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpsubs16 (x, y); +} + +__v2hi test_fpsubs16s (__v2hi x, __v2hi y) +{ + return __builtin_vis_fpsubs16s (x, y); +} + +__v2si test_fpadds32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpadds32 (x, y); +} + +__v1si test_fpadds32s (__v1si x, __v1si y) +{ + return __builtin_vis_fpadds32s (x, y); +} + +__v2si test_fpsubs32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpsubs32 (x, y); +} + +__v1si test_fpsubs32s (__v1si x, __v1si y) +{ + return __builtin_vis_fpsubs32s (x, y); +} + +/* { dg-final { scan-assembler "fpadds16\t%" } } */ +/* { dg-final { scan-assembler "fpadds16s\t%" } } */ +/* { dg-final { scan-assembler "fpsubs16\t%" } } */ +/* { dg-final { scan-assembler "fpsubs16s\t%" } } */ +/* { dg-final { scan-assembler "fpadds32\t%" } } */ +/* { dg-final { scan-assembler "fpadds32s\t%" } } */ +/* { dg-final { scan-assembler "fpsubs32\t%" } } */ +/* { dg-final { scan-assembler "fpsubs32s\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpaddsubi.c b/gcc/testsuite/gcc.target/sparc/fpaddsubi.c new file mode 100644 index 0000000000..a36108e70a --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpaddsubi.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef int __v1si __attribute__((vector_size(4))); +typedef short __v4hi __attribute__((vector_size(8))); +typedef short __v2hi __attribute__((vector_size(4))); + +extern __v1si foo_x (void); +extern __v1si foo_y (void); + +__v4hi test_fpadd16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpadd16 (x, y); +} + +__v2hi test_fpadd16s (__v2hi x, __v2hi y) +{ + return __builtin_vis_fpadd16s (x, y); +} + +__v4hi test_fpsub16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpsub16 (x, y); +} + +__v2hi test_fpsub16s (__v2hi x, __v2hi y) +{ + return __builtin_vis_fpsub16s (x, y); +} + +__v2si test_fpadd32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpadd32 (x, y); +} + +__v1si test_fpadd32s (void) +{ + return __builtin_vis_fpadd32s (foo_x (), foo_y ()); +} + +__v2si test_fpsub32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpsub32 (x, y); +} + +__v1si test_fpsub32s (__v1si x, __v1si y) +{ + return __builtin_vis_fpsub32s (foo_x (), foo_y ()); +} + +/* { dg-final { scan-assembler "fpadd16\t%" } } */ +/* { dg-final { scan-assembler "fpadd16s\t%" } } */ +/* { dg-final { scan-assembler "fpsub16\t%" } } */ +/* { dg-final { scan-assembler "fpsub16s\t%" } } */ +/* { dg-final { scan-assembler "fpadd32\t%" } } */ +/* { dg-final { scan-assembler "fpadd32s\t%" } } */ +/* { dg-final { scan-assembler "fpsub32\t%" } } */ +/* { dg-final { scan-assembler "fpsub32s\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c new file mode 100644 index 0000000000..1f032151c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fshift.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef short __v4hi __attribute__((vector_size(8))); + +__v4hi test_fsll16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fsll16 (x, y); +} + +__v4hi test_fslas16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fslas16 (x, y); +} + +__v4hi test_fsrl16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fsrl16 (x, y); +} + +__v4hi test_fsra16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fsra16 (x, y); +} + +__v2si test_fsll32 (__v2si x, __v2si y) +{ + return __builtin_vis_fsll32 (x, y); +} + +__v2si test_fslas32 (__v2si x, __v2si y) +{ + return __builtin_vis_fslas32 (x, y); +} + +__v2si test_fsrl32 (__v2si x, __v2si y) +{ + return __builtin_vis_fsrl32 (x, y); +} + +__v2si test_fsra32 (__v2si x, __v2si y) +{ + return __builtin_vis_fsra32 (x, y); +} + +/* { dg-final { scan-assembler "fsll16\t%" } } */ +/* { dg-final { scan-assembler "fslas16\t%" } } */ +/* { dg-final { scan-assembler "fsrl16\t%" } } */ +/* { dg-final { scan-assembler "fsra16\t%" } } */ +/* { dg-final { scan-assembler "fsll32\t%" } } */ +/* { dg-final { scan-assembler "fslas32\t%" } } */ +/* { dg-final { scan-assembler "fsrl32\t%" } } */ +/* { dg-final { scan-assembler "fsra32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c new file mode 100644 index 0000000000..6e8f1b3418 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fucmp.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +typedef unsigned char vec8 __attribute__((vector_size(8))); + +long test_fucmple8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmple8 (a, b); +} + +long test_fucmpne8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpne8 (a, b); +} + +long test_fucmpgt8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpgt8 (a, b); +} + +long test_fucmpeq8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpeq8 (a, b); +} + +/* { dg-final { scan-assembler "fucmple8\t%" } } */ +/* { dg-final { scan-assembler "fucmpne8\t%" } } */ +/* { dg-final { scan-assembler "fucmpgt8\t%" } } */ +/* { dg-final { scan-assembler "fucmpeq8\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fxnor.c b/gcc/testsuite/gcc.target/sparc/fxnor.c index a685e08e04..e635d65fdc 100644 --- a/gcc/testsuite/gcc.target/sparc/fxnor.c +++ b/gcc/testsuite/gcc.target/sparc/fxnor.c @@ -12,13 +12,10 @@ vec8 fun8(void) return ~(foo1_8 () ^ foo2_8 ()); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return ~(a ^ b); } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return ~(foo1_16 () ^ foo2_16 ()); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return ~(a ^ b); } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,13 +38,10 @@ vec32 fun32(void) return ~(foo1_32 () ^ foo2_32 ()); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return ~(a ^ b); } -#endif /* This should be transformed into ~(b ^ a). */ @@ -59,38 +50,29 @@ vec8 fun8b(void) return foo1_8 () ^ ~foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2b(vec8 a, vec8 b) { return a ^ ~b; } -#endif vec16 fun16b(void) { return foo1_16 () ^ ~foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2b(vec16 a, vec16 b) { return a ^ ~b; } -#endif vec32 fun32b(void) { return foo1_32 () ^ ~foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2b(vec32 a, vec32 b) { return a ^ ~b; } -#endif -/* { dg-final { scan-assembler-times "fxnor\t%" 6 } } */ +/* { dg-final { scan-assembler-times "fxnor\t%" 12 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fxor.c b/gcc/testsuite/gcc.target/sparc/fxor.c index 581b37b54f..6ca2f76a1e 100644 --- a/gcc/testsuite/gcc.target/sparc/fxor.c +++ b/gcc/testsuite/gcc.target/sparc/fxor.c @@ -12,13 +12,10 @@ vec8 fun8(void) return foo1_8 () ^ foo2_8 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec8 fun8_2(vec8 a, vec8 b) { return a ^ b; } -#endif extern vec16 foo1_16(void); extern vec16 foo2_16(void); @@ -28,13 +25,10 @@ vec16 fun16(void) return foo1_16 () ^ foo2_16 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec16 fun16_2(vec16 a, vec16 b) { return a ^ b; } -#endif extern vec32 foo1_32(void); extern vec32 foo2_32(void); @@ -44,12 +38,9 @@ vec32 fun32(void) return foo1_32 () ^ foo2_32 (); } -#ifndef __LP64__ -/* Test the 32-bit splitter. */ vec32 fun32_2(vec32 a, vec32 b) { return a ^ b; } -#endif -/* { dg-final { scan-assembler-times "fxor\t%" 3 } } */ +/* { dg-final { scan-assembler-times "fxor\t%" 6 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c new file mode 100644 index 0000000000..bc2b8522be --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/lzd.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +int test_clz(int a) +{ + return __builtin_clz(a); +} + +long test_clzl(long a) +{ + return __builtin_clzl(a); +} + +long long test_clzll(long long a) +{ + return __builtin_clzll(a); +} + +/* { dg-final { scan-assembler-times "lzd\t%" 3 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/popc.c b/gcc/testsuite/gcc.target/sparc/popc.c new file mode 100644 index 0000000000..5442a610fa --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/popc.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=niagara2" } */ +int test_popcount(int a) +{ + return __builtin_popcount(a); +} + +long test_popcountl(long a) +{ + return __builtin_popcountl(a); +} + +long long test_popcountll(long long a) +{ + return __builtin_popcountll(a); +} + +/* { dg-final { scan-assembler-times "popc\t%" 3 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/rdgsr.c b/gcc/testsuite/gcc.target/sparc/rdgsr.c new file mode 100644 index 0000000000..e67bdaccde --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/rdgsr.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +long get_gsr (void) +{ + return __builtin_vis_read_gsr (); +} + +/* { dg-final { scan-assembler "rd\t%gsr" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/setcc-1.c b/gcc/testsuite/gcc.target/sparc/setcc-1.c new file mode 100644 index 0000000000..6065bbb132 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/setcc-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +int neq (int a, int b) +{ + return a != b; +} + +int eq (int a, int b) +{ + return a == b; +} + +int lt (unsigned int a, unsigned int b) +{ + return a < b; +} + +int leq (unsigned int a, unsigned int b) +{ + return a <= b; +} + +int geq (unsigned int a, unsigned int b) +{ + return a >= b; +} + +int gt (unsigned int a, unsigned int b) +{ + return a > b; +} + +/* { dg-final { scan-assembler-times "xor\t%" 2 } } */ +/* { dg-final { scan-assembler-times "subcc\t%" 2 } } */ +/* { dg-final { scan-assembler-times "addx\t%" 3 } } */ +/* { dg-final { scan-assembler-times "subx\t%" 3 } } */ +/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */ +/* { dg-final { scan-assembler-not "sra\t%" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/sparc/setcc-2.c b/gcc/testsuite/gcc.target/sparc/setcc-2.c new file mode 100644 index 0000000000..cc17c65f0d --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/setcc-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +int neq (int a, int b) +{ + return -(a != b); +} + +int eq (int a, int b) +{ + return -(a == b); +} + +int lt (unsigned int a, unsigned int b) +{ + return -(a < b); +} + +int leq (unsigned int a, unsigned int b) +{ + return -(a <= b); +} + +int geq (unsigned int a, unsigned int b) +{ + return -(a >= b); +} + +int gt (unsigned int a, unsigned int b) +{ + return -(a > b); +} + +/* { dg-final { scan-assembler-times "xor\t%" 2 } } */ +/* { dg-final { scan-assembler-times "subcc\t%" 2 } } */ +/* { dg-final { scan-assembler-times "addx\t%" 3 } } */ +/* { dg-final { scan-assembler-times "subx\t%" 3 } } */ +/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */ +/* { dg-final { scan-assembler-not "sra\t%" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/sparc/setcc-3.c b/gcc/testsuite/gcc.target/sparc/setcc-3.c new file mode 100644 index 0000000000..8a26b675b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/setcc-3.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O1 -mvis3" } */ + +int neq (long a, long b) +{ + return a != b; +} + +int lt (unsigned long a, unsigned long b) +{ + return a < b; +} + +int gt (unsigned long a, unsigned long b) +{ + return a > b; +} + +/* { dg-final { scan-assembler "xor\t%" } } */ +/* { dg-final { scan-assembler "subcc\t%" } } */ +/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */ +/* { dg-final { scan-assembler-times "cmp\t%" 2 } } */ +/* { dg-final { scan-assembler-not "sra\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/sparc-ret.c b/gcc/testsuite/gcc.target/sparc/sparc-ret.c index 11afc10821..f58b059e5a 100644 --- a/gcc/testsuite/gcc.target/sparc/sparc-ret.c +++ b/gcc/testsuite/gcc.target/sparc/sparc-ret.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "no register windows" { *-*-* } { "-mflat" } { "" } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-mcpu=ultrasparc -O" } */ @@ -11,7 +12,7 @@ int bar (int a, int b, int c, int d, int e, int f, int g, int h) toto (&res); return h; } -/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*ld\[ \t\]*\\\[%sp\\+96\\\]" } } } */ +/* { dg-final { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*ld\[ \t\]*\\\[%sp\\+96\\\]" } } */ int bar2 () { @@ -20,4 +21,4 @@ int bar2 () toto (&res); return res; } -/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*nop" } } } */ +/* { dg-final { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*nop" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc/testsuite/gcc.target/sparc/sparc.exp index 9658d08bc9..51c9c16ecb 100644 --- a/gcc/testsuite/gcc.target/sparc/sparc.exp +++ b/gcc/testsuite/gcc.target/sparc/sparc.exp @@ -24,6 +24,17 @@ if ![istarget sparc*-*-*] then { # Load support procs. load_lib gcc-dg.exp +# Return 1 if vis3 instructions can be compiled. +proc check_effective_target_vis3 { } { + return [check_no_compiler_messages vis3 object { + long long + _vis3_fpadd64 (long long __X, long long __Y) + { + return __builtin_vis_fpadd64 (__X, __Y); + } + } "-mcpu=niagara3 -mvis" ] +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp12.c b/gcc/testsuite/gcc.target/sparc/ultrasp12.c new file mode 100644 index 0000000000..6c37f5662f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/ultrasp12.c @@ -0,0 +1,64 @@ +/* PR rtl-optimization/48830 */ +/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */ + +typedef unsigned char uint8_t; +typedef unsigned int uint32_t; +typedef unsigned long int uint64_t; +typedef unsigned long int uintmax_t; +typedef unsigned char rc_vec_t __attribute__((__vector_size__(8))); +typedef short rc_svec_type_ __attribute__((__vector_size__(8))); +typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4))); + +void +rc_stat_xsum_acc(const uint8_t *__restrict src1, int src1_dim, + const uint8_t *__restrict src2, int src2_dim, + int len, int height, uintmax_t sum[5]) +{ + uint32_t s1 = 0; + uint32_t s2 = 0; + uintmax_t s11 = 0; + uintmax_t s22 = 0; + uintmax_t s12 = 0; + int full = len / ((1024) < (1024) ? (1024) : (1024)); + int rem = len % ((1024) < (1024) ? (1024) : (1024)); + int rem1 = rem / 1; + int y; + unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0; + for (y = 0; y < height; y++) { + rc_vec_t a1, a2, a11, a22, a12; + int i1 = (y)*(src1_dim); + int i2 = (y)*(src2_dim); + int x; + ((a1) = ((rc_vec_t) {0})); + ((a2) = ((rc_vec_t) {0})); + ((a11) = ((rc_vec_t) {0})); + ((a22) = ((rc_vec_t) {0})); + ((a12) = ((rc_vec_t) {0})); + for (x = 0; x < full; x++) { + int k; + for (k = 0; k < ((1024) < (1024) ? (1024) : (1024)) / + 1; k++) + { + do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0); + + } + do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0); + } + for (x = 0; x < rem1; x++) { + do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0); + } + do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0); + + do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0); + } + sum[0] = s1; + sum[1] = s2; + sum[2] = s11; + sum[3] = s22; + sum[4] = s12; + ; +} diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp13.c b/gcc/testsuite/gcc.target/sparc/ultrasp13.c new file mode 100644 index 0000000000..2a068546c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/ultrasp13.c @@ -0,0 +1,23 @@ +/* PR rtl-optimization/48840 */ +/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */ + +typedef unsigned char uint8_t; + +typedef unsigned char rc_vec_t __attribute__((__vector_size__(8))); +typedef short rc_svec_type_ __attribute__((__vector_size__(8))); + +typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4))); +typedef short rc_svec2_type_ __attribute__((__vector_size__(4))); + +void +rc_filter_sobel_3x3_horz_u8(uint8_t *__restrict dst, int dst_dim, + const uint8_t *__restrict src, int src_dim, + int width, int height) +{ + do { int tot = (((width) + (8) - 1) / (8)); int len = tot / 3; int rem = tot % 3; int y; unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0; for (y = 0; y < (height); y++) { rc_vec_t v11, v12, v13; rc_vec_t v21, v22, v23; rc_vec_t v31, v32, v33; rc_vec_t s1, s2, s3; int j = y*(dst_dim); int i2 = y*(src_dim) + 8; int i1 = i2 - (src_dim); int i3 = i2 + (src_dim); int x; ((s1) = *(const rc_vec_t*)(&(src)[i1 - 2*8])); ((s2) = *(const rc_vec_t*)(&(src)[i2 - 2*8])); ((s3) = *(const rc_vec_t*)(&(src)[i3 - 2*8])); do { do { rc_vec_t s1_ = (s1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); ((s1) = *(const rc_vec_t*)(&(src)[i1 - 8])); ((s2) = *(const rc_vec_t*)(&(src)[i2 - 8])); ((s3) = *(const rc_vec_t*)(&(src)[i3 - 8])); do { do { rc_vec_t s1_ = (s1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v22) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); } while (0); ((v13) = ((rc_vec_t) {0})); ((v23) = ((rc_vec_t) {0})); ((v33) = ((rc_vec_t) {0})); (void)v21, (void)v22; (void)v31, (void)v32; for (x = 0; x < len; x++) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v23) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v12); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v11, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v23); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v22, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v13); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v12, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v21); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v23, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v22) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v11); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v13, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v22); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v21, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } if (rem > 0) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v23) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v12); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v11, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v23); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v22, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } if (rem > 1) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v13); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v12, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v21); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v23, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } } ; } while (0); + +} diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c new file mode 100644 index 0000000000..4202bfa6e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_hw } */ +/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */ + +#include "vec-init-1.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c new file mode 100644 index 0000000000..a5c2132393 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis2_hw } */ +/* { dg-options "-mcpu=ultrasparc3 -O2" } */ + +#include "vec-init-1.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c new file mode 100644 index 0000000000..ab916e052c --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis3_hw } */ +/* { dg-options "-mcpu=niagara3 -O2" } */ + +#include "vec-init-1.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-1.inc b/gcc/testsuite/gcc.target/sparc/vec-init-1.inc new file mode 100644 index 0000000000..e27bb6e293 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-1.inc @@ -0,0 +1,85 @@ +typedef int __v1si __attribute__ ((__vector_size__ (4))); +typedef int __v2si __attribute__ ((__vector_size__ (8))); +typedef short __v2hi __attribute__ ((__vector_size__ (4))); +typedef short __v4hi __attribute__ ((__vector_size__ (8))); +typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4))); +typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8))); + +extern void abort (void); + +static void +compare64 (void *p, unsigned long long val) +{ + if (*(unsigned long long *)p != val) + abort(); +} + +static void +compare32 (void *p, unsigned int val) +{ + if (*(unsigned int *)p != val) + abort(); +} + +static void +test_v8qi (unsigned char x) +{ + __v8qi v = { x, x, x, x, x, x, x, x }; + + compare64(&v, 0x4444444444444444ULL); +} + +static void +test_v4qi (unsigned char x) +{ + __v4qi v = { x, x, x, x }; + + compare32(&v, 0x44444444); +} + +static void +test_v4hi (unsigned short x) +{ + __v4hi v = { x, x, x, x, }; + + compare64(&v, 0x3344334433443344ULL); +} + +static void +test_v2hi (unsigned short x) +{ + __v2hi v = { x, x, }; + + compare32(&v, 0x33443344); +} + +static void +test_v2si (unsigned int x) +{ + __v2si v = { x, x, }; + + compare64(&v, 0x1122334411223344ULL); +} + +static void +test_v1si (unsigned int x) +{ + __v1si v = { x }; + + compare32(&v, 0x11223344); +} + +unsigned char x8 = 0x44; +unsigned short x16 = 0x3344; +unsigned int x32 = 0x11223344; + +int main(void) +{ + test_v8qi (x8); + test_v4qi (x8); + test_v4hi (x16); + test_v2hi (x16); + test_v2si (x32); + test_v1si (x32); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c new file mode 100644 index 0000000000..efa08fa248 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_hw } */ +/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */ + +#include "vec-init-2.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c new file mode 100644 index 0000000000..3aa0f51595 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis2_hw } */ +/* { dg-options "-mcpu=ultrasparc3 -O2" } */ + +#include "vec-init-2.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c new file mode 100644 index 0000000000..5f0c65860b --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis3_hw } */ +/* { dg-options "-mcpu=niagara3 -O2" } */ + +#include "vec-init-2.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-2.inc b/gcc/testsuite/gcc.target/sparc/vec-init-2.inc new file mode 100644 index 0000000000..13685a1006 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-2.inc @@ -0,0 +1,94 @@ +typedef short __v2hi __attribute__ ((__vector_size__ (4))); +typedef short __v4hi __attribute__ ((__vector_size__ (8))); + +extern void abort (void); + +static void +compare64 (int n, void *p, unsigned long long val) +{ + unsigned long long *x = (unsigned long long *) p; + + if (*x != val) + abort(); +} + +static void +compare32 (int n, void *p, unsigned int val) +{ + unsigned int *x = (unsigned int *) p; + if (*x != val) + abort(); +} + +#define V2HI_TEST(N, elt0, elt1) \ +static void \ +test_v2hi_##N (unsigned short x, unsigned short y) \ +{ \ + __v2hi v = { (elt0), (elt1) }; \ + compare32(N, &v, ((int)(elt0) << 16) | (elt1)); \ +} + +V2HI_TEST(1, x, y) +V2HI_TEST(2, y, x) +V2HI_TEST(3, x, x) +V2HI_TEST(4, x, 0) +V2HI_TEST(5, 0, x) +V2HI_TEST(6, y, 1) +V2HI_TEST(7, 1, y) +V2HI_TEST(8, 2, 3) +V2HI_TEST(9, 0x400, x) +V2HI_TEST(10, y, 0x8000) + +#define V4HI_TEST(N, elt0, elt1, elt2, elt3) \ +static void \ +test_v4hi_##N (unsigned short a, unsigned short b, unsigned short c, unsigned short d) \ +{ \ + __v4hi v = { (elt0), (elt1), (elt2), (elt3) }; \ + compare64(N, &v, \ + ((long long)(elt0) << 48) | \ + ((long long)(elt1) << 32) | \ + ((long long)(elt2) << 16) | \ + ((long long)(elt3))); \ +} + +V4HI_TEST(1, a, a, a, a) +V4HI_TEST(2, a, b, c, d) +V4HI_TEST(3, a, a, b, b) +V4HI_TEST(4, d, c, b, a) +V4HI_TEST(5, a, 0, 0, 0) +V4HI_TEST(6, a, 0, b, 0) +V4HI_TEST(7, c, 5, 5, 5) +V4HI_TEST(8, d, 6, a, 6) +V4HI_TEST(9, 0x200, 0x300, 0x500, 0x8800) +V4HI_TEST(10, 0x600, a, a, a) + +unsigned short a16 = 0x3344; +unsigned short b16 = 0x5566; +unsigned short c16 = 0x7788; +unsigned short d16 = 0x9911; + +int main(void) +{ + test_v2hi_1 (a16, b16); + test_v2hi_2 (a16, b16); + test_v2hi_3 (a16, b16); + test_v2hi_4 (a16, b16); + test_v2hi_5 (a16, b16); + test_v2hi_6 (a16, b16); + test_v2hi_7 (a16, b16); + test_v2hi_8 (a16, b16); + test_v2hi_9 (a16, b16); + test_v2hi_10 (a16, b16); + + test_v4hi_1 (a16, b16, c16, d16); + test_v4hi_2 (a16, b16, c16, d16); + test_v4hi_3 (a16, b16, c16, d16); + test_v4hi_4 (a16, b16, c16, d16); + test_v4hi_5 (a16, b16, c16, d16); + test_v4hi_6 (a16, b16, c16, d16); + test_v4hi_7 (a16, b16, c16, d16); + test_v4hi_8 (a16, b16, c16, d16); + test_v4hi_9 (a16, b16, c16, d16); + test_v4hi_10 (a16, b16, c16, d16); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c new file mode 100644 index 0000000000..6c826108c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_hw } */ +/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */ + +#include "vec-init-3.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c new file mode 100644 index 0000000000..6424e2f159 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis2_hw } */ +/* { dg-options "-mcpu=ultrasparc3 -O2" } */ + +#include "vec-init-3.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c new file mode 100644 index 0000000000..226c108c5e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ultrasparc_vis3_hw } */ +/* { dg-options "-mcpu=niagara3 -O2" } */ + +#include "vec-init-3.inc" diff --git a/gcc/testsuite/gcc.target/sparc/vec-init-3.inc b/gcc/testsuite/gcc.target/sparc/vec-init-3.inc new file mode 100644 index 0000000000..8a3db2600a --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vec-init-3.inc @@ -0,0 +1,105 @@ +typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4))); +typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8))); + +extern void abort (void); + +static void +compare64 (int n, void *p, unsigned long long val) +{ + unsigned long long *x = (unsigned long long *) p; + + if (*x != val) + abort(); +} + +static void +compare32 (int n, void *p, unsigned int val) +{ + unsigned int *x = (unsigned int *) p; + if (*x != val) + abort(); +} + +#define V4QI_TEST(N, elt0, elt1, elt2, elt3) \ +static void \ +test_v4qi_##N (unsigned char a, unsigned char b, unsigned char c, unsigned char d) \ +{ \ + __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \ + compare32(N, &v, ((int)(elt0) << 24) | \ + ((int)(elt1) << 16) | \ + ((int)(elt2) << 8) | ((int)(elt3))); \ +} + +V4QI_TEST(1, a, a, a, a) +V4QI_TEST(2, b, b, b, b) +V4QI_TEST(3, a, b, c, d) +V4QI_TEST(4, d, c, b, a) +V4QI_TEST(5, a, 0, 0, 0) +V4QI_TEST(6, b, 1, 1, b) +V4QI_TEST(7, c, 5, d, 5) +V4QI_TEST(8, 0x20, 0x30, b, a) +V4QI_TEST(9, 0x40, 0x50, 0x60, 0x70) +V4QI_TEST(10, 0x40, 0x50, 0x60, c) + +#define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \ +static void \ +test_v8qi_##N (unsigned char a, unsigned char b, unsigned char c, unsigned char d, \ + unsigned char e, unsigned char f, unsigned char g, unsigned char h) \ +{ \ + __v8qi v = { (elt0), (elt1), (elt2), (elt3), \ + (elt4), (elt5), (elt6), (elt7) }; \ + compare64(N, &v, ((long long)(elt0) << 56) | \ + ((long long)(elt1) << 48) | \ + ((long long)(elt2) << 40) | \ + ((long long)(elt3) << 32) | \ + ((long long)(elt4) << 24) | \ + ((long long)(elt5) << 16) | \ + ((long long)(elt6) << 8) | \ + ((long long)(elt7) << 0)); \ +} + +V8QI_TEST(1, a, a, a, a, a, a, a, a) +V8QI_TEST(2, a, b, c, d, e, f, g, h) +V8QI_TEST(3, h, g, f, e, d, c, b, a) +V8QI_TEST(4, a, b, a, b, a, b, a, b) +V8QI_TEST(5, c, b, c, b, c, b, c, a) +V8QI_TEST(6, a, 0, 0, 0, 0, 0, 0, 0) +V8QI_TEST(7, b, 1, b, 1, b, 1, b, 1) +V8QI_TEST(8, c, d, 0x20, a, 0x21, b, 0x23, c) +V8QI_TEST(9, 1, 2, 3, 4, 5, 6, 7, 8) +V8QI_TEST(10, a, a, b, b, c, c, d, d) + +unsigned char a8 = 0x33; +unsigned char b8 = 0x55; +unsigned char c8 = 0x77; +unsigned char d8 = 0x99; +unsigned char e8 = 0x11; +unsigned char f8 = 0x22; +unsigned char g8 = 0x44; +unsigned char h8 = 0x66; + +int main(void) +{ + test_v4qi_1 (a8, b8, c8, d8); + test_v4qi_2 (a8, b8, c8, d8); + test_v4qi_3 (a8, b8, c8, d8); + test_v4qi_4 (a8, b8, c8, d8); + test_v4qi_5 (a8, b8, c8, d8); + test_v4qi_6 (a8, b8, c8, d8); + test_v4qi_7 (a8, b8, c8, d8); + test_v4qi_8 (a8, b8, c8, d8); + test_v4qi_9 (a8, b8, c8, d8); + test_v4qi_10 (a8, b8, c8, d8); + + test_v8qi_1 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_2 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_3 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_4 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_5 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_6 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_7 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_8 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_9 (a8, b8, c8, d8, e8, f8, g8, h8); + test_v8qi_10 (a8, b8, c8, d8, e8, f8, g8, h8); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c new file mode 100644 index 0000000000..7286d705dd --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef short __v4hi __attribute__((vector_size(8))); +typedef unsigned char __v8qi __attribute__((vector_size(8))); +typedef long long int64_t; + +__v4hi test_fchksm16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fchksm16 (x, y); +} + +long test_pdistn (__v8qi x, __v8qi y) +{ + return __builtin_vis_pdistn (x, y); +} + +__v4hi test_fmean16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fmean16 (x, y); +} + +int64_t test_fpadd64 (int64_t x, int64_t y) +{ + return __builtin_vis_fpadd64 (x, y); +} + +int64_t test_fpsub64 (int64_t x, int64_t y) +{ + return __builtin_vis_fpsub64 (x, y); +} + +/* { dg-final { scan-assembler "fchksm16\t%" } } */ +/* { dg-final { scan-assembler "pdistn\t%" } } */ +/* { dg-final { scan-assembler "fmean16\t%" } } */ +/* { dg-final { scan-assembler "fpadd64\t%" } } */ +/* { dg-final { scan-assembler "fpsub64\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/vis3move-1.c b/gcc/testsuite/gcc.target/sparc/vis3move-1.c new file mode 100644 index 0000000000..1265d88668 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis3move-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O1 -mvis3" } */ + +double d; +float f; + +int test_convert_from_float(void) +{ + return f; +} + +int test_convert_from_double(void) +{ + return d; +} + +float test_convert_to_float(int x) +{ + return x; +} + +double test_convert_to_double(int x) +{ + return x; +} + +/* { dg-final { scan-assembler-times "movstouw\t%" 2 } } */ +/* { dg-final { scan-assembler-times "movwtos\t%" 2 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/vis3move-2.c b/gcc/testsuite/gcc.target/sparc/vis3move-2.c new file mode 100644 index 0000000000..de79307651 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis3move-2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O1 -mvis3" } */ + +double d; +float f; + +long test_convert_from_float(void) +{ + return f; +} + +long test_convert_from_double(void) +{ + return d; +} + +float test_convert_to_float(long x) +{ + return x; +} + +double test_convert_to_double(long x) +{ + return x; +} + +/* { dg-final { scan-assembler-times "movdtox\t%" 2 } } */ +/* { dg-final { scan-assembler-times "movxtod\t%" 2 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/vis3move-3.c b/gcc/testsuite/gcc.target/sparc/vis3move-3.c new file mode 100644 index 0000000000..3b2116eec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis3move-3.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O1 -mvis3" } */ + +float fnegs (float a) +{ + return -a; +} + +double fnegd (double a) +{ + return -a; +} + +float fmuls (float a, float b) +{ + return a * b; +} + +double fmuld (double a, double b) +{ + return a * b; +} + +double fsmuld (float a, float b) +{ + return (double)a * (double)b; +} + +double fnsmuld (float a, float b) +{ + return -((double)a * (double)b); +} + +/* { dg-final { scan-assembler-times "movwtos\t%" 13 } } */ +/* { dg-final { scan-assembler "fnegs\t%" } } */ +/* { dg-final { scan-assembler "fnegd\t%" } } */ +/* { dg-final { scan-assembler "fmuls\t%" } } */ +/* { dg-final { scan-assembler "fmuld\t%" } } */ +/* { dg-final { scan-assembler "fsmuld\t%" } } */ +/* { dg-final { scan-assembler "fnsmuld\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/wrgsr.c b/gcc/testsuite/gcc.target/sparc/wrgsr.c new file mode 100644 index 0000000000..6cfa0603a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/wrgsr.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +void set_gsr (void) +{ + __builtin_vis_write_gsr (2 << 3); +} + +void set_gsr2 (long x) +{ + __builtin_vis_write_gsr (x); +} + +/* { dg-final { scan-assembler "wr\t%g0, 16, %gsr" } } */ +/* { dg-final { scan-assembler "wr\t%g0, %" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c new file mode 100644 index 0000000000..a432ee1fec --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/xmul.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ +typedef long long int64_t; + +int64_t test_umulxhi (int64_t x, int64_t y) +{ + return __builtin_vis_umulxhi (x, y); +} + +int64_t test_xmulx (int64_t x, int64_t y) +{ + return __builtin_vis_xmulx (x, y); +} + +int64_t test_xmulxhi (int64_t x, int64_t y) +{ + return __builtin_vis_xmulxhi (x, y); +} + +/* { dg-final { scan-assembler "umulxhi\t%" } } */ +/* { dg-final { scan-assembler "xmulx\t%" } } */ +/* { dg-final { scan-assembler "xmulxhi\t%" } } */ diff --git a/gcc/testsuite/gcc.target/tic6x/abi-align-1.c b/gcc/testsuite/gcc.target/tic6x/abi-align-1.c new file mode 100644 index 0000000000..963c2f6825 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/abi-align-1.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ + +/* common */ +char c; +/* arrays must be 8 byte aligned, regardless of size */ +char c_ary[1]; + +/* data */ +char d = 1; +char d_ary[1] = {1}; + +int main () +{ + if (((unsigned long)&c_ary[0] & 7) != 0) + return 1; + if (((unsigned long)&d_ary[0] & 7) != 0) + return 1; + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/bswapl.c b/gcc/testsuite/gcc.target/tic6x/bswapl.c new file mode 100644 index 0000000000..18d6bce7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/bswapl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=c64x+" } */ +/* { dg-final { scan-assembler-not "call" } } */ + +int foo (int x) +{ + return __builtin_bswap32 (x); +} + +long long bar (long long x) +{ + return __builtin_bswap64 (x); +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c b/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c new file mode 100644 index 0000000000..a7deea3e22 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c @@ -0,0 +1,94 @@ +/* Copyright (C) 2009 Free Software Foundation. + + Verify that folding of complex mul and div work correctly. + TI C6X specific version, reduced by two tests that fails due to the + use of implicit -freciprocal-math. + + Origin: Kaveh R. Ghazi, August 13, 2009. */ + +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-add-options ieee } */ + +extern void link_error(int); + +/* Evaluate this expression at compile-time. */ +#define COMPILETIME_TESTIT(TYPE,X,OP,Y,RES) do { \ + if ((_Complex TYPE)(X) OP (_Complex TYPE)(Y) != (_Complex TYPE)(RES)) \ + link_error(__LINE__); \ +} while (0) + +/* Use this error function for cases which only evaluate at + compile-time when optimizing. */ +#ifdef __OPTIMIZE__ +# define ERROR_FUNC(X) link_error(X) +#else +# define ERROR_FUNC(X) __builtin_abort() +#endif + +/* Evaluate this expression at compile-time using static initializers. */ +#define STATICINIT_TESTIT(TYPE,X,OP,Y,RES) do { \ + static const _Complex TYPE foo = (_Complex TYPE)(X) OP (_Complex TYPE)(Y); \ + if (foo != (_Complex TYPE)(RES)) \ + ERROR_FUNC (__LINE__); \ +} while (0) + +/* Evaluate this expression at runtime. */ +#define RUNTIME_TESTIT(TYPE,X,OP,Y,RES) do { \ + volatile _Complex TYPE foo; \ + foo = (_Complex TYPE)(X); \ + foo OP##= (_Complex TYPE)(Y); \ + if (foo != (_Complex TYPE)(RES)) \ + __builtin_abort(); \ +} while (0) + +/* Evaluate this expression at compile-time and runtime. */ +#define TESTIT(TYPE,X,OP,Y,RES) do { \ + STATICINIT_TESTIT(TYPE,X,OP,Y,RES); \ + COMPILETIME_TESTIT(TYPE,X,OP,Y,RES); \ + RUNTIME_TESTIT(TYPE,X,OP,Y,RES); \ +} while (0) + +/* Either the real or imaginary parts should be infinity. */ +#define TEST_ONE_PART_INF(VAL) do { \ + static const _Complex double foo = (VAL); \ + if (! __builtin_isinf(__real foo) && ! __builtin_isinf(__imag foo)) \ + ERROR_FUNC (__LINE__); \ + if (! __builtin_isinf(__real (VAL)) && ! __builtin_isinf(__imag (VAL))) \ + __builtin_abort(); \ +} while (0) + +int main() +{ + /* Test some regular finite values. */ + TESTIT (double, 3.+4.i, *, 2, 6+8i); + TESTIT (double, 3.+4.i, /, 2, 1.5+2i); + TESTIT (int, 3+4i, *, 2, 6+8i); + TESTIT (int, 3+4i, /, 2, 1+2i); + + TESTIT (double, 3.+4.i, *, 2+5i, -14+23i); + TESTIT (int, 3+4i, *, 2+5i, -14+23i); + TESTIT (int, 30+40i, /, 5i, 8-6i); + TESTIT (int, 14+6i, /, 7+3i, 2); + TESTIT (int, 8+24i, /, 4+12i, 2); + + /* Test for accuracy. */ + COMPILETIME_TESTIT (double, + (1 + __DBL_EPSILON__ + 1i), + *, + (1 - __DBL_EPSILON__ + 1i), + -4.93038065763132378382330353301741393545754021943139377981e-32+2i); + + /* This becomes (NaN + iInf). */ +#define VAL1 ((_Complex double)__builtin_inf() * 1i) + + /* Test some C99 Annex G special cases. */ + TEST_ONE_PART_INF ((VAL1) * (VAL1)); + TEST_ONE_PART_INF ((_Complex double)1 / (_Complex double)0); + TEST_ONE_PART_INF ((VAL1) / (_Complex double)1); + + RUNTIME_TESTIT (double, 1, /, VAL1, 0); + STATICINIT_TESTIT (double, 1, /, VAL1, 0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c b/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c new file mode 100644 index 0000000000..5e52284463 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c @@ -0,0 +1,83 @@ +/* { dg-require-effective-target ti_c64xp } */ + +#include <c6x_intrinsics.h> + +extern void abort (void); + +typedef short __v2hi __attribute ((vector_size(4))); + +int a = 0x5000d000; +int b = 0xc0002000; +int c = 0x40009000; +int d = 0x80000001; +int e = 0x50002001; +int f = 0xc0008000; + +int a4 = 0x50d03080; +int b4 = 0xc020f080; +int c4 = 0xc0202080; +int d4 = 0x50003080; +int e4 = 0xc0202180; + +int main () +{ + int v; + long long vll; + + v = _add2 (a, b); + if (v != 0x1000f000) + abort (); + v = _sub2 (a, b); + if (v != 0x9000b000) + abort (); + v = _sub2 (b, a); + if (v != 0x70005000) + abort (); + + v = _add4 (a4, b4); + if (v != 0x10f02000) + abort (); + v = _sub4 (a4, b4); + if (v != 0x90b04000) + abort (); + v = _saddu4 (a4, c4); + if (v != 0xfff050ff) + abort (); + + v = _sadd2 (a, b); + if (v != 0x1000f000) + abort (); + v = _sadd2 (a, c); + if (v != 0x7fff8000) + abort (); + + v = _ssub2 (a, b); + if (v != 0x7fffb000) + abort (); + v = _ssub2 (b, a); + if (v != 0x80005000) + abort (); + + vll = _smpy2ll (a, b); + if (vll != 0xd8000000f4000000ll) + abort (); + vll = _smpy2ll (d, d); + if (vll != 0x7fffffff00000002ll) + abort (); + + v = _avg2 (b, e); + if (v != 0x08002001) + abort (); + v = _avgu4 (d4, e4); + if (v != 0x88102980) + abort (); + + v = _abs2 (a); + if (v != 0x50003000) + abort (); + v = _abs2 (f); + if (v != 0x40007fff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp b/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp new file mode 100644 index 0000000000..3a7f0896e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp @@ -0,0 +1,29 @@ +# Copyright (C) 2009 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `c-torture.exp' driver, looping over +# optimization options. + +load_lib gcc-dg.exp + +if { ![istarget tic6x-*-*] } then { + return +} + +dg-init +gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] "" +dg-finish + diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c b/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c new file mode 100644 index 0000000000..e8e2139ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c @@ -0,0 +1,36 @@ +#include <c6x_intrinsics.h> + +extern void abort (void); + +#define N 4 + +int vals[N] = { 0, 0xffffffff, 0x89abcdef, 0xdeadbeef }; + +int main () +{ + int i; + for (i = 0; i < N; i++) + { + int shf1, shf2; + int v = vals[i]; + unsigned int uv = v; + + for (shf1 = 0; shf1 < 32; shf1++) + for (shf2 = 0; shf2 < 32; shf2++) + { + int r = (shf1 << 5) | shf2; + if (shf2 > shf1) + { + unsigned int mask = (1u << (shf2 - shf1) << 1) - 1; + mask <<= shf1; + if (_clrr (v, r) != (v & ~mask)) + abort (); + } + if (_extr (v, r) != v << shf1 >> shf2) + abort (); + if (_extru (v, r) != uv << shf1 >> shf2) + abort (); + } + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c b/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c new file mode 100644 index 0000000000..4ea3570037 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c @@ -0,0 +1,47 @@ +#include <c6x_intrinsics.h> + +extern void abort (void); + +int a1 = 0x50000000; +int b1 = 0xc0000000; +int c1 = 0x40000000; +int a2 = 0xd0000000; +int b2 = 0x20000000; +int c2 = 0x90000000; +int d = 0x80000000; + +int main () +{ + if (_sadd (a1, b1) != 0x10000000) + abort (); + if (_sadd (a2, b2) != 0xf0000000) + abort (); + if (_sadd (a1, c1) != 0x7fffffff) + abort (); + if (_sadd (a2, c2) != 0x80000000) + abort (); + + if (_ssub (a1, b1) != 0x7fffffff) + abort (); + if (_ssub (a2, b2) != 0xb0000000) + abort (); + if (_ssub (b1, a1) != 0x80000000) + abort (); + if (_ssub (b2, a2) != 0x50000000) + abort (); + + if (_abs (a1) != 0x50000000) + abort (); + if (_abs (b1) != 0x40000000) + abort (); + if (_abs (d) != 0x7fffffff) + abort (); + + if (_sshl (a1, 1) != 0x7fffffff + || _sshl (b2, 1) != 0x40000000 + || _sshl (a2, 1) != 0xa0000000 + || _sshl (a2, 4) != 0x80000000) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c b/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c new file mode 100644 index 0000000000..15a993045c --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c @@ -0,0 +1,20 @@ +#include <c6x_intrinsics.h> + +extern void abort (void); + +int a1 = 0x5000; +int b1 = 0xc000; +int a2 = 0xd000; +int b2 = 0x2000; +int c = 0x8000; +int main () +{ + if (_smpy (a1, b1) != 0xd8000000) + abort (); + if (_smpy (a2, b2) != 0xf4000000) + abort (); + if (_smpy (c, c) != 0x7fffffff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c b/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c new file mode 100644 index 0000000000..c8864da625 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c @@ -0,0 +1,19 @@ +#include <c6x_intrinsics.h> +extern void abort (void); + +int a1 = 0x50000000; +int b1 = 0xc0000000; +int a2 = 0xd0000000; +int b2 = 0x20000000; +int c = 0x80000000; +int main () +{ + if (_smpyh (a1, b1) != 0xd8000000) + abort (); + if (_smpyh (a2, b2) != 0xf4000000) + abort (); + if (_smpyh (c, c) != 0x7fffffff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c b/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c new file mode 100644 index 0000000000..92a50433e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c @@ -0,0 +1,26 @@ +#include <c6x_intrinsics.h> + +extern void abort (void); + +int a1 = 0x5000; +int b1 = 0xc0000000; +int a2 = 0xd000; +int b2 = 0x20000000; +int c = 0x8000; +int main () +{ + if (_smpylh (a1, b1) != 0xd8000000) + abort (); + if (_smpylh (a2, b2) != 0xf4000000) + abort (); + if (_smpylh (c, 0x80000000) != 0x7fffffff) + abort (); + if (_smpyhl (b1, a1) != 0xd8000000) + abort (); + if (_smpyhl (b2, a2) != 0xf4000000) + abort (); + if (_smpyhl (0x80000000, c) != 0x7fffffff) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/tic6x/cold-lc.c b/gcc/testsuite/gcc.target/tic6x/cold-lc.c new file mode 100644 index 0000000000..6793f360de --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/cold-lc.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-calls" } */ + +extern void dump_stack (void) __attribute__ ((__cold__)); +struct thread_info { + struct task_struct *task; +}; +extern struct thread_info *current_thread_info (void); + +void dump_stack (void) +{ + unsigned long stack; + show_stack ((current_thread_info ()->task), &stack); +} + +void die (char *str, void *fp, int nr) +{ + dump_stack (); + while (1); +} + diff --git a/gcc/testsuite/gcc.target/tic6x/ffsdi.c b/gcc/testsuite/gcc.target/tic6x/ffsdi.c new file mode 100644 index 0000000000..6f61be5ae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/ffsdi.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c64xp } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "call" } } */ + +long long foo (long long x) +{ + return __builtin_ffsll (x); +} + +long long bar (long long x) +{ + return __builtin_clzll (x); +} + +long long baz (long long x) +{ + return __builtin_ctzll (x); +} diff --git a/gcc/testsuite/gcc.target/tic6x/ffssi.c b/gcc/testsuite/gcc.target/tic6x/ffssi.c new file mode 100644 index 0000000000..bb83512937 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/ffssi.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=c64x+" } */ +/* { dg-final { scan-assembler-not "call" } } */ + +int foo (int x) +{ + return __builtin_ffsl (x); +} + +int bar (int x) +{ + return __builtin_clzl (x); +} + +int baz (int x) +{ + return __builtin_ctzl (x); +} diff --git a/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c b/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c new file mode 100644 index 0000000000..d7f30165cc --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c67x } */ +/* { dg-options "-O2 -ffinite-math-only" } */ +/* { dg-final { scan-assembler-not "cmpeq" } } */ + +double gedf (double x, double y) +{ + return x >= y; +} + +double ledf (double x, double y) +{ + return x <= y; +} + +float gesf (float x, float y) +{ + return x >= y; +} + +float lesf (float x, float y) +{ + return x <= y; +} diff --git a/gcc/testsuite/gcc.target/tic6x/fpcmp.c b/gcc/testsuite/gcc.target/tic6x/fpcmp.c new file mode 100644 index 0000000000..25eaff4109 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/fpcmp.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c67x } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "cmpeq.p" 4 } } */ + +double gedf (double x, double y) +{ + return x >= y; +} + +double ledf (double x, double y) +{ + return x <= y; +} + +float gesf (float x, float y) +{ + return x >= y; +} + +float lesf (float x, float y) +{ + return x <= y; +} diff --git a/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c b/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c new file mode 100644 index 0000000000..b138865a2a --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c67x } */ +/* { dg-options "-O2 -fno-reciprocal-math" } */ +/* { dg-final { scan-assembler-not "rcpdp" } } */ +/* { dg-final { scan-assembler-not "rcpsp" } } */ + +double f (double x, double y) +{ + return x / y; +} + +float g (float x, float y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/tic6x/fpdiv.c b/gcc/testsuite/gcc.target/tic6x/fpdiv.c new file mode 100644 index 0000000000..e547fb4571 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/fpdiv.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c67x } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "rcpdp" } } */ +/* { dg-final { scan-assembler "rcpsp" } } */ + +double f (double x, double y) +{ + return x / y; +} + +float g (float x, float y) +{ + return x / y; +} diff --git a/gcc/testsuite/gcc.target/tic6x/longcalls.c b/gcc/testsuite/gcc.target/tic6x/longcalls.c new file mode 100644 index 0000000000..273433ceed --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/longcalls.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-calls" } */ +/* { dg-final { scan-assembler-times "\\tcall\[p\]*\[\\t ]*.s" 3 } } */ +/* { dg-final { scan-assembler "call\[p\]*\[\\t ]*.s.\[\\t ]*.f" } } */ +/* { dg-final { scan-assembler-not "call\[p\]*\[\\t ]*.s.\[\\t ]*.g" } } */ +/* { dg-final { scan-assembler-not "call\[p\]*\[\\t ]*.s.\[\\t ]*.h" } } */ + +int x; + +static __attribute__ ((noinline)) void f () +{ + x = 5; +} + +extern void g (); + +static __attribute__ ((noinline)) __attribute__((section(".init.text"))) void h () +{ + x = 5; +} + +int bar () +{ + f (); + g (); + h (); +} diff --git a/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c b/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c new file mode 100644 index 0000000000..4d7816c153 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ti_c64xp } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "dpackx" } } */ + +#include <stdlib.h> + +unsigned long long z = 0x012389ab4567cdefull; + +int main () +{ + unsigned long long z2 = (z << 48) | (z >> 16); + if (z2 != 0xcdef012389ab4567ull) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/tic6x/rotdi16.c b/gcc/testsuite/gcc.target/tic6x/rotdi16.c new file mode 100644 index 0000000000..33b052ad43 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/rotdi16.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include <stdlib.h> + +unsigned long long z = 0x012389ab4567cdefull; + +int main () +{ + unsigned long long z2 = (z << 48) | (z >> 16); + if (z2 != 0xcdef012389ab4567ull) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/tic6x/tic6x.exp b/gcc/testsuite/gcc.target/tic6x/tic6x.exp new file mode 100644 index 0000000000..f9d1c7a162 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/tic6x.exp @@ -0,0 +1,62 @@ +# Copyright (C) 2010 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +if ![istarget tic6x-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Like dg-options, but treats certain C6X-specific options specially: +# +# -march=* +# Select the target architecture. Skip the test if the multilib +# flags force a different arch. +proc dg-c6x-options {args} { + upvar dg-extra-tool-flags extra_tool_flags + upvar dg-do-what do_what + + set multilib_arch "" + set arch "" + + foreach flag [target_info multilib_flags] { + regexp "^-march=(.*)" $flag dummy multilib_arch + } + + set flags [lindex $args 1] + + foreach flag $flags { + regexp "^-march=(.*)" $flag dummy arch + } + + if {$multilib_arch == "" || $multilib_cpu == $arch} { + set extra_tool_flags $flags + } else { + set do_what [list [lindex $do_what 0] "N" "P"] + } +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/tic6x/weak-call.c b/gcc/testsuite/gcc.target/tic6x/weak-call.c new file mode 100644 index 0000000000..9be9304800 --- /dev/null +++ b/gcc/testsuite/gcc.target/tic6x/weak-call.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "call\[\\t ]*.s.\[\\t ]*.f" } } */ +/* { dg-final { scan-assembler-not "call\[\\t ]*.s.\[\\t ]*.g" } } */ + +extern void f () __attribute__ ((weak)); +extern void g () __attribute__ ((weak)) __attribute__ ((noinline)); + +void g () +{ +} + +int main () +{ + f (); + g (); +} |