diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/s390')
69 files changed, 1689 insertions, 53 deletions
diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-1.c b/gcc/testsuite/gcc.target/s390/hotpatch-1.c index b14fa9010a..55088b8b65 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-1.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-1.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-10.c b/gcc/testsuite/gcc.target/s390/hotpatch-10.c index a990c4cad6..d2cb9a2ee8 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-10.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-10.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,0" } */ +/* { dg-options "-mzarch -mhotpatch=0,0" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-11.c b/gcc/testsuite/gcc.target/s390/hotpatch-11.c index 6f8a52b26d..cabb9d263a 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-11.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-11.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=1,0" } */ +/* { dg-options "-mzarch -mhotpatch=1,0" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-12.c b/gcc/testsuite/gcc.target/s390/hotpatch-12.c index b73ca90fd3..fc9adc3336 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-12.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-12.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=999,0" } */ +/* { dg-options "-mzarch -mhotpatch=999,0" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-13.c b/gcc/testsuite/gcc.target/s390/hotpatch-13.c index 150667a1c6..b25fbd3f2a 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-13.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-13.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ #include <stdio.h> @@ -18,4 +18,3 @@ void hp1(void) /* { dg-final { scan-assembler-not "nop\t0" } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ /* { dg-final { scan-assembler "alignment for hotpatch" } } */ -/* { dg-final { scan-assembler-times "\.align\t8" 2 } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-14.c b/gcc/testsuite/gcc.target/s390/hotpatch-14.c index c5f118c1cc..c387d6bf06 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-14.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-14.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ #include <stdio.h> @@ -13,7 +13,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-15.c b/gcc/testsuite/gcc.target/s390/hotpatch-15.c index ef0fb74622..410106bb7c 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-15.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-15.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ #include <stdio.h> @@ -13,7 +13,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler "pre-label.*(1 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-16.c b/gcc/testsuite/gcc.target/s390/hotpatch-16.c index a34bf95c3c..fa06fff491 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-16.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-16.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,0" } */ +/* { dg-options "-mzarch -mhotpatch=0,0" } */ #include <stdio.h> @@ -13,7 +13,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler "pre-label.*(1 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-17.c b/gcc/testsuite/gcc.target/s390/hotpatch-17.c index 66ac725d16..3ef7d69b57 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-17.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-17.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=1,2" } */ +/* { dg-options "-mzarch -mhotpatch=1,2" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-18.c b/gcc/testsuite/gcc.target/s390/hotpatch-18.c index 8b076a4e17..c93af7fa99 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-18.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-18.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=1,2 -mhotpatch=0,0" } */ +/* { dg-options "-mzarch -mhotpatch=1,2 -mhotpatch=0,0" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-19.c b/gcc/testsuite/gcc.target/s390/hotpatch-19.c index 6993c7e855..bb8a137edb 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-19.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-19.c @@ -1,13 +1,12 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=1,2" } */ +/* { dg-options "-mzarch -mhotpatch=1,2" } */ #include <stdio.h> -/* { dg-prune-output "always_inline function might not be inlinable" } */ __attribute__ ((always_inline)) -static void hp2(void) +static inline void hp2(void) { printf("hello, world!\n"); } @@ -19,7 +18,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler "pre-label.*(1 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-2.c b/gcc/testsuite/gcc.target/s390/hotpatch-2.c index 67189f8a28..2a2665e258 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-2.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-2.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,1" } */ +/* { dg-options "-mzarch -mhotpatch=0,1" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(1 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(1 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nopr\t" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-not "nop\t0" } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-20.c b/gcc/testsuite/gcc.target/s390/hotpatch-20.c index 09ef5caaea..222ae5a605 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-20.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-20.c @@ -1,19 +1,17 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ #include <stdio.h> -/* { dg-prune-output "always_inline function might not be inlinable" } */ __attribute__ ((hotpatch(1,2))) __attribute__ ((always_inline)) -static void hp2(void) +static inline void hp2(void) { printf("hello, world!\n"); } -/* { dg-prune-output "called from here" } */ void hp1(void) { hp2(); diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-21.c b/gcc/testsuite/gcc.target/s390/hotpatch-21.c index e909990085..f6e90996ba 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-21.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-21.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,1" } */ +/* { dg-options "-mzarch -mhotpatch=0,1" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-22.c b/gcc/testsuite/gcc.target/s390/hotpatch-22.c index d89d779042..21f7d7e957 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-22.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-22.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,1 -falign-functions=1024" } */ +/* { dg-options "-mzarch -mhotpatch=0,1 -falign-functions=1024" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-23.c b/gcc/testsuite/gcc.target/s390/hotpatch-23.c index 1e05d123c2..6e149cc0b5 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-23.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-23.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,1 -falign-functions=4096" } */ +/* { dg-options "-mzarch -mhotpatch=0,1 -falign-functions=4096" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-24.c b/gcc/testsuite/gcc.target/s390/hotpatch-24.c index fc6427479d..1e47591710 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-24.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-24.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,1 -falign-functions=2048" } */ +/* { dg-options "-mzarch -mhotpatch=0,1 -falign-functions=2048" } */ #include <stdio.h> diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-25.c b/gcc/testsuite/gcc.target/s390/hotpatch-25.c index e9257e3744..e6cdbb6cb1 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-25.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-25.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch" } */ +/* { dg-options "-mzarch" } */ typedef long (*fn_t)(void); @@ -25,9 +25,8 @@ fn_t outer(void) /* { dg-final { scan-assembler "pre-label.*(1 halfwords)" } } */ /* { dg-final { scan-assembler "pre-label.*(4 halfwords)" } } */ /* { dg-final { scan-assembler "pre-label.*(16 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(8 halfwords)" } } */ -/* { dg-final { scan-assembler "post-label.*(32 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nopr\t" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(8 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(32 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ /* { dg-final { scan-assembler-times "alignment for hotpatch" 3 } } */ -/* { dg-final { scan-assembler-times "\.align\t8" 6 } } */ /* { dg-final { scan-assembler "nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr.*\n.*nopr" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-26.c b/gcc/testsuite/gcc.target/s390/hotpatch-26.c new file mode 100644 index 0000000000..eb95c26e25 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/hotpatch-26.c @@ -0,0 +1,17 @@ +/* Functional tests for the function hotpatching feature. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -mhotpatch=1,2" } */ + +__attribute__ ((noreturn)) void hp1(void) +{ + __builtin_unreachable (); +} + +/* Check number of occurences of certain instructions. */ +/* { dg-final { scan-assembler "pre-label NOPs" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ +/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ +/* { dg-final { scan-assembler-times "nop\t0" 1 } } */ +/* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ +/* { dg-final { scan-assembler "alignment for hotpatch" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-27.c b/gcc/testsuite/gcc.target/s390/hotpatch-27.c new file mode 100644 index 0000000000..cdbd4caf90 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/hotpatch-27.c @@ -0,0 +1,17 @@ +/* Functional tests for the function hotpatching feature. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -mhotpatch=1,2" } */ + +__attribute__ ((noreturn)) void hp3(void) +{ + __builtin_unreachable (); +} + +/* Check number of occurences of certain instructions. */ +/* { dg-final { scan-assembler "pre-label NOPs" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ +/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ +/* { dg-final { scan-assembler-times "nop\t0" 1 } } */ +/* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ +/* { dg-final { scan-assembler "alignment for hotpatch" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-28.c b/gcc/testsuite/gcc.target/s390/hotpatch-28.c new file mode 100644 index 0000000000..9922daa8ac --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/hotpatch-28.c @@ -0,0 +1,18 @@ +/* Functional tests for the function hotpatching feature. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -mhotpatch=1,2" } */ + +void hp1 (volatile unsigned int *i) +{ + for (;;) + (*i)++; +} + +/* Check number of occurences of certain instructions. */ +/* { dg-final { scan-assembler "pre-label NOPs" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ +/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ +/* { dg-final { scan-assembler-times "nop\t0" 1 } } */ +/* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ +/* { dg-final { scan-assembler "alignment for hotpatch" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-3.c b/gcc/testsuite/gcc.target/s390/hotpatch-3.c index ec4a978f72..671859116d 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-3.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-3.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,2" } */ +/* { dg-options "-mzarch -mhotpatch=0,2" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(2 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(2 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-4.c b/gcc/testsuite/gcc.target/s390/hotpatch-4.c index d55e71d3d6..b770d4bd67 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-4.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-4.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,3" } */ +/* { dg-options "-mzarch -mhotpatch=0,3" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(3 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(3 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-not "nop\t0" } } */ /* { dg-final { scan-assembler-times "brcl\t0, 0" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-5.c b/gcc/testsuite/gcc.target/s390/hotpatch-5.c index f77d83aea0..f1dcd89def 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-5.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-5.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,4" } */ +/* { dg-options "-mzarch -mhotpatch=0,4" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(4 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(4 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-not "nop\t0" } } */ /* { dg-final { scan-assembler-times "brcl\t0, 0" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-6.c b/gcc/testsuite/gcc.target/s390/hotpatch-6.c index 330cf5d011..6203a72ba2 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-6.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-6.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,5" } */ +/* { dg-options "-mzarch -mhotpatch=0,5" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(5 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(5 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-times "brcl\t0, 0" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-7.c b/gcc/testsuite/gcc.target/s390/hotpatch-7.c index 2f24e3cc15..e201ae940e 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-7.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-7.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -mhotpatch=0,6" } */ +/* { dg-options "-mzarch -mhotpatch=0,6" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(6 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(6 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*brcl\t0, 0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-not "nop\t0" } } */ /* { dg-final { scan-assembler-times "brcl\t0, 0" 2 } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-8.c b/gcc/testsuite/gcc.target/s390/hotpatch-8.c index 7b266bd463..1ea3160c0f 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-8.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-8.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile { target { ! lp64 } } } */ -/* { dg-options "-O3 -mesa -march=g5 -mhotpatch=0,3" } */ +/* { dg-options "-mesa -march=g5 -mhotpatch=0,3" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(3 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(3 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */ /* { dg-final { scan-assembler-times "nop\t0" 1 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-9.c b/gcc/testsuite/gcc.target/s390/hotpatch-9.c index c0ad319c0b..e30f2762d3 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-9.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-9.c @@ -1,7 +1,7 @@ /* Functional tests for the function hotpatching feature. */ /* { dg-do compile { target { ! lp64 } } } */ -/* { dg-options "-O3 -mesa -march=g5 -mhotpatch=0,4" } */ +/* { dg-options "-mesa -march=g5 -mhotpatch=0,4" } */ #include <stdio.h> @@ -12,7 +12,7 @@ void hp1(void) /* Check number of occurences of certain instructions. */ /* { dg-final { scan-assembler-not "pre-label NOPs" } } */ -/* { dg-final { scan-assembler "post-label.*(4 halfwords)" } } */ +/* { dg-final { scan-assembler "^\[^.\].*:\n.*post-label.*(4 halfwords).*\n\(\(.L.*:\n\)\|\(\[\[:space:\]\]*.cfi_.*\n\)\)*\[\[:space:\]\]*nop\t0" } } */ /* { dg-final { scan-assembler-not "nopr\t%r7" } } */ /* { dg-final { scan-assembler-times "nop\t0" 2 } } */ /* { dg-final { scan-assembler-not "brcl\t0, 0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/hotpatch-compile-15.c b/gcc/testsuite/gcc.target/s390/hotpatch-compile-15.c index 4ce7375a7c..12e04ea33e 100644 --- a/gcc/testsuite/gcc.target/s390/hotpatch-compile-15.c +++ b/gcc/testsuite/gcc.target/s390/hotpatch-compile-15.c @@ -3,9 +3,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -mzarch" } */ -/* { dg-prune-output "always_inline function might not be inlinable" } */ -/* { dg-prune-output "called from here" } */ - #include <stdio.h> __attribute__ ((hotpatch(1,2))) @@ -22,14 +19,14 @@ static inline void hp2(void) __attribute__ ((hotpatch(0,0))) __attribute__ ((always_inline)) -static void hp3(void) +static inline void hp3(void) { printf("hello, world!\n"); } __attribute__ ((hotpatch(1,2))) __attribute__ ((always_inline)) -static void hp4(void) +static inline void hp4(void) { printf("hello, world!\n"); } diff --git a/gcc/testsuite/gcc.target/s390/s390.exp b/gcc/testsuite/gcc.target/s390/s390.exp index 431e2c049b..7aad86e9ac 100644 --- a/gcc/testsuite/gcc.target/s390/s390.exp +++ b/gcc/testsuite/gcc.target/s390/s390.exp @@ -37,6 +37,21 @@ proc check_effective_target_htm { } { }] "-march=zEC12 -mzarch" ] } { return 0 } else { return 1 } } +# Return 1 if vector (va - vector add) instructions are understood by +# the assembler and can be executed. This also covers checking for +# the VX kernel feature. A kernel without that feature does not +# enable the vector facility and the following check will die with a +# signal. +proc check_effective_target_vector { } { + if { ![check_runtime s390_check_vector [subst { + int main (void) + { + asm ("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28"); + return 0; + } + }] "-march=z13 -mzarch" ] } { return 0 } else { return 1 } +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { @@ -46,8 +61,20 @@ if ![info exists DEFAULT_CFLAGS] then { # Initialize `dg'. dg-init +set hotpatch_tests $srcdir/$subdir/hotpatch-\[0-9\]*.c + # Main loop. -dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ +dg-runtest [lsort [prune [glob -nocomplain $srcdir/$subdir/*.\[cS\]] \ + $hotpatch_tests]] "" $DEFAULT_CFLAGS + +# Additional hotpatch torture tests. +torture-init +set HOTPATCH_TEST_OPTS [list -Os -O0 -O1 -O2 -O3] +set-torture-options $HOTPATCH_TEST_OPTS +gcc-dg-runtest [lsort [glob -nocomplain $hotpatch_tests]] "" $DEFAULT_CFLAGS +torture-finish + +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*vector*/*.\[cS\]]] \ "" $DEFAULT_CFLAGS # All done. diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-1.c new file mode 100644 index 0000000000..db18e5ec57 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-1.c @@ -0,0 +1,18 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* Make sure the last argument is fetched from the argument overflow area. */ +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,160\\(%r15\\)" { target lp64 } } } */ +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,96\\(%r15\\)" { target ilp32 } } } */ +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +typedef double v2df __attribute__((vector_size(16))); + +v2df +add (v2df a, v2df b, v2df c, v2df d, + v2df e, v2df f, v2df g, v2df h, v2df i) +{ + return a + b + c + d + e + f + g + h + i; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-2.c new file mode 100644 index 0000000000..62663d889e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-2.c @@ -0,0 +1,15 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* This needs to be v24 = v24 * v26 + v28 */ +/* { dg-final { scan-assembler "vfmadb\t%v24,%v24,%v26,%v28" } } */ + +typedef double v2df __attribute__((vector_size(16))); + +v2df +madd (v2df a, v2df b, v2df c) +{ + return a * b + c; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-3.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-3.c new file mode 100644 index 0000000000..4be2360a36 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-3.c @@ -0,0 +1,101 @@ +/* Check calling convention in the vector ABI regarding vector like structs. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* addA */ +/* { dg-final { scan-assembler-times "vfadb\t%v24,%v24,%v26" 1 } } */ + +/* addB and addE*/ +/* { dg-final { scan-assembler-times "vah\t%v24,%v\[0-9\]*,%v\[0-9\]*" 2 } } */ + +/* addC */ +/* { dg-final { scan-assembler-times "vag\t%v24,%v\[0-9\]*,%v\[0-9\]*" 1 } } */ + +/* addB and addC are expected to read the arguments via pointers in r2 and r3 */ +/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,0\\(%r2\\)" 2 } } */ +/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,0\\(%r3\\)" 2 } } */ + +/* addD */ +/* { dg-final { scan-assembler-times "vaf\t%v24,%v24,%v26" 1 } } */ + +/* addE */ +/* { dg-final { scan-assembler-times "vah\t%v24,%v24,%v26" 1 } } */ + +/* addF */ +/* { dg-final { scan-assembler-times "vab\t%v24,%v\[0-9\]*,%v\[0-9\]*" 1 } } */ +/* { dg-final { scan-assembler-times "srlg\t%r\[0-9\]*,%r2,32" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "srlg\t%r\[0-9\]*,%r3,32" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "llgfr\t%.*,%r2" 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "llgfr\t%.*,%r4" 1 { target { ! lp64 } } } } */ + + +typedef double v2df __attribute__((vector_size(16))); +typedef long long v2di __attribute__((vector_size(16))); +typedef int v4si __attribute__((vector_size(16))); +typedef short v8hi __attribute__((vector_size(16))); + +typedef short v2hi __attribute__((vector_size(4))); +typedef char v4qi __attribute__((vector_size(4))); + +/* Vector like structs are passed in VRs. */ +struct A { v2df a; }; + +v2df +addA (struct A a, struct A b) +{ + return a.a + b.a; +} + +/* Only single element vectors qualify as vector type parms. This one + is passed as a struct. Since it is bigger than 8 bytes it is passed + on the stack with the reference being put into r2/r3. */ +struct B { v8hi a; char b;}; + +v8hi +addB (struct B a, struct B b) +{ + return a.a + b.a; +} + +/* The resulting struct is bigger than 16 bytes and therefore passed + on the stack with the references residing in r2/r3. */ +struct C { v2di __attribute__((aligned(32))) a; }; + +v2di +addC (struct C a, struct C b) +{ + return a.a + b.a; +} + +/* The attribute here does not have any effect. So this struct stays + vector like and hence is passed in a VR. */ +struct D { v4si __attribute__((aligned(16))) a; }; + +v4si +addD (struct D a, struct D b) +{ + return a.a + b.a; +} + + +/* Smaller vectors are passed in vector registers. This also applies + for vector like structs. */ +struct E { v2hi a; }; + +v2hi +addE (struct E a, struct E b) +{ + return a.a + b.a; +} + +/* This struct is not passed in VRs because of padding. But since it + fits in a GPR and has a power of two size. It is passed in + GPRs. */ +struct F { v4qi __attribute__((aligned(8))) a; }; + +v4qi +addF (struct F a, struct F b) +{ + return a.a + b.a; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-4.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-4.c new file mode 100644 index 0000000000..fea44f98f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-4.c @@ -0,0 +1,19 @@ +/* Check calling convention in the vector ABI. Smaller vector need to + be placed left-justified in the stack slot. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "lde\t%.*,160\\\(%r15\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "lde\t%.*,168\\\(%r15\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "lde\t%.*,96\\\(%r15\\\)" 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "lde\t%.*,100\\\(%r15\\\)" 1 { target { ! lp64 } } } } */ + +typedef char __attribute__((vector_size(4))) v4qi; + +v4qi +foo (v4qi a, v4qi b, v4qi c, v4qi d, v4qi e, + v4qi f, v4qi g, v4qi h, v4qi i, v4qi j) +{ + return (a + b + c + d + e + f + g + h + i + j); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-align-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-align-1.c new file mode 100644 index 0000000000..10e5617972 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-align-1.c @@ -0,0 +1,48 @@ +/* Check alignment convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +#include <stddef.h> + +/* Vector types get an 8 byte alignment. */ +typedef double v2df __attribute__((vector_size(16))); +typedef struct +{ + char a; + v2df b; +} A; +char c1[offsetof (A, b) == 8 ? 0 : -1]; + +/* Smaller vector allow for smaller alignments. */ +typedef char v4qi __attribute__((vector_size(4))); +typedef struct +{ + char a; + v4qi b; +} B; +char c2[offsetof (B, b) == 4 ? 0 : -1]; + + +typedef double v4df __attribute__((vector_size(32))); +typedef struct +{ + char a; + v4df b; +} C; +char c3[offsetof (C, b) == 8 ? 0 : -1]; + +/* However, we allow the programmer to chose a bigger alignment. */ +typedef struct +{ + char a; + v2df b __attribute__((aligned(16))); +} D; +char c4[offsetof (D, b) == 16 ? 0 : -1]; + +typedef struct +{ + char a; + v2df b; +} __attribute__((packed)) E; +char c5[offsetof (E, b) == 1 ? 0 : -1]; diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-1.c new file mode 100644 index 0000000000..a06b338844 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-1.c @@ -0,0 +1,18 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -mno-vx" } */ + +/* The function passes arguments whose calling conventions change with + -mvx/-mno-vx. In that case GCC has to emit the ABI attribute to + allow GDB and Binutils to detect this. */ +/* { dg-final { scan-assembler "gnu_attribute 8, 1" } } */ + +typedef double v2df __attribute__((vector_size(16))); + +v2df +add (v2df a, v2df b, v2df c, v2df d, + v2df e, v2df f, v2df g, v2df h, v2df i) +{ + return a + b + c + d + e + f + g + h + i; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-2.c new file mode 100644 index 0000000000..97b9748bb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-2.c @@ -0,0 +1,53 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* No abi attribute should be emitted when nothing relevant happened. */ +/* { dg-final { scan-assembler-not "gnu_attribute" } } */ + +#include <stdarg.h> + +/* Local use is ok. */ + +typedef int v4si __attribute__((vector_size(16))); + +static +v4si __attribute__((__noinline__)) +foo (v4si a) +{ + return a + (v4si){ 1, 2, 3, 4 }; +} + +int +bar (int a) +{ + return foo ((v4si){ 1, 1, 1, 1 })[1]; +} + +/* Big vector type only used as function argument and return value + without being a struct/union member. The alignment change is not + relevant here. */ + +typedef double v4df __attribute__((vector_size(32))); + +v4df +add (v4df a, v4df b, v4df c, v4df d, + v4df e, v4df f, v4df g, v4df h, v4df i) +{ + return a + b + c + d + e + f + g + h + i; +} + +double +bar2 (int n, ...) +{ + double ret; + v4df a; + va_list va; + + va_start (va, n); + ret = va_arg (va, v4df)[2]; + va_end (va); + + return ret; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-3.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-3.c new file mode 100644 index 0000000000..f3dc368d26 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-3.c @@ -0,0 +1,18 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a; } s; + +s +add (v4df a, v4df b, v4df c, v4df d, + v4df e, v4df f, v4df g, v4df h, v4df i) +{ + s t; + t.a = a + b + c + d + e + f + g + h + i; + return t; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-4.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-4.c new file mode 100644 index 0000000000..ad9b29a873 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-4.c @@ -0,0 +1,17 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +typedef int __attribute__((vector_size(16))) v4si; + +extern void bar (v4si); + +void +foo (int a) +{ + v4si b = (v4si){ a, a, a, a }; + bar (b); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-5.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-5.c new file mode 100644 index 0000000000..fb5de4e71a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-5.c @@ -0,0 +1,19 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +#include <stdarg.h> + +typedef int __attribute__((vector_size(16))) v4si; + +extern void bar (int, ...); + +void +foo (int a) +{ + v4si b = (v4si){ a, a, a, a }; + bar (1, b); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-6.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-6.c new file mode 100644 index 0000000000..9134fa7c88 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-attr-6.c @@ -0,0 +1,24 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +#include <stdarg.h> + +typedef int __attribute__((vector_size(16))) v4si; + +int +bar (int n, ...) +{ + int ret; + v4si a; + va_list va; + + va_start (va, n); + ret = va_arg (va, v4si)[2]; + va_end (va); + + return ret; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-1.c new file mode 100644 index 0000000000..b6cb0fc4d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-1.c @@ -0,0 +1,24 @@ +/* Check calling convention in the vector ABI for single element vectors. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "vlr\t%v24,%v26" 7 } } */ + +typedef int __attribute__((vector_size(16))) v4si; + +typedef char __attribute__((vector_size(1))) v1qi; +typedef short int __attribute__((vector_size(2))) v1hi; +typedef int __attribute__((vector_size(4))) v1si; +typedef long long __attribute__((vector_size(8))) v1di; +typedef float __attribute__((vector_size(4))) v1sf; +typedef double __attribute__((vector_size(8))) v1df; +typedef long double __attribute__((vector_size(16))) v1tf; + +v1qi foo1 (v4si a, v1qi b) { return b; } +v1hi foo2 (v4si a, v1hi b) { return b; } +v1si foo3 (v4si a, v1si b) { return b; } +v1di foo4 (v4si a, v1di b) { return b; } +v1sf foo5 (v4si a, v1sf b) { return b; } +v1df foo6 (v4si a, v1df b) { return b; } +v1tf foo7 (v4si a, v1tf b) { return b; } diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-2.c new file mode 100644 index 0000000000..4829f024c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-single-2.c @@ -0,0 +1,12 @@ +/* Check calling convention in the vector ABI for single element vectors. */ + +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "vlr\t%v24,%v26" 1 } } */ + +typedef int __attribute__((vector_size(16))) v4si; + +typedef __int128_t __attribute__((vector_size(16))) v1ti; + +v1ti foo (v4si a, v1ti b) { return b; } diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-struct-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-struct-1.c new file mode 100644 index 0000000000..ab27f8310a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-struct-1.c @@ -0,0 +1,37 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* c.i and c.j are passed by reference since a struct with two + elements is no vector type argument. */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,0\\(%r3\\)" } } */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,8\\(%r3\\)" } } */ + +/* just_v2si is passed in a vector reg if it as an incoming arg. + However, as return value it is passed via hidden first pointer + argument. */ +/* { dg-final { scan-assembler ".*st.*\t%v\[0-9\]*,0\\(%r2\\)" } } */ + +/* { dg-final { scan-assembler "gnu_attribute 8, 2" } } */ + +typedef int __attribute__ ((vector_size(8))) v2si; + +struct just_v2si +{ + v2si i; +}; + +struct two_v2si +{ + v2si i, j; +}; + +struct just_v2si +add_structvecs (v2si a, struct just_v2si b, struct two_v2si c) +{ + struct just_v2si res; + + res.i = a + b.i + c.i + c.j; + return res; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-1.c new file mode 100644 index 0000000000..7927fa104c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-1.c @@ -0,0 +1,60 @@ +/* Check calling convention with variable argument lists in the vector + ABI. */ + +/* { dg-do run { target { s390*-*-* } } } */ +/* { dg-require-effective-target vector } */ +/* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ + +/* Make sure arguments are fetched from the argument overflow area. */ +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,352\\(%r15\\)" { target lp64 } } } */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,368\\(%r15\\)" { target lp64 } } } */ +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,376\\(%r15\\)" { target lp64 } } } */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,392\\(%r15\\)" { target lp64 } } } */ + +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,208\\(%r15\\)" { target ilp32 } } } */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,224\\(%r15\\)" { target ilp32 } } } */ +/* { dg-final { scan-assembler "vl\t%v\[0-9\]*,232\\(%r15\\)" { target ilp32 } } } */ +/* { dg-final { scan-assembler "ld\t%v\[0-9\]*,248\\(%r15\\)" { target ilp32 } } } */ + +/* { dg-final { cleanup-saved-temps } } */ + +#include <stdarg.h> + +extern void abort (void); + +typedef long long v2di __attribute__((vector_size(16))); +typedef int v2si __attribute__((vector_size(8))); + +v2di __attribute__((noinline)) +add (int a, ...) +{ + int i; + va_list va; + v2di di_result = { 0, 0 }; + v2si si_result = (v2si){ 0, 0 }; + + va_start (va, a); + + di_result += va_arg (va, v2di); + si_result += va_arg (va, v2si); + di_result += va_arg (va, v2di); + si_result += va_arg (va, v2si); + + va_end (va); + + di_result[0] += si_result[0]; + di_result[1] += si_result[1]; + + return di_result; +} + +int +main () +{ + v2di r = add (4, (v2di){ 11, 21 }, (v2si){ 12, 22 }, (v2di){ 13, 23 }, (v2si){ 14, 24 }); + + if (r[0] != 50 || r[1] != 90) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-2.c new file mode 100644 index 0000000000..8df4d585c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abi-vararg-2.c @@ -0,0 +1,18 @@ +/* Check calling convention in the vector ABI. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -Wno-implicit-function-declaration" } */ + + +typedef long v2di __attribute__((vector_size(16))); +extern v2di foo1 (int, v2di); +extern v2di foo2 (int, int); +extern v2di foo3 (int, ...); + +v2di bar1 (int a) { return foo2 (1, a); } +v2di bar2 (int a) { return foo3 (1, a); } +v2di bar3 (v2di a) { return foo1 (1, a); } +v2di bar4 (v2di a) { return foo3 (1, a); } + +int bar5 (int a) { return foo4 (1, a); } +int bar6 (v2di a) { return foo4 (1, a); } /* { dg-error "Vector argument passed to unprototyped function" } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-clobber-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-clobber-1.c new file mode 100644 index 0000000000..413b6a00f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-clobber-1.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { s390*-*-* } } } */ +/* { dg-require-effective-target vector } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* For FP zero checks we use the ltdbr instruction. Since this is an + load and test it actually writes the FPR. Whenever an FPR gets + written the rest of the overlapping VR is clobbered. */ +typedef double __attribute__((vector_size(16))) v2df; + +v2df a = { 1.0, 2.0 }; + +extern void abort (void); + +void __attribute__((noinline)) +foo (v2df a) +{ + v2df b = { 1.0, 3.0 }; + + b -= a; + + /* Take away all the VRs not overlapping with FPRs. */ + asm volatile ("" : : : + "v16","v17","v18","v19", + "v20","v21","v22","v23", + "v24","v25","v26","v27", + "v28","v29","v30","v31"); + if (b[0] != 0.0) /* ltdbr */ + abort (); + if (b[1] != 1.0) + abort (); +} + +int +main () +{ + foo (a); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-cmp-1.c new file mode 100644 index 0000000000..f46910f5d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-cmp-1.c @@ -0,0 +1,45 @@ +/* Check that the proper unsigned compare instructions are being generated. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "vchlb" 1 } } */ +/* { dg-final { scan-assembler-times "vchlh" 1 } } */ +/* { dg-final { scan-assembler-times "vchlf" 1 } } */ +/* { dg-final { scan-assembler-times "vchlg" 1 } } */ + +typedef __attribute__((vector_size(16))) signed char v16qi; +typedef __attribute__((vector_size(16))) unsigned char uv16qi; + +typedef __attribute__((vector_size(16))) signed short v8hi; +typedef __attribute__((vector_size(16))) unsigned short uv8hi; + +typedef __attribute__((vector_size(16))) signed int v4si; +typedef __attribute__((vector_size(16))) unsigned int uv4si; + +typedef __attribute__((vector_size(16))) signed long long v2di; +typedef __attribute__((vector_size(16))) unsigned long long uv2di; + +v16qi +f (uv16qi a, uv16qi b) +{ + return a > b; +} + +v8hi +g (uv8hi a, uv8hi b) +{ + return a > b; +} + +v4si +h (uv4si a, uv4si b) +{ + return a > b; +} + +v2di +i (uv2di a, uv2di b) +{ + return a > b; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-cmp-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-cmp-2.c new file mode 100644 index 0000000000..999f72cbcb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-cmp-2.c @@ -0,0 +1,38 @@ +/* Check that the proper signed compare instructions are being generated. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "vchb" 1 } } */ +/* { dg-final { scan-assembler-times "vchh" 1 } } */ +/* { dg-final { scan-assembler-times "vchf" 1 } } */ +/* { dg-final { scan-assembler-times "vchg" 1 } } */ + +typedef __attribute__((vector_size(16))) signed char v16qi; +typedef __attribute__((vector_size(16))) signed short v8hi; +typedef __attribute__((vector_size(16))) signed int v4si; +typedef __attribute__((vector_size(16))) signed long long v2di; + +v16qi +f (v16qi a, v16qi b) +{ + return a > b; +} + +v8hi +g (v8hi a, v8hi b) +{ + return a > b; +} + +v4si +h (v4si a, v4si b) +{ + return a > b; +} + +v2di +i (v2di a, v2di b) +{ + return a > b; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-dbl-math-compile-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-dbl-math-compile-1.c new file mode 100644 index 0000000000..f53fb11245 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-dbl-math-compile-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ + +typedef __attribute__((vector_size(16))) double v2df; + +v2df +adddbl (v2df a, v2df b) +{ + return a + b; +} +/* { dg-final { scan-assembler-times "vfadb" 1 } } */ + +v2df +subdbl (v2df a, v2df b) +{ + return a - b; +} +/* { dg-final { scan-assembler-times "vfsdb" 1 } } */ + +v2df +muldbl (v2df a, v2df b) +{ + return a * b; +} +/* { dg-final { scan-assembler-times "vfmdb" 1 } } */ + +v2df +divdbl (v2df a, v2df b) +{ + return a / b; +} +/* { dg-final { scan-assembler-times "vfd" 1 } } */ + +v2df +fmadbl (v2df a, v2df b, v2df c) +{ + return a * b + c; +} +/* { dg-final { scan-assembler-times "vfma" 1 } } */ + +v2df +fmsdbl (v2df a, v2df b, v2df c) +{ + return a * b - c; +} +/* { dg-final { scan-assembler-times "vfms" 1 } } */ + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c new file mode 100644 index 0000000000..dfe19f1913 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ +/* { dg-require-effective-target vector } */ + +typedef unsigned char uv16qi __attribute__((vector_size(16))); +typedef unsigned short uv8hi __attribute__((vector_size(16))); +typedef unsigned int uv4si __attribute__((vector_size(16))); +typedef unsigned long long uv2di __attribute__((vector_size(16))); + +uv2di __attribute__((noinline)) +foo1 () +{ + return (uv2di){ 0xff00ff00ff00ff00, 0x00ff00ff00ff00ff }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v24,43605" 1 } } */ + +uv4si __attribute__((noinline)) +foo2 () +{ + return (uv4si){ 0xff0000ff, 0x0000ffff, 0xffff0000, 0x00ffff00 }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v24,37830" 1 } } */ + +uv8hi __attribute__((noinline)) +foo3a () +{ + return (uv8hi){ 0xff00, 0xff00, 0xff00, 0xff00, + 0xff00, 0xff00, 0xff00, 0xff00 }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v24,43690" 1 } } */ + +uv8hi __attribute__((noinline)) +foo3b () +{ + return (uv8hi){ 0x00ff, 0x00ff, 0x00ff, 0x00ff, + 0x00ff, 0x00ff, 0x00ff, 0x00ff }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v24,21845" 1 } } */ + +uv16qi __attribute__((noinline)) +foo4 () +{ + return (uv16qi){ 0xff, 0xff, 0xff, 0xff, + 0, 0, 0, 0, + 0xff, 0, 0xff, 0, + 0, 0xff, 0, 0xff }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v24,61605" 1 } } */ + +int +main () +{ + if (foo1()[1] != 0x00ff00ff00ff00ffULL) + __builtin_abort (); + + if (foo2()[1] != 0x0000ffff) + __builtin_abort (); + + if (foo3a()[1] != 0xff00) + __builtin_abort (); + + if (foo3b()[1] != 0x00ff) + __builtin_abort (); + + if (foo4()[1] != 0xff) + __builtin_abort (); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-2.c new file mode 100644 index 0000000000..83c64a7732 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-2.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +typedef unsigned char uv16qi __attribute__((vector_size(16))); +typedef unsigned short uv8hi __attribute__((vector_size(16))); +typedef unsigned int uv4si __attribute__((vector_size(16))); +typedef unsigned long long uv2di __attribute__((vector_size(16))); + +/* The elements differ. */ +uv2di __attribute__((noinline)) +foo1 () +{ + return (uv2di){ 0x001fffffffffff00, 0x0000ffffffffff00 }; +} + +/* Non-contiguous bitmasks */ + +uv4si __attribute__((noinline)) +foo2 () +{ + return (uv4si){ 0xff00100f, 0xff00100f, 0xff00100f, 0xff00100f }; +} + +uv8hi __attribute__((noinline)) +foo3a () +{ + return (uv8hi){ 0xf700, 0xf700, 0xf700, 0xf700, + 0xf700, 0xf700, 0xf700, 0xf700 }; +} + +uv8hi __attribute__((noinline)) +foo3b () +{ + return (uv8hi){ 0x10ff, 0x10ff, 0x10ff, 0x10ff, + 0x10ff, 0x10ff, 0x10ff, 0x10ff }; +} + +uv16qi __attribute__((noinline)) +foo4 () +{ + return (uv16qi){ 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82 }; +} +/* { dg-final { scan-assembler-not "vgbm" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c new file mode 100644 index 0000000000..8149e224c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ +/* { dg-require-effective-target vector } */ + +typedef unsigned char uv16qi __attribute__((vector_size(16))); +typedef unsigned short uv8hi __attribute__((vector_size(16))); +typedef unsigned int uv4si __attribute__((vector_size(16))); +typedef unsigned long long uv2di __attribute__((vector_size(16))); + +uv2di __attribute__((noinline)) +foo1 () +{ + return (uv2di){ 0x000fffffffffff00, 0x000fffffffffff00 }; +} +/* { dg-final { scan-assembler-times "vgmg\t%v24,12,55" 1 } } */ + +uv4si __attribute__((noinline)) +foo2 () +{ + return (uv4si){ 0xff00000f, 0xff00000f, 0xff00000f, 0xff00000f }; +} +/* { dg-final { scan-assembler-times "vgmf\t%v24,28,7" 1 } } */ + +uv8hi __attribute__((noinline)) +foo3a () +{ + return (uv8hi){ 0xfff0, 0xfff0, 0xfff0, 0xfff0, + 0xfff0, 0xfff0, 0xfff0, 0xfff0 }; +} +/* { dg-final { scan-assembler-times "vgmh\t%v24,0,11" 1 } } */ + +uv8hi __attribute__((noinline)) +foo3b () +{ + return (uv8hi){ 0x0fff, 0x0fff, 0x0fff, 0x0fff, + 0x0fff, 0x0fff, 0x0fff, 0x0fff }; +} +/* { dg-final { scan-assembler-times "vgmh\t%v24,4,15" 1 } } */ + +uv16qi __attribute__((noinline)) +foo4 () +{ + return (uv16qi){ 0x8, 0x8, 0x8, 0x8, + 0x8, 0x8, 0x8, 0x8, + 0x8, 0x8, 0x8, 0x8, + 0x8, 0x8, 0x8, 0x8 }; +} +/* { dg-final { scan-assembler-times "vgmb\t%v24,4,4" 1 } } */ + +int +main () +{ + if (foo1()[1] != 0x000fffffffffff00ULL) + __builtin_abort (); + + if (foo2()[1] != 0xff00000f) + __builtin_abort (); + + if (foo3a()[1] != 0xfff0) + __builtin_abort (); + + if (foo3b()[1] != 0x0fff) + __builtin_abort (); + + if (foo4()[1] != 0x8) + __builtin_abort (); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c new file mode 100644 index 0000000000..e3ae34154c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +typedef unsigned char uv16qi __attribute__((vector_size(16))); +typedef unsigned short uv8hi __attribute__((vector_size(16))); +typedef unsigned int uv4si __attribute__((vector_size(16))); +typedef unsigned long long uv2di __attribute__((vector_size(16))); + +/* The elements differ. */ +uv2di __attribute__((noinline)) +foo1 () +{ + return (uv2di){ 0x000fffffffffff00, 0x0000ffffffffff00 }; +} + +/* Non-contiguous bitmasks */ + +uv4si __attribute__((noinline)) +foo2 () +{ + return (uv4si){ 0xff00100f, 0xff00100f, 0xff00100f, 0xff00100f }; +} + +uv8hi __attribute__((noinline)) +foo3a () +{ + return (uv8hi){ 0xf700, 0xf700, 0xf700, 0xf700, + 0xf700, 0xf700, 0xf700, 0xf700 }; +} + +uv8hi __attribute__((noinline)) +foo3b () +{ + return (uv8hi){ 0x10ff, 0x10ff, 0x10ff, 0x10ff, + 0x10ff, 0x10ff, 0x10ff, 0x10ff }; +} + +uv16qi __attribute__((noinline)) +foo4 () +{ + return (uv16qi){ 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82, + 0x82, 0x82, 0x82, 0x82 }; +} +/* { dg-final { scan-assembler-not "vgm" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-init-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-init-1.c new file mode 100644 index 0000000000..4deb6b8db5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-init-1.c @@ -0,0 +1,68 @@ +/* Check that the vec_init expander does its job. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + + + + + +typedef __attribute__((vector_size(16))) signed int v4si; + +extern v4si G; + +v4si +f (signed int a) +{ + return G == a; +} +/* { dg-final { scan-assembler-times "vrepf" 1 } } */ + +v4si +g (signed int *a) +{ + return G == *a; +} +/* { dg-final { scan-assembler-times "vlrepf" 1 } } */ + +v4si +h () +{ + return G == 1; +} +/* { dg-final { scan-assembler-times "vgmf\t%v.*,31,31" 1 } } */ + +v4si +i () +{ + return G == -1; +} +/* { dg-final { scan-assembler-times "vone" 1 } } */ + +v4si +j () +{ + return G == 0; +} +/* { dg-final { scan-assembler-times "vzero" 1 } } */ + +v4si +k () +{ + return G == (v4si){ 0xff80, 0xff80, 0xff80, 0xff80 }; +} +/* { dg-final { scan-assembler-times "vgmf\t%v.*,16,24" 1 } } */ + +v4si +l () +{ + return G == (v4si){ 0xf000000f, 0xf000000f, 0xf000000f, 0xf000000f }; +} +/* { dg-final { scan-assembler-times "vgmf\t%v.*,28,3" 1 } } */ + +v4si +m () +{ + return G == (v4si){ 0x00ff00ff, 0x0000ffff, 0xffff0000, 0xff00ff00 }; +} +/* { dg-final { scan-assembler-times "vgbm\t%v.*,21450" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-int-math-compile-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-int-math-compile-1.c new file mode 100644 index 0000000000..f6c38d905d --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-int-math-compile-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +typedef __attribute__((vector_size(16))) signed int v4si; + +v4si +adddbl (v4si a, v4si b) +{ + return a + b; +} + +v4si +subdbl (v4si a, v4si b) +{ + return a - b; +} + +v4si +muldbl (v4si a, v4si b) +{ + return a * b; +} + +v4si +divdbl (v4si a, v4si b) +{ + return a / b; +} + +v4si +fmadbl (v4si a, v4si b, v4si c) +{ + return a * b + c; +} + +v4si +fmsdbl (v4si a, v4si b, v4si c) +{ + return a * b - c; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c new file mode 100644 index 0000000000..b79120f20f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c @@ -0,0 +1,49 @@ +/* Check that we use the scalar variants of vector compares. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "wfcedbs\t%v\[0-9\]*,%v0,%v2" 2 } } */ +/* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v0,%v2" 1 } } */ +/* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */ +/* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v2,%v0" 1 } } */ +/* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */ +/* { dg-final { scan-assembler-times "locrne" 5 } } */ +/* { dg-final { scan-assembler-times "locrno" 1 } } */ + + +int +eq (double a, double b) +{ + return a == b; +} + +int +ne (double a, double b) +{ + return a != b; +} + +int +gt (double a, double b) +{ + return a > b; +} + +int +ge (double a, double b) +{ + return a >= b; +} + +int +lt (double a, double b) +{ + return a < b; +} + +int +le (double a, double b) +{ + return a <= b; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-1.c new file mode 100644 index 0000000000..3517feaba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-1.c @@ -0,0 +1,108 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "veslb" 2 } } */ +/* { dg-final { scan-assembler-times "veslh" 2 } } */ +/* { dg-final { scan-assembler-times "veslf" 2 } } */ +/* { dg-final { scan-assembler-times "veslg" 2 } } */ + +/* { dg-final { scan-assembler-times "vesrab" 1 } } */ +/* { dg-final { scan-assembler-times "vesrah" 1 } } */ +/* { dg-final { scan-assembler-times "vesraf" 1 } } */ +/* { dg-final { scan-assembler-times "vesrag" 1 } } */ + +/* { dg-final { scan-assembler-times "vesrlb" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlh" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlf" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlg" 1 } } */ + +/* { dg-final { scan-assembler-times "veslvb" 2 } } */ +/* { dg-final { scan-assembler-times "veslvh" 2 } } */ +/* { dg-final { scan-assembler-times "veslvf" 2 } } */ +/* { dg-final { scan-assembler-times "veslvg" 2 } } */ + +/* { dg-final { scan-assembler-times "vesravb" 1 } } */ +/* { dg-final { scan-assembler-times "vesravh" 1 } } */ +/* { dg-final { scan-assembler-times "vesravf" 1 } } */ +/* { dg-final { scan-assembler-times "vesravg" 1 } } */ + +/* { dg-final { scan-assembler-times "vesrlvb" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlvh" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlvf" 1 } } */ +/* { dg-final { scan-assembler-times "vesrlvg" 1 } } */ + +typedef __attribute__((vector_size(16))) signed char v16qi; +typedef __attribute__((vector_size(16))) unsigned char uv16qi; + +typedef __attribute__((vector_size(16))) signed short v8hi; +typedef __attribute__((vector_size(16))) unsigned short uv8hi; + +typedef __attribute__((vector_size(16))) signed int v4si; +typedef __attribute__((vector_size(16))) unsigned int uv4si; + +typedef __attribute__((vector_size(16))) signed long long v2di; +typedef __attribute__((vector_size(16))) unsigned long long uv2di; + +uv16qi g_uvqi0, g_uvqi1, g_uvqi2; +v16qi g_vqi0, g_vqi1, g_vqi2; + +uv8hi g_uvhi0, g_uvhi1, g_uvhi2; +v8hi g_vhi0, g_vhi1, g_vhi2; + +uv4si g_uvsi0, g_uvsi1, g_uvsi2; +v4si g_vsi0, g_vsi1, g_vsi2; + +uv2di g_uvdi0, g_uvdi1, g_uvdi2; +v2di g_vdi0, g_vdi1, g_vdi2; + +void +shift_left_by_scalar (int s) +{ + g_uvqi0 = g_uvqi1 << s; + g_vqi0 = g_vqi1 << s; + g_uvhi0 = g_uvhi1 << s; + g_vhi0 = g_vhi1 << s; + g_uvsi0 = g_uvsi1 << s; + g_vsi0 = g_vsi1 << s; + g_uvdi0 = g_uvdi1 << s; + g_vdi0 = g_vdi1 << s; +} + +void +shift_right_by_scalar (int s) +{ + g_uvqi0 = g_uvqi1 >> s; + g_vqi0 = g_vqi1 >> s; + g_uvhi0 = g_uvhi1 >> s; + g_vhi0 = g_vhi1 >> s; + g_uvsi0 = g_uvsi1 >> s; + g_vsi0 = g_vsi1 >> s; + g_uvdi0 = g_uvdi1 >> s; + g_vdi0 = g_vdi1 >> s; +} + +void +shift_left_by_vector () +{ + g_uvqi0 = g_uvqi1 << g_uvqi2; + g_vqi0 = g_vqi1 << g_vqi2; + g_uvhi0 = g_uvhi1 << g_uvhi2; + g_vhi0 = g_vhi1 << g_vhi2; + g_uvsi0 = g_uvsi1 << g_uvsi2; + g_vsi0 = g_vsi1 << g_vsi2; + g_uvdi0 = g_uvdi1 << g_uvdi2; + g_vdi0 = g_vdi1 << g_vdi2; +} + +void +shift_right_by_vector () +{ + g_uvqi0 = g_uvqi1 >> g_uvqi2; + g_vqi0 = g_vqi1 >> g_vqi2; + g_uvhi0 = g_uvhi1 >> g_uvhi2; + g_vhi0 = g_vhi1 >> g_vhi2; + g_uvsi0 = g_uvsi1 >> g_uvsi2; + g_vsi0 = g_vsi1 >> g_vsi2; + g_uvdi0 = g_uvdi1 >> g_uvdi2; + g_vdi0 = g_vdi1 >> g_vdi2; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-sub-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-sub-1.c new file mode 100644 index 0000000000..3fe33dd549 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-sub-1.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + +/* { dg-final { scan-assembler-times "vsb" 2 } } */ +/* { dg-final { scan-assembler-times "vsh" 2 } } */ +/* { dg-final { scan-assembler-times "vsf" 2 } } */ +/* { dg-final { scan-assembler-times "vsg" 2 } } */ +/* { dg-final { scan-assembler-times "vfs" 1 } } */ + + +typedef unsigned char uv16qi __attribute__((vector_size(16))); +typedef signed char v16qi __attribute__((vector_size(16))); +typedef unsigned short uv8hi __attribute__((vector_size(16))); +typedef signed short v8hi __attribute__((vector_size(16))); +typedef unsigned int uv4si __attribute__((vector_size(16))); +typedef signed int v4si __attribute__((vector_size(16))); +typedef unsigned long long uv2di __attribute__((vector_size(16))); +typedef signed long long v2di __attribute__((vector_size(16))); +typedef double v2df __attribute__((vector_size(16))); + +uv16qi g_uvqi0, g_uvqi1, g_uvqi2; +v16qi g_vqi0, g_vqi1, g_vqi2; + +uv8hi g_uvhi0, g_uvhi1, g_uvhi2; +v8hi g_vhi0, g_vhi1, g_vhi2; + +uv4si g_uvsi0, g_uvsi1, g_uvsi2; +v4si g_vsi0, g_vsi1, g_vsi2; + +uv2di g_uvdi0, g_uvdi1, g_uvdi2; +v2di g_vdi0, g_vdi1, g_vdi2; + +v2df g_vdf0, g_vdf1, g_vdf2; + +void +sub1 () +{ + g_vqi0 = g_vqi1 - g_vqi2; + g_uvqi0 = g_uvqi1 - g_uvqi2; + + g_vhi0 = g_vhi1 - g_vhi2; + g_uvhi0 = g_uvhi1 - g_uvhi2; + + g_vsi0 = g_vsi1 - g_vsi2; + g_uvsi0 = g_uvsi1 - g_uvsi2; + + g_vdi0 = g_vdi1 - g_vdi2; + g_uvdi0 = g_uvdi1 - g_uvdi2; + + g_vdf0 = g_vdf1 - g_vdf2; +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-dbl-math-compile-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-dbl-math-compile-1.c new file mode 100644 index 0000000000..31b277bf94 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-dbl-math-compile-1.c @@ -0,0 +1,67 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector --save-temps" } */ + +/* { dg-final { scan-assembler-times "vfcedb\t" 1 } } */ +/* { dg-final { scan-assembler-times "vfchdb\t" 2 } } */ +/* { dg-final { scan-assembler-times "vfchedb\t" 2 } } */ + +/* { dg-final { scan-assembler-times "vfcedbs\t" 2 } } */ +/* { dg-final { scan-assembler-times "vfchdbs\t" 2 } } */ + +/* { dg-final { cleanup-saved-temps } } */ + +#include <vecintrin.h> + +vector bool long long +cmpeq (vector double a, vector double b) +{ + return vec_cmpeq (a, b); /* vfcedb */ +} + +vector bool long long +cmpgt (vector double a, vector double b) +{ + return vec_cmpgt (a, b); /* vfchdb */ +} + +vector bool long long +cmpge (vector double a, vector double b) +{ + return vec_cmpge (a, b); /* vfchedb */ +} + +vector bool long long +cmplt (vector double a, vector double b) +{ + return vec_cmplt (a, b); /* vfchdb */ +} + +vector bool long long +cmple (vector double a, vector double b) +{ + return vec_cmple (a, b); /* vfchedb */ +} + +int +all_eq (vector double a, vector double b) +{ + return vec_all_eq (a, b); +} + +int +any_eq (vector double a, vector double b) +{ + return vec_any_eq (a, b); +} + +int +all_lt (vector double a, vector double b) +{ + return vec_all_lt (a, b); +} + +int +any_lt (vector double a, vector double b) +{ + return vec_any_lt (a, b); +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-elem-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-elem-1.c new file mode 100644 index 0000000000..c8578bf80d --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-elem-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector" } */ + +/* { dg-final { scan-assembler "nilf\t%r2,15" } } */ +/* { dg-final { scan-assembler "vlgvb" } } */ + +signed char +foo(unsigned char uc) +{ + return __builtin_s390_vec_extract((__vector signed char){ 0 }, uc); +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-genbytemask-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-genbytemask-1.c new file mode 100644 index 0000000000..09471f8bc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-genbytemask-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector" } */ + +#include <vecintrin.h> + + +vector unsigned char a, b, c, d; + +int +foo () +{ + a = vec_genmask (0); + b = vec_genmask (65535); + c = vec_genmask (43605); + d = vec_genmask (37830); +} + +/* { dg-final { scan-assembler-times "vzero" 1 } } */ +/* { dg-final { scan-assembler-times "vone" 1 } } */ +/* { dg-final { scan-assembler-times "vgbm\t%v.*,43605" 1 } } */ +/* { dg-final { scan-assembler-times "vgbm\t%v.*,37830" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-genmask-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-genmask-1.c new file mode 100644 index 0000000000..745c1ed6eb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-genmask-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector" } */ + +#include <vecintrin.h> + + +vector unsigned int a, b, c, d, e, f; + +int +foo () +{ + a = vec_genmasks_32 (0, 31); + b = vec_genmasks_32 (0, 0); + c = vec_genmasks_32 (31, 31); + d = vec_genmasks_32 (5, 5); + e = vec_genmasks_32 (31, 0); + f = vec_genmasks_32 (6, 5); +} +/* { dg-final { scan-assembler-times "vone" 1 } } */ +/* { dg-final { scan-assembler-times "vgmf\t%v.*,0,0" 1 } } */ +/* { dg-final { scan-assembler-times "vgmf\t%v.*,31,31" 1 } } */ +/* { dg-final { scan-assembler-times "vgmf\t%v.*,5,5" 1 } } */ +/* { dg-final { scan-assembler-times "vgmf\t%v.*,31,0" 1 } } */ +/* { dg-final { scan-assembler-times "vone" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-lcbb-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-lcbb-1.c new file mode 100644 index 0000000000..3588b61a07 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-lcbb-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector" } */ + +/* { dg-final { scan-assembler-times "\tlcbb\t" 4 } } */ + +#include <vecintrin.h> + +/* CC will be extracted into a GPR and returned. */ +int +foo1 (void *ptr) +{ + return __lcbb (ptr, 64); +} + +int +foo2 (void *ptr) +{ + return __lcbb (ptr, 128) > 16; +} + +int +foo3 (void *ptr) +{ + return __lcbb (ptr, 256) == 16; +} + +int +foo4 (void *ptr) +{ + return __lcbb (ptr, 512) < 16; +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-1.c new file mode 100644 index 0000000000..ca3a943735 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-1.c @@ -0,0 +1,77 @@ +/* Test whether overloading works as expected. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-march=z13 -mzarch -mzvector -fdump-tree-original" } */ + +__vector int var_v4si; +__vector unsigned var_uv4si; +__vector bool var_bv4si; +__vector long long var_v2di; +__vector unsigned long long var_uv2di; +__vector bool long long var_bv2di; +__vector double var_v2df; + +int *intptr; +unsigned *uintptr; +double *dblptr; +unsigned long long ull; +const int *cintptr; +long long* llptr; +unsigned long long* ullptr; + +typedef __vector int v4si; +typedef __vector unsigned int uv4si; + +v4si var2_v4si; +uv4si var2_uv4si; + +void +foo () +{ + __builtin_s390_vec_scatter_element (var_v4si, var_uv4si, intptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var2_v4si, var2_uv4si, intptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_bv4si, var_uv4si, uintptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_uv4si, var_uv4si, uintptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_v2di, var_uv2di, llptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_bv2di, var_uv2di, ullptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_uv2di, var_uv2di, ullptr, (unsigned long long)0); + __builtin_s390_vec_scatter_element (var_v2df, var_uv2di, dblptr, (unsigned long long)0); + + /* While the last argument is a int there is a way to convert it to + unsigned long long, so this variant is supposed to match. */ + __builtin_s390_vec_scatter_element (var_v4si, var_uv4si, intptr, 0); + + __builtin_s390_vec_insert_and_zero (intptr); + __builtin_s390_vec_insert_and_zero (cintptr); + + __builtin_s390_vec_promote ((signed char)1, 1); + __builtin_s390_vec_promote ((unsigned char)1, 1); + __builtin_s390_vec_promote ((short int)1, 1); + __builtin_s390_vec_promote ((unsigned short int)1, 1); + __builtin_s390_vec_promote ((int)1, 1); + __builtin_s390_vec_promote ((unsigned)1, 1); + __builtin_s390_vec_promote ((long long)1, 1); + __builtin_s390_vec_promote ((unsigned long long)1, 1); + __builtin_s390_vec_promote ((double)1, 1); + + /* This is supposed to match vec_promote_s32 */ + __builtin_s390_vec_promote (1, (signed char) -1); + + /* Constants in C usually are considered int. */ + __builtin_s390_vec_promote (1, 1); + + /* And (unsigned) long if they are too big for int. */ + __builtin_s390_vec_promote (1ULL << 32, 1); + __builtin_s390_vec_promote (1LL << 32, 1); +} + +/* { dg-final { scan-tree-dump-times "__builtin_s390_vscef " 5 "original" } } */ +/* { dg-final { scan-tree-dump-times "__builtin_s390_vsceg " 4 "original" } } */ + +/* { dg-final { scan-tree-dump-times "__builtin_s390_vllezf " 2 "original" } } */ + +/* { dg-final { scan-tree-dump-times "__builtin_s390_vlvgb_noin " 2 "original" } } */ +/* { dg-final { scan-tree-dump-times "__builtin_s390_vlvgh_noin " 2 "original" } } */ +/* { dg-final { scan-tree-dump-times "__builtin_s390_vlvgf_noin " 4 "original" } } */ +/* { dg-final { scan-tree-dump-times "__builtin_s390_vlvgg_noin " 4 "original" } } */ +/* { dg-final { scan-tree-dump-times "__builtin_s390_vlvgg_dbl_noin " 1 "original" } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-2.c b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-2.c new file mode 100644 index 0000000000..fd66e02b59 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-2.c @@ -0,0 +1,54 @@ +/* Test whether overloading works as expected. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-march=z13 -mzarch -mzvector" } */ + +__vector int v4si; +__vector unsigned uv4si; +__vector bool bv4si; +__vector long long v2di; +__vector unsigned long long uv2di; +__vector bool long long bv2di; +__vector double v2df; +int *intptr; +unsigned *uintptr; +double *dblptr; +long long ll; +unsigned long long ull; +const int *cintptr; +long long* llptr; +unsigned long long* ullptr; + +void +foo () +{ + __builtin_s390_vec_scatter_element (v4si, uv4si, (int*)0, 0); /* ok */ + __builtin_s390_vec_insert_and_zero (intptr); /* ok */ + + /* The unsigned pointer must not match the signed pointer. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, uintptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* Make sure signed int pointers don't match unsigned int pointers. */ + __builtin_s390_vec_scatter_element (bv4si, uv4si, intptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* Const pointers do not match unqualified operands. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, cintptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* Volatile pointers do not match unqualified operands. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, cintptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* The third operands needs to be double *. */ + __builtin_s390_vec_scatter_element (v2df, uv4si, intptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* This is an ambigious overload. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, 0, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* Pointer to vector must not match. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, &v4si, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + /* Don't accept const int* for int*. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, cintptr, 0); /* { dg-error "invalid parameter combination for intrinsic" } */ + + __builtin_s390_vec_load_pair (ll, ull); /* { dg-error "ambiguous overload for intrinsic" } */ + __builtin_s390_vec_load_pair (ull, ll); /* { dg-error "ambiguous overload for intrinsic" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-3.c b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-3.c new file mode 100644 index 0000000000..761e5b6d36 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-3.c @@ -0,0 +1,19 @@ +/* Check for error messages supposed to be issued during overloading. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-march=z13 -mzarch -mzvector" } */ + +__vector int v4si; +__vector unsigned uv4si; + +int *intptr; +unsigned long long ull; +const unsigned int *ucintptr; + +void +foo () +{ + /* A backend check makes sure the forth operand is a literal. */ + __builtin_s390_vec_gather_element (uv4si, uv4si, ucintptr, 256); /* { dg-error "constant argument 4 for builtin.*is out of range for target type" } */ + __builtin_s390_vec_gather_element (uv4si, uv4si, ucintptr, 5); /* { dg-error "constant argument 4 for builtin.*is out of range" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-4.c b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-4.c new file mode 100644 index 0000000000..66912f9798 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-overloading-4.c @@ -0,0 +1,18 @@ +/* Check for error messages supposed to be issued during builtin expansion. */ + +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-march=z13 -mzarch -mzvector" } */ + +__vector int v4si; +__vector unsigned uv4si; + +int *intptr; +unsigned long long ull; +const unsigned int *ucintptr; + +void +foo () +{ + /* A backend check makes sure the forth operand is a literal. */ + __builtin_s390_vec_scatter_element (v4si, uv4si, intptr, ull); /* { dg-error "constant value required for builtin" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-test-mask-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-test-mask-1.c new file mode 100644 index 0000000000..418d5b20f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-test-mask-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -mzarch -march=z13 -mzvector" } */ + +/* { dg-final { scan-assembler-times "vtm" 2 } } */ +/* { dg-final { scan-assembler-times "ipm" 1 } } */ + +#include <vecintrin.h> + +/* CC will be extracted into a GPR and returned. */ +int +foo (vector unsigned int a, vector unsigned b) +{ + return vec_test_mask (a, b); +} + +extern void baz (void); + +/* In that case the ipm/srl is supposed to optimized out by + combine/s390_canonicalize_comparison. */ +int +bar (vector unsigned int a, vector unsigned b) +{ + if (vec_test_mask (a, b) == 2) + baz (); +} |