diff options
Diffstat (limited to 'gcc/doc/g++.1')
| -rw-r--r-- | gcc/doc/g++.1 | 1297 |
1 files changed, 673 insertions, 624 deletions
diff --git a/gcc/doc/g++.1 b/gcc/doc/g++.1 index 1a7c965a33..3cfb67a46b 100644 --- a/gcc/doc/g++.1 +++ b/gcc/doc/g++.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.29) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -38,8 +46,6 @@ . ds PI \(*p . ds L" `` . ds R" '' -. ds C` -. ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. @@ -47,27 +53,20 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. -.\" -.\" Avoid warning from groff about undefined register 'F'. -.de IX +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -.nr rF 0 -.if \n(.g .if rF .nr rF 1 -.if (\n(rF:(\n(.g==0)) \{ -. if \nF \{ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. nr % 0 +. rr F +.\} +.el \{\ +. de IX .. -. if !\nF==2 \{ -. nr % 0 -. nr F 2 -. \} -. \} .\} -.rr rF .\" .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). .\" Fear. Run. Save yourself. No user-serviceable parts. @@ -133,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2016-04-27" "gcc-6.1.0" "GNU" +.TH GCC 1 "2016-08-22" "gcc-6.2.0" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -154,7 +153,7 @@ Only the most useful options are listed here; see below for the remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. .SH "DESCRIPTION" .IX Header "DESCRIPTION" -When you invoke \s-1GCC,\s0 it normally does preprocessing, compilation, +When you invoke \s-1GCC\s0, it normally does preprocessing, compilation, assembly and linking. The \*(L"overall options\*(R" allow you to stop this process at an intermediate stage. For example, the \fB\-c\fR option says not to run the linker. Then the output consists of object files @@ -173,7 +172,7 @@ that option with all supported languages. .PP The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or -\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a specific version of \s-1GCC.\s0 +\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a specific version of \s-1GCC\s0. When you compile \*(C+ programs, you should invoke \s-1GCC\s0 as \fBg++\fR instead. .PP @@ -195,7 +194,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -1008,14 +1007,15 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions \&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect \&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector -\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mcrypto \-mno\-crypto \-mhtm \-mno\-htm \-mdirect\-move \-mno\-direct\-move \&\-mquad\-memory \-mno\-quad\-memory \&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic \&\-mcompat\-align\-parm \-mno\-compat\-align\-parm \&\-mupper\-regs\-df \-mno\-upper\-regs\-df \-mupper\-regs\-sf \-mno\-upper\-regs\-sf \&\-mupper\-regs \-mno\-upper\-regs \-mmodulo \-mno\-modulo \&\-mfloat128 \-mno\-float128 \-mfloat128\-hardware \-mno\-float128\-hardware -\&\-mpower9\-fusion \-mno\-mpower9\-fusion \-mpower9\-vector \-mno\-power9\-vector\fR +\&\-mpower9\-fusion \-mno\-mpower9\-fusion \-mpower9\-vector \-mno\-power9\-vector +\&\-mpower9\-dform \-mno\-power9\-dform \-mlra \-mno\-lra\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -1202,7 +1202,7 @@ See \s-1RS/6000\s0 and PowerPC Options. .Sp \&\fIzSeries Options\fR See S/390 and zSeries Options. -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1492,7 +1492,7 @@ option. .IX Item "language" Display the options supported for \fIlanguage\fR, where \&\fIlanguage\fR is the name of one of the languages supported in this -version of \s-1GCC.\s0 +version of \s-1GCC\s0. .IP "\fBcommon\fR" 4 .IX Item "common" Display the options that are common to all languages. @@ -1584,7 +1584,7 @@ by \fB\-O3\fR by using: .RE .IP "\fB\-\-version\fR" 4 .IX Item "--version" -Display the version number and copyrights of the invoked \s-1GCC.\s0 +Display the version number and copyrights of the invoked \s-1GCC\s0. .IP "\fB\-pass\-exit\-codes\fR" 4 .IX Item "-pass-exit-codes" Normally the \fBgcc\fR program exits with the code of 1 if any @@ -1628,7 +1628,7 @@ the shared object file is used to identify the plugin for the purposes of argument parsing (See \&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). Each plugin should define the callback functions specified in the -Plugins \s-1API.\s0 +Plugins \s-1API\s0. .IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 .IX Item "-fplugin-arg-name-key=value" Define an argument called \fIkey\fR with a value of \fIvalue\fR @@ -1660,8 +1660,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1684,7 +1684,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1694,8 +1694,8 @@ accepts: In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is equivalent to \fB\-std=c++98\fR. .Sp -This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO -C90 \s0(when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0 +C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the type of system you are using. It also enables the undesirable and @@ -1705,7 +1705,7 @@ the \f(CW\*(C`inline\*(C'\fR keyword. .Sp The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, \&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite -\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO C\s0 program, of +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO\s0 C program, of course, but it is useful to put them in header files that might be included in compilations done with \fB\-ansi\fR. Alternate predefined macros such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or @@ -1722,7 +1722,7 @@ from declaring certain functions or defining certain macros that the programs that might use these names for other things. .Sp Functions that are normally built in but do not have semantics -defined by \s-1ISO C \s0(such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in functions when \fB\-ansi\fR is used. .IP "\fB\-std=\fR" 4 .IX Item "-std=" @@ -1735,9 +1735,9 @@ The compiler can accept several base standards, such as \fBc90\fR or compiler accepts all programs following that standard plus those using \s-1GNU\s0 extensions that do not contradict it. For example, \&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are -incompatible with \s-1ISO C90,\s0 such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in -\&\s-1ISO C90,\s0 such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +\&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR expression. On the other hand, when a \s-1GNU\s0 dialect of a standard is specified, all features supported by the compiler are enabled, even when those features change the meaning of the base standard. As a result, some @@ -1757,11 +1757,11 @@ A value for this option must be provided; possible values are .IP "\fBiso9899:1990\fR" 4 .IX Item "iso9899:1990" .PD -Support all \s-1ISO C90\s0 programs (certain \s-1GNU\s0 extensions that conflict -with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. +Support all \s-1ISO\s0 C90 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. .IP "\fBiso9899:199409\fR" 4 .IX Item "iso9899:199409" -\&\s-1ISO C90\s0 as modified in amendment 1. +\&\s-1ISO\s0 C90 as modified in amendment 1. .IP "\fBc99\fR" 4 .IX Item "c99" .PD 0 @@ -1772,7 +1772,7 @@ with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. .IP "\fBiso9899:199x\fR" 4 .IX Item "iso9899:199x" .PD -\&\s-1ISO C99. \s0 This standard is substantially completely supported, modulo +\&\s-1ISO\s0 C99. This standard is substantially completely supported, modulo bugs and floating-point issues (mainly but not entirely relating to optional C99 features from Annexes F and G). See @@ -1786,7 +1786,7 @@ names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. .IP "\fBiso9899:2011\fR" 4 .IX Item "iso9899:2011" .PD -\&\s-1ISO C11,\s0 the 2011 revision of the \s-1ISO C\s0 standard. This standard is +\&\s-1ISO\s0 C11, the 2011 revision of the \s-1ISO\s0 C standard. This standard is substantially completely supported, modulo bugs, floating-point issues (mainly but not entirely relating to optional C11 features from Annexes F and G) and the optional Annexes K (Bounds-checking @@ -1797,21 +1797,21 @@ interfaces) and L (Analyzability). The name \fBc1x\fR is deprecated. .IP "\fBgnu89\fR" 4 .IX Item "gnu89" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C90 \s0(including some C99 features). +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C90 (including some C99 features). .IP "\fBgnu99\fR" 4 .IX Item "gnu99" .PD 0 .IP "\fBgnu9x\fR" 4 .IX Item "gnu9x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C99. \s0 The name \fBgnu9x\fR is deprecated. +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C99. The name \fBgnu9x\fR is deprecated. .IP "\fBgnu11\fR" 4 .IX Item "gnu11" .PD 0 .IP "\fBgnu1x\fR" 4 .IX Item "gnu1x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C11. \s0 This is the default for C code. +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C11. This is the default for C code. The name \fBgnu1x\fR is deprecated. .IP "\fBc++98\fR" 4 .IX Item "c++98" @@ -1819,7 +1819,7 @@ The name \fBgnu1x\fR is deprecated. .IP "\fBc++03\fR" 4 .IX Item "c++03" .PD -The 1998 \s-1ISO \*(C+\s0 standard plus the 2003 technical corrigendum and some +The 1998 \s-1ISO\s0 \*(C+ standard plus the 2003 technical corrigendum and some additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. .IP "\fBgnu++98\fR" 4 .IX Item "gnu++98" @@ -1834,7 +1834,7 @@ additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. .IP "\fBc++0x\fR" 4 .IX Item "c++0x" .PD -The 2011 \s-1ISO \*(C+\s0 standard plus amendments. +The 2011 \s-1ISO\s0 \*(C+ standard plus amendments. The name \fBc++0x\fR is deprecated. .IP "\fBgnu++11\fR" 4 .IX Item "gnu++11" @@ -1850,7 +1850,7 @@ The name \fBgnu++0x\fR is deprecated. .IP "\fBc++1y\fR" 4 .IX Item "c++1y" .PD -The 2014 \s-1ISO \*(C+\s0 standard plus amendments. +The 2014 \s-1ISO\s0 \*(C+ standard plus amendments. The name \fBc++1y\fR is deprecated. .IP "\fBgnu++14\fR" 4 .IX Item "gnu++14" @@ -1863,7 +1863,7 @@ This is the default for \*(C+ code. The name \fBgnu++1y\fR is deprecated. .IP "\fBc++1z\fR" 4 .IX Item "c++1z" -The next revision of the \s-1ISO \*(C+\s0 standard, tentatively planned for +The next revision of the \s-1ISO\s0 \*(C+ standard, tentatively planned for 2017. Support is highly experimental, and will almost certainly change in incompatible ways in future releases. .IP "\fBgnu++1z\fR" 4 @@ -1925,7 +1925,7 @@ In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since -\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO C99.\s0 +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99. .IP "\fB\-fno\-builtin\fR" 4 .IX Item "-fno-builtin" .PD 0 @@ -1953,7 +1953,7 @@ known not to modify global memory. With the \fB\-fno\-builtin\-\fR\fIfunction\fR option only the built-in function \fIfunction\fR is disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a -function is named that is not built-in in this version of \s-1GCC,\s0 this +function is named that is not built-in in this version of \s-1GCC\s0, this option is ignored. There is no corresponding \&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable built-in functions selectively when using \fB\-fno\-builtin\fR or @@ -2021,7 +2021,7 @@ When the option \fB\-fgnu\-tm\fR is specified, the compiler generates code for the Linux variant of Intel's current Transactional Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is an experimental feature whose interface may change in future versions -of \s-1GCC,\s0 as the official specification changes. Please note that not +of \s-1GCC\s0, as the official specification changes. Please note that not all architectures are supported for this feature. .Sp For more information on \s-1GCC\s0's support for transactional memory, @@ -2058,8 +2058,8 @@ fields declared using a typedef. This is only supported for C, not \*(C+. .IP "\fB\-trigraphs\fR" 4 .IX Item "-trigraphs" -Support \s-1ISO C\s0 trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR -options for strict \s-1ISO C\s0 conformance) implies \fB\-trigraphs\fR. +Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR +options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. .IP "\fB\-traditional\fR" 4 .IX Item "-traditional" .PD 0 @@ -2068,8 +2068,8 @@ options for strict \s-1ISO C\s0 conformance) implies \fB\-trigraphs\fR. .PD Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard C compiler. They are now only supported with the \fB\-E\fR switch. -The preprocessor continues to support a pre-standard mode. See the \s-1GNU -CPP\s0 manual for details. +The preprocessor continues to support a pre-standard mode. See the \s-1GNU\s0 +\&\s-1CPP\s0 manual for details. .IP "\fB\-fcond\-mismatch\fR" 4 .IX Item "-fcond-mismatch" Allow conditional expressions with mismatched types in the second and @@ -2129,8 +2129,8 @@ the native endianness of the target. This option is not supported for \*(C+. \&\fBWarning:\fR the \fB\-fsso\-struct\fR switch causes \s-1GCC\s0 to generate code that is not binary compatible with code generated without it if the specified endianness is not the native endianness of the target. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2142,7 +2142,7 @@ might compile a file \fIfirstClass.C\fR like this: .PP In this example, only \fB\-fstrict\-enums\fR is an option meant only for \*(C+ programs; you can use the other options with any -language supported by \s-1GCC.\s0 +language supported by \s-1GCC\s0. .PP Some options for compiling C programs, such as \fB\-std\fR, are also relevant for \*(C+ programs. @@ -2150,7 +2150,7 @@ relevant for \*(C+ programs. Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: .IP "\fB\-fabi\-version=\fR\fIn\fR" 4 .IX Item "-fabi-version=n" -Use version \fIn\fR of the \*(C+ \s-1ABI. \s0 The default is version 0. +Use version \fIn\fR of the \*(C+ \s-1ABI\s0. The default is version 0. .Sp Version 0 refers to the version conforming most closely to the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0 @@ -2199,7 +2199,7 @@ works around mangling changes by creating an alias with the correct mangled name when defining a symbol with an incorrect mangled name. This switch specifies which \s-1ABI\s0 version to use for the alias. .Sp -With \fB\-fabi\-version=0\fR (the default), this defaults to 8 (\s-1GCC 5\s0 +With \fB\-fabi\-version=0\fR (the default), this defaults to 8 (\s-1GCC\s0 5 compatibility). If another \s-1ABI\s0 version is explicitly selected, this defaults to 0. For compatibility with \s-1GCC\s0 versions 3.2 through 4.9, use \fB\-fabi\-compat\-version=2\fR. @@ -2226,7 +2226,7 @@ exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also .IP "\fB\-fconcepts\fR" 4 .IX Item "-fconcepts" Enable support for the \*(C+ Extensions for Concepts Technical -Specification, \s-1ISO 19217 \s0(2015), which allows code like +Specification, \s-1ISO\s0 19217 (2015), which allows code like .Sp .Vb 2 \& template <class T> concept bool Addable = requires (T t) { t + t; }; @@ -2265,7 +2265,7 @@ Inject friend functions into the enclosing namespace, so that they are visible outside the scope of the class in which they are declared. Friend functions were documented to work this way in the old Annotated \&\*(C+ Reference Manual. -However, in \s-1ISO \*(C+\s0 a friend function that is not declared +However, in \s-1ISO\s0 \*(C+ a friend function that is not declared in an enclosing scope can only be found using argument dependent lookup. \s-1GCC\s0 defaults to the standard behavior. .Sp @@ -2331,7 +2331,7 @@ otherwise be invalid, or have different behavior. .IX Item "-fno-gnu-keywords" Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. -This option is implied by the strict \s-1ISO \*(C+\s0 dialects: \fB\-ansi\fR, +This option is implied by the strict \s-1ISO\s0 \*(C+ dialects: \fB\-ansi\fR, \&\fB\-std=c++98\fR, \fB\-std=c++11\fR, etc. .IP "\fB\-fno\-implicit\-templates\fR" 4 .IX Item "-fno-implicit-templates" @@ -2349,12 +2349,12 @@ controlled by \f(CW\*(C`#pragma implementation\*(C'\fR. This causes linker errors if these functions are not inlined everywhere they are called. .IP "\fB\-fms\-extensions\fR" 4 .IX Item "-fms-extensions" -Disable Wpedantic warnings about constructs used in \s-1MFC,\s0 such as implicit +Disable Wpedantic warnings about constructs used in \s-1MFC\s0, such as implicit int and getting a pointer to member function via non-standard syntax. .IP "\fB\-fno\-nonansi\-builtins\fR" 4 .IX Item "-fno-nonansi-builtins" Disable built-in declarations of functions that are not mandated by -\&\s-1ANSI/ISO C. \s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, \&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. .IP "\fB\-fnothrow\-opt\fR" 4 .IX Item "-fnothrow-opt" @@ -2438,7 +2438,7 @@ warning or error to \fIn\fR. The default value is 10. .IX Item "-ftemplate-depth=n" Set the maximum instantiation depth for template classes to \fIn\fR. A limit on the template instantiation depth is needed to detect -endless recursions during template class instantiation. \s-1ANSI/ISO \*(C+\s0 +endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+ conforming programs must not rely on a maximum depth greater than 17 (changed to 1024 in \*(C+11). The default value is 900, as the compiler can run out of stack space before hitting 1024 in some situations. @@ -2469,7 +2469,7 @@ are taken in different shared objects. The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with \&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection -when used within the \s-1DSO. \s0 Enabling this option can have a dramatic effect +when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect on load and link times of a \s-1DSO\s0 as it massively reduces the size of the dynamic export table when the library makes heavy use of templates. .Sp @@ -2537,9 +2537,9 @@ is used when building the \*(C+ library.) In addition, these optimization, warning, and code generation options have meanings only for \*(C+ programs: .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ it generates code that is probably not compatible with -the vendor-neutral \*(C+ \s-1ABI. \s0 Since G++ now defaults to updating the +the vendor-neutral \*(C+ \s-1ABI\s0. Since G++ now defaults to updating the \&\s-1ABI\s0 with each major release, normally \fB\-Wabi\fR will warn only if there is a check added later in a release series for an \s-1ABI\s0 issue discovered since the initial release. \fB\-Wabi\fR will warn about @@ -2569,7 +2569,7 @@ concerned about the fact that code generated by G++ may not be binary compatible with code generated by other compilers. .Sp Known incompatibilities in \fB\-fabi\-version=2\fR (which was the -default from \s-1GCC 3.4\s0 to 4.9) include: +default from \s-1GCC\s0 3.4 to 4.9) include: .RS 4 .IP "*" 4 A template with a non-type template parameter of reference type was @@ -2597,7 +2597,7 @@ These mangling issues were fixed in \fB\-fabi\-version=5\fR. Scoped enumerators passed as arguments to a variadic function are promoted like unscoped enumerators, causing \f(CW\*(C`va_arg\*(C'\fR to complain. On most targets this does not actually affect the parameter passing -\&\s-1ABI,\s0 as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. +\&\s-1ABI\s0, as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. .Sp Also, the \s-1ABI\s0 changed the mangling of template argument packs, \&\f(CW\*(C`const_cast\*(C'\fR, \f(CW\*(C`static_cast\*(C'\fR, prefix increment/decrement, and @@ -2614,21 +2614,21 @@ When mangling a function type with function-cv-qualifiers, the un-qualified function type was incorrectly treated as a substitution candidate. .Sp -This was fixed in \fB\-fabi\-version=8\fR, the default for \s-1GCC 5.1.\s0 +This was fixed in \fB\-fabi\-version=8\fR, the default for \s-1GCC\s0 5.1. .IP "*" 4 \&\f(CW\*(C`decltype(nullptr)\*(C'\fR incorrectly had an alignment of 1, leading to unaligned accesses. Note that this did not affect the \s-1ABI\s0 of a function with a \f(CW\*(C`nullptr_t\*(C'\fR parameter, as parameters have a minimum alignment. .Sp -This was fixed in \fB\-fabi\-version=9\fR, the default for \s-1GCC 5.2.\s0 +This was fixed in \fB\-fabi\-version=9\fR, the default for \s-1GCC\s0 5.2. .IP "*" 4 Target-specific attributes that affect the identity of a type, such as ia32 calling conventions on a function type (stdcall, regparm, etc.), did not affect the mangled name, leading to name collisions when function pointers were used as template arguments. .Sp -This was fixed in \fB\-fabi\-version=10\fR, the default for \s-1GCC 6.1.\s0 +This was fixed in \fB\-fabi\-version=10\fR, the default for \s-1GCC\s0 6.1. .RE .RS 4 .Sp @@ -2753,7 +2753,7 @@ This is on by default for all pre\-\*(C+11 dialects and all \s-1GNU\s0 dialects: \&\fB\-std=c++98\fR, \fB\-std=gnu++98\fR, \fB\-std=gnu++11\fR, \&\fB\-std=gnu++14\fR. This option is off by default -for \s-1ISO \*(C+11\s0 onwards (\fB\-std=c++11\fR, ...). +for \s-1ISO\s0 \*(C+11 onwards (\fB\-std=c++11\fR, ...). .PP The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. .IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 @@ -2853,34 +2853,34 @@ unsignedness, but the standard mandates the current behavior. .IX Item "-Wtemplates ( and Objective- only)" Warn when a primary template declaration is encountered. Some coding rules disallow templates, and this may be used to enforce that rule. -The warning is inactive inside a system header file, such as the \s-1STL,\s0 so -one can still use the \s-1STL. \s0 One may also instantiate or specialize +The warning is inactive inside a system header file, such as the \s-1STL\s0, so +one can still use the \s-1STL\s0. One may also instantiate or specialize templates. .IP "\fB\-Wmultiple\-inheritance\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wmultiple-inheritance ( and Objective- only)" Warn when a class is defined with multiple direct base classes. Some coding rules disallow multiple inheritance, and this may be used to enforce that rule. The warning is inactive inside a system header file, -such as the \s-1STL,\s0 so one can still use the \s-1STL. \s0 One may also define +such as the \s-1STL\s0, so one can still use the \s-1STL\s0. One may also define classes that indirectly use multiple inheritance. .IP "\fB\-Wvirtual\-inheritance\fR" 4 .IX Item "-Wvirtual-inheritance" Warn when a class is defined with a virtual direct base classe. Some coding rules disallow multiple inheritance, and this may be used to enforce that rule. The warning is inactive inside a system header file, -such as the \s-1STL,\s0 so one can still use the \s-1STL. \s0 One may also define +such as the \s-1STL\s0, so one can still use the \s-1STL\s0. One may also define classes that indirectly use virtual inheritance. .IP "\fB\-Wnamespaces\fR" 4 .IX Item "-Wnamespaces" Warn when a namespace definition is opened. Some coding rules disallow namespaces, and this may be used to enforce that rule. The warning is -inactive inside a system header file, such as the \s-1STL,\s0 so one can still -use the \s-1STL. \s0 One may also use using directives and qualified names. +inactive inside a system header file, such as the \s-1STL\s0, so one can still +use the \s-1STL\s0. One may also use using directives and qualified names. .IP "\fB\-Wno\-terminate\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wno-terminate ( and Objective- only)" Disable the warning about a throw-expression that will immediately result in a call to \f(CW\*(C`terminate\*(C'\fR. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2896,7 +2896,7 @@ For example, you might compile a file \fIsome_class.m\fR like this: .PP In this example, \fB\-fgnu\-runtime\fR is an option meant only for Objective-C and Objective\-\*(C+ programs; you can use the other options with -any language supported by \s-1GCC.\s0 +any language supported by \s-1GCC\s0. .PP Note that since Objective-C is an extension of the C language, Objective-C compilations may also use options specific to the C front-end (e.g., @@ -2921,7 +2921,7 @@ runtime. This is the default for most types of systems. .IP "\fB\-fnext\-runtime\fR" 4 .IX Item "-fnext-runtime" Generate output compatible with the NeXT runtime. This is the default -for NeXT-based systems, including Darwin and Mac \s-1OS X. \s0 The macro +for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X. The macro \&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is used. .IP "\fB\-fno\-nil\-receivers\fR" 4 @@ -2938,7 +2938,7 @@ This option is currently supported only for the NeXT runtime. In that case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for properties and other Objective-C 2.0 additions. Version 1 is the traditional (32\-bit) \s-1ABI\s0 with support for properties and other -Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI. \s0 If +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI\s0. If nothing is specified, the default is Version 0 on 32\-bit target machines, and Version 2 on 64\-bit target machines. .IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 @@ -2962,7 +2962,7 @@ by the runtime immediately after a new object instance is allocated; the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods are invoked immediately before the runtime deallocates an object instance. .Sp -As of this writing, only the NeXT runtime on Mac \s-1OS X 10.4\s0 and later has +As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. .IP "\fB\-fobjc\-direct\-dispatch\fR" 4 @@ -2977,7 +2977,7 @@ is required to use the Objective-C keywords \f(CW@try\fR, \&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and \&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 runtime and the NeXT runtime (but not available in conjunction with -the NeXT runtime on Mac \s-1OS X 10.2\s0 and earlier). +the NeXT runtime on Mac \s-1OS\s0 X 10.2 and earlier). .IP "\fB\-fobjc\-gc\fR" 4 .IX Item "-fobjc-gc" Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ @@ -2986,23 +2986,23 @@ programs. This option is only available with the NeXT runtime; the does not require special compiler flags. .IP "\fB\-fobjc\-nilcheck\fR" 4 .IX Item "-fobjc-nilcheck" -For the NeXT runtime with version 2 of the \s-1ABI,\s0 check for a nil +For the NeXT runtime with version 2 of the \s-1ABI\s0, check for a nil receiver in method invocations before doing the actual method call. This is the default and can be disabled using \&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never checked for nil in this way no matter what this flag is set to. Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older -version of the NeXT runtime \s-1ABI,\s0 is used. +version of the NeXT runtime \s-1ABI\s0, is used. .IP "\fB\-fobjc\-std=objc1\fR" 4 .IX Item "-fobjc-std=objc1" Conform to the language syntax of Objective-C 1.0, the language -recognized by \s-1GCC 4.0. \s0 This only affects the Objective-C additions to +recognized by \s-1GCC\s0 4.0. This only affects the Objective-C additions to the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, which is controlled by the separate C/\*(C+ dialect option flags. When this option is used with the Objective-C or Objective\-\*(C+ compiler, -any Objective-C syntax that is not recognized by \s-1GCC 4.0\s0 is rejected. +any Objective-C syntax that is not recognized by \s-1GCC\s0 4.0 is rejected. This is useful if you need to make sure that your Objective-C code can -be compiled with older versions of \s-1GCC.\s0 +be compiled with older versions of \s-1GCC\s0. .IP "\fB\-freplace\-objc\-classes\fR" 4 .IX Item "-freplace-objc-classes" Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in @@ -3011,7 +3011,7 @@ run time instead. This is used in conjunction with the Fix-and-Continue debugging mode, where the object file in question may be recompiled and dynamically reloaded in the course of program execution, without the need to restart the program itself. Currently, Fix-and-Continue functionality -is only available in conjunction with the NeXT runtime on Mac \s-1OS X 10.3\s0 +is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 and later. .IP "\fB\-fzero\-link\fR" 4 .IX Item "-fzero-link" @@ -3090,7 +3090,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -3212,14 +3212,14 @@ information. The source line is truncated to \fIn\fR characters, if the \fB\-fmessage\-length=n\fR option is given. When the output is done to the terminal, the width is limited to the width given by the \&\fB\s-1COLUMNS\s0\fR environment variable or, if not set, to the terminal width. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there may have been an error. .PP The following language-independent options do not enable specific -warnings but control the kinds of diagnostics produced by \s-1GCC.\s0 +warnings but control the kinds of diagnostics produced by \s-1GCC\s0. .IP "\fB\-fsyntax\-only\fR" 4 .IX Item "-fsyntax-only" Check the code for syntax errors, but don't do anything beyond that. @@ -3294,14 +3294,14 @@ warns that an unrecognized option is present. .IP "\fB\-pedantic\fR" 4 .IX Item "-pedantic" .PD -Issue all the warnings demanded by strict \s-1ISO C\s0 and \s-1ISO \*(C+\s0; +Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+; reject all programs that use forbidden extensions, and some other -programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+. \s0 For \s-1ISO C,\s0 follows the -version of the \s-1ISO C\s0 standard specified by any \fB\-std\fR option used. +programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the +version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used. .Sp -Valid \s-1ISO C\s0 and \s-1ISO \*(C+\s0 programs should compile properly with or without +Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without this option (though a rare few require \fB\-ansi\fR or a -\&\fB\-std\fR option specifying the required version of \s-1ISO C\s0). However, +\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However, without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ features are supported as well. With this option, they are rejected. .Sp @@ -3311,24 +3311,24 @@ warnings are also disabled in the expression that follows \&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use these escape routes; application programs should avoid them. .Sp -Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO -C\s0 conformance. They soon find that it does not do quite what they want: +Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO\s0 +C conformance. They soon find that it does not do quite what they want: it finds some non-ISO practices, but not all\-\-\-only those for which -\&\s-1ISO C \s0\fIrequires\fR a diagnostic, and some others for which +\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which diagnostics have been added. .Sp -A feature to report any failure to conform to \s-1ISO C\s0 might be useful in +A feature to report any failure to conform to \s-1ISO\s0 C might be useful in some instances, but would require considerable additional work and would be quite different from \fB\-Wpedantic\fR. We don't have plans to support such a feature in the near future. .Sp Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a -corresponding \fIbase standard\fR, the version of \s-1ISO C\s0 on which the \s-1GNU\s0 +corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0 extended dialect is based. Warnings from \fB\-Wpedantic\fR are given where they are required by the base standard. (It does not make sense -for such warnings to be given only for features not in the specified \s-1GNU -C\s0 dialect, since by definition the \s-1GNU\s0 dialects of C include all +for such warnings to be given only for features not in the specified \s-1GNU\s0 +C dialect, since by definition the \s-1GNU\s0 dialects of C include all features the compiler supports with the given option, and there would be nothing to warn about.) .IP "\fB\-pedantic\-errors\fR" 4 @@ -3511,7 +3511,7 @@ functions without the attribute specified are disabled by \&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. .Sp The formats are checked against the format features supported by \s-1GNU\s0 -libc version 2.2. These include all \s-1ISO C90\s0 and C99 features, as well +libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 extensions. Other library implementations may not support all these features; \s-1GCC\s0 does not support warning about features that go beyond a @@ -3641,18 +3641,18 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier -such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO C\s0 such a type qualifier has no effect, +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. -\&\s-1ISO C\s0 prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +\&\s-1ISO\s0 C prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function definitions, so such return types always receive a warning even without this option. .Sp This warning is also enabled by \fB\-Wextra\fR. .IP "\fB\-Wignored\-attributes\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-attributes (C and only)" +.IX Item "-Wignored-attributes (C and only)" Warn when an attribute is ignored. This is different from the \&\fB\-Wattributes\fR option in that it warns whenever the compiler decides to drop an attribute, not that the attribute is either unknown, used in a @@ -3665,7 +3665,7 @@ arguments, two, or three arguments of appropriate types. This warning is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR or \fB\-Wpedantic\fR. .IP "\fB\-Wmisleading\-indentation\fR (C and \*(C+ only)" 4 -.IX Item "-Wmisleading-indentation (C and only)" +.IX Item "-Wmisleading-indentation (C and only)" Warn when the indentation of the code does not reflect the block structure. Specifically, a warning is issued for \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR, \f(CW\*(C`while\*(C'\fR, and \&\f(CW\*(C`for\*(C'\fR clauses with a guarded statement that does not use braces, @@ -3904,9 +3904,9 @@ expression to a type other than \f(CW\*(C`bool\*(C'\fR. For example: .Sp This warning is enabled by default for C and \*(C+ programs. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR -built-in functions are used. These functions changed semantics in \s-1GCC 4.4.\s0 +built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 .IX Item "-Wtrigraphs" Warn if any trigraphs are encountered that might change the meaning of @@ -3943,7 +3943,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4097,7 +4097,7 @@ This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. .IP "\fB\-Wunknown\-pragmas\fR" 4 .IX Item "-Wunknown-pragmas" Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by -\&\s-1GCC. \s0 If this command-line option is used, warnings are even issued +\&\s-1GCC\s0. If this command-line option is used, warnings are even issued for unknown pragmas in system header files. This is not the case if the warnings are only enabled by the \fB\-Wall\fR command-line option. .IP "\fB\-Wno\-pragmas\fR" 4 @@ -4401,13 +4401,13 @@ probably mistaken. .IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 .IX Item "-Wtraditional (C and Objective-C only)" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C equivalent, and/or problematic constructs that should be avoided. .RS 4 .IP "*" 4 Macro parameters that appear within string literals in the macro body. In traditional C macro replacement takes place within string literals, -but in \s-1ISO C\s0 it does not. +but in \s-1ISO\s0 C it does not. .IP "*" 4 In traditional C, some preprocessor directives did not exist. Traditional preprocessors only considered a line to be a directive @@ -4462,9 +4462,9 @@ versa. The absence of these prototypes when compiling with traditional C causes serious problems. This is a subset of the possible conversion warnings; for the full set use \fB\-Wtraditional\-conversion\fR. .IP "*" 4 -Use of \s-1ISO C\s0 style function definitions. This warning intentionally is +Use of \s-1ISO\s0 C style function definitions. This warning intentionally is \&\fInot\fR issued for prototype declarations or variadic functions -because these \s-1ISO C\s0 features appear in your code when using +because these \s-1ISO\s0 C features appear in your code when using libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and \&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions because that feature is already a \s-1GCC\s0 extension and thus not relevant to @@ -4482,8 +4482,8 @@ except when the same as the default promotion. .IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 .IX Item "-Wdeclaration-after-statement (C and Objective-C only)" Warn when a declaration is found after a statement in a block. This -construct, known from \*(C+, was introduced with \s-1ISO C99\s0 and is by default -allowed in \s-1GCC. \s0 It is not supported by \s-1ISO C90. \s0 +construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default +allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90. .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" Warn if an undefined identifier is evaluated in an \f(CW\*(C`#if\*(C'\fR directive. @@ -4615,7 +4615,7 @@ use of the flexible member array extension to avoid the warning at level 2. .IP "\fB\-Wpointer\-arith\fR" 4 .IX Item "-Wpointer-arith" Warn about anything that depends on the \*(L"size of\*(R" a function type or -of \f(CW\*(C`void\*(C'\fR. \s-1GNU C\s0 assigns these types a size of 1, for +of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers to functions. In \*(C+, warn also when an arithmetic operation involves \&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-Wpedantic\fR. @@ -4633,14 +4633,14 @@ For example, warn if a call to a function returning an integer type is cast to a pointer type. .IP "\fB\-Wc90\-c99\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc90-c99-compat (C and Objective-C only)" -Warn about features not present in \s-1ISO C90,\s0 but present in \s-1ISO C99.\s0 +Warn about features not present in \s-1ISO\s0 C90, but present in \s-1ISO\s0 C99. For instance, warn about use of variable length arrays, \f(CW\*(C`long long\*(C'\fR type, \f(CW\*(C`bool\*(C'\fR type, compound literals, designated initializers, and so on. This option is independent of the standards mode. Warnings are disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. .IP "\fB\-Wc99\-c11\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc99-c11-compat (C and Objective-C only)" -Warn about features not present in \s-1ISO C99,\s0 but present in \s-1ISO C11.\s0 +Warn about features not present in \s-1ISO\s0 C99, but present in \s-1ISO\s0 C11. For instance, warn about use of anonymous structures and unions, \&\f(CW\*(C`_Atomic\*(C'\fR type qualifier, \f(CW\*(C`_Thread_local\*(C'\fR storage-class specifier, \&\f(CW\*(C`_Alignas\*(C'\fR specifier, \f(CW\*(C`Alignof\*(C'\fR operator, \f(CW\*(C`_Generic\*(C'\fR keyword, @@ -4648,19 +4648,19 @@ and so on. This option is independent of the standards mode. Warnings are disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. .IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc++-compat (C and Objective-C only)" -Warn about \s-1ISO C\s0 constructs that are outside of the common subset of -\&\s-1ISO C\s0 and \s-1ISO \*(C+,\s0 e.g. request for implicit conversion from +Warn about \s-1ISO\s0 C constructs that are outside of the common subset of +\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from \&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. .IP "\fB\-Wc++11\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wc++11-compat ( and Objective- only)" -Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 1998\s0 -and \s-1ISO \*(C+ 2011,\s0 e.g., identifiers in \s-1ISO \*(C+ 1998\s0 that are keywords -in \s-1ISO \*(C+ 2011. \s0 This warning turns on \fB\-Wnarrowing\fR and is +Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 1998 +and \s-1ISO\s0 \*(C+ 2011, e.g., identifiers in \s-1ISO\s0 \*(C+ 1998 that are keywords +in \s-1ISO\s0 \*(C+ 2011. This warning turns on \fB\-Wnarrowing\fR and is enabled by \fB\-Wall\fR. .IP "\fB\-Wc++14\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wc++14-compat ( and Objective- only)" -Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2011\s0 -and \s-1ISO \*(C+ 2014. \s0 This warning is enabled by \fB\-Wall\fR. +Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 2011 +and \s-1ISO\s0 \*(C+ 2014. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wcast\-qual\fR" 4 .IX Item "-Wcast-qual" Warn whenever a pointer is cast so as to remove a type qualifier from @@ -4984,26 +4984,26 @@ Usually they indicate a typo in the user's code, as they have implementation-defined values, and should not be used in portable code. .IP "\fB\-Wnormalized\fR[\fB=\fR<\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR>]" 4 .IX Item "-Wnormalized[=<none|id|nfc|nfkc>]" -In \s-1ISO C\s0 and \s-1ISO \*(C+,\s0 two identifiers are different if they are +In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are different sequences of characters. However, sometimes when characters outside the basic \s-1ASCII\s0 character set are used, you can have two different character sequences that look the same. To avoid confusion, -the \s-1ISO 10646\s0 standard sets out some \fInormalization rules\fR which +the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which when applied ensure that two sequences that look the same are turned into the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that have not been normalized; this option controls that warning. .Sp -There are four levels of warning supported by \s-1GCC. \s0 The default is +There are four levels of warning supported by \s-1GCC\s0. The default is \&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is -not in the \s-1ISO 10646 \*(L"C\*(R"\s0 normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the recommended form for most uses. It is equivalent to \&\fB\-Wnormalized\fR. .Sp Unfortunately, there are some characters allowed in identifiers by -\&\s-1ISO C\s0 and \s-1ISO \*(C+\s0 that, when turned into \s-1NFC,\s0 are not allowed in +\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+ that, when turned into \s-1NFC\s0, are not allowed in identifiers. That is, there's no way to use these symbols in portable -\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC. -\&\s0\fB\-Wnormalized=id\fR suppresses the warning for these characters. +\&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0. +\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. It is hoped that future versions of the standards involved will correct this, which is why this option is not the default. .Sp @@ -5013,11 +5013,11 @@ only do this if you are using some other normalization scheme (like \&\*(L"D\*(R"), because otherwise you can easily create bugs that are literally impossible to see. .Sp -Some characters in \s-1ISO 10646\s0 have distinct meanings but look identical +Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical in some fonts or display methodologies, especially once formatting has -been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT LATIN SMALL -LETTER N\*(R",\s0 displays just like a regular \f(CW\*(C`n\*(C'\fR that has been -placed in a superscript. \s-1ISO 10646\s0 defines the \fI\s-1NFKC\s0\fR +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0 +\&\s-1LETTER\s0 N\*(R", displays just like a regular \f(CW\*(C`n\*(C'\fR that has been +placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR normalization scheme to convert all these into a standard form as well, and \s-1GCC\s0 warns if your code is not in \s-1NFKC\s0 if you use \&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning @@ -5079,9 +5079,9 @@ have the packed attribute: .IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 .IX Item "-Wpacked-bitfield-compat" The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute -on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC 4.4\s0 but +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC\s0 4.4 but the change can lead to differences in the structure layout. \s-1GCC\s0 -informs you when the offset of such a field has changed in \s-1GCC 4.4.\s0 +informs you when the offset of such a field has changed in \s-1GCC\s0 4.4. For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR and \f(CW\*(C`b\*(C'\fR in this structure: .Sp @@ -5128,7 +5128,7 @@ warnings produced by \fB\-Winline\fR to appear or disappear. .IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wno-invalid-offsetof ( and Objective- only)" Suppress warnings from applying the \f(CW\*(C`offsetof\*(C'\fR macro to a non-POD -type. According to the 2014 \s-1ISO \*(C+\s0 standard, applying \f(CW\*(C`offsetof\*(C'\fR +type. According to the 2014 \s-1ISO\s0 \*(C+ standard, applying \f(CW\*(C`offsetof\*(C'\fR to a non-standard-layout type is undefined. In existing \*(C+ implementations, however, \f(CW\*(C`offsetof\*(C'\fR typically gives meaningful results. This flag is for users who are aware that they are @@ -5153,12 +5153,12 @@ the search path but can't be used. .IP "\fB\-Wlong\-long\fR" 4 .IX Item "-Wlong-long" Warn if \f(CW\*(C`long long\*(C'\fR type is used. This is enabled by either -\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO C90\s0 and \*(C+98 +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98 modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. .IP "\fB\-Wvariadic\-macros\fR" 4 .IX Item "-Wvariadic-macros" -Warn if variadic macros are used in \s-1ISO C90\s0 mode, or if the \s-1GNU\s0 -alternate syntax is used in \s-1ISO C99\s0 mode. This is enabled by either +Warn if variadic macros are used in \s-1ISO\s0 C90 mode, or if the \s-1GNU\s0 +alternate syntax is used in \s-1ISO\s0 C99 mode. This is enabled by either \&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR. To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR. .IP "\fB\-Wvarargs\fR" 4 @@ -5222,7 +5222,7 @@ standard's minimum limit, but very portable programs should avoid using longer strings. .Sp The limit applies \fIafter\fR string constant concatenation, and does -not count the trailing \s-1NUL. \s0 In C90, the limit was 509 characters; in +not count the trailing \s-1NUL\s0. In C90, the limit was 509 characters; in C99, it was raised to 4095. \*(C+98 does not specify a normative minimum maximum, so we do not diagnose overlength strings in \*(C+. .Sp @@ -5244,7 +5244,7 @@ attribute. .IX Item "-Whsa" Issue a warning when \s-1HSAIL\s0 cannot be emitted for the compiled function or OpenMP construct. -.SS "Options for Debugging Your Program" +.Sh "Options for Debugging Your Program" .IX Subsection "Options for Debugging Your Program" To tell \s-1GCC\s0 to emit extra information for use by a debugger, in almost all cases you need only to add \fB\-g\fR to your other options. @@ -5267,7 +5267,7 @@ information useful for debugging do not run at all, so that .IP "\fB\-g\fR" 4 .IX Item "-g" Produce debugging information in the operating system's native format -(stabs, \s-1COFF, XCOFF,\s0 or \s-1DWARF\s0). \s-1GDB\s0 can work with this debugging +(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0). \s-1GDB\s0 can work with this debugging information. .Sp On most systems that use stabs format, \fB\-g\fR enables use of extra @@ -5279,8 +5279,8 @@ to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, \&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). .IP "\fB\-ggdb\fR" 4 .IX Item "-ggdb" -Produce debugging information for use by \s-1GDB. \s0 This means to use the -most expressive format available (\s-1DWARF,\s0 stabs, or the native format +Produce debugging information for use by \s-1GDB\s0. This means to use the +most expressive format available (\s-1DWARF\s0, stabs, or the native format if neither of those are supported), including \s-1GDB\s0 extensions if at all possible. .IP "\fB\-gdwarf\fR" 4 @@ -5294,22 +5294,22 @@ The value of \fIversion\fR may be either 2, 3, 4 or 5; the default version for most targets is 4. \s-1DWARF\s0 Version 5 is only experimental. .Sp Note that with \s-1DWARF\s0 Version 2, some ports require and always -use some non-conflicting \s-1DWARF 3\s0 extensions in the unwind tables. +use some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables. .Sp -Version 4 may require \s-1GDB 7.0\s0 and \fB\-fvar\-tracking\-assignments\fR +Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR for maximum benefit. .Sp \&\s-1GCC\s0 no longer supports \s-1DWARF\s0 Version 1, which is substantially different than Version 2 and later. For historical reasons, some other DWARF-related options (including \fB\-feliminate\-dwarf2\-dups\fR and \fB\-fno\-dwarf2\-cfi\-asm\fR) retain a reference to \s-1DWARF\s0 Version 2 -in their names, but apply to all currently-supported versions of \s-1DWARF.\s0 +in their names, but apply to all currently-supported versions of \s-1DWARF\s0. .IP "\fB\-gstabs\fR" 4 .IX Item "-gstabs" Produce debugging information in stabs format (if that is supported), without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 -systems. On \s-1MIPS,\s0 Alpha and System V Release 4 systems this option -produces stabs debugging output that is not understood by \s-1DBX\s0 or \s-1SDB.\s0 +systems. On \s-1MIPS\s0, Alpha and System V Release 4 systems this option +produces stabs debugging output that is not understood by \s-1DBX\s0 or \s-1SDB\s0. On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. .IP "\fB\-gstabs+\fR" 4 .IX Item "-gstabs+" @@ -5325,7 +5325,7 @@ System V Release 4. .IP "\fB\-gxcoff\fR" 4 .IX Item "-gxcoff" Produce debugging information in \s-1XCOFF\s0 format (if that is supported). -This is the format used by the \s-1DBX\s0 debugger on \s-1IBM RS/6000\s0 systems. +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems. .IP "\fB\-gxcoff+\fR" 4 .IX Item "-gxcoff+" Produce debugging information in \s-1XCOFF\s0 format (if that is supported), @@ -5369,7 +5369,7 @@ you use \fB\-g3\fR. \&\fB\-gdwarf\fR does not accept a concatenated debug level, to avoid confusion with \fB\-gdwarf\-\fR\fIlevel\fR. Instead use an additional \fB\-g\fR\fIlevel\fR option to change the -debug level for \s-1DWARF.\s0 +debug level for \s-1DWARF\s0. .IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 .IX Item "-feliminate-unused-debug-symbols" Produce debugging information in stabs format (if that is supported), @@ -5422,7 +5422,7 @@ be useful, this option requires a debugger capable of reading \fI.dwo\fR files. .IP "\fB\-gpubnames\fR" 4 .IX Item "-gpubnames" -Generate \s-1DWARF \s0\f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections. +Generate \s-1DWARF\s0 \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections. .IP "\fB\-ggnu\-pubnames\fR" 4 .IX Item "-ggnu-pubnames" Generate \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections in a format @@ -5550,7 +5550,7 @@ This option works only with \s-1DWARF\s0 debug output. .IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 .IX Item "-fno-dwarf2-cfi-asm" Emit \s-1DWARF\s0 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section -instead of using \s-1GAS \s0\f(CW\*(C`.cfi_*\*(C'\fR directives. +instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. .IP "\fB\-fno\-eliminate\-unused\-debug\-types\fR" 4 .IX Item "-fno-eliminate-unused-debug-types" Normally, when producing \s-1DWARF\s0 output, \s-1GCC\s0 avoids producing debug symbol @@ -5562,7 +5562,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -5761,7 +5761,7 @@ function calls and pops them all at once. Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. .IP "\fB\-fforward\-propagate\fR" 4 .IX Item "-fforward-propagate" -Perform a forward propagation pass on \s-1RTL. \s0 The pass tries to combine two +Perform a forward propagation pass on \s-1RTL\s0. The pass tries to combine two instructions and checks if the result can be simplified. If loop unrolling is active, two passes are performed and the second is scheduled after loop unrolling. @@ -5787,7 +5787,7 @@ restore frame pointers; it also makes an extra register available in many functions. \fBIt also makes debugging impossible on some machines.\fR .Sp -On some machines, such as the \s-1VAX,\s0 this flag has no effect, because +On some machines, such as the \s-1VAX\s0, this flag has no effect, because the standard calling sequence automatically handles the frame pointer and nothing is saved by pretending it doesn't exist. The machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls @@ -5912,7 +5912,7 @@ attribute or declspec In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR into the object file, even if the function has been inlined into all of its callers. This switch does not affect functions using the -\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90. \s0 In \*(C+, emit any and all +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C90. In \*(C+, emit any and all inline functions into the object file. .IP "\fB\-fkeep\-static\-functions\fR" 4 .IX Item "-fkeep-static-functions" @@ -5986,7 +5986,7 @@ The default is \fB\-ffunction\-cse\fR .IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 .IX Item "-fno-zero-initialized-in-bss" If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that -are initialized to zero into \s-1BSS. \s0 This can save space in the resulting +are initialized to zero into \s-1BSS\s0. This can save space in the resulting code. .Sp This option turns off this behavior because some programs explicitly @@ -6114,11 +6114,11 @@ instructions to support this. Enabled by default at \fB\-O\fR and higher on architectures that support this. .IP "\fB\-fdce\fR" 4 .IX Item "-fdce" -Perform dead code elimination (\s-1DCE\s0) on \s-1RTL.\s0 +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL\s0. Enabled by default at \fB\-O\fR and higher. .IP "\fB\-fdse\fR" 4 .IX Item "-fdse" -Perform dead store elimination (\s-1DSE\s0) on \s-1RTL.\s0 +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL\s0. Enabled by default at \fB\-O\fR and higher. .IP "\fB\-fif\-conversion\fR" 4 .IX Item "-fif-conversion" @@ -6161,8 +6161,8 @@ Note however that in some environments this assumption is not true. Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization for programs that depend on that behavior. .Sp -This option is enabled by default on most targets. On Nios \s-1II ELF,\s0 it -defaults to off. On \s-1AVR\s0 and \s-1CR16,\s0 this option is completely disabled. +This option is enabled by default on most targets. On Nios \s-1II\s0 \s-1ELF\s0, it +defaults to off. On \s-1AVR\s0 and \s-1CR16\s0, this option is completely disabled. .Sp Passes that use the dataflow information are enabled independently at different optimization levels. @@ -6281,7 +6281,7 @@ pseudo-register that does not get a hard register gets a separate stack slot, and as a result function stack frames are larger. .IP "\fB\-flra\-remat\fR" 4 .IX Item "-flra-remat" -Enable CFG-sensitive rematerialization in \s-1LRA. \s0 Instead of loading +Enable CFG-sensitive rematerialization in \s-1LRA\s0. Instead of loading values of spilled pseudos, \s-1LRA\s0 tries to rematerialize (recalculate) values if it is profitable. .Sp @@ -6440,9 +6440,9 @@ When pipelining loops during selective scheduling, also pipeline outer loops. This option has no effect unless \fB\-fsel\-sched\-pipelining\fR is turned on. .IP "\fB\-fsemantic\-interposition\fR" 4 .IX Item "-fsemantic-interposition" -Some object formats, like \s-1ELF,\s0 allow interposing of symbols by the +Some object formats, like \s-1ELF\s0, allow interposing of symbols by the dynamic linker. -This means that for symbols exported from the \s-1DSO,\s0 the compiler cannot perform +This means that for symbols exported from the \s-1DSO\s0, the compiler cannot perform interprocedural propagation, inlining and other optimizations in anticipation that the function or variable in question may change. While this feature is useful, for example, to rewrite memory allocation functions by a debugging @@ -6512,7 +6512,7 @@ at \fB\-O\fR and higher. Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions that are computed on all paths leading to the redundant computation. -This analysis is faster than \s-1PRE,\s0 though it exposes fewer redundancies. +This analysis is faster than \s-1PRE\s0, though it exposes fewer redundancies. This flag is enabled by default at \fB\-O\fR and higher. .IP "\fB\-ftree\-phiprop\fR" 4 .IX Item "-ftree-phiprop" @@ -6583,7 +6583,7 @@ The optimization reduces code size and may disturb unwind stacks by replacing a function by equivalent one with a different name. The optimization works more effectively with link time optimization enabled. .Sp -Nevertheless the behavior is similar to Gold Linker \s-1ICF\s0 optimization, \s-1GCC ICF\s0 +Nevertheless the behavior is similar to Gold Linker \s-1ICF\s0 optimization, \s-1GCC\s0 \s-1ICF\s0 works on different levels and thus the optimizations are not same \- there are equivalences that are found only by \s-1GCC\s0 and equivalences found only by Gold. .Sp @@ -6625,7 +6625,7 @@ sign operations if the sign of a value never matters. The flag is enabled by default at \fB\-O\fR and higher. .IP "\fB\-fssa\-phiopt\fR" 4 .IX Item "-fssa-phiopt" -Perform pattern matching on \s-1SSA PHI\s0 nodes to optimize conditional +Perform pattern matching on \s-1SSA\s0 \s-1PHI\s0 nodes to optimize conditional code. This pass is enabled by default at \fB\-O\fR and higher. .IP "\fB\-ftree\-switch\-conversion\fR" 4 .IX Item "-ftree-switch-conversion" @@ -6694,7 +6694,7 @@ transformation infrastructure. Enable the identity transformation for graphite. For every SCoP we generate the polyhedral representation and transform it back to gimple. Using \&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the -\&\s-1GIMPLE \-\s0> \s-1GRAPHITE \-\s0> \s-1GIMPLE\s0 transformation. Some minimal optimizations +\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations are also performed by the code generator isl, like index splitting and dead code elimination in loops. .IP "\fB\-floop\-nest\-optimize\fR" 4 @@ -7192,7 +7192,7 @@ targets. Constructs webs as commonly used for register allocation purposes and assign each web individual pseudo register. This allows the register allocation pass to operate on pseudos directly, but also strengthens several other optimization -passes, such as \s-1CSE,\s0 loop optimizer and trivial dead code remover. It can, +passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can, however, make debugging impossible, since variables no longer stay in a \&\*(L"home register\*(R". .Sp @@ -7210,7 +7210,7 @@ information. .IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 .IX Item "-flto[=n]" This option runs the standard link-time optimizer. When invoked -with source code, it generates \s-1GIMPLE \s0(one of \s-1GCC\s0's internal +with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal representations) and writes it to special \s-1ELF\s0 sections in the object file. When the object files are linked together, all the function bodies are read from these \s-1ELF\s0 sections and instantiated as if they @@ -7333,7 +7333,7 @@ over \fB\-ffp\-contract=fast\fR. You can override them at link time. .Sp If \s-1LTO\s0 encounters objects with C linkage declared with incompatible types in separate translation units to be linked together (undefined -behavior according to \s-1ISO C99 6.2.7\s0), a non-fatal diagnostic may be +behavior according to \s-1ISO\s0 C99 6.2.7), a non-fatal diagnostic may be issued. The behavior is still undefined at run time. Similar diagnostics may be raised for other languages. .Sp @@ -7356,7 +7356,7 @@ regular (non-LTO) compilation. If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say \&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you are using a linker with plugin support. To create static libraries suitable -for \s-1LTO,\s0 use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR +for \s-1LTO\s0, use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR and \fBranlib\fR; to show the symbols of object files with \s-1GIMPLE\s0 bytecode, use \&\fBgcc-nm\fR. Those commands require that \fBar\fR, \fBranlib\fR @@ -7391,7 +7391,7 @@ The current implementation of \s-1LTO\s0 makes no attempt to generate bytecode that is portable between different types of hosts. The bytecode files are versioned and there is a strict version check, so bytecode files generated in one version of -\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC.\s0 +\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC\s0. .Sp Link-time optimization does not work well with generation of debugging information. Combining \fB\-flto\fR with @@ -7462,8 +7462,8 @@ and the object code. This makes them usable for both \s-1LTO\s0 linking and norm linking. This option is effective only when compiling with \fB\-flto\fR and is ignored at link time. .Sp -\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO,\s0 but -requires the complete toolchain to be aware of \s-1LTO.\s0 It requires a linker with +\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO\s0, but +requires the complete toolchain to be aware of \s-1LTO\s0. It requires a linker with linker plugin support for basic functionality. Additionally, \&\fBnm\fR, \fBar\fR and \fBranlib\fR need to support linker plugins to allow a full-featured build environment @@ -7550,7 +7550,7 @@ E.g. .Ve .Sp Then use the \fBcreate_gcov\fR tool to convert the raw profile data -to a format that can be used by \s-1GCC. \s0 You must also supply the +to a format that can be used by \s-1GCC\s0. You must also supply the unstripped binary for your program to this tool. See <\fBhttps://github.com/google/autofdo\fR>. .Sp @@ -7580,15 +7580,15 @@ them to store all pertinent intermediate computations into variables. .IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 .IX Item "-fexcess-precision=style" This option allows further control over excess precision on machines -where floating-point registers have more precision than the \s-1IEEE -\&\s0\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not +where floating-point registers have more precision than the \s-1IEEE\s0 +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not support operations rounding to those types. By default, \&\fB\-fexcess\-precision=fast\fR is in effect; this means that operations are carried out in the precision of the registers and that it is unpredictable when rounding to the types specified in the source code takes place. When compiling C, if \&\fB\-fexcess\-precision=standard\fR is specified then excess -precision follows the rules specified in \s-1ISO C99\s0; in particular, +precision follows the rules specified in \s-1ISO\s0 C99; in particular, both casts and assignments cause values to be rounded to their semantic types (whereas \fB\-ffloat\-store\fR only affects assignments). This option is enabled by default for C if a strict @@ -7652,7 +7652,7 @@ The default is \fB\-fno\-unsafe\-math\-optimizations\fR. .IP "\fB\-fassociative\-math\fR" 4 .IX Item "-fassociative-math" Allow re-association of operands in series of floating-point operations. -This violates the \s-1ISO C\s0 and \*(C+ language standard by possibly changing +This violates the \s-1ISO\s0 C and \*(C+ language standard by possibly changing computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as well as ignore NaNs and inhibit or create underflow or overflow (and thus cannot be used on code that relies on rounding behavior like @@ -7755,8 +7755,8 @@ whether the result of a complex multiplication or division is \f(CW\*(C`NaN default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by \&\fB\-ffast\-math\fR. .Sp -This option controls the default setting of the \s-1ISO C99 -\&\s0\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +This option controls the default setting of the \s-1ISO\s0 C99 +\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to all languages. .IP "\fB\-fcx\-fortran\-rules\fR" 4 .IX Item "-fcx-fortran-rules" @@ -8016,7 +8016,7 @@ optimization is not done. .IP "\fBmax-gcse-insertion-ratio\fR" 4 .IX Item "max-gcse-insertion-ratio" If the ratio of expression insertions to deletions is larger than this value -for any expression, then \s-1RTL PRE\s0 inserts or removes the expression and thus +for any expression, then \s-1RTL\s0 \s-1PRE\s0 inserts or removes the expression and thus leaves partially redundant computations in the instruction stream. The default value is 20. .IP "\fBmax-pending-list-length\fR" 4 .IX Item "max-pending-list-length" @@ -8031,7 +8031,7 @@ when modulo scheduling a loop. Larger values can exponentially increase compilation time. .IP "\fBmax-inline-insns-single\fR" 4 .IX Item "max-inline-insns-single" -Several parameters control the tree inliner used in \s-1GCC.\s0 +Several parameters control the tree inliner used in \s-1GCC\s0. This number sets the maximum number of instructions (counted in \s-1GCC\s0's internal representation) in a single function that the tree inliner considers for inlining. This only affects functions declared @@ -8361,7 +8361,7 @@ Tuning this may improve compilation speed; it has no effect on code generation. .Sp The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when -\&\s-1RAM \s0>= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is +\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If \&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower bound of 30% is used. Setting this parameter and @@ -8376,7 +8376,7 @@ by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, tuning this may improve compilation speed, and has no effect on code generation. .Sp -The default is the smaller of \s-1RAM/8, RLIMIT_RSS,\s0 or a limit that +The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit that tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but with a lower bound of 4096 (four megabytes) and an upper bound of 131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a @@ -8585,7 +8585,7 @@ This value is the best found from numerous experiments. This optimization is called inheritance. \s-1EBB\s0 is used as a region to do this optimization. The parameter defines a minimal fall-through edge probability in percentage used to add \s-1BB\s0 to inheritance \s-1EBB\s0 in -\&\s-1LRA. \s0 The default value of the parameter is 40. The value was chosen +\&\s-1LRA\s0. The default value of the parameter is 40. The value was chosen from numerous runs of \s-1SPEC2000\s0 on x86\-64. .IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 .IX Item "loop-invariant-max-bbs-in-loop" @@ -8727,7 +8727,7 @@ The number of partitions should exceed the number of CPUs used for compilation. The default value is 32. .IP "\fBlto-min-partition\fR" 4 .IX Item "lto-min-partition" -Size of minimal partition for \s-1WHOPR \s0(in estimated instructions). +Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). This prevents expenses of splitting very small programs into too many partitions. .IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 @@ -8863,7 +8863,7 @@ we may be able to devirtualize speculatively. .RE .RS 4 .RE -.SS "Program Instrumentation Options" +.Sh "Program Instrumentation Options" .IX Subsection "Program Instrumentation Options" \&\s-1GCC\s0 supports a number of command-line options that control adding run-time instrumentation to the code it normally generates. @@ -9023,7 +9023,7 @@ at runtime. Current suboptions are: .IX Item "-fsanitize=shift" This option enables checking that the result of a shift operation is not undefined. Note that what exactly is considered undefined differs -slightly between C and \*(C+, as well as between \s-1ISO C90\s0 and C99, etc. +slightly between C and \*(C+, as well as between \s-1ISO\s0 C90 and C99, etc. .IP "\fB\-fsanitize=integer\-divide\-by\-zero\fR" 4 .IX Item "-fsanitize=integer-divide-by-zero" Detect integer division by zero as well as \f(CW\*(C`INT_MIN / \-1\*(C'\fR division. @@ -9524,9 +9524,9 @@ name, such as \f(CW\*(C`vector<int> blah(const vector<int> &)\*(C'\fR, not the internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The match is done on substrings: if the \fIsym\fR parameter is a substring of the function name, it is considered to be a match. For C99 and \*(C+ -extended identifiers, the function name must be given in \s-1UTF\-8,\s0 not +extended identifiers, the function name must be given in \s-1UTF\-8\s0, not using universal character names. -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9650,7 +9650,7 @@ get trigraph conversion without warnings, but get the other .IP "\fB\-Wtraditional\fR" 4 .IX Item "-Wtraditional" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C equivalent, and problematic constructs which should be avoided. .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" @@ -9703,7 +9703,7 @@ in finding bugs in your own code, therefore suppressed. If you are responsible for the system library, you may want to see them. .IP "\fB\-w\fR" 4 .IX Item "-w" -Suppress all warnings, including those which \s-1GNU CPP\s0 issues by default. +Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. .IP "\fB\-pedantic\fR" 4 .IX Item "-pedantic" Issue all the mandatory diagnostics listed in the C standard. Some of @@ -9843,10 +9843,10 @@ This option allows use of a precompiled header together with \fB\-E\fR. It inse \&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark the place where the precompiled header was found, and its \fIfilename\fR. When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR -and loads the \s-1PCH.\s0 +and loads the \s-1PCH\s0. .Sp This option is off by default, because the resulting preprocessed output -is only really suitable as input to \s-1GCC. \s0 It is switched on by +is only really suitable as input to \s-1GCC\s0. It is switched on by \&\fB\-save\-temps\fR. .Sp You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is @@ -9899,7 +9899,7 @@ may be one of: .el .IP "\f(CWiso9899:1990\fR" 4 .IX Item "iso9899:1990" .PD -The \s-1ISO C\s0 standard from 1990. \fBc90\fR is the customary shorthand for +The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for this version of the standard. .Sp The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. @@ -9921,7 +9921,7 @@ The 1990 C standard, as amended in 1994. .el .IP "\f(CWc9x\fR" 4 .IX Item "c9x" .PD -The revised \s-1ISO C\s0 standard, published in December 1999. Before +The revised \s-1ISO\s0 C standard, published in December 1999. Before publication, this was known as C9X. .ie n .IP """iso9899:2011""" 4 .el .IP "\f(CWiso9899:2011\fR" 4 @@ -9934,7 +9934,7 @@ publication, this was known as C9X. .el .IP "\f(CWc1x\fR" 4 .IX Item "c1x" .PD -The revised \s-1ISO C\s0 standard, published in December 2011. Before +The revised \s-1ISO\s0 C standard, published in December 2011. Before publication, this was known as C1X. .ie n .IP """gnu90""" 4 .el .IP "\f(CWgnu90\fR" 4 @@ -9966,7 +9966,7 @@ The 2011 C standard plus \s-1GNU\s0 extensions. .ie n .IP """c++98""" 4 .el .IP "\f(CWc++98\fR" 4 .IX Item "c++98" -The 1998 \s-1ISO \*(C+\s0 standard plus amendments. +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. .ie n .IP """gnu++98""" 4 .el .IP "\f(CWgnu++98\fR" 4 .IX Item "gnu++98" @@ -10118,7 +10118,7 @@ line. If the value is less than 1 or greater than 100, the option is ignored. The default is 8. .IP "\fB\-fdebug\-cpp\fR" 4 .IX Item "-fdebug-cpp" -This option is only useful for debugging \s-1GCC. \s0 When used with +This option is only useful for debugging \s-1GCC\s0. When used with \&\fB\-E\fR, dumps debugging information about location maps. Every token in the output is preceded by the dump of the map its location belongs to. The dump of the map holding the location of a token would @@ -10151,12 +10151,12 @@ Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default .IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fexec-charset=charset" Set the execution character set, used for string and character -constants. The default is \s-1UTF\-8. \s0\fIcharset\fR can be any encoding +constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fwide-exec-charset=charset" Set the wide execution character set, used for wide string and -character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with \&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have @@ -10164,9 +10164,9 @@ problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. .IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 .IX Item "-finput-charset=charset" Set the input character set, used for translation from the character -set of the input file to the source character set used by \s-1GCC. \s0 If the +set of the input file to the source character set used by \s-1GCC\s0. If the locale does not specify, or \s-1GCC\s0 cannot get this information from the -locale, the default is \s-1UTF\-8. \s0 This can be overridden by either the locale +locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale or this command-line option. Currently the command-line option takes precedence if there's a conflict. \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. @@ -10203,7 +10203,7 @@ Cancel an assertion with the predicate \fIpredicate\fR and answer .IX Item "-dCHARS" \&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, and must not be preceded by a space. Other characters are interpreted -by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so +by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so are silently ignored. If you specify characters whose behavior conflicts, the result is undefined. .RS 4 @@ -10279,12 +10279,12 @@ The \fB\-CC\fR option is generally used to support lint comments. .IP "\fB\-traditional\-cpp\fR" 4 .IX Item "-traditional-cpp" Try to imitate the behavior of old-fashioned C preprocessors, as -opposed to \s-1ISO C\s0 preprocessors. +opposed to \s-1ISO\s0 C preprocessors. .IP "\fB\-trigraphs\fR" 4 .IX Item "-trigraphs" Process trigraph sequences. These are three-character sequences, all starting with \fB??\fR, that -are defined by \s-1ISO C\s0 to stand for single characters. For example, +are defined by \s-1ISO\s0 C to stand for single characters. For example, \&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character constant for a newline. By default, \s-1GCC\s0 ignores trigraphs, but in standard-conforming modes it converts them. See the \fB\-std\fR and @@ -10310,7 +10310,7 @@ Print text describing all the command-line options instead of preprocessing anything. .IP "\fB\-v\fR" 4 .IX Item "-v" -Verbose mode. Print out \s-1GNU CPP\s0's version number at the beginning of +Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of execution, and report the final form of the include path. .IP "\fB\-H\fR" 4 .IX Item "-H" @@ -10325,9 +10325,9 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .IP "\fB\-\-version\fR" 4 .IX Item "--version" .PD -Print out \s-1GNU CPP\s0's version number. With one dash, proceed to +Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -10342,7 +10342,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10632,7 +10632,7 @@ different symbols to force loading of additional library modules. \&\fB\-z\fR is passed directly on to the linker along with the keyword \&\fIkeyword\fR. See the section in the documentation of your linker for permitted values and their meanings. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10766,7 +10766,7 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. @@ -10973,7 +10973,7 @@ Use it to conform to a non-default application binary interface. .IX Item "-fshort-wchar" Override the underlying type for \f(CW\*(C`wchar_t\*(C'\fR to be \f(CW\*(C`short unsigned int\*(C'\fR instead of the default for the target. This option is -useful for building programs to run under \s-1WINE.\s0 +useful for building programs to run under \s-1WINE\s0. .Sp \&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate code that is not binary compatible with code generated without that switch. @@ -10986,7 +10986,7 @@ such variables in different compilation units by placing the variables in a common block. This is the behavior specified by \fB\-fcommon\fR, and is the default for \s-1GCC\s0 on most targets. -On the other hand, this behavior is not required by \s-1ISO C,\s0 and on some +On the other hand, this behavior is not required by \s-1ISO\s0 C, and on some targets may carry a speed or code size penalty on variable references. The \fB\-fno\-common\fR option specifies that the compiler should place uninitialized global variables in the data section of the object file, @@ -11041,12 +11041,12 @@ loader is not part of \s-1GCC\s0; it is part of the operating system). If the \s-1GOT\s0 size for the linked executable exceeds a machine-specific maximum size, you get an error message from the linker indicating that \&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR -instead. (These maximums are 8k on the \s-1SPARC,\s0 28k on AArch64 and 32k -on the m68k and \s-1RS/6000. \s0 The x86 has no such limit.) +instead. (These maximums are 8k on the \s-1SPARC\s0, 28k on AArch64 and 32k +on the m68k and \s-1RS/6000\s0. The x86 has no such limit.) .Sp Position-independent code requires special support, and therefore works only on certain machines. For the x86, \s-1GCC\s0 supports \s-1PIC\s0 for System V -but not for the Sun 386i. Code generated for the \s-1IBM RS/6000\s0 is always +but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always position-independent. .Sp When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR @@ -11056,7 +11056,7 @@ are defined to 1. If supported for the target machine, emit position-independent code, suitable for dynamic linking and avoiding any limit on the size of the global offset table. This option makes a difference on AArch64, m68k, -PowerPC and \s-1SPARC.\s0 +PowerPC and \s-1SPARC\s0. .Sp Position-independent code requires special support, and therefore works only on certain machines. @@ -11215,7 +11215,7 @@ always specify visibility when it is not the default; i.e., declarations only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this abundantly clear also aids readability and self-documentation of the code. -Note that due to \s-1ISO \*(C+\s0 specification requirements, \f(CW\*(C`operator new\*(C'\fR and +Note that due to \s-1ISO\s0 \*(C+ specification requirements, \f(CW\*(C`operator new\*(C'\fR and \&\f(CW\*(C`operator delete\*(C'\fR must always be of default visibility. .Sp Be aware that headers from outside your project, in particular system @@ -11227,7 +11227,7 @@ before including any such headers. \&\f(CW\*(C`extern\*(C'\fR declarations are not affected by \fB\-fvisibility\fR, so a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with no modifications. However, this means that calls to \f(CW\*(C`extern\*(C'\fR -functions with no explicit visibility use the \s-1PLT,\s0 so it is more +functions with no explicit visibility use the \s-1PLT\s0, so it is more effective to use \f(CW\*(C`_\|_attribute ((visibility))\*(C'\fR and/or \&\f(CW\*(C`#pragma GCC visibility\*(C'\fR to tell the compiler which \f(CW\*(C`extern\*(C'\fR declarations should be treated as hidden. @@ -11279,7 +11279,7 @@ family of functions. The default value of this option is enabled, thus the only useful form of the option is \fB\-fno\-sync\-libcalls\fR. This option is used in the implementation of the \fIlibatomic\fR runtime library. -.SS "\s-1GCC\s0 Developer Options" +.Sh "\s-1GCC\s0 Developer Options" .IX Subsection "GCC Developer Options" This section describes command-line options that are primarily of interest to \s-1GCC\s0 developers, including options to support compiler @@ -11689,7 +11689,7 @@ by some other path. When dumping pretty-printed trees, this option inhibits dumping the bodies of control structures. .Sp -When dumping \s-1RTL,\s0 print the \s-1RTL\s0 in slim (condensed) form instead of +When dumping \s-1RTL\s0, print the \s-1RTL\s0 in slim (condensed) form instead of the default LISP-like representation. .IP "\fBraw\fR" 4 .IX Item "raw" @@ -11724,7 +11724,7 @@ Enable showing virtual operands for every statement. Enable showing line numbers for statements. .IP "\fBuid\fR" 4 .IX Item "uid" -Enable showing the unique \s-1ID \s0(\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. .IP "\fBverbose\fR" 4 .IX Item "verbose" Enable showing the tree dump for each statement. @@ -11806,7 +11806,7 @@ Dump aliasing information for each function. The file name is made by appending \fI.alias\fR to the source file name. .IP "\fBccp\fR" 4 .IX Item "ccp" -Dump each function after \s-1CCP. \s0 The file name is made by appending +Dump each function after \s-1CCP\s0. The file name is made by appending \&\fI.ccp\fR to the source file name. .IP "\fBstoreccp\fR" 4 .IX Item "storeccp" @@ -12034,7 +12034,7 @@ dependence info. .IX Item "-fdisable-kind-pass=range-list" .PD This is a set of options that are used to explicitly disable/enable -optimization passes. These options are intended for use for debugging \s-1GCC.\s0 +optimization passes. These options are intended for use for debugging \s-1GCC\s0. Compiler users should use regular options for enabling/disabling passes instead. .RS 4 @@ -12439,11 +12439,11 @@ anything else. .IX Item "-dumpspecs" Print the compiler's built-in specs\-\-\-and don't do anything else. (This is used when \s-1GCC\s0 itself is being built.) -.SS "Machine-Dependent Options" +.Sh "Machine-Dependent Options" .IX Subsection "Machine-Dependent Options" Each target machine supported by \s-1GCC\s0 can have its own options\-\-\-for example, to allow you to compile for a particular processor variant or -\&\s-1ABI,\s0 or to control optimizations specific to that machine. By +\&\s-1ABI\s0, or to control optimizations specific to that machine. By convention, the names of machine-specific options start with \&\fB\-m\fR. .PP @@ -12464,7 +12464,7 @@ but long int and pointer are 64\-bit. .Sp The default depends on the specific target configuration. Note that the \s-1LP64\s0 and \s-1ILP32\s0 ABIs are not link-compatible; you must compile your -entire program with the same \s-1ABI,\s0 and link with a compatible set of libraries. +entire program with the same \s-1ABI\s0, and link with a compatible set of libraries. .IP "\fB\-mbig\-endian\fR" 4 .IX Item "-mbig-endian" Generate big-endian code. This is the default when \s-1GCC\s0 is configured for an @@ -12627,7 +12627,7 @@ Override tuning decisions made by the back-end in response to a for \fIstring\fR in this option are not guaranteed to be consistent across releases. .Sp -This option is only intended to be useful when developing \s-1GCC.\s0 +This option is only intended to be useful when developing \s-1GCC\s0. .IP "\fB\-mpc\-relative\-literal\-loads\fR" 4 .IX Item "-mpc-relative-literal-loads" Enable \s-1PC\s0 relative literal loads. If this option is used, literal @@ -12762,7 +12762,7 @@ This is the mode used for floating-point calculations with round-to-nearest-or-even rounding mode. .IP "\fBint\fR" 4 .IX Item "int" -This is the mode used to perform integer calculations in the \s-1FPU,\s0 e.g. +This is the mode used to perform integer calculations in the \s-1FPU\s0, e.g. integer multiply, or integer multiply-and-accumulate. .RE .RS 4 @@ -12828,21 +12828,21 @@ values for \fIcpu\fR are .IP "\fBarc600\fR" 4 .IX Item "arc600" .PD -Compile for \s-1ARC600. \s0 Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. +Compile for \s-1ARC600\s0. Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. .IP "\fB\s-1ARC601\s0\fR" 4 .IX Item "ARC601" .PD 0 .IP "\fBarc601\fR" 4 .IX Item "arc601" .PD -Compile for \s-1ARC601. \s0 Alias: \fB\-mARC601\fR. +Compile for \s-1ARC601\s0. Alias: \fB\-mARC601\fR. .IP "\fB\s-1ARC700\s0\fR" 4 .IX Item "ARC700" .PD 0 .IP "\fBarc700\fR" 4 .IX Item "arc700" .PD -Compile for \s-1ARC700. \s0 Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. +Compile for \s-1ARC700\s0. Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. This is the default when configured with \fB\-\-with\-cpu=arc700\fR. .IP "\fB\s-1ARCEM\s0\fR" 4 .IX Item "ARCEM" @@ -12850,14 +12850,14 @@ This is the default when configured with \fB\-\-with\-cpu=arc700\fR. .IP "\fBarcem\fR" 4 .IX Item "arcem" .PD -Compile for \s-1ARC EM.\s0 +Compile for \s-1ARC\s0 \s-1EM\s0. .IP "\fB\s-1ARCHS\s0\fR" 4 .IX Item "ARCHS" .PD 0 .IP "\fBarchs\fR" 4 .IX Item "archs" .PD -Compile for \s-1ARC HS.\s0 +Compile for \s-1ARC\s0 \s-1HS\s0. .RE .RS 4 .RE @@ -12883,7 +12883,7 @@ Generate Extended arithmetic instructions. Currently only supported. This is always enabled for \fB\-mcpu=ARC700\fR. .IP "\fB\-mno\-mpy\fR" 4 .IX Item "-mno-mpy" -Do not generate mpy instructions for \s-1ARC700.\s0 +Do not generate mpy instructions for \s-1ARC700\s0. .IP "\fB\-mmul32x16\fR" 4 .IX Item "-mmul32x16" Generate 32x16 bit multiply and mac instructions. @@ -12908,7 +12908,7 @@ implementation. implementation. .IP "\fB\-msimd\fR" 4 .IX Item "-msimd" -Enable generation of \s-1ARC SIMD\s0 instructions via target-specific +Enable generation of \s-1ARC\s0 \s-1SIMD\s0 instructions via target-specific builtins. Only valid for \fB\-mcpu=ARC700\fR. .IP "\fB\-msoft\-float\fR" 4 .IX Item "-msoft-float" @@ -12923,17 +12923,17 @@ Generate swap instructions. .IP "\fB\-matomic\fR" 4 .IX Item "-matomic" This enables Locked Load/Store Conditional extension to implement -atomic memopry built-in functions. Not available for \s-1ARC\s0 6xx or \s-1ARC -EM\s0 cores. +atomic memopry built-in functions. Not available for \s-1ARC\s0 6xx or \s-1ARC\s0 +\&\s-1EM\s0 cores. .IP "\fB\-mdiv\-rem\fR" 4 .IX Item "-mdiv-rem" Enable \s-1DIV/REM\s0 instructions for ARCv2 cores. .IP "\fB\-mcode\-density\fR" 4 .IX Item "-mcode-density" -Enable code density instructions for \s-1ARC EM,\s0 default on for \s-1ARC HS.\s0 +Enable code density instructions for \s-1ARC\s0 \s-1EM\s0, default on for \s-1ARC\s0 \s-1HS\s0. .IP "\fB\-mll64\fR" 4 .IX Item "-mll64" -Enable double load/store operations for \s-1ARC HS\s0 cores. +Enable double load/store operations for \s-1ARC\s0 \s-1HS\s0 cores. .IP "\fB\-mmpy\-option=\fR\fImulto\fR" 4 .IX Item "-mmpy-option=multo" Compile ARCv2 code with a multiplier design option. \fBwlh1\fR is @@ -12945,32 +12945,32 @@ No multiplier available. .IP "\fB1\fR" 4 .IX Item "1" The multiply option is set to w: 16x16 multiplier, fully pipelined. -The following instructions are enabled: \s-1MPYW,\s0 and \s-1MPYUW.\s0 +The following instructions are enabled: \s-1MPYW\s0, and \s-1MPYUW\s0. .IP "\fB2\fR" 4 .IX Item "2" The multiply option is set to wlh1: 32x32 multiplier, fully pipelined (1 stage). The following instructions are additionally -enabled: \s-1MPY, MPYU, MPYM, MPYMU,\s0 and \s-1MPY_S.\s0 +enabled: \s-1MPY\s0, \s-1MPYU\s0, \s-1MPYM\s0, \s-1MPYMU\s0, and \s-1MPY_S\s0. .IP "\fB3\fR" 4 .IX Item "3" The multiply option is set to wlh2: 32x32 multiplier, fully pipelined -(2 stages). The following instructions are additionally enabled: \s-1MPY, -MPYU, MPYM, MPYMU,\s0 and \s-1MPY_S.\s0 +(2 stages). The following instructions are additionally enabled: \s-1MPY\s0, +\&\s-1MPYU\s0, \s-1MPYM\s0, \s-1MPYMU\s0, and \s-1MPY_S\s0. .IP "\fB4\fR" 4 .IX Item "4" The multiply option is set to wlh3: Two 16x16 multiplier, blocking, -sequential. The following instructions are additionally enabled: \s-1MPY, -MPYU, MPYM, MPYMU,\s0 and \s-1MPY_S.\s0 +sequential. The following instructions are additionally enabled: \s-1MPY\s0, +\&\s-1MPYU\s0, \s-1MPYM\s0, \s-1MPYMU\s0, and \s-1MPY_S\s0. .IP "\fB5\fR" 4 .IX Item "5" The multiply option is set to wlh4: One 16x16 multiplier, blocking, -sequential. The following instructions are additionally enabled: \s-1MPY, -MPYU, MPYM, MPYMU,\s0 and \s-1MPY_S.\s0 +sequential. The following instructions are additionally enabled: \s-1MPY\s0, +\&\s-1MPYU\s0, \s-1MPYM\s0, \s-1MPYMU\s0, and \s-1MPY_S\s0. .IP "\fB6\fR" 4 .IX Item "6" The multiply option is set to wlh5: One 32x4 multiplier, blocking, -sequential. The following instructions are additionally enabled: \s-1MPY, -MPYU, MPYM, MPYMU,\s0 and \s-1MPY_S.\s0 +sequential. The following instructions are additionally enabled: \s-1MPY\s0, +\&\s-1MPYU\s0, \s-1MPYM\s0, \s-1MPYMU\s0, and \s-1MPY_S\s0. .RE .RS 4 .Sp @@ -12989,33 +12989,33 @@ extensions. .IX Item "fpud" Enables support for double precision floating point hardware extensions. The single precision floating point extension is also -enabled. Not available for \s-1ARC EM.\s0 +enabled. Not available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpuda\fR" 4 .IX Item "fpuda" Enables support for double precision floating point hardware extensions using double precision assist instructions. The single precision floating point extension is also enabled. This option is -only available for \s-1ARC EM.\s0 +only available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpuda_div\fR" 4 .IX Item "fpuda_div" Enables support for double precision floating point hardware extensions using double precision assist instructions, and simple precision square-root and divide hardware extensions. The single precision floating point extension is also enabled. This option is -only available for \s-1ARC EM.\s0 +only available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpuda_fma\fR" 4 .IX Item "fpuda_fma" Enables support for double precision floating point hardware extensions using double precision assist instructions, and simple precision fused multiple and add hardware extension. The single precision floating point extension is also enabled. This option is -only available for \s-1ARC EM.\s0 +only available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpuda_all\fR" 4 .IX Item "fpuda_all" Enables support for double precision floating point hardware extensions using double precision assist instructions, and all simple precision hardware extensions. The single precision floating point -extension is also enabled. This option is only available for \s-1ARC EM.\s0 +extension is also enabled. This option is only available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpus_div\fR" 4 .IX Item "fpus_div" Enables support for single precision floating point, and single @@ -13024,7 +13024,7 @@ precision square-root and divide hardware extensions. .IX Item "fpud_div" Enables support for double precision floating point, and double precision square-root and divide hardware extensions. This option -includes option \fBfpus_div\fR. Not available for \s-1ARC EM.\s0 +includes option \fBfpus_div\fR. Not available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpus_fma\fR" 4 .IX Item "fpus_fma" Enables support for single precision floating point, and single @@ -13033,7 +13033,7 @@ precision fused multiple and add hardware extensions. .IX Item "fpud_fma" Enables support for double precision floating point, and double precision fused multiple and add hardware extensions. This option -includes option \fBfpus_fma\fR. Not available for \s-1ARC EM.\s0 +includes option \fBfpus_fma\fR. Not available for \s-1ARC\s0 \s-1EM\s0. .IP "\fBfpus_all\fR" 4 .IX Item "fpus_all" Enables support for all single precision floating point hardware @@ -13041,7 +13041,7 @@ extensions. .IP "\fBfpud_all\fR" 4 .IX Item "fpud_all" Enables support for all single and double precision floating point -hardware extensions. Not available for \s-1ARC EM.\s0 +hardware extensions. Not available for \s-1ARC\s0 \s-1EM\s0. .RE .RS 4 .RE @@ -13192,9 +13192,8 @@ Expand \f(CW\*(C`adddi3\*(C'\fR and \f(CW\*(C`subdi3\*(C'\fR at rtl generation t Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed stores exist, which is not the case. -.IP "\fB\-mlra\fR" 4 -.IX Item "-mlra" -Enable Local Register Allocation. This is still experimental for \s-1ARC,\s0 +.Sp +Enable Local Register Allocation. This is still experimental for \s-1ARC\s0, so by default the compiler uses standard reload (i.e. \fB\-mno\-lra\fR). .IP "\fB\-mlra\-priority\-none\fR" 4 @@ -13300,7 +13299,7 @@ The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release: .IP "\fB\-margonaut\fR" 4 .IX Item "-margonaut" -Obsolete \s-1FPX.\s0 +Obsolete \s-1FPX\s0. .IP "\fB\-mbig\-endian\fR" 4 .IX Item "-mbig-endian" .PD 0 @@ -13363,7 +13362,7 @@ Replaced by \fB\-mmultcost\fR. These \fB\-m\fR options are defined for the \s-1ARM\s0 port: .IP "\fB\-mabi=\fR\fIname\fR" 4 .IX Item "-mabi=name" -Generate code for the specified \s-1ABI. \s0 Permissible values are: \fBapcs-gnu\fR, +Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR, \&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. .IP "\fB\-mapcs\-frame\fR" 4 .IX Item "-mapcs-frame" @@ -13407,7 +13406,7 @@ and uses FPU-specific calling conventions. .Sp The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must -compile your entire program with the same \s-1ABI,\s0 and link with a +compile your entire program with the same \s-1ABI\s0, and link with a compatible set of libraries. .IP "\fB\-mlittle\-endian\fR" 4 .IX Item "-mlittle-endian" @@ -13541,7 +13540,7 @@ If the selected floating-point hardware includes the \s-1NEON\s0 extension (e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point operations are not generated by \s-1GCC\s0's auto-vectorization pass unless \&\fB\-funsafe\-math\-optimizations\fR is also specified. This is -because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE 754\s0 standard for +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. .Sp @@ -13616,7 +13615,7 @@ otherwise the default is \fBR10\fR. .IX Item "-mpic-data-is-text-relative" Assume that each data segments are relative to text segment at load time. Therefore, it permits addressing data using PC-relative operations. -This option is on by default for targets other than VxWorks \s-1RTP.\s0 +This option is on by default for targets other than VxWorks \s-1RTP\s0. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -13742,7 +13741,7 @@ off by default. .IX Item "-masm-syntax-unified" Assume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. This option has no impact -on Thumb2. However, this may change in future releases of \s-1GCC.\s0 +on Thumb2. However, this may change in future releases of \s-1GCC\s0. Divided syntax should be considered deprecated. .IP "\fB\-mrestrict\-it\fR" 4 .IX Item "-mrestrict-it" @@ -13811,37 +13810,37 @@ The default for this option is@tie{}\fBavr2\fR. .ie n .IP """avr6""" 4 .el .IP "\f(CWavr6\fR" 4 .IX Item "avr6" -\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC,\s0 i.e. with more than 128@tie{}KiB of program memory. +\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC\s0, i.e. with more than 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega256rfr2\*(C'\fR, \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR, \f(CW\*(C`atmega2564rfr2\*(C'\fR. .ie n .IP """avrxmega2""" 4 .el .IP "\f(CWavrxmega2\fR" 4 .IX Item "avrxmega2" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16a4u\*(C'\fR, \f(CW\*(C`atxmega16c4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, \f(CW\*(C`atxmega16e5\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32a4u\*(C'\fR, \f(CW\*(C`atxmega32c3\*(C'\fR, \f(CW\*(C`atxmega32c4\*(C'\fR, \f(CW\*(C`atxmega32d3\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, \f(CW\*(C`atxmega32e5\*(C'\fR, \f(CW\*(C`atxmega8e5\*(C'\fR. .ie n .IP """avrxmega4""" 4 .el .IP "\f(CWavrxmega4\fR" 4 .IX Item "avrxmega4" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64a3u\*(C'\fR, \f(CW\*(C`atxmega64a4u\*(C'\fR, \f(CW\*(C`atxmega64b1\*(C'\fR, \f(CW\*(C`atxmega64b3\*(C'\fR, \f(CW\*(C`atxmega64c3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR, \f(CW\*(C`atxmega64d4\*(C'\fR. .ie n .IP """avrxmega5""" 4 .el .IP "\f(CWavrxmega5\fR" 4 .IX Item "avrxmega5" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. -\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. +\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. .ie n .IP """avrxmega6""" 4 .el .IP "\f(CWavrxmega6\fR" 4 .IX Item "avrxmega6" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128a3u\*(C'\fR, \f(CW\*(C`atxmega128b1\*(C'\fR, \f(CW\*(C`atxmega128b3\*(C'\fR, \f(CW\*(C`atxmega128c3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, \f(CW\*(C`atxmega128d4\*(C'\fR, \f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192a3u\*(C'\fR, \f(CW\*(C`atxmega192c3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, \f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256a3u\*(C'\fR, \f(CW\*(C`atxmega256c3\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR, \f(CW\*(C`atxmega384c3\*(C'\fR, \f(CW\*(C`atxmega384d3\*(C'\fR. .ie n .IP """avrxmega7""" 4 .el .IP "\f(CWavrxmega7\fR" 4 .IX Item "avrxmega7" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. -\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. +\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. .ie n .IP """avrtiny""" 4 .el .IP "\f(CWavrtiny\fR" 4 .IX Item "avrtiny" -\&\*(L"\s-1TINY\*(R"\s0 Tiny core devices with 512@tie{}B up to 4@tie{}KiB of program memory. +\&\*(L"\s-1TINY\s0\*(R" Tiny core devices with 512@tie{}B up to 4@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny10\*(C'\fR, \f(CW\*(C`attiny20\*(C'\fR, \f(CW\*(C`attiny4\*(C'\fR, \f(CW\*(C`attiny40\*(C'\fR, \f(CW\*(C`attiny5\*(C'\fR, \f(CW\*(C`attiny9\*(C'\fR. .ie n .IP """avr1""" 4 .el .IP "\f(CWavr1\fR" 4 @@ -14057,7 +14056,7 @@ command-line option. .IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 -.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" .PD 0 .ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 .el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 @@ -14252,7 +14251,7 @@ The definition of these macros is affected by \fB\-mtiny\-stack\fR. .el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 .IX Item "__AVR_SP8__" .PD -The device has the \s-1SPH \s0(high part of stack pointer) special function +The device has the \s-1SPH\s0 (high part of stack pointer) special function register or has an 8\-bit stack pointer, respectively. The definition of these macros is affected by \fB\-mmcu=\fR and in the cases of \fB\-mmcu=avr2\fR and \fB\-mmcu=avr25\fR also @@ -14285,7 +14284,7 @@ This macro reflects the \fB\-mno\-interrupts\fR command-line option. .el .IP "\f(CW_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_\fR" 4 .IX Item "__AVR_ERRATA_SKIP_JMP_CALL__" .PD -Some \s-1AVR\s0 devices (\s-1AT90S8515,\s0 ATmega103) must not skip 32\-bit +Some \s-1AVR\s0 devices (\s-1AT90S8515\s0, ATmega103) must not skip 32\-bit instructions because of a hardware erratum. Skip instructions are \&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also @@ -14293,7 +14292,7 @@ set. .ie n .IP """_\|_AVR_ISA_RMW_\|_""" 4 .el .IP "\f(CW_\|_AVR_ISA_RMW_\|_\fR" 4 .IX Item "__AVR_ISA_RMW__" -The device has Read-Modify-Write instructions (\s-1XCH, LAC, LAS\s0 and \s-1LAT\s0). +The device has Read-Modify-Write instructions (\s-1XCH\s0, \s-1LAC\s0, \s-1LAS\s0 and \s-1LAT\s0). .ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW""" 4 .el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 .IX Item "__AVR_SFR_OFFSET__=offset" @@ -14477,8 +14476,8 @@ should be used instead of \f(CW\*(C`main\*(C'\fR. This option can only be used in conjunction with \fB\-mmulticore\fR. .IP "\fB\-msdram\fR" 4 .IX Item "-msdram" -Build a standalone application for \s-1SDRAM.\s0 Proper start files and -link scripts are used to put the application into \s-1SDRAM,\s0 and the macro +Build a standalone application for \s-1SDRAM\s0. Proper start files and +link scripts are used to put the application into \s-1SDRAM\s0, and the macro \&\f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR is defined. The loader should initialize \s-1SDRAM\s0 before loading the application. .IP "\fB\-micplb\fR" 4 @@ -14537,7 +14536,7 @@ These options are defined specifically for the \s-1CRIS\s0 ports. .PD Generate code for the specified architecture. The choices for \&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for -respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX.\s0 +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0. Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is \&\fBv10\fR. .IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 @@ -14630,7 +14629,7 @@ or storage for local variables needs to be allocated. With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) instruction sequences that load addresses for functions from the \s-1PLT\s0 part of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the -\&\s-1PLT. \s0 The default is \fB\-mgotplt\fR. +\&\s-1PLT\s0. The default is \fB\-mgotplt\fR. .IP "\fB\-melf\fR" 4 .IX Item "-melf" Legacy no-op option only recognized with the cris-axis-elf and @@ -14686,7 +14685,7 @@ However, \fBfar\fR is not valid with \fB\-mcr16c\fR, as the These options are defined for all architectures running the Darwin operating system. .PP -\&\s-1FSF GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates +\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates an object file for the single architecture that \s-1GCC\s0 was built to target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple \&\fB\-arch\fR options are used; it does so by running the compiler or @@ -14746,7 +14745,7 @@ warn about constructs contained within header files found via .IX Item "-gused" Emit debugging information for symbols that are used. For stabs debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. -This is by default \s-1ON.\s0 +This is by default \s-1ON\s0. .IP "\fB\-gfull\fR" 4 .IX Item "-gfull" Emit debugging information for all symbols and types. @@ -14822,7 +14821,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fB\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -14996,7 +14995,7 @@ compilers call this option \fB\-ieee_with_no_inexact\fR. .IP "\fB\-mieee\-with\-inexact\fR" 4 .IX Item "-mieee-with-inexact" This is like \fB\-mieee\fR except the generated code also maintains -the \s-1IEEE \s0\fIinexact-flag\fR. Turning on this option causes the +the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to \&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute @@ -15122,8 +15121,8 @@ before it can find the variables and constants in its own data segment. .IP "\fB\-mno\-max\fR" 4 .IX Item "-mno-max" .PD -Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX, -CIX, FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0, +\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. .IP "\fB\-mfloat\-vax\fR" 4 @@ -15132,7 +15131,7 @@ of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. .IP "\fB\-mfloat\-ieee\fR" 4 .IX Item "-mfloat-ieee" .PD -Generate code that uses (does not use) \s-1VAX F\s0 and G floating-point +Generate code that uses (does not use) \s-1VAX\s0 F and G floating-point arithmetic instead of \s-1IEEE\s0 single and double precision. .IP "\fB\-mexplicit\-relocs\fR" 4 .IX Item "-mexplicit-relocs" @@ -15187,7 +15186,7 @@ The default is \fB\-mlarge\-text\fR. Set the instruction set and instruction scheduling parameters for machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR style name or the corresponding chip number. \s-1GCC\s0 supports scheduling -parameters for the \s-1EV4, EV5\s0 and \s-1EV6\s0 family of processors and +parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, \s-1GCC\s0 defaults to the processor on which the compiler was built. @@ -15232,14 +15231,14 @@ Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions .IP "\fB21264\fR" 4 .IX Item "21264" .PD -Schedules as an \s-1EV6\s0 and supports the \s-1BWX, FIX,\s0 and \s-1MAX\s0 extensions. +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. .IP "\fBev67\fR" 4 .IX Item "ev67" .PD 0 .IP "\fB21264a\fR" 4 .IX Item "21264a" .PD -Schedules as an \s-1EV6\s0 and supports the \s-1BWX, CIX, FIX,\s0 and \s-1MAX\s0 extensions. +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. .RE .RS 4 .Sp @@ -15280,9 +15279,9 @@ A decimal number representing clock cycles. .IX Item "main" .PD The compiler contains estimates of the number of clock cycles for -\&\*(L"typical\*(R" \s-1EV4 & EV5\s0 hardware for the Level 1, 2 & 3 caches +\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches (also called Dcache, Scache, and Bcache), as well as to main memory. -Note that L3 is only valid for \s-1EV5.\s0 +Note that L3 is only valid for \s-1EV5\s0. .RE .RS 4 .RE @@ -15315,7 +15314,7 @@ real hardware; you must provide your own runtime library for whatever I/O functions are needed. .IP "\fB\-mlra\fR" 4 .IX Item "-mlra" -Enable Local Register Allocation. This is still experimental for \s-1FT32,\s0 +Enable Local Register Allocation. This is still experimental for \s-1FT32\s0, so by default the compiler uses standard reload. .IP "\fB\-mnodiv\fR" 4 .IX Item "-mnodiv" @@ -15374,7 +15373,7 @@ Use multiply and add/subtract instructions. Do not use multiply and add/subtract instructions. .IP "\fB\-mfdpic\fR" 4 .IX Item "-mfdpic" -Select the \s-1FDPIC ABI,\s0 which uses function descriptors to represent +Select the \s-1FDPIC\s0 \s-1ABI\s0, which uses function descriptors to represent pointers to functions. Without any PIC/PIE\-related options, it implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the @@ -15397,7 +15396,7 @@ Assume a large \s-1TLS\s0 segment when generating thread-local code. Do not assume a large \s-1TLS\s0 segment when generating thread-local code. .IP "\fB\-mgprel\-ro\fR" 4 .IX Item "-mgprel-ro" -Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC ABI\s0 for data +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data that is known to be in read-only sections. It's enabled by default, except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help make the global offset table smaller, it trades 1 instruction for 4. @@ -15541,7 +15540,7 @@ Select the processor type for which to generate code. Possible values are These \fB\-m\fR options are defined for GNU/Linux targets: .IP "\fB\-mglibc\fR" 4 .IX Item "-mglibc" -Use the \s-1GNU C\s0 library. This is the default except +Use the \s-1GNU\s0 C library. This is the default except on \fB*\-*\-linux\-*uclibc*\fR, \fB*\-*\-linux\-*musl*\fR and \&\fB*\-*\-linux\-*android*\fR targets. .IP "\fB\-muclibc\fR" 4 @@ -15625,8 +15624,8 @@ These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: .IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 .IX Item "-march=architecture-type" Generate code for the specified architecture. The choices for -\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0, \s0\fB1.1\fR for \s-1PA -1.1,\s0 and \fB2.0\fR for \s-1PA 2.0\s0 processors. Refer to +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0 +1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to \&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered architectures runs on higher numbered architectures, but not the @@ -15652,7 +15651,7 @@ floating-point operations, the compiler aborts. .IP "\fB\-mdisable\-indexing\fR" 4 .IX Item "-mdisable-indexing" Prevent the compiler from using indexing address modes. This avoids some -rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH.\s0 +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0. .IP "\fB\-mno\-space\-regs\fR" 4 .IX Item "-mno-space-regs" Generate code that assumes the target has no space registers. This allows @@ -15709,17 +15708,17 @@ cross-compilation. \&\fB\-msoft\-float\fR changes the calling convention in the output file; therefore, it is only useful if you compile \fIall\fR of a program with this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for this to work. .IP "\fB\-msio\fR" 4 .IX Item "-msio" -Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO. \s0 The default is +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is \&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, -\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO. \s0 These +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These options are available under HP-UX and HI-UX. .IP "\fB\-mgnu\-ld\fR" 4 .IX Item "-mgnu-ld" -Use options specific to \s-1GNU \s0\fBld\fR. +Use options specific to \s-1GNU\s0 \fBld\fR. This passes \fB\-shared\fR to \fBld\fR when building a shared library. It is the default when \s-1GCC\s0 is configured, explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not @@ -15729,10 +15728,10 @@ The \fBld\fR that is called is determined by the \&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available -on the 64\-bit HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +on the 64\-bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. .IP "\fB\-mhp\-ld\fR" 4 .IX Item "-mhp-ld" -Use options specific to \s-1HP \s0\fBld\fR. +Use options specific to \s-1HP\s0 \fBld\fR. This passes \fB\-b\fR to \fBld\fR when building a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all links. It is the default when \s-1GCC\s0 is configured, explicitly or @@ -15743,7 +15742,7 @@ The \fBld\fR that is called is determined by the \fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and finally by the user's \&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit -HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. .IP "\fB\-mlong\-calls\fR" 4 .IX Item "-mlong-calls" Generate code that uses long call sequences. This ensures that a call @@ -15752,7 +15751,7 @@ long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the -\&\s-1PA 2.0\s0 and \s-1PA 1.X\s0 architectures. Sibcalls are always limited at +\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at 240,000 bytes. .Sp Distances are measured from the beginning of functions when using the @@ -15780,7 +15779,7 @@ is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX \&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 and later. .Sp -\&\fB\-munix=93\fR provides the same predefines as \s-1GCC 3.3\s0 and 3.4. +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4. \&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. \&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, @@ -15846,7 +15845,7 @@ Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. .IP "\fB\-mno\-pic\fR" 4 .IX Item "-mno-pic" Generate code that does not use a global pointer register. The result -is not position independent code, and violates the \s-1IA\-64 ABI.\s0 +is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0. .IP "\fB\-mvolatile\-asm\-stop\fR" 4 .IX Item "-mvolatile-asm-stop" .PD 0 @@ -15950,7 +15949,7 @@ Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and 64. .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 .IX Item "-mtune=cpu-type" -Tune the instruction scheduling for a particular \s-1CPU,\s0 Valid values are +Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are \&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR, and \fBmckinley\fR. .IP "\fB\-milp32\fR" 4 @@ -16399,7 +16398,7 @@ have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions. .IP "\fB\-mcpu32\fR" 4 .IX Item "-mcpu32" -Generate output for a \s-1CPU32. \s0 This is the default +Generate output for a \s-1CPU32\s0. This is the default when the compiler is configured for CPU32\-based systems. It is equivalent to \fB\-march=cpu32\fR. .Sp @@ -16408,16 +16407,16 @@ Use this option for microcontrollers with a 68336, 68340, 68341, 68349 and 68360. .IP "\fB\-m5200\fR" 4 .IX Item "-m5200" -Generate output for a 520X ColdFire \s-1CPU. \s0 This is the default +Generate output for a 520X ColdFire \s-1CPU\s0. This is the default when the compiler is configured for 520X\-based systems. It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated in favor of that option. .Sp Use this option for microcontroller with a 5200 core, including -the \s-1MCF5202, MCF5203, MCF5204\s0 and \s-1MCF5206.\s0 +the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0. .IP "\fB\-m5206e\fR" 4 .IX Item "-m5206e" -Generate output for a 5206e ColdFire \s-1CPU. \s0 The option is now +Generate output for a 5206e ColdFire \s-1CPU\s0. The option is now deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. .IP "\fB\-m528x\fR" 4 .IX Item "-m528x" @@ -16426,15 +16425,15 @@ The option is now deprecated in favor of the equivalent \&\fB\-mcpu=528x\fR. .IP "\fB\-m5307\fR" 4 .IX Item "-m5307" -Generate output for a ColdFire 5307 \s-1CPU. \s0 The option is now deprecated +Generate output for a ColdFire 5307 \s-1CPU\s0. The option is now deprecated in favor of the equivalent \fB\-mcpu=5307\fR. .IP "\fB\-m5407\fR" 4 .IX Item "-m5407" -Generate output for a ColdFire 5407 \s-1CPU. \s0 The option is now deprecated +Generate output for a ColdFire 5407 \s-1CPU\s0. The option is now deprecated in favor of the equivalent \fB\-mcpu=5407\fR. .IP "\fB\-mcfv4e\fR" 4 .IX Item "-mcfv4e" -Generate output for a ColdFire V4e family \s-1CPU \s0(e.g. 547x/548x). +Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to \fB\-mcpu=547x\fR, and is now deprecated in favor of that option. @@ -16461,14 +16460,14 @@ The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. .IX Item "-m68881" .PD Generate floating-point instructions. This is the default for 68020 -and above, and for ColdFire devices that have an \s-1FPU. \s0 It defines the +and above, and for ColdFire devices that have an \s-1FPU\s0. It defines the macro \f(CW\*(C`_\|_HAVE_68881_\|_\*(C'\fR on M680x0 targets and \f(CW\*(C`_\|_mcffpu_\|_\*(C'\fR on ColdFire targets. .IP "\fB\-msoft\-float\fR" 4 .IX Item "-msoft-float" Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also -the default for ColdFire devices that have no \s-1FPU.\s0 +the default for ColdFire devices that have no \s-1FPU\s0. .IP "\fB\-mdiv\fR" 4 .IX Item "-mdiv" .PD 0 @@ -16478,8 +16477,8 @@ the default for ColdFire devices that have no \s-1FPU.\s0 Generate (do not generate) ColdFire hardware divide and remainder instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 -architectures. Otherwise, the default is taken from the target \s-1CPU -\&\s0(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For +architectures. Otherwise, the default is taken from the target \s-1CPU\s0 +(either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR). For example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for \&\fB\-mcpu=5206e\fR. .Sp @@ -16598,7 +16597,7 @@ that works if the \s-1GOT\s0 has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; \fB\-fPIC\fR suffices. .Sp -\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. While this is relatively efficient, it only works if the \s-1GOT\s0 is smaller than about 64k. Anything larger causes the linker to report an error such as: @@ -16740,7 +16739,7 @@ useful unless you also provide \fB\-mminmax\fR. Selects one of the built-in core configurations. Each MeP chip has one or more modules in it; each module has a core \s-1CPU\s0 and a variety of coprocessors, optional instructions, and peripherals. The -\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC,\s0 provides these +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these configurations through this option; using this option is the same as using all the corresponding command-line options. The default configuration is \fBdefault\fR. @@ -16843,7 +16842,7 @@ Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. .IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 .IX Item "-mcpu=cpu-type" -Use features of, and schedule code for, the given \s-1CPU.\s0 +Use features of, and schedule code for, the given \s-1CPU\s0. Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and \&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, @@ -16929,7 +16928,7 @@ configurations. .IP "\fB\-march=\fR\fIarch\fR" 4 .IX Item "-march=arch" Generate code that runs on \fIarch\fR, which can be the name of a -generic \s-1MIPS ISA,\s0 or the name of a particular processor. +generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor. The \s-1ISA\s0 names are: \&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, \&\fBmips32\fR, \fBmips32r2\fR, \fBmips32r3\fR, \fBmips32r5\fR, @@ -16964,7 +16963,7 @@ The processor names are: \&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR, \&\fBxlr\fR and \fBxlp\fR. The special value \fBfrom-abi\fR selects the -most compatible architecture for the selected \s-1ABI \s0(that is, +most compatible architecture for the selected \s-1ABI\s0 (that is, \&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). .Sp The native Linux/GNU toolchain also supports the value \fBnative\fR, @@ -17060,7 +17059,7 @@ Equivalent to \fB\-march=mips64r6\fR. .IX Item "-mno-mips16" .PD Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targeting a -\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE.\s0 +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE\s0. .Sp \&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. @@ -17075,7 +17074,7 @@ not intended for ordinary use in compiling user code. .IP "\fB\-mno\-interlink\-compressed\fR" 4 .IX Item "-mno-interlink-compressed" .PD -Require (do not require) that code using the standard (uncompressed) \s-1MIPS ISA\s0 +Require (do not require) that code using the standard (uncompressed) \s-1MIPS\s0 \s-1ISA\s0 be link-compatible with \s-1MIPS16\s0 and microMIPS code, and vice versa. .Sp For example, code using the standard \s-1ISA\s0 encoding cannot jump directly @@ -17103,20 +17102,20 @@ and are retained for backwards compatibility. .IP "\fB\-mabi=eabi\fR" 4 .IX Item "-mabi=eabi" .PD -Generate code for the given \s-1ABI.\s0 +Generate code for the given \s-1ABI\s0. .Sp Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally generates 64\-bit code when you select a 64\-bit architecture, but you can use \fB\-mgp32\fR to get 32\-bit code instead. .Sp -For information about the O64 \s-1ABI,\s0 see +For information about the O64 \s-1ABI\s0, see <\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. .Sp \&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with \&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \f(CW\*(C`mthc1\*(C'\fR and \f(CW\*(C`mfhc1\*(C'\fR instructions and is therefore only supported for -\&\s-1MIPS32R2, MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. +\&\s-1MIPS32R2\s0, \s-1MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. .Sp The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64\-bit register @@ -17127,11 +17126,11 @@ remains the same in that the even-numbered double-precision registers are saved. .Sp Two additional variants of the o32 \s-1ABI\s0 are supported to enable -a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX -\&\s0(\fB\-mfpxx\fR) and \s-1FP64A \s0(\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). +a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX\s0 +(\fB\-mfpxx\fR) and \s-1FP64A\s0 (\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). The \s-1FPXX\s0 extension mandates that all code must execute correctly when run using 32\-bit or 64\-bit registers. The code can be interlinked -with either \s-1FP32\s0 or \s-1FP64,\s0 but not both. +with either \s-1FP32\s0 or \s-1FP64\s0, but not both. The \s-1FP64A\s0 extension is similar to the \s-1FP64\s0 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the \f(CW\*(C`FRE\*(C'\fR mode of FPUs in \s-1MIPS32R5\s0 @@ -17178,7 +17177,7 @@ executables both smaller and quicker. .PD Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects -\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI,\s0 this option +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI\s0, this option has no effect without \fB\-msym32\fR. .Sp You can make \fB\-mplt\fR the default by configuring @@ -17193,7 +17192,7 @@ You can make \fB\-mplt\fR the default by configuring Lift (do not lift) the usual restrictions on the size of the global offset table. .Sp -\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. While this is relatively efficient, it only works if the \s-1GOT\s0 is smaller than about 64k. Anything larger causes the linker to report an error such as: @@ -17261,8 +17260,8 @@ operations. This is the default. .IX Item "-mno-odd-spreg" .PD Enable the use of odd-numbered single-precision floating-point registers -for the o32 \s-1ABI. \s0 This is the default for processors that are known to -support these registers. When using the o32 \s-1FPXX ABI, \s0\fB\-mno\-odd\-spreg\fR +for the o32 \s-1ABI\s0. This is the default for processors that are known to +support these registers. When using the o32 \s-1FPXX\s0 \s-1ABI\s0, \fB\-mno\-odd\-spreg\fR is set by default. .IP "\fB\-mabs=2008\fR" 4 .IX Item "-mabs=2008" @@ -17271,7 +17270,7 @@ is set by default. .IX Item "-mabs=legacy" .PD These options control the treatment of the special not-a-number (NaN) -\&\s-1IEEE 754\s0 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and +\&\s-1IEEE\s0 754 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and \&\f(CW\*(C`neg.\f(CIfmt\f(CW\*(C'\fR machine instructions. .Sp By default or when \fB\-mabs=legacy\fR is used the legacy @@ -17282,7 +17281,7 @@ manipulate the sign bit of floating-point datum manually is used instead unless the \fB\-ffinite\-math\-only\fR option has also been specified. .Sp -The \fB\-mabs=2008\fR option selects the \s-1IEEE 754\-2008\s0 treatment. In +The \fB\-mabs=2008\fR option selects the \s-1IEEE\s0 754\-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used @@ -17294,14 +17293,14 @@ for the respective operations. .IX Item "-mnan=legacy" .PD These options control the encoding of the special not-a-number (NaN) -\&\s-1IEEE 754\s0 floating-point data. +\&\s-1IEEE\s0 754 floating-point data. .Sp The \fB\-mnan=legacy\fR option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signalling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1. .Sp -The \fB\-mnan=2008\fR option selects the \s-1IEEE 754\-2008\s0 encoding. In +The \fB\-mnan=2008\fR option selects the \s-1IEEE\s0 754\-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0. @@ -17331,8 +17330,8 @@ configurations; see the installation documentation for details. .IP "\fB\-mno\-dsp\fR" 4 .IX Item "-mno-dsp" .PD -Use (do not use) revision 1 of the \s-1MIPS DSP ASE. - \s0 This option defines the +Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines \&\f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 1. .IP "\fB\-mdspr2\fR" 4 @@ -17341,8 +17340,8 @@ preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines .IP "\fB\-mno\-dspr2\fR" 4 .IX Item "-mno-dspr2" .PD -Use (do not use) revision 2 of the \s-1MIPS DSP ASE. - \s0 This option defines the +Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the preprocessor macros \f(CW\*(C`_\|_mips_dsp\*(C'\fR and \f(CW\*(C`_\|_mips_dspr2\*(C'\fR. It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. .IP "\fB\-msmartmips\fR" 4 @@ -17351,7 +17350,7 @@ It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. .IP "\fB\-mno\-smartmips\fR" 4 .IX Item "-mno-smartmips" .PD -Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE.\s0 +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0. .IP "\fB\-mpaired\-single\fR" 4 .IX Item "-mpaired-single" .PD 0 @@ -17376,7 +17375,7 @@ hardware floating-point support to be enabled. .IP "\fB\-mno\-mips3d\fR" 4 .IX Item "-mno-mips3d" .PD -Use (do not use) the \s-1MIPS\-3D ASE. \s0 +Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0. The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. .IP "\fB\-mmicromips\fR" 4 .IX Item "-mmicromips" @@ -17401,7 +17400,7 @@ Use (do not use) \s-1MT\s0 Multithreading instructions. .IP "\fB\-mno\-mcu\fR" 4 .IX Item "-mno-mcu" .PD -Use (do not use) the \s-1MIPS MCU ASE\s0 instructions. +Use (do not use) the \s-1MIPS\s0 \s-1MCU\s0 \s-1ASE\s0 instructions. .IP "\fB\-meva\fR" 4 .IX Item "-meva" .PD 0 @@ -17433,7 +17432,7 @@ determined. Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. .Sp The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on -the \s-1ABI. \s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use 32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, or the same size as integer registers, whichever is smaller. @@ -17444,7 +17443,7 @@ or the same size as integer registers, whichever is smaller. .IX Item "-mno-sym32" .PD Assume (do not assume) that all symbols have 32\-bit values, regardless -of the selected \s-1ABI. \s0 This option is useful in combination with +of the selected \s-1ABI\s0. This option is useful in combination with \&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 to generate shorter and faster references to symbolic addresses. .IP "\fB\-G\fR \fInum\fR" 4 @@ -17549,13 +17548,13 @@ but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically -redirect PC-relative loads to the instruction \s-1RAM.\s0 +redirect PC-relative loads to the instruction \s-1RAM\s0. .IP "\fB\-mcode\-readable=no\fR" 4 .IX Item "-mcode-readable=no" Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data \&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect -PC-relative loads to the instruction \s-1RAM.\s0 +PC-relative loads to the instruction \s-1RAM\s0. .RE .RS 4 .RE @@ -17597,7 +17596,7 @@ The default is \fB\-mcheck\-zero\-division\fR. .PD \&\s-1MIPS\s0 systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in -smaller code, but is only supported on \s-1MIPS II\s0 and later. Also, some +smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to allow conditional traps on architectures that support them and @@ -17635,7 +17634,7 @@ This option has no effect on abicalls code. The default is .IX Item "-mno-mad" .PD Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR -instructions, as provided by the R4650 \s-1ISA.\s0 +instructions, as provided by the R4650 \s-1ISA\s0. .IP "\fB\-mimadd\fR" 4 .IX Item "-mimadd" .PD 0 @@ -17673,7 +17672,7 @@ assembler files (with a \fB.s\fR suffix) when assembling them. .IX Item "-mno-fix-24k" .PD Work around the 24K E48 (lost data on stores during refill) errata. -The workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +The workarounds are implemented by the assembler rather than by \s-1GCC\s0. .IP "\fB\-mfix\-r4000\fR" 4 .IX Item "-mfix-r4000" .PD 0 @@ -17733,8 +17732,8 @@ otherwise. .IP "\fB\-mno\-fix\-rm7000\fR" 4 .IX Item "-mno-fix-rm7000" .PD -Work around the \s-1RM7000 \s0\f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The -workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +Work around the \s-1RM7000\s0 \f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC\s0. .IP "\fB\-mfix\-vr4120\fR" 4 .IX Item "-mfix-vr4120" .PD 0 @@ -17760,10 +17759,10 @@ instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itse .RE .IP "\fB\-mfix\-vr4130\fR" 4 .IX Item "-mfix-vr4130" -Work around the \s-1VR4130 \s0\f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The -workarounds are implemented by the assembler rather than by \s-1GCC,\s0 +Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC\s0, although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the -\&\s-1VR4130 \s0\f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR instructions are available instead. .IP "\fB\-mfix\-sb1\fR" 4 .IX Item "-mfix-sb1" @@ -17771,7 +17770,7 @@ instructions are available instead. .IP "\fB\-mno\-fix\-sb1\fR" 4 .IX Item "-mno-fix-sb1" .PD -Work around certain \s-1SB\-1 CPU\s0 core errata. +Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata. (This flag currently works around the \s-1SB\-1\s0 revision 2 \&\*(L"F1\*(R" and \*(L"F2\*(R" floating-point errata.) .IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 @@ -17910,7 +17909,7 @@ Specifies whether \s-1FP\s0 exceptions are enabled. This affects how The default is that \s-1FP\s0 exceptions are enabled. .Sp -For instance, on the \s-1SB\-1,\s0 if \s-1FP\s0 exceptions are disabled, and we are emitting +For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting 64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one \&\s-1FP\s0 pipe. .IP "\fB\-mvr4130\-align\fR" 4 @@ -17924,7 +17923,7 @@ instructions together if the first one is 8\-byte aligned. When this option is enabled, \s-1GCC\s0 aligns pairs of instructions that it thinks should execute in parallel. .Sp -This option only has an effect when optimizing for the \s-1VR4130.\s0 +This option only has an effect when optimizing for the \s-1VR4130\s0. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level \fB\-O3\fR. .IP "\fB\-msynci\fR" 4 @@ -17990,8 +17989,8 @@ The default is \fB\-mno\-mcount\-ra\-address\fR. .IP "\fB\-mno\-frame\-header\-opt\fR" 4 .IX Item "-mno-frame-header-opt" .PD -Enable (disable) frame header optimization in the o32 \s-1ABI. \s0 When using the -o32 \s-1ABI,\s0 calling functions will allocate 16 bytes on the stack for the called +Enable (disable) frame header optimization in the o32 \s-1ABI\s0. When using the +o32 \s-1ABI\s0, calling functions will allocate 16 bytes on the stack for the called function to write out register arguments. When enabled, this optimization will suppress the allocation of the frame header if it can be determined that it is unused. @@ -18026,7 +18025,7 @@ to the \f(CW\*(C`rE\*(C'\fR epsilon register. .PD Generate code that passes function parameters and return values that (in the called function) are seen as registers \f(CW$0\fR and up, as opposed to -the \s-1GNU ABI\s0 which uses global registers \f(CW$231\fR and up. +the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up. .IP "\fB\-mzero\-extend\fR" 4 .IX Item "-mzero-extend" .PD 0 @@ -18110,7 +18109,7 @@ Do not generate code using features specific to the \s-1AM33\s0 processor. This is the default. .IP "\fB\-mam33\-2\fR" 4 .IX Item "-mam33-2" -Generate code using features specific to the \s-1AM33/2.0\s0 processor. +Generate code using features specific to the \s-1AM33/2\s0.0 processor. .IP "\fB\-mam34\fR" 4 .IX Item "-mam34" Generate code using features specific to the \s-1AM34\s0 processor. @@ -18195,8 +18194,8 @@ header file. The option also sets the \s-1ISA\s0 to use. If the \s-1MCU\s0 name is one that is known to only support the 430 \s-1ISA\s0 then that is selected, otherwise the 430X \s-1ISA\s0 is selected. A generic \s-1MCU\s0 name of \fBmsp430\fR can also be -used to select the 430 \s-1ISA. \s0 Similarly the generic \fBmsp430x\fR \s-1MCU\s0 -name selects the 430X \s-1ISA.\s0 +used to select the 430 \s-1ISA\s0. Similarly the generic \fBmsp430x\fR \s-1MCU\s0 +name selects the 430X \s-1ISA\s0. .Sp In addition an MCU-specific linker script is added to the linker command line. The script's name is the name of the \s-1MCU\s0 with @@ -18220,7 +18219,7 @@ This option enables or disables warnings about conflicts between the .IX Item "-mcpu=" Specifies the \s-1ISA\s0 to use. Accepted values are \fBmsp430\fR, \&\fBmsp430x\fR and \fBmsp430xv2\fR. This option is deprecated. The -\&\fB\-mmcu=\fR option should be used to select the \s-1ISA.\s0 +\&\fB\-mmcu=\fR option should be used to select the \s-1ISA\s0. .IP "\fB\-msim\fR" 4 .IX Item "-msim" Link to the simulator runtime libraries and linker script. Overrides @@ -18420,7 +18419,7 @@ global pointer. .Sp The default is \fB\-mgpopt\fR except when \fB\-fpic\fR or \&\fB\-fPIC\fR is specified to generate position-independent code. -Note that the Nios \s-1II ABI\s0 does not permit GP-relative accesses from +Note that the Nios \s-1II\s0 \s-1ABI\s0 does not permit GP-relative accesses from shared libraries. .Sp You may need to specify \fB\-mno\-gpopt\fR explicitly when building @@ -18497,8 +18496,8 @@ and not emit \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`mulx\*(C'\fR. .IP "\fB\-mno\-cdx\fR" 4 .IX Item "-mno-cdx" .PD -Enable or disable generation of Nios \s-1II R2 BMX \s0(bit manipulation) and -\&\s-1CDX \s0(code density) instructions. Enabling these instructions also +Enable or disable generation of Nios \s-1II\s0 R2 \s-1BMX\s0 (bit manipulation) and +\&\s-1CDX\s0 (code density) instructions. Enabling these instructions also requires \fB\-march=r2\fR. Since these instructions are optional extensions to the R2 architecture, the default is not to emit them. .IP "\fB\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR" 4 @@ -18515,7 +18514,7 @@ of the default behavior of using a library call. .Sp The following values of \fIinsn\fR are supported. Except as otherwise noted, floating-point operations are expected to be implemented with -normal \s-1IEEE 754\s0 semantics and correspond directly to the C operators or the +normal \s-1IEEE\s0 754 semantics and correspond directly to the C operators or the equivalent \s-1GCC\s0 built-in functions. .Sp Single-precision floating point: @@ -18674,14 +18673,14 @@ configuration by using the \f(CW\*(C`target("custom\-fpu\-cfg=\f(CIname\f(CW")\* function attribute or pragma. .PP -These additional \fB\-m\fR options are available for the Altera Nios \s-1II -ELF \s0(bare-metal) target: +These additional \fB\-m\fR options are available for the Altera Nios \s-1II\s0 +\&\s-1ELF\s0 (bare-metal) target: .IP "\fB\-mhal\fR" 4 .IX Item "-mhal" -Link with \s-1HAL BSP. \s0 This suppresses linking with the GCC-provided C runtime +Link with \s-1HAL\s0 \s-1BSP\s0. This suppresses linking with the GCC-provided C runtime startup and termination code, and is typically used in conjunction with \&\fB\-msys\-crt0=\fR to specify the location of the alternate startup code -provided by the \s-1HAL BSP.\s0 +provided by the \s-1HAL\s0 \s-1BSP\s0. .IP "\fB\-msmallc\fR" 4 .IX Item "-msmallc" Link with a limited version of the C library, \fB\-lsmallc\fR, rather than @@ -18695,7 +18694,7 @@ when linking. This option is only useful in conjunction with \fB\-mhal\fR. \&\fIsystemlib\fR is the library name of the library that provides low-level system calls required by the C library, e.g. \f(CW\*(C`read\*(C'\fR and \f(CW\*(C`write\*(C'\fR. -This option is typically used to link with a library provided by a \s-1HAL BSP.\s0 +This option is typically used to link with a library provided by a \s-1HAL\s0 \s-1BSP\s0. .PP \fINvidia \s-1PTX\s0 Options\fR .IX Subsection "Nvidia PTX Options" @@ -18707,7 +18706,7 @@ These options are defined for Nvidia \s-1PTX:\s0 .IP "\fB\-m64\fR" 4 .IX Item "-m64" .PD -Generate code for 32\-bit or 64\-bit \s-1ABI.\s0 +Generate code for 32\-bit or 64\-bit \s-1ABI\s0. .IP "\fB\-mmainkernel\fR" 4 .IX Item "-mmainkernel" Link in code for a _\|_main kernel. This is for stand-alone instead of @@ -18736,13 +18735,13 @@ Return floating-point results in ac0 (fr0 in Unix assembler syntax). Return floating-point results in memory. This is the default. .IP "\fB\-m40\fR" 4 .IX Item "-m40" -Generate code for a \s-1PDP\-11/40.\s0 +Generate code for a \s-1PDP\-11/40\s0. .IP "\fB\-m45\fR" 4 .IX Item "-m45" -Generate code for a \s-1PDP\-11/45. \s0 This is the default. +Generate code for a \s-1PDP\-11/45\s0. This is the default. .IP "\fB\-m10\fR" 4 .IX Item "-m10" -Generate code for a \s-1PDP\-11/10.\s0 +Generate code for a \s-1PDP\-11/10\s0. .IP "\fB\-mbcopy\-builtin\fR" 4 .IX Item "-mbcopy-builtin" Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the @@ -18814,14 +18813,14 @@ for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. generated with this option runs on any of the other \s-1AE\s0 types. The code is not as efficient as it would be if compiled for a specific \&\s-1AE\s0 type, and some types of operation (e.g., multiplication) do not -work properly on all types of \s-1AE.\s0 +work properly on all types of \s-1AE\s0. .Sp -\&\fB\-mae=MUL\fR selects a \s-1MUL AE\s0 type. This is the most useful \s-1AE\s0 type +\&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type for compiled code, and is the default. .Sp -\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE. \s0 Code compiled with this +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC\s0 \s-1AE\s0. Code compiled with this option may suffer from poor performance of byte (char) manipulation, -since the \s-1DSP AE\s0 does not provide hardware support for byte load/stores. +since the \s-1DSP\s0 \s-1AE\s0 does not provide hardware support for byte load/stores. .IP "\fB\-msymbol\-as\-address\fR" 4 .IX Item "-msymbol-as-address" Enable the compiler to directly use a symbol name as an address in a @@ -18834,7 +18833,7 @@ rather than being permanently enabled. .IX Item "-mno-inefficient-warnings" Disables warnings about the generation of inefficient code. These warnings can be generated, for example, when compiling code that -performs byte-level memory operations on the \s-1MAC AE\s0 type. The \s-1MAC AE\s0 has +performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has no hardware support for byte-level memory operations, so all byte load/stores must be synthesized from word load/store operations. This is inefficient and a warning is generated to indicate @@ -18869,9 +18868,9 @@ Specifies the type of hardware multiplication and division support to be used. The simplest is \f(CW\*(C`none\*(C'\fR, which uses software for both multiplication and division. This is the default. The \f(CW\*(C`g13\*(C'\fR value is for the hardware multiply/divide peripheral found on the -\&\s-1RL78/G13 \s0(S2 core) targets. The \f(CW\*(C`g14\*(C'\fR value selects the use of -the multiplication and division instructions supported by the \s-1RL78/G14 -\&\s0(S3 core) parts. The value \f(CW\*(C`rl78\*(C'\fR is an alias for \f(CW\*(C`g14\*(C'\fR and +\&\s-1RL78/G13\s0 (S2 core) targets. The \f(CW\*(C`g14\*(C'\fR value selects the use of +the multiplication and division instructions supported by the \s-1RL78/G14\s0 +(S3 core) parts. The value \f(CW\*(C`rl78\*(C'\fR is an alias for \f(CW\*(C`g14\*(C'\fR and the value \f(CW\*(C`mg10\*(C'\fR is an alias for \f(CW\*(C`none\*(C'\fR. .Sp In addition a C preprocessor macro is defined, based upon the setting @@ -18888,7 +18887,7 @@ of this option. Possible values are: \f(CW\*(C`_\|_RL78_MUL_NONE_\|_\*(C'\fR, .IX Item "-mcpu=rl78" .PD Specifies the \s-1RL78\s0 core to target. The default is the G14 core, also -known as an S3 core or just \s-1RL78. \s0 The G13 or S2 core does not have +known as an S3 core or just \s-1RL78\s0. The G13 or S2 core does not have multiply or divide instructions, instead it uses a hardware peripheral for these operations. The G10 or S1 core does not have register banks, so it uses a different calling convention. @@ -18940,10 +18939,10 @@ Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is \&\fB\-m32bit\-doubles\fR. .PP -\fI\s-1IBM RS/6000\s0 and PowerPC Options\fR +\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR .IX Subsection "IBM RS/6000 and PowerPC Options" .PP -These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: +These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC: .IP "\fB\-mpowerpc\-gpopt\fR" 4 .IX Item "-mpowerpc-gpopt" .PD 0 @@ -18988,7 +18987,7 @@ These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: .PD You use these options to specify which instructions are available on the processor you are using. The default value of these options is -determined when configuring \s-1GCC. \s0 Specifying the +determined when configuring \s-1GCC\s0. Specifying the \&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option rather than the options listed above. @@ -19062,9 +19061,9 @@ following options: \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float \&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx -\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mcrypto \-mdirect\-move \-mhtm \-mpower8\-fusion \-mpower8\-vector \&\-mquad\-memory \-mquad\-memory\-atomic \-mmodulo \-mfloat128 \-mfloat128\-hardware -\&\-mpower9\-fusion \-mpower9\-vector\fR +\&\-mpower9\-fusion \-mpower9\-vector \-mpower9\-dform\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -19073,7 +19072,7 @@ capabilities. If you wish to set an individual option to a particular value, you may specify it after the \fB\-mcpu\fR option, like \&\fB\-mcpu=970 \-mno\-altivec\fR. .Sp -On \s-1AIX,\s0 the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are not enabled or disabled by the \fB\-mcpu\fR option at present because \&\s-1AIX\s0 does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your @@ -19161,14 +19160,14 @@ Generate code that allows \fBld\fR and \fBld.so\fR to build executables and shared libraries with non-executable \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections. This is a PowerPC -32\-bit \s-1SYSV ABI\s0 option. +32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IP "\fB\-mbss\-plt\fR" 4 .IX Item "-mbss-plt" -Generate code that uses a \s-1BSS \s0\f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR +Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR fills in, and requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections that are both writable and executable. -This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IP "\fB\-misel\fR" 4 .IX Item "-misel" .PD 0 @@ -19180,6 +19179,11 @@ This switch enables or disables the generation of \s-1ISEL\s0 instructions. .IX Item "-misel=yes/no" This switch has been deprecated. Use \fB\-misel\fR and \&\fB\-mno\-isel\fR instead. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Enable Local Register Allocation. This is still experimental for PowerPC, +so by default the compiler uses standard reload +(i.e. \fB\-mno\-lra\fR). .IP "\fB\-mspe\fR" 4 .IX Item "-mspe" .PD 0 @@ -19217,7 +19221,7 @@ more direct access to the \s-1VSX\s0 instruction set. .PD Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version -2.07 of the PowerPC \s-1ISA.\s0 +2.07 of the PowerPC \s-1ISA\s0. .IP "\fB\-mdirect\-move\fR" 4 .IX Item "-mdirect-move" .PD 0 @@ -19226,7 +19230,16 @@ access to the cryptographic instructions that were added in version .PD Generate code that uses (does not use) the instructions to move data between the general purpose registers and the vector/scalar (\s-1VSX\s0) -registers that were added in version 2.07 of the PowerPC \s-1ISA.\s0 +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mhtm\fR" 4 +.IX Item "-mhtm" +.PD 0 +.IP "\fB\-mno\-htm\fR" 4 +.IX Item "-mno-htm" +.PD +Enable (disable) the use of the built-in functions that allow direct +access to the Hardware Transactional Memory (\s-1HTM\s0) instructions that +were added in version 2.07 of the PowerPC \s-1ISA\s0. .IP "\fB\-mpower8\-fusion\fR" 4 .IX Item "-mpower8-fusion" .PD 0 @@ -19243,7 +19256,7 @@ later processors. .IX Item "-mno-power8-vector" .PD Generate code that uses (does not use) the vector and scalar -instructions that were added in version 2.07 of the PowerPC \s-1ISA. \s0 Also +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also enable the use of built-in functions that allow more direct access to the vector instructions. .IP "\fB\-mquad\-memory\fR" 4 @@ -19273,7 +19286,7 @@ instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of Generate code that uses (does not use) the scalar double precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.06 of the -PowerPC \s-1ISA. \s0\fB\-mupper\-regs\-df\fR is turned on by default if you +PowerPC \s-1ISA\s0. \fB\-mupper\-regs\-df\fR is turned on by default if you use any of the \fB\-mcpu=power7\fR, \fB\-mcpu=power8\fR, or \&\fB\-mvsx\fR options. .IP "\fB\-mupper\-regs\-sf\fR" 4 @@ -19285,7 +19298,7 @@ use any of the \fB\-mcpu=power7\fR, \fB\-mcpu=power8\fR, or Generate code that uses (does not use) the scalar single precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.07 of the -PowerPC \s-1ISA. \s0\fB\-mupper\-regs\-sf\fR is turned on by default if you +PowerPC \s-1ISA\s0. \fB\-mupper\-regs\-sf\fR is turned on by default if you use either of the \fB\-mcpu=power8\fR or \fB\-mpower8\-vector\fR options. .IP "\fB\-mupper\-regs\fR" 4 @@ -19312,23 +19325,35 @@ hardware instructions. .Sp The \s-1VSX\s0 instruction set (\fB\-mvsx\fR, \fB\-mcpu=power7\fR, or \&\fB\-mcpu=power8\fR) must be enabled to use the \fB\-mfloat128\fR -option. The \f(CW\*(C`\-mfloat128\*(C'\fR option only works on PowerPC 64\-bit +option. The \fB\-mfloat128\fR option only works on PowerPC 64\-bit Linux systems. +.Sp +If you use the \s-1ISA\s0 3.0 instruction set (\fB\-mcpu=power9\fR), the +\&\fB\-mfloat128\fR option will also enable the generation of \s-1ISA\s0 3.0 +\&\s-1IEEE\s0 128\-bit floating point instructions. Otherwise, \s-1IEEE\s0 128\-bit +floating point will be done with software emulation. .IP "\fB\-mfloat128\-hardware\fR" 4 .IX Item "-mfloat128-hardware" .PD 0 .IP "\fB\-mno\-float128\-hardware\fR" 4 .IX Item "-mno-float128-hardware" .PD -Enable/disable using \s-1ISA 3.0\s0 hardware instructions to support the +Enable/disable using \s-1ISA\s0 3.0 hardware instructions to support the \&\fI_\|_float128\fR data type. +.Sp +If you use \fB\-mfloat128\-hardware\fR, it will enable the option +\&\fB\-mfloat128\fR as well. +.Sp +If you select \s-1ISA\s0 3.0 instructions with \fB\-mcpu=power9\fR, but do +not use either \fB\-mfloat128\fR or \fB\-mfloat128\-hardware\fR, +the \s-1IEEE\s0 128\-bit floating point support will not be enabled. .IP "\fB\-mmodulo\fR" 4 .IX Item "-mmodulo" .PD 0 .IP "\fB\-mno\-modulo\fR" 4 .IX Item "-mno-modulo" .PD -Generate code that uses (does not use) the \s-1ISA 3.0\s0 integer modulo +Generate code that uses (does not use) the \s-1ISA\s0 3.0 integer modulo instructions. The \fB\-mmodulo\fR option is enabled by default with the \fB\-mcpu=power9\fR option. .IP "\fB\-mpower9\-fusion\fR" 4 @@ -19347,9 +19372,19 @@ processors. .IX Item "-mno-power9-vector" .PD Generate code that uses (does not use) the vector and scalar -instructions that were added in version 2.07 of the PowerPC \s-1ISA. \s0 Also +instructions that were added in version 3.0 of the PowerPC \s-1ISA\s0. Also enable the use of built-in functions that allow more direct access to the vector instructions. +.IP "\fB\-mpower9\-dform\fR" 4 +.IX Item "-mpower9-dform" +.PD 0 +.IP "\fB\-mno\-power9\-dform\fR" 4 +.IX Item "-mno-power9-dform" +.PD +Enable (disable) scalar d\-form (register + offset) memory instructions +to load/store traditional Altivec registers. If the \fI\s-1LRA\s0\fR register +allocator is enabled, also enable (disable) vector d\-form memory +instructions. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -19392,12 +19427,12 @@ pointer to 64 bits, and generates code for PowerPC64, as for .IP "\fB\-mminimal\-toc\fR" 4 .IX Item "-mminimal-toc" .PD -Modify generation of the \s-1TOC \s0(Table Of Contents), which is created for +Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for every executable file. The \fB\-mfull\-toc\fR option is selected by default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for each unique non-automatic variable reference in your program. \s-1GCC\s0 -also places floating-point constants in the \s-1TOC. \s0 However, only -16,384 entries are available in the \s-1TOC.\s0 +also places floating-point constants in the \s-1TOC\s0. However, only +16,384 entries are available in the \s-1TOC\s0. .Sp If you receive a linker error message that saying you have overflowed the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used @@ -19405,7 +19440,7 @@ with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. \&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to generate code to calculate the sum of an address and a constant at -run time instead of putting that sum into the \s-1TOC. \s0 You may specify one +run time instead of putting that sum into the \s-1TOC\s0. You may specify one or both of these options. Each causes \s-1GCC\s0 to produce very slightly slower and larger code at the expense of conserving \s-1TOC\s0 space. .Sp @@ -19421,7 +19456,7 @@ only on files that contain less frequently-executed code. .IP "\fB\-maix32\fR" 4 .IX Item "-maix32" .PD -Enable 64\-bit \s-1AIX ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit \&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and @@ -19432,8 +19467,8 @@ implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. .IP "\fB\-mno\-xl\-compat\fR" 4 .IX Item "-mno-xl-compat" .PD -Produce code that conforms more closely to \s-1IBM XL\s0 compiler semantics -when using AIX-compatible \s-1ABI. \s0 Pass floating-point arguments to +Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics +when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to prototyped functions beyond the register save area (\s-1RSA\s0) on the stack in addition to argument FPRs. Do not assume that most significant double in 128\-bit long double value is properly rounded when comparing @@ -19442,16 +19477,16 @@ support routines. .Sp The \s-1AIX\s0 calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the -address of its arguments with fewer arguments than declared. \s-1IBM XL\s0 +address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0 compilers access floating-point arguments that do not fit in the \&\s-1RSA\s0 from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by -default and only is necessary when calling subroutines compiled by \s-1IBM -XL\s0 compilers without optimization. +default and only is necessary when calling subroutines compiled by \s-1IBM\s0 +\&\s-1XL\s0 compilers without optimization. .IP "\fB\-mpe\fR" 4 .IX Item "-mpe" -Support \fI\s-1IBM RS/6000 SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an application written to use message passing with special startup code to enable the application to run. The system must have \s-1PE\s0 installed in the standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file @@ -19465,11 +19500,11 @@ option are incompatible. .IP "\fB\-malign\-power\fR" 4 .IX Item "-malign-power" .PD -On \s-1AIX,\s0 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option \&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified -alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI.\s0 +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0. .Sp On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR is not supported. @@ -19503,7 +19538,7 @@ Specify type of floating-point unit. Valid values for \fIname\fR are and \fBdp_full\fR (equivalent to \fB\-mdouble\-float\fR). .IP "\fB\-mxilinx\-fpu\fR" 4 .IX Item "-mxilinx-fpu" -Perform optimizations for the floating-point unit on Xilinx \s-1PPC 405/440.\s0 +Perform optimizations for the floating-point unit on Xilinx \s-1PPC\s0 405/440. .IP "\fB\-mmultiple\fR" 4 .IX Item "-mmultiple" .PD 0 @@ -19574,7 +19609,7 @@ mapped to \fB\-ffp\-contract=off\fR. .IX Item "-mno-mulhw" .PD Generate code that uses (does not use) the half-word multiply and -multiply-accumulate instructions on the \s-1IBM 405, 440, 464\s0 and 476 processors. +multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors. .IP "\fB\-mdlmzb\fR" 4 @@ -19584,7 +19619,7 @@ processors. .IX Item "-mno-dlmzb" .PD Generate code that uses (does not use) the string-search \fBdlmzb\fR -instruction on the \s-1IBM 405, 440, 464\s0 and 476 processors. This instruction is +instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors. .IP "\fB\-mno\-bit\-align\fR" 4 .IX Item "-mno-bit-align" @@ -19664,7 +19699,7 @@ processor in big-endian mode. The \fB\-mbig\-endian\fR option is the same as \fB\-mbig\fR. .IP "\fB\-mdynamic\-no\-pic\fR" 4 .IX Item "-mdynamic-no-pic" -On Darwin and Mac \s-1OS X\s0 systems, compile code so that it is not +On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries. @@ -19770,11 +19805,11 @@ On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system. .IP "\fB\-maix\-struct\-return\fR" 4 .IX Item "-maix-struct-return" -Return all structures in memory (as specified by the \s-1AIX ABI\s0). +Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0). .IP "\fB\-msvr4\-struct\-return\fR" 4 .IX Item "-msvr4-struct-return" Return structures smaller than 8 bytes in registers (as specified by the -\&\s-1SVR4 ABI\s0). +\&\s-1SVR4\s0 \s-1ABI\s0). .IP "\fB\-mabi=\fR\fIabi-type\fR" 4 .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. @@ -19783,29 +19818,29 @@ Valid values are \fBaltivec\fR, \fBno-altivec\fR, \fBspe\fR, \&\fBelfv1\fR, \fBelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" -Extend the current \s-1ABI\s0 with \s-1SPE ABI\s0 extensions. This does not change -the default \s-1ABI,\s0 instead it adds the \s-1SPE ABI\s0 extensions to the current -\&\s-1ABI.\s0 +Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change +the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current +\&\s-1ABI\s0. .IP "\fB\-mabi=no\-spe\fR" 4 .IX Item "-mabi=no-spe" -Disable Book-E \s-1SPE ABI\s0 extensions for the current \s-1ABI.\s0 +Disable Book-E \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0. .IP "\fB\-mabi=ibmlongdouble\fR" 4 .IX Item "-mabi=ibmlongdouble" Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double. -This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IP "\fB\-mabi=ieeelongdouble\fR" 4 .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. .IP "\fB\-mabi=elfv1\fR" 4 .IX Item "-mabi=elfv1" -Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI.\s0 +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. Overriding the default \s-1ABI\s0 requires special system support and is likely to fail in spectacular ways. .IP "\fB\-mabi=elfv2\fR" 4 .IX Item "-mabi=elfv2" -Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI.\s0 +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. Overriding the default \s-1ABI\s0 requires special system support and is likely to fail in spectacular ways. @@ -19959,7 +19994,7 @@ On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jb callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl -callee\*(C'\fR if the \s-1PPC \s0\f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; +callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32\-bit address of the callee @@ -20055,7 +20090,7 @@ which handle the double-precision reciprocal square root calculations. .PD Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC -\&\s-1ABI. \s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or +\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or \&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an @@ -20128,14 +20163,14 @@ pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. .PD Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions -of \s-1GCC.\s0 +of \s-1GCC\s0. .Sp -Older versions of \s-1GCC \s0(prior to 4.9.0) incorrectly did not align a +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a structure parameter on a 128\-bit boundary when that structure contained a member requiring 128\-bit alignment. This is corrected in more -recent versions of \s-1GCC. \s0 This option may be used to generate code +recent versions of \s-1GCC\s0. This option may be used to generate code that is compatible with functions compiled with older versions of -\&\s-1GCC.\s0 +\&\s-1GCC\s0. .Sp The \fB\-mno\-compat\-align\-parm\fR option is the default. .PP @@ -20170,12 +20205,12 @@ values, however, so the \s-1FPU\s0 hardware is not used for doubles if the .Sp \&\fINote\fR If the \fB\-fpu\fR option is enabled then \&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. -This is because the \s-1RX FPU\s0 instructions are themselves unsafe. +This is because the \s-1RX\s0 \s-1FPU\s0 instructions are themselves unsafe. .IP "\fB\-mcpu=\fR\fIname\fR" 4 .IX Item "-mcpu=name" -Selects the type of \s-1RX CPU\s0 to be targeted. Currently three types are +Selects the type of \s-1RX\s0 \s-1CPU\s0 to be targeted. Currently three types are supported, the generic \fB\s-1RX600\s0\fR and \fB\s-1RX200\s0\fR series hardware and -the specific \fB\s-1RX610\s0\fR \s-1CPU. \s0 The default is \fB\s-1RX600\s0\fR. +the specific \fB\s-1RX610\s0\fR \s-1CPU\s0. The default is \fB\s-1RX600\s0\fR. .Sp The only difference between \fB\s-1RX600\s0\fR and \fB\s-1RX610\s0\fR is that the \&\fB\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. @@ -20426,7 +20461,7 @@ register is always saved two words below the backchain. .Sp As long as the stack frame backchain is not used, code generated with \&\fB\-mpacked\-stack\fR is call-compatible with code generated with -\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC 2.95\s0 for +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for S/390 or zSeries generated code that uses the stack frame backchain at run time, not just for debugging purposes. Such code is not call-compatible with code compiled with \fB\-mpacked\-stack\fR. Also, note that the @@ -20453,8 +20488,8 @@ which does not have this limitation. .IX Item "-m31" .PD When \fB\-m31\fR is specified, generate code compliant to the -GNU/Linux for S/390 \s-1ABI. \s0 When \fB\-m64\fR is specified, generate -code compliant to the GNU/Linux for zSeries \s-1ABI. \s0 This allows \s-1GCC\s0 in +GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in particular to generate 64\-bit instructions. For the \fBs390\fR targets, the default is \fB\-m31\fR, while the \fBs390x\fR targets default to \fB\-m64\fR. @@ -20467,11 +20502,11 @@ targets default to \fB\-m64\fR. When \fB\-mzarch\fR is specified, generate code using the instructions available on z/Architecture. When \fB\-mesa\fR is specified, generate code using the -instructions available on \s-1ESA/390. \s0 Note that \fB\-mesa\fR is +instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is not possible with \fB\-m64\fR. -When generating code compliant to the GNU/Linux for S/390 \s-1ABI,\s0 +When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0, the default is \fB\-mesa\fR. When generating code compliant -to the GNU/Linux for zSeries \s-1ABI,\s0 the default is \fB\-mzarch\fR. +to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR. .IP "\fB\-mhtm\fR" 4 .IX Item "-mhtm" .PD 0 @@ -20494,7 +20529,7 @@ available with the vector extension facility introduced with the \s-1IBM\s0 z13 machine generation. This option changes the \s-1ABI\s0 for some vector type values with regard to alignment and calling conventions. In case vector type values are -being used in an ABI-relevant context a \s-1GAS \s0\fB.gnu_attribute\fR +being used in an ABI-relevant context a \s-1GAS\s0 \fB.gnu_attribute\fR command will be added to mark the resulting binary with the \s-1ABI\s0 used. \&\fB\-mvx\fR is enabled by default when using \fB\-march=z13\fR. .IP "\fB\-mzvector\fR" 4 @@ -20553,9 +20588,9 @@ The default is the value used for \fB\-march\fR. .IP "\fB\-mno\-tpf\-trace\fR" 4 .IX Item "-mno-tpf-trace" .PD -Generate code that adds (does not add) in \s-1TPF OS\s0 specific branches to trace +Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace routines in the operating system. This option is off by default, even -when compiling for the \s-1TPF OS.\s0 +when compiling for the \s-1TPF\s0 \s-1OS\s0. .IP "\fB\-mfused\-madd\fR" 4 .IX Item "-mfused-madd" .PD 0 @@ -20648,16 +20683,16 @@ Specify the \s-1SCORE7D\s0 as the target architecture. These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: .IP "\fB\-m1\fR" 4 .IX Item "-m1" -Generate code for the \s-1SH1.\s0 +Generate code for the \s-1SH1\s0. .IP "\fB\-m2\fR" 4 .IX Item "-m2" -Generate code for the \s-1SH2.\s0 +Generate code for the \s-1SH2\s0. .IP "\fB\-m2e\fR" 4 .IX Item "-m2e" Generate code for the SH2e. .IP "\fB\-m2a\-nofpu\fR" 4 .IX Item "-m2a-nofpu" -Generate code for the SH2a without \s-1FPU,\s0 or for a SH2a\-FPU in such a way +Generate code for the SH2a without \s-1FPU\s0, or for a SH2a\-FPU in such a way that the floating-point unit is not used. .IP "\fB\-m2a\-single\-only\fR" 4 .IX Item "-m2a-single-only" @@ -20673,7 +20708,7 @@ Generate code for the SH2a\-FPU assuming the floating-point unit is in double-precision mode by default. .IP "\fB\-m3\fR" 4 .IX Item "-m3" -Generate code for the \s-1SH3.\s0 +Generate code for the \s-1SH3\s0. .IP "\fB\-m3e\fR" 4 .IX Item "-m3e" Generate code for the SH3e. @@ -20690,10 +20725,10 @@ Generate code for the \s-1SH4\s0 assuming the floating-point unit is in single-precision mode by default. .IP "\fB\-m4\fR" 4 .IX Item "-m4" -Generate code for the \s-1SH4.\s0 +Generate code for the \s-1SH4\s0. .IP "\fB\-m4\-100\fR" 4 .IX Item "-m4-100" -Generate code for \s-1SH4\-100.\s0 +Generate code for \s-1SH4\-100\s0. .IP "\fB\-m4\-100\-nofpu\fR" 4 .IX Item "-m4-100-nofpu" Generate code for \s-1SH4\-100\s0 in such a way that the @@ -20708,7 +20743,7 @@ Generate code for \s-1SH4\-100\s0 in such a way that no double-precision floating-point operations are used. .IP "\fB\-m4\-200\fR" 4 .IX Item "-m4-200" -Generate code for \s-1SH4\-200.\s0 +Generate code for \s-1SH4\-200\s0. .IP "\fB\-m4\-200\-nofpu\fR" 4 .IX Item "-m4-200-nofpu" Generate code for \s-1SH4\-200\s0 without in such a way that the @@ -20723,7 +20758,7 @@ Generate code for \s-1SH4\-200\s0 in such a way that no double-precision floating-point operations are used. .IP "\fB\-m4\-300\fR" 4 .IX Item "-m4-300" -Generate code for \s-1SH4\-300.\s0 +Generate code for \s-1SH4\-300\s0. .IP "\fB\-m4\-300\-nofpu\fR" 4 .IX Item "-m4-300-nofpu" Generate code for \s-1SH4\-300\s0 without in such a way that the @@ -20738,10 +20773,10 @@ Generate code for \s-1SH4\-300\s0 in such a way that no double-precision floating-point operations are used. .IP "\fB\-m4\-340\fR" 4 .IX Item "-m4-340" -Generate code for \s-1SH4\-340 \s0(no \s-1MMU,\s0 no \s-1FPU\s0). +Generate code for \s-1SH4\-340\s0 (no \s-1MMU\s0, no \s-1FPU\s0). .IP "\fB\-m4\-500\fR" 4 .IX Item "-m4-500" -Generate code for \s-1SH4\-500 \s0(no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the +Generate code for \s-1SH4\-500\s0 (no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the assembler. .IP "\fB\-m4a\-nofpu\fR" 4 .IX Item "-m4a-nofpu" @@ -20784,7 +20819,7 @@ Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use 16\-bit offsets. .IP "\fB\-mbitops\fR" 4 .IX Item "-mbitops" -Enable the use of bit manipulation instructions on \s-1SH2A.\s0 +Enable the use of bit manipulation instructions on \s-1SH2A\s0. .IP "\fB\-mfmovd\fR" 4 .IX Item "-mfmovd" Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for @@ -20831,7 +20866,7 @@ Dump instruction size and location in the assembly code. .IP "\fB\-mpadstruct\fR" 4 .IX Item "-mpadstruct" This option is deprecated. It pads structures to multiple of 4 bytes, -which is incompatible with the \s-1SH ABI.\s0 +which is incompatible with the \s-1SH\s0 \s-1ABI\s0. .IP "\fB\-matomic\-model=\fR\fImodel\fR" 4 .IX Item "-matomic-model=model" Sets the model of atomic operations and additional parameters as a comma @@ -20848,7 +20883,7 @@ Generate GNU/Linux compatible gUSA software atomic sequences for the atomic built-in functions. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for SH3* and SH4* single-core systems. This option is enabled by default when -the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A,\s0 +the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A\s0, this option also partially utilizes the hardware atomic instructions \&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless \&\fBstrict\fR is specified. @@ -20928,20 +20963,20 @@ Set the division strategy to be used for integer division operations. .IX Item "call-div1" Calls a library function that uses the single-step division instruction \&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an -unspecified result and does not trap. This is the default except for \s-1SH4, -SH2A\s0 and SHcompact. +unspecified result and does not trap. This is the default except for \s-1SH4\s0, +\&\s-1SH2A\s0 and SHcompact. .IP "\fBcall-fp\fR" 4 .IX Item "call-fp" Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is -the default for SHcompact with \s-1FPU. \s0 Specifying this for targets that do not +the default for SHcompact with \s-1FPU\s0. Specifying this for targets that do not have a double precision \s-1FPU\s0 defaults to \f(CW\*(C`call\-div1\*(C'\fR. .IP "\fBcall-table\fR" 4 .IX Item "call-table" Calls a library function that uses a lookup table for small divisors and the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division by zero calculates an unspecified result and does not trap. This is the default -for \s-1SH4. \s0 Specifying this for targets that do not have dynamic shift +for \s-1SH4\s0. Specifying this for targets that do not have dynamic shift instructions defaults to \f(CW\*(C`call\-div1\*(C'\fR. .RE .RS 4 @@ -20985,14 +21020,14 @@ is being compiled for. Assume (do not assume) that zero displacement conditional branch instructions \&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the compiler prefers zero displacement branch code sequences. This is -enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A. \s0 It can be explicitly +enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A\s0. It can be explicitly disabled by specifying \fB\-mno\-zdcbranch\fR. .IP "\fB\-mcbranch\-force\-delay\-slot\fR" 4 .IX Item "-mcbranch-force-delay-slot" Force the usage of delay slots for conditional branches, which stuffs the delay slot with a \f(CW\*(C`nop\*(C'\fR if a suitable instruction can't be found. By default this option is disabled. It can be enabled to work around hardware bugs as -found in the original \s-1SH7055.\s0 +found in the original \s-1SH7055\s0. .IP "\fB\-mfused\-madd\fR" 4 .IX Item "-mfused-madd" .PD 0 @@ -21014,7 +21049,7 @@ mapped to \fB\-ffp\-contract=off\fR. Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine and cosine approximations. The option \fB\-mfsca\fR must be used in combination with \fB\-funsafe\-math\-optimizations\fR. It is enabled by default -when generating code for \s-1SH4A. \s0 Using \fB\-mno\-fsca\fR disables sine and cosine +when generating code for \s-1SH4A\s0. Using \fB\-mno\-fsca\fR disables sine and cosine approximations even if \fB\-funsafe\-math\-optimizations\fR is in effect. .IP "\fB\-mfsrra\fR" 4 .IX Item "-mfsrra" @@ -21026,7 +21061,7 @@ Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction f reciprocal square root approximations. The option \fB\-mfsrra\fR must be used in combination with \fB\-funsafe\-math\-optimizations\fR and \&\fB\-ffinite\-math\-only\fR. It is enabled by default when generating code for -\&\s-1SH4A. \s0 Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations +\&\s-1SH4A\s0. Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations even if \fB\-funsafe\-math\-optimizations\fR and \fB\-ffinite\-math\-only\fR are in effect. .IP "\fB\-mpretend\-cmove\fR" 4 @@ -21035,7 +21070,7 @@ Prefer zero-displacement conditional branches for conditional move instruction patterns. This can result in faster code on the \s-1SH4\s0 processor. .IP "\fB\-mfdpic\fR" 4 .IX Item "-mfdpic" -Generate code using the \s-1FDPIC ABI.\s0 +Generate code using the \s-1FDPIC\s0 \s-1ABI\s0. .PP \fISolaris 2 Options\fR .IX Subsection "Solaris 2 Options" @@ -21083,7 +21118,7 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC SVR4 ABI\s0 reserves for applications. Like the +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the global register 1, each global register 2 through 4 is then treated as an allocable register that is clobbered by function calls. This is the default. .Sp @@ -21129,7 +21164,7 @@ cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and \&\fB\-msoft\-float\fR changes the calling convention in the output file; therefore, it is only useful if you compile \fIall\fR of a program with this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for this to work. .IP "\fB\-mhard\-quad\-float\fR" 4 .IX Item "-mhard-quad-float" @@ -21139,7 +21174,7 @@ instructions. .IX Item "-msoft-quad-float" Generate output containing library calls for quad-word (long double) floating-point instructions. The functions called are those specified -in the \s-1SPARC ABI. \s0 This is the default. +in the \s-1SPARC\s0 \s-1ABI\s0. This is the default. .Sp As of this writing, there are no \s-1SPARC\s0 implementations that have hardware support for the quad-word floating-point instructions. They all invoke @@ -21180,10 +21215,10 @@ With \fB\-mfaster\-structs\fR, the compiler assumes that structures should have 8\-byte alignment. This enables the use of pairs of \&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. -However, the use of this changed alignment directly violates the \s-1SPARC -ABI. \s0 Thus, it's intended only for use on targets where the developer +However, the use of this changed alignment directly violates the \s-1SPARC\s0 +\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with -the rules of the \s-1ABI.\s0 +the rules of the \s-1ABI\s0. .IP "\fB\-mstd\-struct\-return\fR" 4 .IX Item "-mstd-struct-return" .PD 0 @@ -21192,7 +21227,7 @@ the rules of the \s-1ABI.\s0 .PD With \fB\-mstd\-struct\-return\fR, the compiler generates checking code in functions returning structures or unions to detect size mismatches -between the two sides of function calls, as per the 32\-bit \s-1ABI.\s0 +between the two sides of function calls, as per the 32\-bit \s-1ABI\s0. .Sp The default is \fB\-mno\-std\-struct\-return\fR. This option has no effect in 64\-bit mode. @@ -21204,7 +21239,7 @@ for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBleon\fR, \fBleon3\fR, \fBleon3v7\fR, \fBsparclite\fR, \fBf930\fR, \&\fBf934\fR, \fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, -\&\fBniagara3\fR and \fBniagara4\fR. +\&\fBniagara3\fR, \fBniagara4\fR and \fBniagara7\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -21232,7 +21267,7 @@ f930, f934, sparclite86x tsc701 .IP "v9" 4 .IX Item "v9" -ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7 .RE .RS 4 .Sp @@ -21245,22 +21280,22 @@ SPARCStation 1, 2, \s-1IPX\s0 etc. With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 -but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=supersparc\fR, the compiler additionally +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series. .Sp With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step -and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7.\s0 +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the -Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU. \s0 With +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With \&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu -\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU.\s0 +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0. .Sp With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet -but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=tsc701\fR, the compiler additionally +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally optimizes it for the \s-1TEMIC\s0 SPARClet chip. .Sp With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 @@ -21275,7 +21310,9 @@ Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With \&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler -additionally optimizes it for Sun UltraSPARC T4 chips. +additionally optimizes it for Sun UltraSPARC T4 chips. With +\&\fB\-mcpu=niagara7\fR, the compiler additionally optimizes it for +Oracle \s-1SPARC\s0 M7 chips. .RE .IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 .IX Item "-mtune=cpu_type" @@ -21285,19 +21322,20 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. .Sp The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those -that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, -\&\fBleon3v7\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, -\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, -\&\fBniagara3\fR and \fBniagara4\fR. With native Solaris and GNU/Linux -toolchains, \fBnative\fR can also be used. +that select a particular \s-1CPU\s0 implementation. Those are +\&\fBcypress\fR, \fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, +\&\fBleon3\fR, \fBleon3v7\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, +\&\fBniagara4\fR and \fBniagara7\fR. With native Solaris and +GNU/Linux toolchains, \fBnative\fR can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 .IP "\fB\-mno\-v8plus\fR" 4 .IX Item "-mno-v8plus" .PD -With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI. \s0 The +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The difference from the V8 \s-1ABI\s0 is that the global and out registers are considered 64 bits wide. This is enabled by default on Solaris in 32\-bit mode for all \s-1SPARC\-V9\s0 processors. @@ -21331,6 +21369,17 @@ version 3.0 of the UltraSPARC Visual Instruction Set extensions. The default is \fB\-mvis3\fR when targeting a cpu that supports such instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR also sets \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mvis4\fR" 4 +.IX Item "-mvis4" +.PD 0 +.IP "\fB\-mno\-vis4\fR" 4 +.IX Item "-mno-vis4" +.PD +With \fB\-mvis4\fR, \s-1GCC\s0 generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis4\fR when targeting a cpu that supports such +instructions, such as niagara\-7 and later. Setting \fB\-mvis4\fR +also sets \fB\-mvis3\fR, \fB\-mvis2\fR and \fB\-mvis\fR. .IP "\fB\-mcbcond\fR" 4 .IX Item "-mcbcond" .PD 0 @@ -21752,9 +21801,9 @@ This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 architecture. .Sp -This option is enabled by default when the \s-1RH850 ABI\s0 is +This option is enabled by default when the \s-1RH850\s0 \s-1ABI\s0 is in use (see \fB\-mrh850\-abi\fR), and disabled by default when the -\&\s-1GCC ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated +\&\s-1GCC\s0 \s-1ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR is defined. .IP "\fB\-mrelax\fR" 4 .IX Item "-mrelax" @@ -21794,7 +21843,7 @@ selected because its use is still experimental. .IP "\fB\-mghs\fR" 4 .IX Item "-mghs" .PD -Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI. \s0 This is the +Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI\s0. This is the default. With this version of the \s-1ABI\s0 the following rules apply: .RS 4 .IP "*" 4 @@ -21819,7 +21868,7 @@ When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol .RE .IP "\fB\-mgcc\-abi\fR" 4 .IX Item "-mgcc-abi" -Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI. \s0 With this +Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI\s0. With this version of the \s-1ABI\s0 the following rules apply: .RS 4 .IP "*" 4 @@ -21914,7 +21963,7 @@ Generate code containing library calls for floating-point. \&\fB\-msoft\-float\fR changes the calling convention in the output file; therefore, it is only useful if you compile \fIall\fR of a program with this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for this to work. .IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 .IX Item "-mcpu=cpu_type" @@ -21942,8 +21991,8 @@ the access to general registers. This is the default. .IP "\fB\-muser\-mode\fR" 4 .IX Item "-muser-mode" Generate code for the user mode, where the access to some general registers -is forbidden: on the \s-1GR5,\s0 registers r24 to r31 cannot be accessed in this -mode; on the \s-1GR6,\s0 only registers r29 to r31 are affected. +is forbidden: on the \s-1GR5\s0, registers r24 to r31 cannot be accessed in this +mode; on the \s-1GR6\s0, only registers r29 to r31 are affected. .PP \fI\s-1VMS\s0 Options\fR .IX Subsection "VMS Options" @@ -22026,10 +22075,10 @@ produces code optimized for the local machine under the constraints of the selected instruction set. .IP "\fBi386\fR" 4 .IX Item "i386" -Original Intel i386 \s-1CPU.\s0 +Original Intel i386 \s-1CPU\s0. .IP "\fBi486\fR" 4 .IX Item "i486" -Intel i486 \s-1CPU. \s0(No scheduling is implemented for this chip.) +Intel i486 \s-1CPU\s0. (No scheduling is implemented for this chip.) .IP "\fBi586\fR" 4 .IX Item "i586" .PD 0 @@ -22039,13 +22088,13 @@ Intel i486 \s-1CPU. \s0(No scheduling is implemented for this chip.) Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. .IP "\fBlakemont\fR" 4 .IX Item "lakemont" -Intel Lakemont \s-1MCU,\s0 based on Intel Pentium \s-1CPU.\s0 +Intel Lakemont \s-1MCU\s0, based on Intel Pentium \s-1CPU\s0. .IP "\fBpentium-mmx\fR" 4 .IX Item "pentium-mmx" -Intel Pentium \s-1MMX CPU,\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +Intel Pentium \s-1MMX\s0 \s-1CPU\s0, based on Pentium core with \s-1MMX\s0 instruction set support. .IP "\fBpentiumpro\fR" 4 .IX Item "pentiumpro" -Intel Pentium Pro \s-1CPU.\s0 +Intel Pentium Pro \s-1CPU\s0. .IP "\fBi686\fR" 4 .IX Item "i686" When used with \fB\-march\fR, the Pentium Pro @@ -22053,7 +22102,7 @@ instruction set is used, so the code runs on all i686 family chips. When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR. .IP "\fBpentium2\fR" 4 .IX Item "pentium2" -Intel Pentium \s-1II CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 instruction set +Intel Pentium \s-1II\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 instruction set support. .IP "\fBpentium3\fR" 4 .IX Item "pentium3" @@ -22061,101 +22110,101 @@ support. .IP "\fBpentium3m\fR" 4 .IX Item "pentium3m" .PD -Intel Pentium \s-1III CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction +Intel Pentium \s-1III\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. .IP "\fBpentium-m\fR" 4 .IX Item "pentium-m" -Intel Pentium M; low-power version of Intel Pentium \s-1III CPU\s0 -with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. +Intel Pentium M; low-power version of Intel Pentium \s-1III\s0 \s-1CPU\s0 +with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. .IP "\fBpentium4\fR" 4 .IX Item "pentium4" .PD 0 .IP "\fBpentium4m\fR" 4 .IX Item "pentium4m" .PD -Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. +Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. .IP "\fBprescott\fR" 4 .IX Item "prescott" -Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction +Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. .IP "\fBnocona\fR" 4 .IX Item "nocona" -Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, -SSE2\s0 and \s-1SSE3\s0 instruction set support. +Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, +\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. .IP "\fBcore2\fR" 4 .IX Item "core2" -Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBnehalem\fR" 4 .IX Item "nehalem" -Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2\s0 and \s-1POPCNT\s0 instruction set support. +Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2 and \s-1POPCNT\s0 instruction set support. .IP "\fBwestmere\fR" 4 .IX Item "westmere" -Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AES\s0 and \s-1PCLMUL\s0 instruction set support. +Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. .IP "\fBsandybridge\fR" 4 .IX Item "sandybridge" -Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AES\s0 and \s-1PCLMUL\s0 instruction set support. +Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. .IP "\fBivybridge\fR" 4 .IX Item "ivybridge" -Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND\s0 and F16C +Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. .IP "\fBhaswell\fR" 4 .IX Item "haswell" -Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, -BMI, BMI2\s0 and F16C instruction set support. +Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, +\&\s-1BMI\s0, \s-1BMI2\s0 and F16C instruction set support. .IP "\fBbroadwell\fR" 4 .IX Item "broadwell" -Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, -BMI, BMI2, F16C, RDSEED, ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. +Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, +\&\s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1RDSEED\s0, \s-1ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. .IP "\fBskylake\fR" 4 .IX Item "skylake" -Intel Skylake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC\s0 and +Intel Skylake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, +\&\s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1RDSEED\s0, \s-1ADCX\s0, \s-1PREFETCHW\s0, \s-1CLFLUSHOPT\s0, \s-1XSAVEC\s0 and \&\s-1XSAVES\s0 instruction set support. .IP "\fBbonnell\fR" 4 .IX Item "bonnell" -Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBsilvermont\fR" 4 .IX Item "silvermont" -Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL\s0 and \s-1RDRND\s0 instruction set support. +Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AES\s0, \s-1PCLMUL\s0 and \s-1RDRND\s0 instruction set support. .IP "\fBknl\fR" 4 .IX Item "knl" -Intel Knight's Landing \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, -SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER\s0 and +Intel Knight's Landing \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, +\&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, +\&\s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1RDSEED\s0, \s-1ADCX\s0, \s-1PREFETCHW\s0, \s-1AVX512F\s0, \s-1AVX512PF\s0, \s-1AVX512ER\s0 and \&\s-1AVX512CD\s0 instruction set support. .IP "\fBskylake\-avx512\fR" 4 .IX Item "skylake-avx512" -Intel Skylake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, -SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, -AVX512VL, AVX512BW, AVX512DQ\s0 and \s-1AVX512CD\s0 instruction set support. +Intel Skylake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, +\&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1PKU\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, +\&\s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1RDSEED\s0, \s-1ADCX\s0, \s-1PREFETCHW\s0, \s-1CLFLUSHOPT\s0, \s-1XSAVEC\s0, \s-1XSAVES\s0, \s-1AVX512F\s0, +\&\s-1AVX512VL\s0, \s-1AVX512BW\s0, \s-1AVX512DQ\s0 and \s-1AVX512CD\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" -\&\s-1AMD K6 CPU\s0 with \s-1MMX\s0 instruction set support. +\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. .IP "\fBk6\-2\fR" 4 .IX Item "k6-2" .PD 0 .IP "\fBk6\-3\fR" 4 .IX Item "k6-3" .PD -Improved versions of \s-1AMD K6 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. .IP "\fBathlon\fR" 4 .IX Item "athlon" .PD 0 .IP "\fBathlon-tbird\fR" 4 .IX Item "athlon-tbird" .PD -\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions support. .IP "\fBathlon\-4\fR" 4 .IX Item "athlon-4" @@ -22165,7 +22214,7 @@ support. .IP "\fBathlon-mp\fR" 4 .IX Item "athlon-mp" .PD -Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 instruction set support. .IP "\fBk8\fR" 4 .IX Item "k8" @@ -22177,9 +22226,9 @@ instruction set support. .IP "\fBathlon-fx\fR" 4 .IX Item "athlon-fx" .PD -Processors based on the \s-1AMD K8\s0 core with x86\-64 instruction set support, +Processors based on the \s-1AMD\s0 K8 core with x86\-64 instruction set support, including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors. -(This supersets \s-1MMX, SSE, SSE2,\s0 3DNow!, enhanced 3DNow! and 64\-bit +(This supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit instruction set extensions.) .IP "\fBk8\-sse3\fR" 4 .IX Item "k8-sse3" @@ -22189,7 +22238,7 @@ instruction set extensions.) .IP "\fBathlon64\-sse3\fR" 4 .IX Item "athlon64-sse3" .PD -Improved versions of \s-1AMD K8\s0 cores with \s-1SSE3\s0 instruction set support. +Improved versions of \s-1AMD\s0 K8 cores with \s-1SSE3\s0 instruction set support. .IP "\fBamdfam10\fR" 4 .IX Item "amdfam10" .PD 0 @@ -22197,63 +22246,63 @@ Improved versions of \s-1AMD K8\s0 cores with \s-1SSE3\s0 instruction set suppor .IX Item "barcelona" .PD CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This -supersets \s-1MMX, SSE, SSE2, SSE3, SSE4A,\s0 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit instruction set extensions.) .IP "\fBbdver1\fR" 4 .IX Item "bdver1" CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This -supersets \s-1FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set extensions.) +supersets \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, +\&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions.) .IP "\fBbdver2\fR" 4 .IX Item "bdver2" \&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, -SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set +supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, +\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions.) .IP "\fBbdver3\fR" 4 .IX Item "bdver3" \&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, -PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and +supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1FSGSBASE\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, +\&\s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions. .IP "\fBbdver4\fR" 4 .IX Item "bdver4" \&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, -AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, -SSE4.2, ABM\s0 and 64\-bit instruction set extensions. +supersets \s-1BMI\s0, \s-1BMI2\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1FSGSBASE\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1XOP\s0, \s-1LWP\s0, +\&\s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, +\&\s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions. .IP "\fBznver1\fR" 4 .IX Item "znver1" \&\s-1AMD\s0 Family 17h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, -SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, -SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT,\s0 and 64\-bit +supersets \s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1FMA\s0, \s-1FSGSBASE\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1ADCX\s0, \s-1RDSEED\s0, \s-1MWAITX\s0, +\&\s-1SHA\s0, \s-1CLZERO\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0, \s-1XSAVEC\s0, \s-1XSAVES\s0, \s-1CLFLUSHOPT\s0, \s-1POPCNT\s0, and 64\-bit instruction set extensions. .IP "\fBbtver1\fR" 4 .IX Item "btver1" CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This -supersets \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM\s0 and 64\-bit +supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4A\s0, \s-1CX16\s0, \s-1ABM\s0 and 64\-bit instruction set extensions.) .IP "\fBbtver2\fR" 4 .IX Item "btver2" CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This -includes \s-1MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, -SSE4A, SSSE3, SSE3, SSE2, SSE, MMX\s0 and 64\-bit instruction set extensions. +includes \s-1MOVBE\s0, F16C, \s-1BMI\s0, \s-1AVX\s0, \s-1PCL_MUL\s0, \s-1AES\s0, \s-1SSE4\s0.2, \s-1SSE4\s0.1, \s-1CX16\s0, \s-1ABM\s0, +\&\s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE3\s0, \s-1SSE2\s0, \s-1SSE\s0, \s-1MMX\s0 and 64\-bit instruction set extensions. .IP "\fBwinchip\-c6\fR" 4 .IX Item "winchip-c6" -\&\s-1IDT\s0 WinChip C6 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 instruction +\&\s-1IDT\s0 WinChip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction set support. .IP "\fBwinchip2\fR" 4 .IX Item "winchip2" -\&\s-1IDT\s0 WinChip 2 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +\&\s-1IDT\s0 WinChip 2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! instruction set support. .IP "\fBc3\fR" 4 .IX Item "c3" -\&\s-1VIA C3 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is +\&\s-1VIA\s0 C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is implemented for this chip.) .IP "\fBc3\-2\fR" 4 .IX Item "c3-2" -\&\s-1VIA C3\-2 \s0(Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +\&\s-1VIA\s0 C3\-2 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is implemented for this chip.) .IP "\fBgeode\fR" 4 @@ -22287,7 +22336,7 @@ of your application will have, then you should use this option. .Sp As new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of -\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +\&\s-1GCC\s0, code generation controlled by this option will change to reflect the processors that are most common at the time that version of \s-1GCC\s0 is released. .Sp @@ -22299,7 +22348,7 @@ processors) for which the code is optimized. .IP "\fBintel\fR" 4 .IX Item "intel" Produce code optimized for the most current Intel processors, which are -Haswell and Silvermont for this version of \s-1GCC. \s0 If you know the \s-1CPU\s0 +Haswell and Silvermont for this version of \s-1GCC\s0. If you know the \s-1CPU\s0 on which your code will run, then you should use the corresponding \&\fB\-mtune\fR or \fB\-march\fR option instead of \fB\-mtune=intel\fR. But, if you want your application performs better on both Haswell and @@ -22307,7 +22356,7 @@ Silvermont, then you should use this option. .Sp As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of -\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +\&\s-1GCC\s0, code generation controlled by this option will change to reflect the most current Intel processors at the time that version of \s-1GCC\s0 is released. .Sp @@ -22392,7 +22441,7 @@ comparison is unordered. .IX Item "-msoft-float" Generate output containing library calls for floating point. .Sp -\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC.\s0 +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0. Normally the facilities of the machine's usual C compiler are used, but this can't be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for @@ -22407,8 +22456,8 @@ Do not use the \s-1FPU\s0 registers for return values of functions. .Sp The usual calling convention has functions return values of types \&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there -is no \s-1FPU. \s0 The idea is that the operating system should emulate -an \s-1FPU.\s0 +is no \s-1FPU\s0. The idea is that the operating system should emulate +an \s-1FPU\s0. .Sp The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned in ordinary \s-1CPU\s0 registers instead. @@ -22453,7 +22502,7 @@ so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. .Sp Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR to be aligned to an 8\- or 16\-byte boundary. In arrays or structures -conforming to the \s-1ABI,\s0 this is not possible. So specifying +conforming to the \s-1ABI\s0, this is not possible. So specifying \&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional 32\-bit zero. @@ -22464,7 +22513,7 @@ its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-by Notice that neither of these options enable any extra precision over the x87 standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. .Sp -\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this changes the size of structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, as well as modifying the function calling convention for functions taking @@ -22484,7 +22533,7 @@ type. This is the default for 32\-bit Bionic C library. A size of 128 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \&\f(CW\*(C`_\|_float128\*(C'\fR type. This is the default for 64\-bit Bionic C library. .Sp -\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this changes the size of structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, as well as modifying the function calling convention for functions taking @@ -22493,7 +22542,7 @@ with code compiled without that switch. .IP "\fB\-malign\-data=\fR\fItype\fR" 4 .IX Item "-malign-data=type" Control how \s-1GCC\s0 aligns variables. Supported values for \fItype\fR are -\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC 4.8\s0 +\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC\s0 4.8 and earlier, \fBabi\fR uses alignment value as specified by the psABI, and \fBcacheline\fR uses increased alignment value to match the cache line size. \fBcompat\fR is the default. @@ -22555,7 +22604,7 @@ Studio compilers until version 12. Later compiler versions (starting with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if you need to remain compatible with existing code produced by those -previous compiler versions or older versions of \s-1GCC.\s0 +previous compiler versions or older versions of \s-1GCC\s0. .IP "\fB\-mpc32\fR" 4 .IX Item "-mpc32" .PD 0 @@ -22616,7 +22665,7 @@ the one specified by \fB\-mpreferred\-stack\-boundary\fR is used. .Sp On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or -suffer significant run time performance penalties. On Pentium \s-1III,\s0 the +suffer significant run time performance penalties. On Pentium \s-1III\s0, the Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work properly if it is not 16\-byte aligned. .Sp @@ -22732,11 +22781,11 @@ preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. .IP "\fB\-mpku\fR" 4 .IX Item "-mpku" .PD -These switches enable the use of instructions in the \s-1MMX, SSE, -SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, -SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, -AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR, -XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU\s0 or 3DNow! +These switches enable the use of instructions in the \s-1MMX\s0, \s-1SSE\s0, +\&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AVX2\s0, \s-1AVX512F\s0, \s-1AVX512PF\s0, \s-1AVX512ER\s0, \s-1AVX512CD\s0, +\&\s-1SHA\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, F16C, \s-1FMA\s0, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, +\&\s-1AVX512VL\s0, \s-1AVX512BW\s0, \s-1AVX512DQ\s0, \s-1AVX512IFMA\s0 \s-1AVX512VBMI\s0, \s-1BMI\s0, \s-1BMI2\s0, \s-1FXSR\s0, +\&\s-1XSAVE\s0, \s-1XSAVEOPT\s0, \s-1LZCNT\s0, \s-1RTM\s0, \s-1MPX\s0, \s-1MWAITX\s0, \s-1PKU\s0 or 3DNow! extended instruction sets. Each has a corresponding \fB\-mno\-\fR option to disable use of these instructions. .Sp @@ -22813,7 +22862,7 @@ This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit Early Intel Pentium 4 CPUs with Intel 64 support, prior to the introduction of Pentium 4 G1 step in December 2005, lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions -which are supported by \s-1AMD64.\s0 +which are supported by \s-1AMD64\s0. These are load and store instructions, respectively, for certain status flags. In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions; @@ -22889,7 +22938,7 @@ external library. Supported values for \fItype\fR are \fBsvml\fR for the Intel short vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. To use this option, both \fB\-ftree\-vectorize\fR and -\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML \s0 +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0 ABI-compatible library must be specified at link time. .Sp \&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, @@ -22912,7 +22961,7 @@ when \fB\-mveclibabi=acml\fR is used. .IX Item "-mabi=name" Generate code for the specified calling convention. Permissible values are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and -\&\fBms\fR for the Microsoft \s-1ABI. \s0 The default is to use the Microsoft +\&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft \&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. You can control this behavior for specific functions by using the function attributes \f(CW\*(C`ms_abi\*(C'\fR and \f(CW\*(C`sysv_abi\*(C'\fR. @@ -22977,7 +23026,7 @@ can straddle a storage-unit boundary are determine by these rules: declared: the first member has the lowest memory address and the last member the highest. .IP "2. Every data object has an alignment requirement. The alignment requirement" 4 -.IX Item "2. Every data object has an alignment requirement. The alignment requirement" +.IX Item "2. Every data object has an alignment requirement. The alignment requirement" for all data except structures, unions, and arrays is either the size of the object or the current packing size (specified with either the \&\f(CW\*(C`aligned\*(C'\fR attribute or the \f(CW\*(C`pack\*(C'\fR pragma), @@ -23162,7 +23211,7 @@ or whether the thread base pointer must be added. Whether or not this is valid depends on the operating system, and whether it maps the segment to cover the entire \s-1TLS\s0 area. .Sp -For systems that use the \s-1GNU C\s0 Library, the default is on. +For systems that use the \s-1GNU\s0 C Library, the default is on. .IP "\fB\-msse2avx\fR" 4 .IX Item "-msse2avx" .PD 0 @@ -23213,7 +23262,7 @@ register when there are no variable arguments passed in vector registers. \&\fBWarning:\fR Since \s-1RAX\s0 register is used to avoid unnecessarily saving vector registers on stack when passing variable arguments, the impacts of this option are callees may waste some stack space, -misbehave or jump to a random location. \s-1GCC 4.4\s0 or newer don't have +misbehave or jump to a random location. \s-1GCC\s0 4.4 or newer don't have those issues, regardless the \s-1RAX\s0 register value. .IP "\fB\-m8bit\-idiv\fR" 4 .IX Item "-m8bit-idiv" @@ -23368,7 +23417,7 @@ appropriately. This option is available for MinGW targets. It specifies that the executable flag for the stack used by nested functions isn't set. This is necessary for binaries running in kernel mode of -Microsoft Windows, as there the User32 \s-1API,\s0 which is used to set executable +Microsoft Windows, as there the User32 \s-1API\s0, which is used to set executable privileges, isn't available. .IP "\fB\-fwritable\-relocated\-rdata\fR" 4 .IX Item "-fwritable-relocated-rdata" @@ -23453,7 +23502,7 @@ kernel code. These options control the treatment of literal pools. The default is \&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate section in the output file. This allows the literal pool to be placed -in a data \s-1RAM/ROM,\s0 and it also allows the linker to combine literal +in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal pools from separate object files to remove redundant literals and improve code size. With \fB\-mtext\-section\-literals\fR, the literals are interspersed in the text section in order to keep them as close as @@ -23526,7 +23575,7 @@ aspects of the compilation environment. Note that you can also specify places to search using options such as \&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These take precedence over places specified using environment variables, which -in turn take precedence over those specified by the configuration of \s-1GCC.\s0 +in turn take precedence over those specified by the configuration of \s-1GCC\s0. .IP "\fB\s-1LANG\s0\fR" 4 .IX Item "LANG" .PD 0 @@ -23543,7 +23592,7 @@ national conventions. \s-1GCC\s0 inspects the locale categories \&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do so. These locale categories can be set to any value supported by your installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United -Kingdom encoded in \s-1UTF\-8.\s0 +Kingdom encoded in \s-1UTF\-8\s0. .Sp The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character classification. \s-1GCC\s0 uses it to determine the character boundaries in @@ -23723,7 +23772,7 @@ and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, .IX Header "AUTHOR" See the Info entry for \fBgcc\fR, or <\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, -for contributors to \s-1GCC.\s0 +for contributors to \s-1GCC\s0. .SH "COPYRIGHT" .IX Header "COPYRIGHT" Copyright (c) 1988\-2016 Free Software Foundation, Inc. |