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Diffstat (limited to 'gcc/config/mips/mips-dspr2.md')
-rw-r--r--gcc/config/mips/mips-dspr2.md87
1 files changed, 48 insertions, 39 deletions
diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md
index 108f51be6c..3fe401f9f7 100644
--- a/gcc/config/mips/mips-dspr2.md
+++ b/gcc/config/mips/mips-dspr2.md
@@ -1,4 +1,4 @@
-;; Copyright (C) 2007, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2014 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
@@ -79,7 +79,7 @@
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
"ISA_HAS_DSPR2"
"absq_s.qb\t%0,%z1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalusat")
(set_attr "mode" "SI")])
(define_insn "mips_addu_ph"
@@ -91,7 +91,7 @@
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
"ISA_HAS_DSPR2"
"addu.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addu_s_ph"
@@ -104,7 +104,7 @@
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
"ISA_HAS_DSPR2"
"addu_s.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalusat")
(set_attr "mode" "SI")])
(define_insn "mips_adduh_qb"
@@ -114,7 +114,7 @@
UNSPEC_ADDUH_QB))]
"ISA_HAS_DSPR2"
"adduh.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_adduh_r_qb"
@@ -124,7 +124,7 @@
UNSPEC_ADDUH_R_QB))]
"ISA_HAS_DSPR2"
"adduh_r.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalusat")
(set_attr "mode" "SI")])
(define_insn "mips_append"
@@ -139,7 +139,7 @@
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
return "append\t%0,%z2,%3";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_balign"
@@ -154,7 +154,7 @@
operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
return "balign\t%0,%z2,%3";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_eq_qb"
@@ -169,7 +169,7 @@
UNSPEC_CMPGDU_EQ_QB))])]
"ISA_HAS_DSPR2"
"cmpgdu.eq.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_lt_qb"
@@ -184,7 +184,7 @@
UNSPEC_CMPGDU_LT_QB))])]
"ISA_HAS_DSPR2"
"cmpgdu.lt.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_cmpgdu_le_qb"
@@ -199,7 +199,7 @@
UNSPEC_CMPGDU_LE_QB))])]
"ISA_HAS_DSPR2"
"cmpgdu.le.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_dpa_w_ph"
@@ -210,7 +210,8 @@
UNSPEC_DPA_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpa.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dps_w_ph"
@@ -221,7 +222,8 @@
UNSPEC_DPS_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dps.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mulv2hi3"
@@ -301,7 +303,8 @@
UNSPEC_MULSA_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"mulsa.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_precr_qb_ph"
@@ -311,7 +314,7 @@
UNSPEC_PRECR_QB_PH))]
"ISA_HAS_DSPR2"
"precr.qb.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_precr_sra_ph_w"
@@ -326,7 +329,7 @@
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
return "precr_sra.ph.w\t%0,%z2,%3";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_precr_sra_r_ph_w"
@@ -341,7 +344,7 @@
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
return "precr_sra_r.ph.w\t%0,%z2,%3";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_prepend"
@@ -356,7 +359,7 @@
operands[3] = GEN_INT (INTVAL (operands[3]) & 31);
return "prepend\t%0,%z2,%3";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_shra_qb"
@@ -374,7 +377,7 @@
}
return "shrav.qb\t%0,%z1,%2";
}
- [(set_attr "type" "shift")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
@@ -393,7 +396,7 @@
}
return "shrav_r.qb\t%0,%z1,%2";
}
- [(set_attr "type" "shift")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_shrl_ph"
@@ -411,7 +414,7 @@
}
return "shrlv.ph\t%0,%z1,%2";
}
- [(set_attr "type" "shift")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subu_ph"
@@ -424,7 +427,7 @@
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
"ISA_HAS_DSPR2"
"subu.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subu_s_ph"
@@ -437,7 +440,7 @@
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
"ISA_HAS_DSPR2"
"subu_s.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalusat")
(set_attr "mode" "SI")])
(define_insn "mips_subuh_qb"
@@ -447,7 +450,7 @@
UNSPEC_SUBUH_QB))]
"ISA_HAS_DSPR2"
"subuh.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subuh_r_qb"
@@ -457,7 +460,7 @@
UNSPEC_SUBUH_R_QB))]
"ISA_HAS_DSPR2"
"subuh_r.qb\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addqh_ph"
@@ -467,7 +470,7 @@
UNSPEC_ADDQH_PH))]
"ISA_HAS_DSPR2"
"addqh.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addqh_r_ph"
@@ -477,7 +480,7 @@
UNSPEC_ADDQH_R_PH))]
"ISA_HAS_DSPR2"
"addqh_r.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addqh_w"
@@ -487,7 +490,7 @@
UNSPEC_ADDQH_W))]
"ISA_HAS_DSPR2"
"addqh.w\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_addqh_r_w"
@@ -497,7 +500,7 @@
UNSPEC_ADDQH_R_W))]
"ISA_HAS_DSPR2"
"addqh_r.w\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subqh_ph"
@@ -507,7 +510,7 @@
UNSPEC_SUBQH_PH))]
"ISA_HAS_DSPR2"
"subqh.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subqh_r_ph"
@@ -517,7 +520,7 @@
UNSPEC_SUBQH_R_PH))]
"ISA_HAS_DSPR2"
"subqh_r.ph\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subqh_w"
@@ -527,7 +530,7 @@
UNSPEC_SUBQH_W))]
"ISA_HAS_DSPR2"
"subqh.w\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_subqh_r_w"
@@ -537,7 +540,7 @@
UNSPEC_SUBQH_R_W))]
"ISA_HAS_DSPR2"
"subqh_r.w\t%0,%z1,%z2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "dspalu")
(set_attr "mode" "SI")])
(define_insn "mips_dpax_w_ph"
@@ -548,7 +551,8 @@
UNSPEC_DPAX_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpax.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dpsx_w_ph"
@@ -559,7 +563,8 @@
UNSPEC_DPSX_W_PH))]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsx.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dpaqx_s_w_ph"
@@ -574,7 +579,8 @@
UNSPEC_DPAQX_S_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_s.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dpaqx_sa_w_ph"
@@ -589,7 +595,8 @@
UNSPEC_DPAQX_SA_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_sa.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmacsat")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dpsqx_s_w_ph"
@@ -604,7 +611,8 @@
UNSPEC_DPSQX_S_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_s.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmac")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
(define_insn "mips_dpsqx_sa_w_ph"
@@ -619,5 +627,6 @@
UNSPEC_DPSQX_SA_W_PH))])]
"ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
- [(set_attr "type" "imadd")
+ [(set_attr "type" "dspmacsat")
+ (set_attr "accum_in" "1")
(set_attr "mode" "SI")])
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