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author | Lorry Tar Creator <lorry-tar-importer@baserock.org> | 2014-10-30 09:35:42 +0000 |
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committer | <> | 2015-01-09 11:51:27 +0000 |
commit | c27a97d04853380f1e80525391b3f0d156ed4c84 (patch) | |
tree | 68ffaade7c605bc80cffa18360799c98a810976f /gcc/testsuite/gcc.target/aarch64/vsub_f64.c | |
parent | 6af3fdec2262dd94954acc5e426ef71cbd4521d3 (diff) | |
download | gcc-tarball-c27a97d04853380f1e80525391b3f0d156ed4c84.tar.gz |
Imported from /home/lorry/working-area/delta_gcc-tarball/gcc-4.9.2.tar.bz2.gcc-4.9.2
Diffstat (limited to 'gcc/testsuite/gcc.target/aarch64/vsub_f64.c')
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vsub_f64.c | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/vsub_f64.c b/gcc/testsuite/gcc.target/aarch64/vsub_f64.c new file mode 100644 index 0000000000..abf4fc42d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vsub_f64.c @@ -0,0 +1,116 @@ +/* Test vsub works correctly. */ +/* { dg-do run } */ +/* { dg-options "--save-temps" } */ + +#include <arm_neon.h> + +#define FLT_EPSILON __FLT_EPSILON__ +#define DBL_EPSILON __DBL_EPSILON__ + +#define TESTA0 1 +#define TESTA1 0.2223 +#define TESTA2 0 +#define TESTA3 -0.76544 +/* 2^54, double has 53 significand bits + according to Double-precision floating-point format. */ +#define TESTA4 18014398509481984 +#define TESTA5 2.0 + +#define TESTB0 0.66667 +#define TESTB1 2 +#define TESTB2 0 +#define TESTB3 -2 +#define TESTB4 1.0 +#define TESTB5 (1.0 / TESTA4) + +#define ANSW0 0.33333 +#define ANSW1 -1.7777 +#define ANSW2 0 +#define ANSW3 1.23456 +#define ANSW4 TESTA4 +#define ANSW5 2.0 + +extern void abort (void); + +#define EPSILON __DBL_EPSILON__ +#define ISNAN(a) __builtin_isnan (a) +/* FP_equals is implemented like this to execute subtraction + exectly once during a single test run. */ +#define FP_equals(a, b, epsilon) \ +( \ + ((a) == (b)) \ + || (ISNAN (a) && ISNAN (b)) \ + || (((a > b) && (a < (b + epsilon))) \ + || ((b > a) && (b < (a + epsilon)))) \ +) + +int +test_vsub_f64 () +{ + float64x1_t a; + float64x1_t b; + float64x1_t c; + + a = TESTA0; + b = TESTB0; + c = ANSW0; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + a = TESTA1; + b = TESTB1; + c = ANSW1; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + a = TESTA2; + b = TESTB2; + c = ANSW2; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + a = TESTA3; + b = TESTB3; + c = ANSW3; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + a = TESTA4; + b = TESTB4; + c = ANSW4; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + a = TESTA5; + b = TESTB5; + c = ANSW5; + + a = vsub_f64 (a, b); + if (!FP_equals (a, c, EPSILON)) + return 1; + + return 0; +} + +/* { dg-final { scan-assembler-times "fsub\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 6 } } */ + +int +main (int argc, char **argv) +{ + if (test_vsub_f64 ()) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ |