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authorlaksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2>2015-03-14 10:04:17 +0000
committerlaksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2>2015-03-14 10:04:17 +0000
commitfe8c8eef1370534fa2c939a834612484367fa2a8 (patch)
tree547aab3931f7b994835c89f38fdfec6ed799929c /rtl/arm
parenta28ba1693ea10ac21967e17cd66f622bb27a10bb (diff)
downloadfpc-fe8c8eef1370534fa2c939a834612484367fa2a8.tar.gz
Undo recent VFP assembler changes to make bootstrapping from 3.0.1 possible.
git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@30183 3ad0048d-3df7-0310-abae-a5850022a9f2
Diffstat (limited to 'rtl/arm')
-rw-r--r--rtl/arm/arm.inc4
-rw-r--r--rtl/arm/mathu.inc4
-rw-r--r--rtl/arm/setjump.inc10
3 files changed, 9 insertions, 9 deletions
diff --git a/rtl/arm/arm.inc b/rtl/arm/arm.inc
index ff5af344d1..73f40211df 100644
--- a/rtl/arm/arm.inc
+++ b/rtl/arm/arm.inc
@@ -44,7 +44,7 @@ Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
{ Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
asm
- vmrs r0,fpscr
+ fmrx r0,fpscr
// set "round to nearest" mode
and r0,r0,#0xff3fffff
// mask "exception happened" and overflow flags
@@ -59,7 +59,7 @@ begin
// enable invalid operation, div-by-zero and overflow exceptions
orr r0,r0,#0x00000700
{$endif}
- vmsr fpscr,r0
+ fmxr fpscr,r0
end;
end;
{$endif}
diff --git a/rtl/arm/mathu.inc b/rtl/arm/mathu.inc
index fc8f30c622..f41e0630c6 100644
--- a/rtl/arm/mathu.inc
+++ b/rtl/arm/mathu.inc
@@ -161,13 +161,13 @@ const
function VFP_GetCW : dword; nostackframe; assembler;
asm
- vmrs r0,fpscr
+ fmrx r0,fpscr
end;
procedure VFP_SetCW(cw : dword); nostackframe; assembler;
asm
- vmsr fpscr,r0
+ fmxr fpscr,r0
end;
diff --git a/rtl/arm/setjump.inc b/rtl/arm/setjump.inc
index ebd55b817b..bcd66193d1 100644
--- a/rtl/arm/setjump.inc
+++ b/rtl/arm/setjump.inc
@@ -18,12 +18,12 @@ function fpc_setjmp(var S : jmp_buf) : longint;assembler;[Public, alias : 'FPC_S
asm
{$if defined(FPUVFPV2) or defined(FPUVFPV3) or defined(FPUVFPV3_D16)}
{$if defined(CPUARMV3) or defined(CPUARMV4) or defined(CPUARMV5)}
- vstmia r0!, {d8-d15}
+ fstmiax r0!, {d8-d15}
// according to the ARM Developer Suite Assembler Guide Version 1.2
// fstmiad increases the address register always by 2n+1 words, so fix this
sub r0,r0,#4
{$else}
- vstmia r0!, {d8-d15}
+ fstmiad r0!, {d8-d15}
{$endif}
{$endif}
@@ -70,7 +70,7 @@ procedure fpc_longjmp(var S : jmp_buf;value : longint);assembler;[Public, alias
it eq
moveq r0, #1
{$if defined(FPUVFPV2) or defined(FPUVFPV3) or defined(FPUVFPV3_D16)}
- vldmia ip!, {d8-d15}
+ fldmiad ip!, {d8-d15}
{$endif}
ldmia ip!, {v1-v6, sl, fp}
ldr sp, [ip]
@@ -103,12 +103,12 @@ procedure fpc_longjmp(var S : jmp_buf;value : longint);assembler;[Public, alias
moveq r0, #1
{$if defined(FPUVFPV2) or defined(FPUVFPV3) or defined(FPUVFPV3_D16)}
{$if defined(CPUARMV3) or defined(CPUARMV4) or defined(CPUARMV5)}
- vldmia ip!, {d8-d15}
+ fldmiax ip!, {d8-d15}
// according to the ARM Developer Suite Assembler Guide Version 1.2
// increases fldmiax the address register always by 2n+1 words, so fix this
sub ip,ip,#4
{$else}
- vldmia ip!, {d8-d15}
+ fldmiad ip!, {d8-d15}
{$endif}
{$endif}
ldmia ip,{v1-v6, sl, fp, sp, pc}