diff options
| author | Lauren Post <lauren.post@freescale.com> | 2016-03-22 22:08:25 +0100 |
|---|---|---|
| committer | Peter Seiderer <ps.report@gmx.net> | 2019-12-05 22:35:58 +0100 |
| commit | 8c1185d22cb5ea09dea063bd4a0a4f8b64487919 (patch) | |
| tree | f824b118ad863044fc10831005c468bb0e310f8b /xf86drm.h | |
| parent | 8de2696213d0f25a10a167b5fd6c312d6ce6a1af (diff) | |
| download | drm-8c1185d22cb5ea09dea063bd4a0a4f8b64487919.tar.gz | |
Add ARM support into xf86drm.h
This provides support for Xorg interface. Without this the vivante
samples will hang during close requiring a reboot
[Adapted from yocto project]
Upstream-Status: Pending
Signed-off-by: Lauren Post <lauren.post@freescale.com>
Signed-off-by: Evan Kotara <evan.kotara@freescale.com>
[Thomas: change CAS code to only be used on ARMv6/ARMv7, and not
ARMv4/ARMv5, which don't support ldrex/strex. If no CAS implementation
is provided libdrm falls back to a system call for locking/unlocking.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
---
Changes v1 -> v2:
- add comment explaining exclusion of ARMv4/ARMv5 and lower
Diffstat (limited to 'xf86drm.h')
| -rw-r--r-- | xf86drm.h | 23 |
1 files changed, 23 insertions, 0 deletions
@@ -481,6 +481,29 @@ do { register unsigned int __old __asm("o0"); \ : "cr0", "memory"); \ } while (0) +# elif defined (__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ + || defined (__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ + || defined (__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) \ + || defined (__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) + /* excluding ARMv4/ARMv5 and lower (lacking ldrex/strex support) */ + #undef DRM_DEV_MODE + #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) + + #define DRM_CAS(lock,old,new,__ret) \ + do { \ + __asm__ __volatile__ ( \ + "1: ldrex %0, [%1]\n" \ + " teq %0, %2\n" \ + " ite eq\n" \ + " strexeq %0, %3, [%1]\n" \ + " movne %0, #1\n" \ + : "=&r" (__ret) \ + : "r" (lock), "r" (old), "r" (new) \ + : "cc","memory"); \ + } while (0) + #endif /* architecture */ #endif /* __GNUC__ >= 2 */ |