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| author | Marek Olšák <maraeo@gmail.com> | 2012-10-16 02:08:02 +0200 |
|---|---|---|
| committer | Marek Olšák <maraeo@gmail.com> | 2012-10-26 20:00:59 +0200 |
| commit | e32fff8e9ea8d522679eaab21a9555cab134fb36 (patch) | |
| tree | 7d64d94e069c1283cc74d859218e9c9c583effbf /radeon | |
| parent | bc494b310d76f701798aee0f2b0b472d608cbfaf (diff) | |
| download | drm-e32fff8e9ea8d522679eaab21a9555cab134fb36.tar.gz | |
radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'radeon')
| -rw-r--r-- | radeon/radeon_surface.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 66c24449..eb587d24 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, } else { /* tile split must be >= 256 for colorbuffer surfaces */ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + if (surf->tile_split > 4096) + surf->tile_split = 4096; } } else { /* set tile split to row size */ |