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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2015-09-18 11:26:39 -0700 |
|---|---|---|
| committer | Sarah Sharp <sarah.a.sharp@linux.intel.com> | 2016-01-06 11:56:42 -0800 |
| commit | 242f77ce03f4db371d8de3de1bef8622c0fe7488 (patch) | |
| tree | a8fd880fa01602428ea8e33ce5e6ab5d12f07dc5 /intel | |
| parent | b38a4b2326c1be5702f5cb73a53c0ed74c12d510 (diff) | |
| download | drm-242f77ce03f4db371d8de3de1bef8622c0fe7488.tar.gz | |
intel/kbl: Add Kabylake PCI ids
Also, following kernel definition Kabylake is skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Diffstat (limited to 'intel')
| -rw-r--r-- | intel/intel_chipset.h | 57 |
1 files changed, 56 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 26fbee4d..35148e52 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -187,6 +187,29 @@ #define PCI_CHIP_SKYLAKE_H_GT4 0x193B #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D +#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 +#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 +#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 +#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 +#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 +#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E +#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E +#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 +#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 +#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 +#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B +#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B +#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B +#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A +#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A +#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A +#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A +#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D + #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 @@ -375,6 +398,37 @@ (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) +#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT1 || \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) + +#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) + +#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT3 || \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) + +#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT4 || \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT4 || \ + (devid) == PCI_CHIP_KABYLAKE_WKS_GT4) + +#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ + IS_KBL_GT2(devid) || \ + IS_KBL_GT3(devid) || \ + IS_KBL_GT4(devid)) + #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ IS_SKL_GT3(devid) || \ @@ -385,7 +439,8 @@ (devid) == PCI_CHIP_BROXTON_2) #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ - IS_BROXTON(devid)) + IS_BROXTON(devid) || \ + IS_KABYLAKE(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ |