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* Fix ChaCha AVX2 implementation (GH #1069)Jeffrey Walton2021-09-201-3/+0
| | | | Many thanks to Jack Lloyd
* Disable ChaCha20 AVX2 implementation (GH #1069)Jeffrey Walton2021-09-171-0/+3
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* Add EnumToInt conversion macro for enum-enum conversion warnings (GH #1016)Jeffrey Walton2021-03-091-4/+4
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* Clear C++20 enum-enum conversion warnings (GH #1016)Jeffrey Walton2021-03-091-4/+4
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* Use Altivec as minimum ISA of ChaCha Simon64 and Speck64Jeffrey Walton2020-04-051-25/+3
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* Add XLC 12 loads and stores for AIX (PR #907)Jeffrey Walton2019-10-261-8/+8
| | | Add XLC 12 loads and stores for AIX
* Use PowerPC unaligned loads and stores with Power8 (GH #825, PR #826)Jeffrey Walton2019-04-271-8/+8
| | | Use PowerPC unaligned loads and stores with Power8. Formerly we were using Power7 as the floor because the IBM POWER Architecture manuals said unaligned loads and stores were available. However, some compilers generate bad code for unaligned loads and stores using `-march=power7`, so bump to a known good.
* Clear unused warnings with MSVCJeffrey Walton2019-02-221-0/+2
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* Latch previous ROUNDS in Salsa and ChaCha ciphers (GH #800, PR #804)Jeffrey Walton2019-02-121-14/+21
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* Back-off ChaCha assert at the moment (GH #790)Jeffrey Walton2019-02-111-1/+1
| | | | We don't know what we are supposed to do at the moment. We need the CFRG or IETF to say what is supposed to happen.
* Add IETF XChaCha20Poly1305 (GH #727, PR #795)Jeffrey Walton2019-02-061-1/+1
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* Add IETF XChaCha (GH #727, PR #794)Jeffrey Walton2019-02-061-12/+129
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* Update commentsJeffrey Walton2019-01-301-1/+2
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* Use ROUNDS constant for ChaChaTLSJeffrey Walton2019-01-251-9/+4
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* Switch to RFC 8439 for ChaChaTLSJeffrey Walton2019-01-251-5/+11
| | | | Unfortunately the block counter wrap problem is still present.
* Update commentsJeffrey Walton2019-01-251-5/+9
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* Update commentsJeffrey Walton2019-01-251-4/+5
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* Update commentsJeffrey Walton2019-01-251-2/+5
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* Update commentsJeffrey Walton2019-01-251-11/+8
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* Refactor ChaCha and ChaChaTLS use a common coreJeffrey Walton2019-01-251-112/+75
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* Refactor ChaCha and ChaChaTLS use a common coreJeffrey Walton2019-01-251-292/+186
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* Enable SIMD implementation for ChaChaTLS (GH #265)Jeffrey Walton2019-01-251-64/+48
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* Use word64 for ChaChaTLS InitialBlock (GH #265)Jeffrey Walton2019-01-251-3/+3
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* Remove rounds from ChaChaTLSJeffrey Walton2019-01-241-5/+5
| | | | Rounds are alwys 20 in the IETF implementation.
* Fix AlgorithmProvider for ChaChaTLSJeffrey Walton2019-01-241-4/+12
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* Add ChaChaTLS implementation (GH #265)Jeffrey Walton2019-01-241-2/+281
| | | | We tweaked ChaCha to arrive at the IETF's implementation specified by RFC 7539. We are not sure how to handle block counter wrap. At the moment the caller is responsible for managing it. We were not able to find a reference implementation so we disable SIMD implementations like SSE, AVX, NEON and Power4. We need the wide block tests for corner cases to ensure our implementation is correct.
* Fix ChaCha compiler crash for GCC 3.3Jeffrey Walton2018-12-291-5/+10
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* Add BLAKE2s and ChaCha CORE SIMD function (GH #656)Jeffrey Walton2018-11-181-6/+4
| | | | | The CORE function provides the implementation for ChaCha_OperateKeystream_ALTIVEC, ChaCha_OperateKeystream_POWER7, BLAKE2_Compress32_ALTIVEC and BLAKE2_Compress32_POWER7. Depending on the options used to compile the source files, either POWER7 or ALTIVEC will be used. This is needed to support the "new toolchain, ancient hardware" use case.
* Switch between POWER7 and POWER4 (GH #656)Jeffrey Walton2018-11-181-3/+24
| | | | | This is kind of tricky. We automatically drop from POWER7 to POWER4 if 7 is notavailable. However, if POWER7 is available the runtime test checks for HasAltivec(), and not HasPower7(), if the drop does not occur. All of this goodness is happening on an old Apple G4 laptop with Gentoo. It is a "new toolchain on old hardware".
* Make Altivec vector wraps friendly to downgradesJeffrey Walton2018-11-151-7/+12
| | | | The way the existing ppc_simd.h is written makes it hard to to switch between the old Altivec loads and stores and the new POWER7 loads and stores. This checkin rewrites the wrappers to use _ALTIVEC_, _ARCH_PWR7 and _ARCH_PWR8. The wrappers in this file now honor -maltivec, -mcpu-power7 and -mcpu=power8. It allows users to compile a source file, like chacha_simd.cpp, with a lower ISA and things just work for them.
* Drop ChaCha requirements to POWER7Jeffrey Walton2018-11-141-12/+12
| | | | This costs about 0.6 cpb (700 MB/s on GCC112), but it makes the faster algorithm available to more machines. In the future we may want to provide both POWER7 and POWER8
* Add ChaCha AVX2 implementation (GH #735)Jeffrey Walton2018-11-081-7/+49
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* Skip unneeded wrap check in SIMD book keeping (GH #732)Jeffrey Walton2018-11-041-6/+9
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* Work-around potential counter increment problem in ChaCha20 (GH #732)Jeffrey Walton2018-11-041-90/+103
| | | | | | | | This is only a work-around for the moment. The issue only affects SIMD code. The problem is, the algorithm we use performs a 32-bit add as an intermediate result, but we really need a 64-bit add. We are running 4 transforms in parallel, and we can't add and carry the way we need to. The workaround is, whenever we could cross the 32-bit counter boundary we use the C version of the transform. We determine the cross-over point by 'bool safe = 0xffffffff - state.low > 4'. When not safe we skip the SIMD version of the algorithm and use the C version. Once we are safe again we use the SIMD version again. The work-around costs us about 0.1 to 0.2 cpb. At 1.10 or 1.15 cpb that equates to about 200 MB/s on a Skylake. We'd like to get it back eventually.
* Add ChaCha Power8 implementationJeffrey Walton2018-10-271-0/+32
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* Remove xorInput parameter from ChaCha SIMD functionsJeffrey Walton2018-10-261-8/+8
| | | | We can use the input pointer directly after checking KeystreamOperation
* Add ChaCha AlgorithmName overrideJeffrey Walton2018-10-261-0/+5
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* Whitespace check-inJeffrey Walton2018-10-251-111/+111
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* Add ChaCha NEON implementationJeffrey Walton2018-10-251-1/+33
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* Add SSSE3 rotates when availableJeffrey Walton2018-10-241-10/+1
| | | | This change obtains the remaining 0.1 to 0.15 cpb. It should be engaged with -march=native
* Move input xor to ChaCha_OperateKeystream_SSE2Jeffrey Walton2018-10-241-9/+15
| | | | This picks up about 0.2 cpb in ChaCha::OperateKeystream. It may not sound like much but it puts SSE2 intrinsics version on par with the ASM version of Salsa20. Salsa20 leads ChaCha by 0.1 to 0.15 cpb, which equates to about 50 MB/s.
* Fix ChaCha compile on ARM and MIPSJeffrey Walton2018-10-241-5/+9
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* Remove unneeded params from ChaCha_OperateKeystream_SSE2Jeffrey Walton2018-10-231-3/+2
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* Remove old comments from chacha.cppJeffrey Walton2018-10-231-9/+2
| | | | This should have been done at 916c4484a270
* Add ChaCha SSE2 implementationJeffrey Walton2018-10-231-11/+48
| | | | | | | | Thanks to Jack Lloyd and Botan for allowing us to use the implementation. The numbers for SSE2 are very good. When compared with Salsa20 ASM the results are: * Salsa20 2.55 cpb; ChaCha/20 2.90 cpb * Salsa20/12 1.61 cpb; ChaCha/12 1.90 cpb * Salsa20/8 1.34 cpb; ChaCha/8 1.5 cpb
* Fix ChaCha debug buildsJeffrey Walton2018-08-181-1/+1
| | | | This broke at https://github.com/weidai11/cryptopp/commit/e2be0cdecce7
* Make ChaCha an Salsa use the same design patternJeffrey Walton2018-08-171-21/+13
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* Backout ChaCha changes to Crypto++ 7.0Jeffrey Walton2018-07-251-15/+21
| | | | These changes made it in by accident at Commit b74a6f444568. We were going to try to let them ride but they broke versioning. They may be added later but we should avoid the change at this time.
* Add algorithm provider member function to Algorithm classJeffrey Walton2018-07-061-21/+14
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* Switch to rotlConstant and rotrConstantJeffrey Walton2017-11-251-4/+4
| | | | This will help Clang and its need for a constexpr
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