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authorJeffrey Walton <noloader@gmail.com>2020-04-09 06:25:37 -0400
committerJeffrey Walton <noloader@gmail.com>2020-04-09 06:25:37 -0400
commitdeec6d0d1d894a94054f470e7a7a7bae481b52f7 (patch)
tree5d039b3221ceb5744ecc199284e20445563d4e8b /ppc_simd.h
parent318cc3ac4bce1bdbf284adbcb1a4666f235ae832 (diff)
downloadcryptopp-git-deec6d0d1d894a94054f470e7a7a7bae481b52f7.tar.gz
Fix 32-bit Altive rotate left and right
Diffstat (limited to 'ppc_simd.h')
-rw-r--r--ppc_simd.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/ppc_simd.h b/ppc_simd.h
index d6dff66d..3897bd6a 100644
--- a/ppc_simd.h
+++ b/ppc_simd.h
@@ -2091,8 +2091,13 @@ inline uint32x4_p VecRotateLeft64(const uint32x4_p val)
template<>
inline uint32x4_p VecRotateLeft64<8>(const uint32x4_p val)
{
+#if (CRYPTOPP_BIG_ENDIAN)
const uint8x16_p m = { 1,2,3,4, 5,6,7,0, 9,10,11,12, 13,14,15,8 };
return VecPermute(val, m);
+#else
+ const uint8x16_p m = { 7,0,1,2, 3,4,5,6, 15,8,9,10, 11,12,13,14 };
+ return VecPermute(val, m);
+#endif
}
// 64-bit elements available at POWER7 with VSX, but vec_rl and vec_sl require POWER8
@@ -2175,8 +2180,13 @@ inline uint32x4_p VecRotateRight64(const uint32x4_p val)
template<>
inline uint32x4_p VecRotateRight64<8>(const uint32x4_p val)
{
+#if (CRYPTOPP_BIG_ENDIAN)
const uint8x16_p m = { 7,0,1,2, 3,4,5,6, 15,8,9,10, 11,12,13,14 };
return VecPermute(val, m);
+#else
+ const uint8x16_p m = { 1,2,3,4, 5,6,7,0, 9,10,11,12, 13,14,15,8 };
+ return VecPermute(val, m);
+#endif
}
#if defined(__VSX__) || defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)