Introduce arm support in crossystem.

This CL builds upon earlier firmware and kernel changes (see CLs
related to the same bug, chromium-os:12522).

ARM firmware now simulates both Nvram storage and VDAT buffer, the
structures the x86 version uses extensively to communicate back and
forth between firmware/kernel/userland.

So, to make crossystem work on arm, all what's needed is to provide
architecture specific interface to Nvram and VDAT simulation, and
architecture specific processing for variables which are accessed on
ARM platforms in a different way.

The few discrepancies and platform specifics which had to be addressed
for ARM specifically are as follows:

- the Nvram contents are cached in the shared memory and available for
  reading as part of /sys/kernel/debug/chromeos_arm. When writing
  Nvram, the same file needs to be written, but only the 16 bytes
  (representing the Nvram contents) are aacepted.

- the VDAT buffer also comes from the shared memory (as part of the
  same sysfs file)

- when crossystem starts, it needs to read in this shared memory
  contents, a` weak' function VbArchInit() is being added such that it
  is provided on ARM platforms only, on x86 an empty stub is called.

- current developer/recovery request/ro firmware switch states are
  retrieved through GPIO drivers. The GPIO numbers are defined in the
  file, the GPIO driver is supposed to be configured before
  crsossystem can operate.

- the BINF values are supplied through an array within shared memory,
  it would be easy to refactor both x86 and ARM use the same code to
  process BINF values, but with this submission the code is duplicated
  to minimize x86 impact.

- the following crossystem variables do not have ARM equivalents,
  thier values are reported as '(error)':

   recoverysw_ec_boot
   savedmem_base
   savedmem_size

BUG=chromium-os:12522
TEST=manual:

. bring up a kaen system
. execute the following script to enable the appropriate GPIOSs:

 for gpio in 56 59 168; do echo $gpio > /sys/class/gpio/export; done

. run `crossystem' and observe reasonable output values

. to verify that it reads GPIOs properly, try

  echo $(./crossystem recoverysw_cur)

  with the miniservo 'GOOG_REC' button pressed and released, observe
  different readings (note that the state of the button is reversed,
  the released button is reported as '1')

. to verify the write capabilities, note that the nvram contents can
  be accessed using the following shell commands

     echo 3 > /proc/sys/vm/drop_caches
     2>/dev/null dd if=/dev/mmcblk0 of=/tmp/blk bs=16 count=1 && \
       od -t x1 /tmp/blk | head -1

 (the first command cause the device cache dropped, and the second
 command accesses the device contents.

   vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
   localhost var # echo $(./crossystem fwb_tries)
   10
   localhost var # echo 3 > /proc/sys/vm/drop_caches
   localhost var # 2>/dev/null dd if=/dev/mmcblk0 of=/tmp/blk bs=16 count=1 && od -t x1 /tmp/blk | head -1
   0000000 60 0a 00 be 00 00 00 00 00 00 00 02 00 00 00 a2
   localhost var # ./crossystem fwb_tries=9
   localhost var # echo $(./crossystem fwb_tries)
   9
   localhost var # echo 3 > /proc/sys/vm/drop_caches
   localhost var # 2>/dev/null dd if=/dev/mmcblk0 of=/tmp/blk bs=16 count=1 && od -t x1 /tmp/blk | head -1
   0000000 60 09 00 be 00 00 00 00 00 00 00 02 00 00 00 8a
   localhost var #
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Change-Id: Ie4c6ff44441d98a42b1057953208fdb90c08f46d
Reviewed-on: http://gerrit.chromium.org/gerrit/113
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/host/include/crossystem_arch.h b/host/include/crossystem_arch.h
index ee8425b4..6d33c65b 100644
--- a/host/include/crossystem_arch.h
+++ b/host/include/crossystem_arch.h
@@ -11,6 +11,14 @@
 #include "vboot_nvstorage.h"
 #include "vboot_struct.h"
 
+/* Firmware types from BINF.3. Placed in the common file because both x86 and
+ * arm use this. The constants are defined in "Chrome OS Main Processor
+ * Firmware Spec"
+ */
+#define BINF3_RECOVERY   0
+#define BINF3_NORMAL     1
+#define BINF3_DEVELOPER  2
+
 
 /* INTERNAL APIS FOR CROSSYSTEM AVAILABLE TO ARCH-SPECIFIC FUNCTIONS */