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authorSubrata Banik <subrata.banik@intel.com>2020-04-27 09:56:47 +0530
committerCommit Bot <commit-bot@chromium.org>2020-04-28 08:04:54 +0000
commitb2dca286baa74b71da70fb59e8a3f94df57269fe (patch)
treeedc42b8b34124ab6ffe6425c3a9b33bb478daf73
parent5859c78660a9c8faf26b21210116c9d569c35b24 (diff)
downloadvboot-b2dca286baa74b71da70fb59e8a3f94df57269fe.tar.gz
crossystem: add support for ADL gpiochip
On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly. TEST=run 'crossystem wpsw_cur' and see '0' rather than an error on ADLRVP platform. Change-Id: I7c8ead83717b7be35ce68026768f6f0f5b1efa1c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_reference/+/2167671 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Subrata Banik <subrata.banik@intel.corp-partner.google.com>
-rw-r--r--host/arch/x86/lib/crossystem_arch.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/host/arch/x86/lib/crossystem_arch.c b/host/arch/x86/lib/crossystem_arch.c
index a9fa6233..00c844b4 100644
--- a/host/arch/x86/lib/crossystem_arch.c
+++ b/host/arch/x86/lib/crossystem_arch.c
@@ -725,6 +725,9 @@ static const struct GpioChipset chipsets_supported[] = {
{ "INT34BB:00", FindGpioChipOffsetByLabel },
{ "INT34C8:00", FindGpioChipOffsetByLabel },
{ "INT34C5:00", FindGpioChipOffsetByLabel },
+ /* INTC105x are for Alderlake */
+ { "INTC1055:00", FindGpioChipOffsetByLabel },
+ { "INTC1056:00", FindGpioChipOffsetByLabel },
/* INT3453 are for GLK */
{ "INT3453:00", FindGpioChipOffsetByLabel },
{ "INT3453:01", FindGpioChipOffsetByLabel },