diff options
Diffstat (limited to 't20')
| -rw-r--r-- | t20/nvbctlib_t20.c | 656 | ||||
| -rw-r--r-- | t20/nvboot_bct_t20.h | 310 | ||||
| -rw-r--r-- | t20/nvboot_sdram_param_t20.h | 366 | ||||
| -rw-r--r-- | t20/parse_t20.c | 254 |
4 files changed, 1586 insertions, 0 deletions
diff --git a/t20/nvbctlib_t20.c b/t20/nvbctlib_t20.c new file mode 100644 index 0000000..ec2fd3d --- /dev/null +++ b/t20/nvbctlib_t20.c @@ -0,0 +1,656 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t20.h" +#include "string.h" + +/* nvbctlib_t20.c: The implementation of the nvbctlib API for t20. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) return -ENODATA; \ + *data = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *data = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *data = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = data; \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +int +t20_set_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(nand, clock_divider); + CASE_SET_DEV_PARAM(nand, nand_timing); + CASE_SET_DEV_PARAM(nand, nand_timing2); + CASE_SET_DEV_PARAM(nand, block_size_log2); + CASE_SET_DEV_PARAM(nand, page_size_log2); + + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_get_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(nand, clock_divider); + CASE_GET_DEV_PARAM(nand, nand_timing); + CASE_GET_DEV_PARAM(nand, nand_timing2); + CASE_GET_DEV_PARAM(nand, block_size_log2); + CASE_GET_DEV_PARAM(nand, page_size_log2); + + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_set_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_post_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(emc_clock_divider); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_quse_extra); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg1); + CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly); + CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); + CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly); + CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly_msb); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(emc_adr_cfg1); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(mc_lowlatency_config); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_ref_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev0); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev1); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_emr2); + CASE_SET_SDRAM_PARAM(emc_emrs_emr3); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim0); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim1); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim2); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t20_get_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_post_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(emc_clock_divider); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg1); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(emc_adr_cfg1); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(mc_lowlatency_config); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_emr2); + CASE_GET_SDRAM_PARAM(emc_emrs_emr3); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + DEFAULT(); + } + return 0; +} + +int +t20_getbl_param(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_setbl_param(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_bct_get_value(parse_token id, u_int32_t *data, u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_reserved_offset: + *data = (u_int8_t *)&(samplebct.reserved) + - (u_int8_t *)&samplebct; + break; + + case token_bct_size: + *data = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *data = (u_int8_t *)&(samplebct.random_aes_blk) + - (u_int8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *data = sizeof(nvboot_config_table) - sizeof(nvboot_hash); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t20_bct_set_value(parse_token id, u_int32_t data, u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_bct_set_data(parse_token id, + u_int8_t *data, + u_int32_t length, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + CASE_SET_DATA(crypto_hash, sizeof(nvboot_hash)); + + default: + return -ENODATA; + } + + return 0; +} + +void t20_init_bad_block_table(build_image_context *context) +{ + u_int32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +void t20_get_cbootimage_interf(bct_parse_interface *cbootimage_bct_interf) +{ + cbootimage_bct_interf->init_bad_block_table = t20_init_bad_block_table; + cbootimage_bct_interf->set_dev_param = t20_set_dev_param; + cbootimage_bct_interf->get_dev_param = t20_get_dev_param; + cbootimage_bct_interf->set_sdram_param = t20_set_sdram_param; + cbootimage_bct_interf->get_sdram_param = t20_get_sdram_param; + cbootimage_bct_interf->setbl_param = t20_setbl_param; + cbootimage_bct_interf->getbl_param = t20_getbl_param; + cbootimage_bct_interf->set_value = t20_bct_set_value; + cbootimage_bct_interf->get_value = t20_bct_get_value; + cbootimage_bct_interf->set_data = t20_bct_set_data; +} diff --git a/t20/nvboot_bct_t20.h b/t20/nvboot_bct_t20.h new file mode 100644 index 0000000..5102629 --- /dev/null +++ b/t20/nvboot_bct_t20.h @@ -0,0 +1,310 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef INCLUDED_NVBOOT_BCT_H +#define INCLUDED_NVBOOT_BCT_H + +#include <sys/types.h> +#include "nvboot_sdram_param_t20.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 298 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 3 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* Defines the params that can be configured for NAND devices. */ +typedef struct nvboot_nand_params_rec { + /** + * Specifies the clock divider for the PLL_P 432MHz source. + * If it is set to 18, then clock source to Nand controller is + * 432 / 18 = 24MHz. + */ + u_int8_t clock_divider; + + /* Specifies the value to be programmed to Nand Timing Register 1 */ + u_int32_t nand_timing; + + /* Specifies the value to be programmed to Nand Timing Register 2 */ + u_int32_t nand_timing2; + + /* Specifies the block size in log2 bytes */ + u_int8_t block_size_log2; + + /* Specifies the page size in log2 bytes */ + u_int8_t page_size_log2; +} nvboot_nand_params; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC + * controller runs at 432/18 = 24MHz. + */ + u_int8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + u_int8_t max_power_class_supported; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be PLLC. */ + nvboot_spi_clock_source_pllc_out0, + + /* Specifies SPI clock source to be PLLM. */ + nvboot_spi_clock_source_pllm_out0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + nvboot_spi_clock_source clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + u_int8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + u_int8_t read_command_type_fast; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + /* Specifies optimized parameters for NAND */ + nvboot_nand_params nand_params; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies NAND. */ + nvboot_dev_type_nand, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + u_int32_t version; + u_int32_t start_blk; + u_int32_t start_page; + u_int32_t length; + u_int32_t load_addr; + u_int32_t entry_point; + u_int32_t attribute; + nvboot_hash crypto_hash; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + u_int32_t entries_used; + u_int8_t virtual_blk_size_log2; + u_int8_t block_size_log2; + u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_hash crypto_hash; + nvboot_hash random_aes_blk; + u_int32_t boot_data_version; + u_int32_t block_size_log2; + u_int32_t page_size_log2; + u_int32_t partition_size; + u_int32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + u_int32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + nvboot_badblock_table badblock_table; + u_int32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + u_int8_t enable_fail_back; + u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_H */ diff --git a/t20/nvboot_sdram_param_t20.h b/t20/nvboot_sdram_param_t20.h new file mode 100644 index 0000000..fdf1631 --- /dev/null +++ b/t20/nvboot_sdram_param_t20.h @@ -0,0 +1,366 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* Specifies the CPCON value for PllM */ + u_int32_t pllm_charge_pump_setup_ctrl; + /* Specifies the LPCON value for PllM */ + u_int32_t pllm_loop_filter_setup_ctrl; + /* Specifies the M value for PllM */ + u_int32_t pllm_input_divider; + /* Specifies the N value for PllM */ + u_int32_t pllm_feedback_divider; + /* Specifies the P value for PllM */ + u_int32_t pllm_post_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + u_int32_t pllm_stable_time; + + /* Specifies the divider for the EMC Clock Source */ + u_int32_t emc_clock_divider; + + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + u_int32_t emc_auto_cal_interval; + /** + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + u_int32_t emc_auto_cal_config; + /** + * Specifies the time for the calibration to + * stabilize (in microseconds) + */ + u_int32_t emc_auto_cal_wait; + + /** + * Specifies the time to wait after pin programming (in microseconds) + * Dram vendors require at least 200us. + */ + u_int32_t emc_pin_program_wait; + + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + u_int32_t emc_rc; + /* Specifies the value for EMC_RFC */ + u_int32_t emc_rfc; + /* Specifies the value for EMC_RAS */ + u_int32_t emc_ras; + /* Specifies the value for EMC_RP */ + u_int32_t emc_rp; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + u_int32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + u_int32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + u_int32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + u_int32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + u_int32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + u_int32_t emc_rext; + /* Specifies the value for EMC_WDV */ + u_int32_t emc_wdv; + /* Specifies the value for EMC_QUSE */ + u_int32_t emc_quse; + /* Specifies the value for EMC_QRST */ + u_int32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + u_int32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + u_int32_t emc_rdv; + /* Specifies the value for EMC_REFRESH */ + u_int32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + u_int32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PDEX2WR */ + u_int32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + u_int32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + u_int32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + u_int32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + u_int32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + u_int32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + u_int32_t emc_txsr; + /* Specifies the value for EMC_TCKE */ + u_int32_t emc_tcke; + /* Specifies the value for EMC_TFAW */ + u_int32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + u_int32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + u_int32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + u_int32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + u_int32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + u_int32_t emc_quse_extra; + + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG1 */ + u_int32_t emc_fbio_cfg1; + /* Specifies the value for EMC_FBIO_DQSIB_DLY */ + u_int32_t emc_fbio_dqsib_dly; + /* Specifies the value for EMC_FBIO_DQSIB_DLY_MSB */ + u_int32_t emc_fbio_dqsib_dly_msb; + /* Specifies the value for EMC_FBIO_QUSE_DLY */ + u_int32_t emc_fbio_quse_dly; + /* Specifies the value for EMC_FBIO_QUSE_DLY_MSB */ + u_int32_t emc_fbio_quse_dly_msb; + /* Specifies the value for EMC_FBIO_CFG5 */ + u_int32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + u_int32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + u_int32_t emc_fbio_spare; + + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + u_int32_t emc_mrs; + /* Specifies the value for EMC_EMRS */ + u_int32_t emc_emrs; + /* Specifies the first of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw1; + /* Specifies the second of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw2; + /* Specifies the third of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw3; + + /* Specifies the EMC_MRW reset command value */ + u_int32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + u_int32_t emc_mrw_reset_ninit_wait; + + /** + * Specifies the value for EMC_ADR_CFG + * The same value is also used for MC_EMC_ADR_CFG + */ + u_int32_t emc_adr_cfg; + /* Specifies the value for EMC_ADR_CFG_1 */ + u_int32_t emc_adr_cfg1; + + /** + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + * EMEM_SIZE_KB must be <= (Device size in KB * Number of Devices) + */ + u_int32_t mc_emem_cfg; + + /** + * Specifies the value for MC_LOWLATENCY_CONFIG + * Mainly for LL_DRAM_INTERLEAVE: Some DRAMs do not support interleave + * mode. If so, turn off this bit to get the correct low-latency path + * behavior. Reset is ENABLED. + */ + u_int32_t mc_lowlatency_config; + /* Specifies the value for EMC_CFG */ + u_int32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + u_int32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + u_int32_t emc_dbg; + + /* + * Specifies the value for AHB_ARBITRATION_XBAR_CTRL. + * This is used to set the Memory Inid done + */ + u_int32_t ahb_arbitration_xbar_ctrl; + + /* + * Specifies the value for EMC_CFG_DIG_DLL + * Note: Trigger bits are set by the SDRAM code. + */ + u_int32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_DLL_XFORM_DQS */ + u_int32_t emc_dll_xform_dqs; + /* Specifies the value for EMC_DLL_XFORM_QUSE */ + u_int32_t emc_dll_xform_quse; + + /* + * Specifies the delay after prgramming the PIN/NOP register during a + * WarmBoot0 sequence (in microseconds) + */ + u_int32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + u_int32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_read; + + /* + * Specifies the value for EMC_ZCAL_REF_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_ref_cnt; + /* + * Specifies the value for EMC_ZCAL_WAIT_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_wait_cnt; + /* + * Specifies the value for EMC_ZCAL_MRW_CMD + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_mrw_cmd; + + /* + * Specifies the MRS command value for initilizing + * the mode register. + */ + u_int32_t emc_mrs_reset_dll; + /* Specifies the MRW command for ZQ initialization of device 0 */ + u_int32_t emc_mrw_zq_init_dev0; + /* Specifies the MRW command for ZQ initialization of device 1 */ + u_int32_t emc_mrw_zq_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + u_int32_t emc_mrw_zq_init_wait; + /* + * Specifies the wait time after sending an MRS DLL reset command + * (in microseconds) + */ + u_int32_t emc_mrs_reset_dll_wait; + /* + * Specifies the first of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr2; + /* + * Specifies the second of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr3; + /* Specifies the EMRS command to enable the DDR2 DLL */ + u_int32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + u_int32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + u_int32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + u_int32_t emc_ddr2_wait; + + + /* Clock trimmers */ + + /* Specifies the value for EMC_CFG_CLKTRIM_0 */ + u_int32_t emc_cfg_clktrim0; + /* Specifies the value for EMC_CFG_CLKTRIM_1 */ + u_int32_t emc_cfg_clktrim1; + /* Specifies the value for EMC_CFG_CLKTRIM_2 */ + u_int32_t emc_cfg_clktrim2; + + + /* Pad controls */ + + /* Specifies the value for PMC_DDR_PWR */ + u_int32_t pmc_ddr_pwr; + /* Specifies the value for APB_MISC_GP_XM2CFGAPADCTRL */ + u_int32_t apb_misc_gp_xm2cfga_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL */ + u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL2 */ + u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL */ + u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL2 */ + u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CLKCFGPADCTRL */ + u_int32_t apb_misc_gp_xm2clkcfg_Pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2COMPPADCTRL */ + u_int32_t apb_misc_gp_xm2comp_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2VTTGENPADCTRL */ + u_int32_t apb_misc_gp_xm2vttgen_pad_ctrl; + + /* + * Specifies storage for arbitration configuration registers + * Data passed through to the Bootloader but not used by + * the Boot ROM + */ + u_int32_t arbitration_config[NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS]; +} nvboot_sdram_params; + +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H */ + diff --git a/t20/parse_t20.c b/t20/parse_t20.c new file mode 100644 index 0000000..b24f9fc --- /dev/null +++ b/t20/parse_t20.c @@ -0,0 +1,254 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * parse_t20.c - Parsing code for t20 + */ + +#include "../parse.h" +#include "nvboot_bct_t20.h" + +enum_item s_devtype_table_t20[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "NvBootDevType_Nand", nvboot_dev_type_nand }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { "Nand", nvboot_dev_type_nand }, + + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t20[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t20[] = { + { + "NvBootSpiClockSource_PllPOut0", + nvboot_spi_clock_source_pllp_out0 + }, + { + "NvBootSpiClockSource_PllCOut0", + nvboot_spi_clock_source_pllc_out0 + }, + { + "NvBootSpiClockSource_PllMOut0", + nvboot_spi_clock_source_pllm_out0 + }, + { + "NvBootSpiClockSource_ClockM", + nvboot_spi_clock_source_clockm + }, + + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + + + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t20[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t20[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t20 }, + + { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, + { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "EmcClockDivider", TOKEN(emc_clock_divider) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg1", TOKEN(emc_fbio_cfg1) }, + { "EmcFbioDqsibDlyMsb", TOKEN(emc_fbio_dqsib_dly_msb) }, + { "EmcFbioDqsibDly", TOKEN(emc_fbio_dqsib_dly) }, + { "EmcFbioQuseDlyMsb", TOKEN(emc_fbio_quse_dly_msb) }, + { "EmcFbioQuseDly", TOKEN(emc_fbio_quse_dly) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, + { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg1", TOKEN(emc_adr_cfg1) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "McLowLatencyConfig", TOKEN(mc_lowlatency_config) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgClktrim0", TOKEN(emc_cfg_clktrim0) }, + { "EmcCfgClktrim1", TOKEN(emc_cfg_clktrim1) }, + { "EmcCfgClktrim2", TOKEN(emc_cfg_clktrim2) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "AhbArbitrationXbarCtrl", TOKEN(ahb_arbitration_xbar_ctrl) }, + { "EmcDllXformDqs", TOKEN(emc_dll_xform_dqs) }, + { "EmcDllXformQUse", TOKEN(emc_dll_xform_quse) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalRefCnt", TOKEN(emc_zcal_ref_cnt) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcMrwZqInitDev0", TOKEN(emc_mrw_zq_init_dev0) }, + { "EmcMrwZqInitDev1", TOKEN(emc_mrw_zq_init_dev1) }, + { "EmcMrwZqInitWait", TOKEN(emc_mrw_zq_init_wait) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "ApbMiscGpXm2CfgAPadCtrl", TOKEN(apb_misc_gp_xm2cfga_pad_ctrl) }, + { "ApbMiscGpXm2CfgCPadCtrl2", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl2) }, + { "ApbMiscGpXm2CfgCPadCtrl", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl) }, + { "ApbMiscGpXm2CfgDPadCtrl2", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl2) }, + { "ApbMiscGpXm2CfgDPadCtrl", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl) }, + { "ApbMiscGpXm2ClkCfgPadCtrl", TOKEN(apb_misc_gp_xm2clkcfg_Pad_ctrl)}, + { "ApbMiscGpXm2CompPadCtrl", TOKEN(apb_misc_gp_xm2comp_pad_ctrl) }, + { "ApbMiscGpXm2VttGenPadCtrl", TOKEN(apb_misc_gp_xm2vttgen_pad_ctrl)}, + { NULL, 0, 0, NULL } +}; + +field_item s_nand_table_t20[] = { + { "ClockDivider", TOKEN(nand_clock_divider) }, + /* Note: NandTiming2 must appear before NandTiming, because NandTiming + * is a prefix of NandTiming2 and would otherwise match first. + */ + { "NandTiming2", TOKEN(nand_nand_timing2) }, + { "NandTiming", TOKEN(nand_nand_timing) }, + { "BlockSizeLog2", TOKEN(nand_block_size_log2) }, + { "PageSizeLog2", TOKEN(nand_page_size_log2) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t20[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t20 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t20[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t20 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t20[] = { + { "NandParams.", token_nand_params, + s_nand_table_t20, t20_set_dev_param }, + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t20, t20_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t20, t20_set_dev_param }, + + { NULL, 0, NULL } +}; |