diff options
Diffstat (limited to 'src/t132/nvboot_bct_t132.h')
| -rw-r--r-- | src/t132/nvboot_bct_t132.h | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/src/t132/nvboot_bct_t132.h b/src/t132/nvboot_bct_t132.h index 8c6fd6b..7dc0bf2 100644 --- a/src/t132/nvboot_bct_t132.h +++ b/src/t132/nvboot_bct_t132.h @@ -115,7 +115,7 @@ enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; * Defines the storage for a hash value (128 bits). */ typedef struct nvboot_hash_rec { - u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; } nvboot_hash; /* @@ -124,7 +124,7 @@ typedef struct nvboot_hash_rec { */ typedef struct nvboot_rsa_key_modulus_rec { /* The modulus size is 2048-bits. */ - u_int32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_key_modulus; typedef struct nvboot_rsa_pss_sig_rec { @@ -133,7 +133,7 @@ typedef struct nvboot_rsa_pss_sig_rec { * length in octets of the RSA modulus. * In our case, it's 2048-bits. */ - u_int32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_pss_sig; typedef struct nvboot_object_signature_rec { @@ -151,10 +151,10 @@ typedef struct nvboot_object_signature_rec { } nvboot_object_signature; typedef struct nvboot_ecid_rec { - u_int32_t ecid_0; - u_int32_t ecid_1; - u_int32_t ecid_2; - u_int32_t ecid_3; + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; } nvboot_ecid; /* Defines various data widths supported. */ @@ -191,7 +191,7 @@ typedef struct nvboot_sdmmc_params_rec { * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC * controller runs at 216/9 = 24MHz. */ - u_int8_t clock_divider; + uint8_t clock_divider; /* Specifies the data bus width. Supported data widths are 4/8 bits. */ nvboot_sdmmc_data_width data_width; @@ -202,10 +202,10 @@ typedef struct nvboot_sdmmc_params_rec { * supported within the power class range (0 to Max) if the selected * data width cannot be used at the chosen clock frequency. */ - u_int8_t max_power_class_supported; + uint8_t max_power_class_supported; /* Specifies the max page size supported by driver */ - u_int8_t multi_page_support; + uint8_t multi_page_support; } nvboot_sdmmc_params; typedef enum { @@ -226,7 +226,7 @@ typedef struct nvboot_spiflash_params_rec { /** * Specifies the clock source to use. */ - u_int32_t clock_source; + uint32_t clock_source; /** * Specifes the clock divider to use. @@ -238,24 +238,24 @@ typedef struct nvboot_spiflash_params_rec { * FAST_READ at 40MHz: 11 * FAST_READ at 50MHz: 9 */ - u_int8_t clock_divider; + uint8_t clock_divider; /** * Specifies the type of command for read operations. * NV_FALSE specifies a NORMAL_READ Command * NV_TRUE specifies a FAST_READ Command */ - u_int8_t read_command_type_fast; + uint8_t read_command_type_fast; /* 0 = 2k page size, 1 = 16K page size */ - u_int8_t page_size_2k_or_16k; + uint8_t page_size_2k_or_16k; } nvboot_spiflash_params; /** * Defines the union of the parameters required by each device. */ typedef union { - u_int8_t size[64]; + uint8_t size[64]; /* Specifies optimized parameters for eMMC and eSD */ nvboot_sdmmc_params sdmmc_params; /* Specifies optimized parameters for SPI NOR */ @@ -296,20 +296,20 @@ typedef struct nvboot_mts_info_rec * Specifies a version number for the MTS image. The assignment of * numbers is arbitrary; the numbers are only used to identify redundant. */ - u_int32_t version; + uint32_t version; /* * Specifies the first physical block on the secondary boot device * that contains the start of the MTS image. The first block can never be * a known bad block. */ - u_int32_t start_blk; + uint32_t start_blk; /* * Specifies the page within the first block that contains the start * of the MTS image. */ - u_int32_t start_page; + uint32_t start_page; /* * Specifies the length of the MTS image in bytes. MTS image must be @@ -318,22 +318,22 @@ typedef struct nvboot_mts_info_rec * a page. Add another 16 bytes to work around this restriction if * needed. */ - u_int32_t length; + uint32_t length; /* * Specifies the starting address of the memory region into which the * MTS will be loaded. This is optional. */ - u_int32_t load_addr; + uint32_t load_addr; /* Specifies the entry point address in the loaded MTS image. Optional */ - u_int32_t entry_point; + uint32_t entry_point; /* * Specifies an attribute available for use by other code. * Not interpreted by the Boot ROM. */ - u_int32_t attribute; + uint32_t attribute; } nvboot_mts_info; @@ -344,13 +344,13 @@ typedef struct nvboot_mts_info_rec * the device. */ typedef struct nv_bootloader_info_rec { - u_int32_t version; - u_int32_t start_blk; - u_int32_t start_page; - u_int32_t length; - u_int32_t load_addr; - u_int32_t entry_point; - u_int32_t attribute; + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ nvboot_object_signature signature; @@ -360,15 +360,15 @@ typedef struct nv_bootloader_info_rec { * Defines the bad block table structure stored in the BCT. */ typedef struct nvboot_badblock_table_rec { - u_int32_t entries_used; - u_int8_t virtual_blk_size_log2; - u_int8_t block_size_log2; - u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; /* * Add a reserved field as padding to make the bad block table structure * a multiple of 16 bytes (AES block size). */ - u_int8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; } nvboot_badblock_table; /** @@ -383,31 +383,31 @@ typedef struct nvboot_config_table_rec { nvboot_badblock_table badblock_table; nvboot_rsa_key_modulus key; nvboot_object_signature signature; - u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; - u_int32_t odm_data; - u_int32_t reserved1; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint32_t odm_data; + uint32_t reserved1; /* START OF SIGNED SECTION OF THE BCT */ nvboot_hash random_aes_blk; nvboot_ecid unique_chip_id; - u_int32_t boot_data_version; - u_int32_t block_size_log2; - u_int32_t page_size_log2; - u_int32_t partition_size; - u_int32_t num_param_sets; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; - u_int32_t num_sdram_sets; + uint32_t num_sdram_sets; nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; - u_int32_t bootloader_used; + uint32_t bootloader_used; nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; /* * Specify the number of Mts boot components described in the mts boot * table. */ - u_int32_t mts_boot_components_used; + uint32_t mts_boot_components_used; /* * Specify the information needed to locate and validate Denver Boot. @@ -416,7 +416,7 @@ typedef struct nvboot_config_table_rec { */ nvboot_mts_info mts_boot_components[NVBOOT_MAX_MTS_COMPONENTS]; - u_int8_t enable_fail_back; + uint8_t enable_fail_back; /* * Specify whether or not to enable JTAG access when the JTAG disable fuse @@ -424,15 +424,15 @@ typedef struct nvboot_config_table_rec { * secure_jtag_control = NV_FALSE (0) = Disable JTAG access. * secure_jtag_control = NV_TRUE (1) = Enable JTAG access. */ - u_int8_t secure_jtag_control; + uint8_t secure_jtag_control; /* * Specify whether or not to enable denver dfd access * cust_denver_dfd_en = NV_FALSE (0) = Disable Dfd access. * cust_denver_dfd_en = NV_TRUE (1) = Enable Dfd access. */ - u_int8_t cust_denver_dfd_en; + uint8_t cust_denver_dfd_en; - u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; } nvboot_config_table; #endif /* #ifndef INCLUDED_NVBOOT_BCT_T132_H */ |