diff options
| author | Peer Chen <pchen@nvidia.com> | 2012-03-13 11:12:39 +0800 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-04-10 10:55:18 -0700 |
| commit | 6f2cbc73840678445a3986c520d81f5ea44e85f5 (patch) | |
| tree | 7081f7bde5a7a17dafb10dcd0c85c07479dd3bba | |
| parent | 56f4048a7b55e60e037c06aae38c080b00c89014 (diff) | |
| download | nvidia-cbootimage-6f2cbc73840678445a3986c520d81f5ea44e85f5.tar.gz | |
CHROMIUM: cbootimage: Add t30 support
Add the t30 chip support to cbootimage file, use can append
-t20/-t30 chipname option to support the different chip
explicitly, the default is t20 if without this chipname option.
BUG=None
TEST=Test done locally with .cfg file
Change-Id: I0e77f0e0ce2a324bee3287787dcab1c15f3512e4
Reviewed-on: https://gerrit.chromium.org/gerrit/17911
Commit-Ready: Peer Chen <pchen@nvidia.com>
Tested-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | GNUmakefile | 20 | ||||
| -rw-r--r-- | aes_ref.c | 2 | ||||
| -rw-r--r-- | bct_dump.c | 154 | ||||
| -rw-r--r-- | cbootimage.c | 117 | ||||
| -rw-r--r-- | cbootimage.h | 59 | ||||
| -rw-r--r-- | context.c | 61 | ||||
| -rw-r--r-- | context.h | 2 | ||||
| -rw-r--r-- | crypto.c | 11 | ||||
| -rw-r--r-- | crypto.h | 2 | ||||
| -rw-r--r-- | data_layout.c | 499 | ||||
| -rw-r--r-- | data_layout.h | 7 | ||||
| -rw-r--r-- | nvaes_ref.h | 2 | ||||
| -rw-r--r-- | nvbctlib.h | 281 | ||||
| -rw-r--r-- | nvboot_sdram_param.h | 328 | ||||
| -rw-r--r-- | parse.c | 757 | ||||
| -rw-r--r-- | parse.h | 434 | ||||
| -rw-r--r-- | set.c | 437 | ||||
| -rw-r--r-- | set.h | 55 | ||||
| -rw-r--r-- | t20/nvbctlib_t20.c (renamed from nvbctlib_ap20.c) | 554 | ||||
| -rw-r--r-- | t20/nvboot_bct_t20.h (renamed from nvboot_bct.h) | 86 | ||||
| -rw-r--r-- | t20/nvboot_sdram_param_t20.h | 366 | ||||
| -rw-r--r-- | t20/parse_t20.c | 254 | ||||
| -rw-r--r-- | t30/nvbctlib_t30.c | 863 | ||||
| -rw-r--r-- | t30/nvboot_bct_t30.h | 374 | ||||
| -rw-r--r-- | t30/nvboot_sdram_param_t30.h | 571 | ||||
| -rw-r--r-- | t30/parse_t30.c | 363 |
26 files changed, 4180 insertions, 2479 deletions
diff --git a/GNUmakefile b/GNUmakefile index fa02155..0fdc002 100644 --- a/GNUmakefile +++ b/GNUmakefile @@ -8,15 +8,18 @@ all: $(TARGETS) # Build the cbootimage tool. # CBOOTIMAGE_C_FILES := cbootimage.c -CBOOTIMAGE_C_FILES += nvbctlib_ap20.c CBOOTIMAGE_C_FILES += data_layout.c -CBOOTIMAGE_C_FILES += parse.c CBOOTIMAGE_C_FILES += set.c CBOOTIMAGE_C_FILES += crypto.c CBOOTIMAGE_C_FILES += aes_ref.c CBOOTIMAGE_C_FILES += context.c +CBOOTIMAGE_C_FILES += parse.c +CBOOTIMAGE_C_FILES += t30/parse_t30.c +CBOOTIMAGE_C_FILES += t20/parse_t20.c +CBOOTIMAGE_C_FILES += t30/nvbctlib_t30.c +CBOOTIMAGE_C_FILES += t20/nvbctlib_t20.c -CBOOTIMAGE_OBJS := $(patsubst %.c,%.o,$(notdir $(CBOOTIMAGE_C_FILES))) +CBOOTIMAGE_OBJS := $(patsubst %.c,%.o,$(CBOOTIMAGE_C_FILES)) cbootimage: $(CBOOTIMAGE_OBJS) $(CC) -o $@ $^ $(CFLAGS) @@ -26,15 +29,18 @@ cbootimage: $(CBOOTIMAGE_OBJS) # the given BCT file. # BCT_DUMP_C_FILES := bct_dump.c -BCT_DUMP_C_FILES += nvbctlib_ap20.c BCT_DUMP_C_FILES += data_layout.c -BCT_DUMP_C_FILES += parse.c BCT_DUMP_C_FILES += set.c BCT_DUMP_C_FILES += crypto.c BCT_DUMP_C_FILES += aes_ref.c BCT_DUMP_C_FILES += context.c +BCT_DUMP_C_FILES += parse.c +BCT_DUMP_C_FILES += t30/parse_t30.c +BCT_DUMP_C_FILES += t20/parse_t20.c +BCT_DUMP_C_FILES += t30/nvbctlib_t30.c +BCT_DUMP_C_FILES += t20/nvbctlib_t20.c -BCT_DUMP_OBJS := $(patsubst %.c,%.o,$(notdir $(BCT_DUMP_C_FILES))) +BCT_DUMP_OBJS := $(patsubst %.c,%.o,$(BCT_DUMP_C_FILES)) bct_dump: $(BCT_DUMP_OBJS) $(CC) -o $@ $^ $(CFLAGS) @@ -43,4 +49,4 @@ bct_dump: $(BCT_DUMP_OBJS) # Remove built targets, object files and temporary editor files. # clean: - rm -rf *.o *~ $(TARGETS) + rm -f $(CBOOTIMAGE_OBJS) $(BCT_DUMP_OBJS) *~ $(TARGETS) @@ -1,5 +1,5 @@ /* - * (C) Copyright 2011 + * (C) Copyright 2012 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -21,49 +21,50 @@ */ #include "cbootimage.h" -#include "nvbctlib.h" #include "data_layout.h" #include "context.h" #include "parse.h" - +#include "t20/nvboot_bct_t20.h" #include <string.h> int enable_debug = 0; +bct_parse_interface *g_bct_parse_interf; + typedef struct { - nvbct_lib_id id; + parse_token id; char const * message; } value_data; static value_data const values[] = { - { nvbct_lib_id_boot_data_version, "Version = 0x%08x;\n" }, - { nvbct_lib_id_block_size_log2, "BlockSize = 0x%08x;\n" }, - { nvbct_lib_id_page_size_log2, "PageSize = 0x%08x;\n" }, - { nvbct_lib_id_partition_size, "PartitionSize = 0x%08x;\n" }, - { nvbct_lib_id_bootloader_used, "# Bootloader used = %d;\n" }, - { nvbct_lib_id_bootloaders_max, "# Bootloaders max = %d;\n" }, - { nvbct_lib_id_bct_size, "# BCT size = %d;\n" }, - { nvbct_lib_id_hash_size, "# Hash size = %d;\n" }, - { nvbct_lib_id_crypto_offset, "# Crypto offset = %d;\n" }, - { nvbct_lib_id_crypto_length, "# Crypto length = %d;\n" }, - { nvbct_lib_id_max_bct_search_blks, "# Max BCT search blocks = %d;\n" }, + { token_boot_data_version, "Version = 0x%08x;\n" }, + { token_block_size_log2, "BlockSize = 0x%08x;\n" }, + { token_page_size_log2, "PageSize = 0x%08x;\n" }, + { token_partition_size, "PartitionSize = 0x%08x;\n" }, + { token_bootloader_used, "# Bootloader used = %d;\n" }, + { token_bootloaders_max, "# Bootloaders max = %d;\n" }, + { token_bct_size, "# BCT size = %d;\n" }, + { token_hash_size, "# Hash size = %d;\n" }, + { token_crypto_offset, "# Crypto offset = %d;\n" }, + { token_crypto_length, "# Crypto length = %d;\n" }, + { token_max_bct_search_blks, "# Max BCT search blocks = %d;\n" }, }; static value_data const bl_values[] = { - { nvbct_lib_id_bl_version, "Version = 0x%08x;\n" }, - { nvbct_lib_id_bl_start_blk, "Start block = %d;\n" }, - { nvbct_lib_id_bl_start_page, "Start page = %d;\n" }, - { nvbct_lib_id_bl_length, "Length = %d;\n" }, - { nvbct_lib_id_bl_load_addr, "Load address = 0x%08x;\n" }, - { nvbct_lib_id_bl_entry_point, "Entry point = 0x%08x;\n" }, - { nvbct_lib_id_bl_attribute, "Attributes = 0x%08x;\n" }, + { token_bl_version, "Version = 0x%08x;\n" }, + { token_bl_start_blk, "Start block = %d;\n" }, + { token_bl_start_page, "Start page = %d;\n" }, + { token_bl_length, "Length = %d;\n" }, + { token_bl_load_addr, "Load address = 0x%08x;\n" }, + { token_bl_entry_point, "Entry point = 0x%08x;\n" }, + { token_bl_attribute, "Attributes = 0x%08x;\n" }, }; /*****************************************************************************/ static void usage(void) { printf("Usage: bct_dump bctfile\n"); - printf(" bctfile BCT filename to read and display\n"); + printf(" bctfile BCT filename to read and display\n"); } /*****************************************************************************/ static int max_width(field_item const * table) @@ -71,8 +72,7 @@ static int max_width(field_item const * table) int width = 0; int i; - for (i = 0; table[i].name != NULL; ++i) - { + for (i = 0; table[i].name != NULL; ++i) { int length = strlen(table[i].name); if (width < length) @@ -88,14 +88,8 @@ static enum_item const * find_enum_item(build_image_context *context, { int i; - for (i = 0; table[i].name != NULL; ++i) - { - u_int32_t table_value; - - if (!context->bctlib.get_value(table[i].value, - &table_value, - context->bct) && - table_value == value) + for (i = 0; table[i].name != NULL; ++i) { + if (table[i].value == value) return table + i; } @@ -118,8 +112,7 @@ static int display_field_value(build_image_context *context, field_item const * item, u_int32_t value) { - switch (item->type) - { + switch (item->type) { case field_type_enum: display_enum_value(context, item->enum_table, value); break; @@ -148,6 +141,7 @@ int main(int argc, char *argv[]) u_int32_t parameters_used; u_int32_t sdram_used; nvboot_dev_type type; + nvboot_config_table *bct = NULL; u_int32_t data; int i; int j; @@ -157,34 +151,35 @@ int main(int argc, char *argv[]) memset(&context, 0, sizeof(build_image_context)); - context.bct_filename = argv[1]; - - /* Set up the Nvbctlib function pointers. */ - nvbct_lib_get_fns(&(context.bctlib)); - - e = init_context(&context); - if (e != 0) { - printf("context initialization failed. Aborting.\n"); - return e; + g_bct_parse_interf = malloc(sizeof(bct_parse_interface)); + if (g_bct_parse_interf == NULL) { + printf("Insufficient memory to proceed.\n"); + return -EINVAL; } - read_bct_file(&context); + context.bct_filename = argv[1]; + e = read_bct_file(&context); + if (e != 0) + return e; + bct = (nvboot_config_table *)(context.bct); /* Display root values */ for (i = 0; i < sizeof(values) / sizeof(values[0]); ++i) { - e = context.bctlib.get_value(values[i].id, &data, context.bct); + e = g_bct_parse_interf->get_value(values[i].id, + &data, + context.bct); if (e != 0) data = -1; - else if (values[i].id == nvbct_lib_id_block_size_log2 || - values[i].id == nvbct_lib_id_page_size_log2) + else if (values[i].id == token_block_size_log2 || + values[i].id == token_page_size_log2) data = 1 << data; printf(values[i].message, data); } /* Display bootloader values */ - e = context.bctlib.get_value(nvbct_lib_id_bootloader_used, + e = g_bct_parse_interf->get_value(token_bootloader_used, &bootloaders_used, context.bct); @@ -199,7 +194,7 @@ int main(int argc, char *argv[]) for (i = 0; i < bootloaders_used; ++i) { for (j = 0; j < bl_count; ++j) { - e = context.bctlib.getbl_param(i, + e = g_bct_parse_interf->getbl_param(i, bl_values[j].id, &data, context.bct); @@ -214,7 +209,7 @@ int main(int argc, char *argv[]) } /* Display flash device parameters */ - e = context.bctlib.get_value(nvbct_lib_id_num_param_sets, + e = g_bct_parse_interf->get_value(token_num_param_sets, ¶meters_used, context.bct); @@ -223,30 +218,36 @@ int main(int argc, char *argv[]) char const * prefix = NULL; field_item const * item; - e = context.bctlib.getdev_param(i, - nvbct_lib_id_dev_type, - &type, - context.bct); - + e = g_bct_parse_interf->get_dev_param(&context, + i, + token_dev_type, + &type); printf("\n" "DevType[%d] = ", i); - display_enum_value(&context, s_devtype_table, type); + display_enum_value(&context, s_devtype_table_t20, type); printf(";\n"); - switch (type) - { + switch (type) { case nvboot_dev_type_spi: - device_field_table = s_spiflash_table; + device_field_table = s_spiflash_table_t20; prefix = "SpiFlashParams"; break; case nvboot_dev_type_sdmmc: - device_field_table = s_sdmmc_table; + if (bct->boot_data_version == + NVBOOT_BOOTDATA_VERSION(3, 1)) + device_field_table = s_sdmmc_table_t30; + else + device_field_table = s_sdmmc_table_t20; prefix = "SdmmcParams"; break; case nvboot_dev_type_nand: - device_field_table = s_nand_table; + if (bct->boot_data_version == + NVBOOT_BOOTDATA_VERSION(3, 1)) + device_field_table = s_nand_table_t30; + else + device_field_table = s_nand_table_t20; prefix = "NandParams"; break; @@ -262,10 +263,10 @@ int main(int argc, char *argv[]) int width = max_width(device_field_table); for (item = device_field_table; item->name != NULL; ++item) { - e = context.bctlib.getdev_param(i, - item->enum_value, - &data, - context.bct); + g_bct_parse_interf->get_dev_param(&context, + i, + item->token, + &data); printf("DeviceParam[%d].%s.%-*s = ", i, prefix, width, item->name); @@ -279,21 +280,28 @@ int main(int argc, char *argv[]) } /* Display SDRAM parameters */ - e = context.bctlib.get_value(nvbct_lib_id_num_sdram_sets, + e = g_bct_parse_interf->get_value(token_num_sdram_sets, &sdram_used, context.bct); for (i = 0; (e == 0) && (i < sdram_used); ++i) { - int width = max_width(s_sdram_field_table); - field_item const * item; + field_item const *s_sdram_field_table; + field_item const *item; printf("\n"); + if (bct->boot_data_version == NVBOOT_BOOTDATA_VERSION(3, 1)) + s_sdram_field_table = s_sdram_field_table_t30; + else + s_sdram_field_table = s_sdram_field_table_t20; + + int width = max_width(s_sdram_field_table); + for (item = s_sdram_field_table; item->name != NULL; ++item) { - e = context.bctlib.get_sdram_params(i, - item->enum_value, - &data, - context.bct); + e = g_bct_parse_interf ->get_sdram_param(&context, + i, + item->token, + &data); printf("SDRAM[%d].%-*s = ", i, width, item->name); if (e != 0) diff --git a/cbootimage.c b/cbootimage.c index a4263aa..0356ecf 100644 --- a/cbootimage.c +++ b/cbootimage.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -25,12 +25,12 @@ */ #include "cbootimage.h" -#include "nvbctlib.h" #include "crypto.h" #include "data_layout.h" #include "parse.h" #include "set.h" #include "context.h" +#include <getopt.h> /* * Global data @@ -39,11 +39,20 @@ int enable_debug = 0; static int help_only = 0; // Only print help & exit +bct_parse_interface *g_bct_parse_interf; /* * Function prototypes */ int main(int argc, char *argv[]); +struct option cbootcmd[] = { + {"help", 0, NULL, 'h'}, + {"debug", 0, NULL, 'd'}, + {"generate", 1, NULL, 'g'}, + {"tegra", 1, NULL, 't'}, + {0, 0, 0, 0}, +}; + int write_image_file(build_image_context *context) { @@ -60,6 +69,8 @@ usage(void) printf(" -h, --help, -? Display this message.\n"); printf(" -d, --debug Output debugging information.\n"); printf(" -gbct Generate the new bct file.\n"); + printf(" [-t20|-t25|-t30] Select one of the possible\n"); + printf(" target devices, -t20 if unspecified\n"); printf(" configfile File with configuration information\n"); printf(" imagename Output image name\n"); } @@ -68,33 +79,60 @@ static int process_command_line(int argc, char *argv[], build_image_context *context) { int arg = 1; + int c; context->generate_bct = 0; - while (arg < argc) { - /* Process the next argument. */ - if (!strcmp(argv[arg], "-h") || - !strcmp(argv[arg], "--help") || - !strcmp(argv[arg], "-?")) { + g_bct_parse_interf = malloc(sizeof(bct_parse_interface)); + if (g_bct_parse_interf == NULL) { + printf("Insufficient memory to proceed.\n"); + return -EINVAL; + } + /* Make the default interface to t20. */ + t20_get_cbootimage_interf(g_bct_parse_interf); + context->boot_data_version = NVBOOT_BOOTDATA_VERSION(2, 1); + + while ((c = getopt_long(argc, argv, "hdg:t:", cbootcmd, NULL)) != -1) { + switch (c) { + case 'h': help_only = 1; usage(); return 0; - } else if (!strcmp(argv[arg], "-d") || - !strcmp(argv[arg], "--debug")) { + case 'd': enable_debug = 1; arg++; - } else if (!strcmp(argv[arg], "-gbct")) { - context->generate_bct = 1; - arg++; - } else if (argv[arg][0] == '-') { - printf("Illegal option %s\n", argv[arg]); - usage(); - return -EINVAL; + break; + case 'g': + if (!strcasecmp("bct", optarg)) { + context->generate_bct = 1; + arg++; + } else { + printf("Invalid argument!\n"); + usage(); + return -EINVAL; + } + break; + case 't': + if (!(strcasecmp("20", optarg) + && strcasecmp("25", optarg))) { + /* Assign the interface based on the chip. */ + t20_get_cbootimage_interf(g_bct_parse_interf); + context->boot_data_version = + NVBOOT_BOOTDATA_VERSION(2, 1); + arg++; + } else if (!(strcasecmp("30", optarg))) { + t30_get_cbootimage_interf(g_bct_parse_interf); + context->boot_data_version = + NVBOOT_BOOTDATA_VERSION(3, 1); + arg++; + } else { + printf("Unsupported chipname!\n"); + usage(); + return -EINVAL; + } + break; } - else - break; /* Finished with options */ } - /* Handle file specification errors. */ switch (argc - arg) { case 0: @@ -127,9 +165,6 @@ process_command_line(int argc, char *argv[], build_image_context *context) /* Record the output filename */ context->image_filename = argv[arg + 1]; - /* Set up the Nvbctlib function pointers. */ - nvbct_lib_get_fns(&(context->bctlib)); - return 0; } @@ -138,7 +173,6 @@ main(int argc, char *argv[]) { int e = 0; build_image_context context; - u_int32_t data = 0; memset(&context, 0, sizeof(build_image_context)); @@ -146,9 +180,15 @@ main(int argc, char *argv[]) if (process_command_line(argc, argv, &context) != 0) return -EINVAL; + assert(g_bct_parse_interf != NULL); + if (help_only) return 1; + g_bct_parse_interf->get_value(token_bct_size, + &context.bct_size, + context.bct); + e = init_context(&context); if (e != 0) { printf("context initialization failed. Aborting.\n"); @@ -157,9 +197,7 @@ main(int argc, char *argv[]) if (enable_debug) { /* Debugging information... */ - e = context.bctlib.get_value(nvbct_lib_id_bct_size, - &data, context.bct); - printf("bct size: %d\n", e == 0 ? data : -1); + printf("bct size: %d\n", e == 0 ? context.bct_size : -1); } /* Open the raw output file. */ @@ -171,11 +209,16 @@ main(int argc, char *argv[]) goto fail; } - /* Parse & process the contents of the config file. */ - process_config_file(&context); - + /* first, if we aren't generating the bct, read in config file */ + if (context.generate_bct == 0) { + process_config_file(&context, 1); + } /* Generate the new bct file */ - if (context.generate_bct != 0) { + else { + /* Initialize the bct memory */ + init_bct(&context); + /* Parse & process the contents of the config file. */ + process_config_file(&context, 0); /* Update the BCT */ begin_update(&context); /* Signing the bct. */ @@ -183,20 +226,13 @@ main(int argc, char *argv[]) if (e != 0) printf("Signing BCT failed, error: %d.\n", e); - fwrite(context.bct, 1, sizeof(nvboot_config_table), + fwrite(context.bct, 1, context.bct_size, context.raw_file); printf("New BCT file %s has been successfully generated!\n", context.image_filename); goto fail; } - /* Update the bct file */ - /* Update the add on file */ - e = update_addon_item(&context); - if ( e!= 0) { - printf("Write addon item failed, error: %d.\n", e); - goto fail; - } /* Peform final signing & encryption of bct. */ e = sign_bct(&context, context.bct); if (e != 0) { @@ -218,6 +254,9 @@ main(int argc, char *argv[]) /* Clean up memory. */ cleanup_context(&context); - + if (g_bct_parse_interf) { + free(g_bct_parse_interf); + g_bct_parse_interf = NULL; + } return e; } diff --git a/cbootimage.h b/cbootimage.h index 0077d66..5f9166e 100644 --- a/cbootimage.h +++ b/cbootimage.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -27,8 +27,6 @@ #ifndef INCLUDED_BUILDIMAGE_H #define INCLUDED_BUILDIMAGE_H -#include "nvboot_bct.h" -#include "nvbctlib.h" #include <stdio.h> #include <stdlib.h> #include <assert.h> @@ -51,50 +49,16 @@ typedef enum { file_type_bl = 0, file_type_bct, - file_type_addon } file_type; + /* - * Structures + * The main context data structure of cbootimage tool */ -typedef struct item_rec -{ - u_int8_t unique_name[4]; - u_int32_t Location; - u_int32_t size; - u_int32_t attribute; - u_int32_t reserve[4]; - u_int32_t item_checksum[4]; -}item; - -typedef struct addon_item_rec -{ - struct item_rec item; - char addon_filename[MAX_BUFFER]; - int item_index; - struct addon_item_rec *next; -}addon_item; - -typedef struct table_rec -{ - u_int8_t magic_id[8]; - u_int32_t table_checksum[4]; - u_int32_t table_size; - -}table; - -typedef struct addon_table_rec -{ - struct table_rec table; - u_int8_t addon_item_no; - struct addon_item_rec *addon_item_list; -}addon_table; - typedef struct build_image_context_rec { FILE *config_file; char *image_filename; FILE *raw_file; - nvbct_lib_fns bctlib; u_int32_t block_size; u_int32_t block_size_log2; u_int32_t page_size; @@ -116,10 +80,11 @@ typedef struct build_image_context_rec u_int8_t generate_bct; u_int8_t *bct; - struct addon_table_rec addon_tbl; char *bct_filename; u_int32_t last_bl_blk; - u_int32_t addon_tbl_blk; + u_int32_t bct_size; /* The BCT file size */ + u_int32_t boot_data_version; /* The boot data version of BCT */ + u_int8_t bct_init; /* The flag for the memory allocation of bct */ } build_image_context; /* Function prototypes */ @@ -129,16 +94,4 @@ int write_image_file(build_image_context *context); /* Global data */ extern int enable_debug; -/* Useful macros */ - -#define GET_VALUE(id, ptr) \ - (void)context->bctlib.get_value(nvbct_lib_id_##id, \ - ptr, \ - context->bct); - -#define SET_VALUE(id, value) \ - (void)context->bctlib.set_value(nvbct_lib_id_##id, \ - value, \ - context->bct); - #endif /* #ifndef INCLUDED_BUILDIMAGE_H */ @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -24,61 +24,22 @@ #include "data_layout.h" #include "set.h" -static int -query_alloc(build_image_context *context, - nvbct_lib_id size_id, - u_int8_t **dst) -{ - u_int32_t size; - - /* Note: 3rd argument not used in this particular query. */ - if (context->bctlib.get_value(size_id, &size, context->bct) != 0) - return -ENODATA; - - *dst = malloc(size); - - if (*dst == NULL) - return -ENOMEM; - - memset(*dst, 0, size); - - return 0; -} - void cleanup_context(build_image_context *context) { - destroy_block_list(context->memory); - destroy_addon_list(context->addon_tbl.addon_item_list); - free(context->bct); + destroy_block_list(context->memory); + free(context->bct); } int init_context(build_image_context *context) { - int e = 0; - - /* Set defaults */ - context->memory = new_block_list(); - context->next_bct_blk = 0; /* Default to block 0 */ - - /* Allocate space for the bct. - * Note that this is different from the old code which pointed directly - * into a memory image. - */ - e = query_alloc(context, nvbct_lib_id_bct_size, &(context->bct)); - if (e != 0) - goto fail; - - context_set_value(context, token_page_size, 2048); - context_set_value(context, token_redundancy, 1); - context_set_value(context, token_version, 1); - context_set_value(context, token_bct_copy, 2); - - return 0; - - fail: - cleanup_context(context); - - return e; + /* Set defaults */ + context->memory = new_block_list(); + context->next_bct_blk = 0; /* Default to block 0 */ + context_set_value(context, token_redundancy, 1); + context_set_value(context, token_version, 1); + context_set_value(context, token_bct_copy, 2); + + return 0; } @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -1,5 +1,5 @@ /* - * (C) Copyright 2011 + * (C) Copyright 2012 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ * crypto.c - Cryptography support */ #include "crypto.h" +#include "parse.h" #include "nvaes_ref.h" #include <stdio.h> @@ -270,15 +271,15 @@ sign_bct(build_image_context *context, assert(bct != NULL); - if (context->bctlib.get_value(nvbct_lib_id_hash_size, + if (g_bct_parse_interf->get_value(token_hash_size, &hash_size, bct) != 0) return -ENODATA; - if (context->bctlib.get_value(nvbct_lib_id_crypto_offset, + if (g_bct_parse_interf->get_value(token_crypto_offset, &Offset, bct) != 0) return -ENODATA; - if (context->bctlib.get_value(nvbct_lib_id_crypto_length, + if (g_bct_parse_interf->get_value(token_crypto_length, &length, bct) != 0) return -ENODATA; @@ -289,7 +290,7 @@ sign_bct(build_image_context *context, e = sign_data_block(bct + Offset, length, hash_buffer); if (e != 0) goto fail; - e = context->bctlib.set_data(nvbct_lib_id_crypto_hash, + e = g_bct_parse_interf->set_data(token_crypto_hash, hash_buffer, hash_size, bct); @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. diff --git a/data_layout.c b/data_layout.c index 13c5056..d5c5732 100644 --- a/data_layout.c +++ b/data_layout.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -29,6 +29,9 @@ #include "cbootimage.h" #include "crypto.h" #include "set.h" +#include "context.h" +#include "parse.h" +#include "t20/nvboot_bct_t20.h" #include <sys/param.h> typedef struct blk_data_rec @@ -78,18 +81,17 @@ set_bl_data(build_image_context *context, static int write_bootloaders(build_image_context *context); -static u_int32_t find_new_bct_blk(build_image_context *context); +static void find_new_bct_blk(build_image_context *context); static int finish_update(build_image_context *context); -static void init_bad_block_table(build_image_context *context); -static u_int32_t +u_int32_t iceil_log2(u_int32_t a, u_int32_t b) { return (a + (1 << b) - 1) >> b; } /* Returns the smallest power of 2 >= a */ -static u_int32_t +u_int32_t ceil_log2(u_int32_t a) { u_int32_t result; @@ -101,28 +103,6 @@ ceil_log2(u_int32_t a) return result; } -static void init_bad_block_table(build_image_context *context) -{ - u_int32_t bytes_per_entry; - nvboot_badblock_table *table; - nvboot_config_table *bct; - - bct = (nvboot_config_table *)(context->bct); - - assert(context != NULL); - assert(bct != NULL); - - table = &(bct->badblock_table); - - bytes_per_entry = ICEIL(context->partition_size, - NVBOOT_BAD_BLOCK_TABLE_SIZE); - table->block_size_log2 = context->block_size_log2; - table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), - table->block_size_log2); - table->entries_used = iceil_log2(context->partition_size, - table->virtual_blk_size_log2); -} - static block_data *new_block(u_int32_t blk_number, u_int32_t block_size) { block_data *new_block = malloc(sizeof(block_data)); @@ -286,21 +266,16 @@ write_bct(build_image_context *context, u_int32_t block, u_int32_t bct_slot) { - u_int32_t bct_size; u_int32_t pagesremaining; u_int32_t page; u_int32_t pages_per_bct; u_int8_t *buffer; u_int8_t *data; - int e = 0; + int err = 0; assert(context); - /* Note: 3rd argument not used in this particular query. */ - (void)context->bctlib.get_value(nvbct_lib_id_bct_size, - &bct_size, context->bct); - - pages_per_bct = iceil_log2(bct_size, context->page_size_log2); + pages_per_bct = iceil_log2(context->bct_size, context->page_size_log2); pagesremaining = pages_per_bct; page = bct_slot * pages_per_bct; @@ -310,20 +285,20 @@ write_bct(build_image_context *context, return -ENOMEM; memset(buffer, 0, pages_per_bct * context->page_size); - memcpy(buffer, context->bct, bct_size); + memcpy(buffer, context->bct, context->bct_size); - insert_padding(buffer, bct_size); + insert_padding(buffer, context->bct_size); /* Encrypt and compute hash */ - e = sign_bct(context, buffer); - if (e != 0) + err = sign_bct(context, buffer); + if (err != 0) goto fail; /* Write the BCT data to the storage device, picking up ECC errors */ data = buffer; while (pagesremaining > 0) { - e = write_page(context, block, page, data); - if (e != 0) + err = write_page(context, block, page, data); + if (err != 0) goto fail; page++; pagesremaining--; @@ -332,28 +307,28 @@ write_bct(build_image_context *context, fail: /* Cleanup */ free(buffer); - return e; + return err; } -#define SET_BL_FIELD(instance, field, value) \ +#define SET_BL_FIELD(instance, field, value) \ do { \ - (void)context->bctlib.setbl_param(instance, \ - nvbct_lib_id_bl_##field, \ - &(value), \ - context->bct); \ + g_bct_parse_interf->setbl_param(instance, \ + token_bl_##field, \ + &(value), \ + context->bct); \ } while (0); -#define GET_BL_FIELD(instance, field, ptr) \ -(void)context->bctlib.getbl_param(instance, \ - nvbct_lib_id_bl_##field, \ - ptr, \ +#define GET_BL_FIELD(instance, field, ptr) \ +g_bct_parse_interf->getbl_param(instance, \ + token_bl_##field, \ + ptr, \ context->bct); -#define COPY_BL_FIELD(from, to, field) \ -do { \ - u_int32_t v; \ - GET_BL_FIELD(from, field, &v); \ - SET_BL_FIELD(to, field, v); \ +#define COPY_BL_FIELD(from, to, field) \ +do { \ + u_int32_t v; \ + GET_BL_FIELD(from, field, &v); \ + SET_BL_FIELD(to, field, v); \ } while (0); static void @@ -374,14 +349,16 @@ set_bl_data(build_image_context *context, SET_BL_FIELD(instance, attribute, context->newbl_attr); } - /* + * Load the bootloader image then update it with the information + * from config file. * In the interest of expediency, all BL's allocated from bottom to top start * at page 0 of a block, and all BL's allocated from top to bottom end at * the end of a block. + * + * @param context The main context pointer + * @return 0 for success */ -/* TODO: Check for partition overflow */ -/* TODO: Refactor this code! */ static int write_bootloaders(build_image_context *context) { @@ -396,7 +373,6 @@ write_bootloaders(build_image_context *context) u_int8_t *bl_storage; /* Holds the Bl after reading */ u_int8_t *buffer; /* Holds the Bl for writing */ u_int8_t *src; /* Scans through the Bl during writing */ - u_int32_t bl_length; /* In bytes */ u_int32_t bl_actual_size; /* In bytes */ u_int32_t pagesremaining; u_int32_t virtual_blk; @@ -409,15 +385,17 @@ write_bootloaders(build_image_context *context) u_int32_t hash_size; u_int32_t bootloaders_max; file_type bl_filetype = file_type_bl; - int e = 0; + int err = 0; assert(context); pages_per_blk = 1 << (context->block_size_log2 - context->page_size_log2); - GET_VALUE(hash_size, &hash_size); - GET_VALUE(bootloaders_max, &bootloaders_max); + g_bct_parse_interf->get_value(token_hash_size, + &hash_size, context->bct); + g_bct_parse_interf->get_value(token_bootloaders_max, + &bootloaders_max, context->bct); hash_buffer = malloc(hash_size); if (hash_buffer == NULL) @@ -435,7 +413,8 @@ write_bootloaders(build_image_context *context) * a BL in the device. */ GET_BL_FIELD(0, version, &bl_0_version); - GET_VALUE(bootloader_used, &bl_used); + g_bct_parse_interf->get_value(token_bootloader_used, + &bl_used, context->bct); for (bl_instance = 0; bl_instance < bl_used; bl_instance++) { u_int32_t bl_version; GET_BL_FIELD(bl_instance, version, &bl_version); @@ -464,12 +443,12 @@ write_bootloaders(build_image_context *context) COPY_BL_FIELD(inst_from, inst_to, entry_point); COPY_BL_FIELD(inst_from, inst_to, attribute); - (void)context->bctlib.getbl_param(inst_from, - nvbct_lib_id_bl_crypto_hash, + g_bct_parse_interf->getbl_param(inst_from, + token_bl_crypto_hash, (u_int32_t*)hash_buffer, context->bct); - (void)context->bctlib.setbl_param(inst_to, - nvbct_lib_id_bl_crypto_hash, + g_bct_parse_interf->setbl_param(inst_to, + token_bl_crypto_hash, (u_int32_t*)hash_buffer, context->bct); bl_move_remaining--; @@ -477,9 +456,7 @@ write_bootloaders(build_image_context *context) /* Read the BL into memory. */ if (read_from_image(context->newbl_filename, - context->page_size, &bl_storage, - &bl_length, &bl_actual_size, bl_filetype) == 1) { printf("Error reading Bootloader %s.\n", @@ -487,7 +464,7 @@ write_bootloaders(build_image_context *context) exit(1); } - pages_in_bl = iceil_log2(bl_length, context->page_size_log2); + pages_in_bl = iceil_log2(bl_actual_size, context->page_size_log2); current_blk = context->next_bct_blk; current_page = 0; @@ -551,8 +528,8 @@ write_bootloaders(build_image_context *context) sign_data_block(buffer, bl_actual_size, hash_buffer); - (void)context->bctlib.setbl_param(bl_instance, - nvbct_lib_id_bl_crypto_hash, + g_bct_parse_interf->setbl_param(bl_instance, + token_bl_crypto_hash, (u_int32_t*)hash_buffer, context->bct); @@ -569,9 +546,9 @@ write_bootloaders(build_image_context *context) erase_block(context, current_blk); } - e = write_page(context, + err = write_page(context, current_blk, current_page, src); - if (e != 0) + if (err != 0) goto fail; pagesremaining--; src += context->page_size; @@ -586,13 +563,11 @@ write_bootloaders(build_image_context *context) free(buffer); } - (void)context->bctlib.set_value(nvbct_lib_id_bootloader_used, + g_bct_parse_interf->set_value(token_bootloader_used, context->redundancy + bl_move_count, context->bct); if (enable_debug) { - GET_VALUE(bootloader_used, &bl_used); - for (i = 0; i < bootloaders_max; i++) { u_int32_t version; u_int32_t start_blk; @@ -618,8 +593,8 @@ write_bootloaders(build_image_context *context) load_addr, entry_point); - (void)context->bctlib.getbl_param(i, - nvbct_lib_id_bl_crypto_hash, + g_bct_parse_interf->getbl_param(i, + token_bl_crypto_hash, (u_int32_t*)hash_buffer, context->bct); for (j = 0; j < hash_size / 4; j++) { @@ -637,173 +612,20 @@ fail: free(buffer); free(bl_storage); free(hash_buffer); - printf("Write bootloader failed, error: %d.\n", e); - return e; -} - -int -update_addon_item(build_image_context *context) -{ - u_int8_t *aoi_storage; - u_int8_t *buffer=NULL; - u_int8_t *src=NULL; - u_int32_t aoi_length; - u_int32_t aoi_actual_size; - u_int32_t pages_count; - u_int32_t pagesremaining; - u_int32_t current_blk; - u_int32_t current_page; - u_int32_t pages_per_blk; - u_int32_t table_length; - u_int32_t hash_size; - int i; - u_int8_t magicid[8] = "ChromeOs"; - struct addon_item_rec *current_item; - file_type aoi_filetype = file_type_addon; - int e = 0; - - /* Read the Addon item into memory. */ - GET_VALUE(hash_size, &hash_size); - pages_per_blk = 1 << (context->block_size_log2 - - context->page_size_log2); - current_blk = context->last_bl_blk; - - /* Get the addon table block number */ - current_blk++; - context->addon_tbl_blk = current_blk; - - /* write the addon item */ - current_item = context->addon_tbl.addon_item_list; - for(i = 0; i < context->addon_tbl.addon_item_no; i++) { - - if (read_from_image(current_item->addon_filename, - context->page_size, - &aoi_storage, - &aoi_length, - &aoi_actual_size, - aoi_filetype) == 1) { - printf("Error reading addon file %s.\n", - context->addon_tbl.addon_item_list->addon_filename); - - exit(1); - } - pages_count = iceil_log2(aoi_length, context->page_size_log2); - - /* Create a local copy of the BCT data */ - buffer = malloc(pages_count * context->page_size); - if (buffer == NULL) - return -ENOMEM; - - memset(buffer, 0, pages_count * context->page_size); - memcpy(buffer, aoi_storage, aoi_actual_size); - insert_padding(buffer, aoi_actual_size); - /* Encrypt and compute hash */ - sign_data_block(buffer, - aoi_actual_size, - (u_int8_t *)current_item->item.item_checksum); - - pagesremaining = pages_count; - src = buffer; - current_blk++; - current_page = 0; - current_item->item.Location = current_blk; - current_item->item.size = aoi_actual_size; - while (pagesremaining) { - if (current_page == 0) { - /* Erase the block before writing into it. */ - e = erase_block(context, current_blk); - if (e != 0) - goto fail_on_item; - } - e = write_page(context, - current_blk, current_page, src); - if (e != 0) - goto fail_on_item; - pagesremaining--; - src += context->page_size; - current_page++; - if (current_page >= pages_per_blk) { - current_page = 0; - current_blk++; - } - } - current_item = current_item->next; - free(aoi_storage); - free(buffer); - } - - /* write add on table */ - current_blk = context->addon_tbl_blk; - current_item = context->addon_tbl.addon_item_list; - current_page = 0; - table_length = sizeof(struct table_rec) + - context->addon_tbl.addon_item_no * sizeof(struct item_rec); - context->addon_tbl.table.table_size= table_length; - memcpy(context->addon_tbl.table.magic_id, magicid, 8); - pages_count = iceil_log2(table_length, context->page_size_log2); - buffer = malloc(pages_count * context->page_size); - if (buffer == NULL) - return -ENOMEM; - - memset(buffer, 0, pages_count * context->page_size); - src = buffer; - memcpy(src, &context->addon_tbl, sizeof(struct table_rec)); - src += sizeof(struct table_rec); - - for(i = 0; i < context->addon_tbl.addon_item_no; i++) { - memcpy(src, current_item, sizeof(struct item_rec)); - src += sizeof(struct item_rec); - current_item = current_item->next; - } - insert_padding(buffer, table_length); - - pagesremaining = pages_count; - src = buffer; - - /* Encrypt and compute hash */ - e = sign_data_block(buffer, - table_length, - (u_int8_t *)context->addon_tbl.table.table_checksum); - if (e != 0) - goto fail_on_table; - memcpy(src+sizeof(context->addon_tbl.table.magic_id), - context->addon_tbl.table.table_checksum, - hash_size); - - while (pagesremaining) { - if (current_page == 0) { - e = erase_block(context, current_blk); - if (e != 0) - goto fail_on_table; - } - e = write_page(context, current_blk, current_page, src); - if(e != 0) - goto fail_on_table; - pagesremaining--; - src += context->page_size; - current_page++; - } - free(buffer); - return 0; - -fail_on_item: - free(aoi_storage); - -fail_on_table: - free(buffer); - return e; + printf("Write bootloader failed, error: %d.\n", err); + return err; } void update_context(struct build_image_context_rec *context) { - (void)context->bctlib.get_value(nvbct_lib_id_partition_size, + g_bct_parse_interf->get_value(token_partition_size, &context->partition_size, context->bct); - (void)context->bctlib.get_value(nvbct_lib_id_page_size_log2, + g_bct_parse_interf->get_value(token_page_size_log2, &context->page_size_log2, context->bct); - (void)context->bctlib.get_value(nvbct_lib_id_block_size_log2, + g_bct_parse_interf->get_value(token_block_size_log2, &context->block_size_log2, context->bct); @@ -812,112 +634,114 @@ update_context(struct build_image_context_rec *context) context->pages_per_blk = 1 << (context->block_size_log2 - context->page_size_log2); } -void + +/* + * Allocate and initialize the memory for bct data. + * + * @param context The main context pointer + * @return 0 for success + */ +int +init_bct(struct build_image_context_rec *context) +{ + /* Allocate space for the bct. */ + context->bct = malloc(context->bct_size); + + if (context->bct == NULL) + return -ENOMEM; + + memset(context->bct, 0, context->bct_size); + context->bct_init = 1; + + return 0; +} + +/* + * Read the bct data from given file to allocated memory. + * Assign the global parse interface to corresponding hardware interface + * according to the boot data version in bct file. + * + * @param context The main context pointer + * @return 0 for success + */ +int read_bct_file(struct build_image_context_rec *context) { u_int8_t *bct_storage; /* Holds the Bl after reading */ - u_int32_t bct_length; /* In bytes */ u_int32_t bct_actual_size; /* In bytes */ - u_int32_t bct_size; file_type bct_filetype = file_type_bct; + nvboot_config_table *bct = NULL; + int err = 0; - bct_size = sizeof(nvboot_config_table); if (read_from_image(context->bct_filename, - context->page_size, &bct_storage, - &bct_length, &bct_actual_size, bct_filetype) == 1) { printf("Error reading bct file %s.\n", context->bct_filename); exit(1); } - memcpy(context->bct, bct_storage, bct_size); + context->bct_size = bct_actual_size; + if (context->bct_init != 1) + err = init_bct(context); + if (err != 0) { + printf("Context initialization failed. Aborting.\n"); + return err; + } + memcpy(context->bct, bct_storage, context->bct_size); free(bct_storage); - update_context(context); -} -void destroy_addon_list(struct addon_item_rec *addon_list) -{ - struct addon_item_rec *next; - - while (addon_list) { - next = addon_list->next; - free(addon_list); - addon_list = next; + bct = (nvboot_config_table *)(context->bct); + if (bct->boot_data_version == NVBOOT_BOOTDATA_VERSION(3, 1)) { + t30_get_cbootimage_interf(g_bct_parse_interf); + context->boot_data_version = + NVBOOT_BOOTDATA_VERSION(3, 1); + } + else { + t20_get_cbootimage_interf(g_bct_parse_interf); + context->boot_data_version = + NVBOOT_BOOTDATA_VERSION(2, 1); } + return err; } - -static u_int32_t +/* + * Update the next_bct_blk and make it point to the next + * new blank block according to bct_copy given. + * + * @param context The main context pointer + */ +static void find_new_bct_blk(build_image_context *context) { - u_int32_t current_blk; u_int32_t max_bct_search_blks; assert(context); - current_blk = context->next_bct_blk; + g_bct_parse_interf->get_value(token_hash_size, + &max_bct_search_blks, context->bct); - GET_VALUE(max_bct_search_blks, &max_bct_search_blks); - - if (current_blk >= max_bct_search_blks) { + if (context->next_bct_blk > max_bct_search_blks) { printf("Error: Unable to locate a journal block.\n"); exit(1); } context->next_bct_blk++; - return current_blk; } /* - * Logic for updating a BCT or BL: - * - begin_update(): - * - If the device is blank: - * - Identify & erase a journal block. - * - If the journal block has gone bad: - * - Perform an UpdateBL to move the good bootloader out of the - * way, if needed. - * - Erase the new journal block - * - Write the good BCT to slot 0 of the new journal block. - * - If the journal block is full: - * - Erase block 0 - * - Write 0's to BCT slot 0. - * - Write the good BCT to slot 1. - * - Erase the journal block. - * - Write the good BCT to slot 0 of the journal block. - * - Erase block 0 - * - If updating the BL, do so here. - * - finish_update(): - * - Write the new BCT to the next available of the journal block. - * - Write the new BCT to slot 0 of block 0. - */ - -/* - begin_update(): - * - Test the following conditions in this order: - * - If the device is blank: - * - Identify & erase a journal block. - * - If the journal block has gone bad: - * - Perform an UpdateBL to move the good bootloader out of the - * way, if needed. - * - Erase the new journal block - * - Write the good BCT to slot 0 of the new journal block. - * - If the journal block is full: - * - Erase block 0 - * - Write 0's to BCT slot 0. - * - Write the good BCT to slot 1. - * - Erase the journal block. - * - Write the good BCT to slot 0 of the journal block. - * - Erase block 0 + * Initialization before bct and bootloader update. + * Find the new blank block and erase it. + * + * @param context The main context pointer + * @return 0 for success */ int begin_update(build_image_context *context) { u_int32_t pages_per_bct; u_int32_t pages_per_blk; - u_int32_t bct_size; u_int32_t hash_size; u_int32_t reserved_size; u_int32_t reserved_offset; - u_int32_t current_bct_blk; - int e = 0; + int err = 0; int i; assert(context); @@ -927,65 +751,68 @@ begin_update(build_image_context *context) u_int32_t block_size_log2; u_int32_t page_size_log2; - GET_VALUE(block_size_log2, &block_size_log2); - GET_VALUE(page_size_log2, &page_size_log2); + g_bct_parse_interf->get_value(token_block_size_log2, + &block_size_log2, context->bct); + g_bct_parse_interf->get_value(token_page_size_log2, + &page_size_log2, context->bct); printf("begin_update(): bct data: b=%d p=%d\n", block_size_log2, page_size_log2); } - SET_VALUE(boot_data_version, NVBOOT_BOOTDATA_VERSION(2, 1)); - GET_VALUE(bct_size, &bct_size); - GET_VALUE(hash_size, &hash_size); - GET_VALUE(reserved_size, &reserved_size); - GET_VALUE(reserved_offset, &reserved_offset); + g_bct_parse_interf->set_value(token_boot_data_version, + context->boot_data_version, context->bct); + g_bct_parse_interf->get_value(token_hash_size, + &hash_size, context->bct); + g_bct_parse_interf->get_value(token_reserved_size, + &reserved_size, context->bct); + g_bct_parse_interf->get_value(token_reserved_offset, + &reserved_offset, context->bct); - pages_per_bct = iceil_log2(bct_size, context->page_size_log2); + pages_per_bct = iceil_log2(context->bct_size, context->page_size_log2); pages_per_blk = (1 << (context->block_size_log2 - context->page_size_log2)); /* Initialize the bad block table field. */ - init_bad_block_table(context); + g_bct_parse_interf->init_bad_block_table(context); /* Fill the reserved data w/the padding pattern. */ write_padding(context->bct + reserved_offset, reserved_size); - /* Find the next bct block starting at block 0. */ + /* Find the next bct block starting at block 1. */ for (i = 0; i < context->bct_copy; i++) { - current_bct_blk = find_new_bct_blk(context); - e = erase_block(context, current_bct_blk); - if (e != 0) + find_new_bct_blk(context); + err = erase_block(context, i); + if (err != 0) goto fail; } return 0; fail: - printf("Erase block failed, error: %d.\n", e); - return e; + printf("Erase block failed, error: %d.\n", err); + return err; } - /* - * - finish_update(): - * - Write the new BCT to the next available of the journal block. - * - Write the new BCT to slot 0 of block 0. - * For now, ignore end state. + * Write the new BCT to the next available of the journal block. + * Write the new BCT to slot 0 of block 0. + * + * @param context The main context pointer + * @return 0 for success */ static int finish_update(build_image_context *context) { - u_int32_t current_bct_blk; - int e = 0; + int err = 0; int i; - current_bct_blk = context->next_bct_blk; for (i = 0; i < context->bct_copy; i++) { - e = write_bct(context, --current_bct_blk, 0); - if (e != 0) + err = write_bct(context, i, 0); + if (err != 0) goto fail; } return 0; fail: - printf("Write BCT failed, error: %d.\n", e); - return e; + printf("Write BCT failed, error: %d.\n", err); + return err; } /* @@ -1005,12 +832,16 @@ update_bl(build_image_context *context) return 1; return 0; } + /* * To write the current image: - * - Loop over all blocks in the block data list: - * - Write out the data of real blocks. - * - Write out 0's for unused blocks. - * - Stop on the last used page of the last used block. + * Loop over all blocks in the block data list: + * Write out the data of real blocks. + * Write out 0's for unused blocks. + * Stop on the last used page of the last used block. + * + * @param context The main context pointer + * @return 0 for success */ int write_block_raw(build_image_context *context) diff --git a/data_layout.h b/data_layout.h index 1513183..296c09b 100644 --- a/data_layout.h +++ b/data_layout.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -36,7 +36,6 @@ typedef struct blk_data_rec *blk_data_handle; blk_data_handle new_block_list(void); void destroy_block_list(blk_data_handle); -void destroy_addon_list(struct addon_item_rec *addon_list); int update_bl(struct build_image_context_rec *context); @@ -44,11 +43,11 @@ update_bl(struct build_image_context_rec *context); void update_context(struct build_image_context_rec *context); -void +int read_bct_file(struct build_image_context_rec *context); int -update_addon_item(struct build_image_context_rec *context); +init_bct(struct build_image_context_rec *context); int write_block_raw(struct build_image_context_rec *context); diff --git a/nvaes_ref.h b/nvaes_ref.h index a974845..10ef553 100644 --- a/nvaes_ref.h +++ b/nvaes_ref.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. diff --git a/nvbctlib.h b/nvbctlib.h deleted file mode 100644 index 9138b42..0000000 --- a/nvbctlib.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * nvbctlib is a library for accessing data in BCTs from different versions - * of the BootROM. This provides a means for one utility program to - * reference data which is stored differently by different versions of chips, - * often with the same header file names. - * - * In essence, nvbctlib.h defines an API for selecting chip versions and - * accessing BCT data, and a separate source file wraps the API implementation - * around the header files that are unique to a chip version. - */ - -#ifndef INCLUDED_NVBCTLIB_H -#define INCLUDED_NVBCTLIB_H - -#include <sys/types.h> -/* - * nvbct_lib_id defines tokens used for querying or setting values within, or - * about, the BCT. These are used to identify values within structures, - * sizes and other properties of structures, and values for enumerated - * constants. - */ -typedef enum { - nvbct_lib_id_none = 0, - - nvbct_lib_id_crypto_hash, - nvbct_lib_id_random_aes_blk, - nvbct_lib_id_boot_data_version, - nvbct_lib_id_block_size_log2, - nvbct_lib_id_page_size_log2, - nvbct_lib_id_partition_size, - nvbct_lib_id_dev_type, - nvbct_lib_id_bootloader_used, - nvbct_lib_id_bootloaders_max, - nvbct_lib_id_reserved, - nvbct_lib_id_reserved_size, - nvbct_lib_id_reserved_offset, - nvbct_lib_id_bct_size, - nvbct_lib_id_hash_size, - nvbct_lib_id_crypto_offset, - nvbct_lib_id_crypto_length, - nvbct_lib_id_max_bct_search_blks, - nvbct_lib_id_num_param_sets, - nvbct_lib_id_dev_type_nand, - nvbct_lib_id_dev_type_sdmmc, - nvbct_lib_id_dev_type_spi, - nvbct_lib_id_num_sdram_sets, - - nvbct_lib_id_nand_clock_divider, - nvbct_lib_id_nand_nand_timing, - nvbct_lib_id_nand_nand_timing2, - nvbct_lib_id_nand_block_size_log2, - nvbct_lib_id_nand_page_size_log2, - nvbct_lib_id_sdmmc_clock_divider, - nvbct_lib_id_sdmmc_data_width, - nvbct_lib_id_sdmmc_max_power_class_supported, - nvbct_lib_id_spiflash_read_command_type_fast, - nvbct_lib_id_spiflash_clock_source, - nvbct_lib_id_spiflash_clock_divider, - nvbct_lib_id_sdmmc_data_width_4bit, - nvbct_lib_id_sdmmc_data_width_8bit, - nvbct_lib_id_spi_clock_source_pllp_out0, - nvbct_lib_id_spi_clock_source_pllc_out0, - nvbct_lib_id_spi_clock_source_pllm_out0, - nvbct_lib_id_spi_clock_source_clockm, - - nvbct_lib_id_bl_version, - nvbct_lib_id_bl_start_blk, - nvbct_lib_id_bl_start_page, - nvbct_lib_id_bl_length, - nvbct_lib_id_bl_load_addr, - nvbct_lib_id_bl_entry_point, - nvbct_lib_id_bl_attribute, - nvbct_lib_id_bl_crypto_hash, - - nvbct_lib_id_memory_type_none, - nvbct_lib_id_memory_type_ddr2, - nvbct_lib_id_memory_type_ddr, - nvbct_lib_id_memory_type_lpddr2, - nvbct_lib_id_memory_type_lpddr, - - nvbct_lib_id_sdram_memory_type, - nvbct_lib_id_sdram_pllm_charge_pump_setup_ctrl, - nvbct_lib_id_sdram_pllm_loop_filter_setup_ctrl, - nvbct_lib_id_sdram_pllm_input_divider, - nvbct_lib_id_sdram_pllm_feedback_divider, - nvbct_lib_id_sdram_pllm_post_divider, - nvbct_lib_id_sdram_pllm_stable_time, - nvbct_lib_id_sdram_emc_clock_divider, - nvbct_lib_id_sdram_emc_auto_cal_interval, - nvbct_lib_id_sdram_emc_auto_cal_config, - nvbct_lib_id_sdram_emc_auto_cal_wait, - nvbct_lib_id_sdram_emc_pin_program_wait, - nvbct_lib_id_sdram_emc_rc, - nvbct_lib_id_sdram_emc_rfc, - nvbct_lib_id_sdram_emc_ras, - nvbct_lib_id_sdram_emc_rp, - nvbct_lib_id_sdram_emc_r2w, - nvbct_lib_id_sdram_emc_w2r, - nvbct_lib_id_sdram_emc_r2p, - nvbct_lib_id_sdram_emc_w2p, - nvbct_lib_id_sdram_emc_rd_rcd, - nvbct_lib_id_sdram_emc_wr_rcd, - nvbct_lib_id_sdram_emc_rrd, - nvbct_lib_id_sdram_emc_rext, - nvbct_lib_id_sdram_emc_wdv, - nvbct_lib_id_sdram_emc_quse, - nvbct_lib_id_sdram_emc_qrst, - nvbct_lib_id_sdram_emc_qsafe, - nvbct_lib_id_sdram_emc_rdv, - nvbct_lib_id_sdram_emc_refresh, - nvbct_lib_id_sdram_emc_burst_refresh_num, - nvbct_lib_id_sdram_emc_pdex2wr, - nvbct_lib_id_sdram_emc_pdex2rd, - nvbct_lib_id_sdram_emc_pchg2pden, - nvbct_lib_id_sdram_emc_act2pden, - nvbct_lib_id_sdram_emc_ar2pden, - nvbct_lib_id_sdram_emc_rw2pden, - nvbct_lib_id_sdram_emc_txsr, - nvbct_lib_id_sdram_emc_tcke, - nvbct_lib_id_sdram_emc_tfaw, - nvbct_lib_id_sdram_emc_trpab, - nvbct_lib_id_sdram_emc_tclkstable, - nvbct_lib_id_sdram_emc_tclkstop, - nvbct_lib_id_sdram_emc_trefbw, - nvbct_lib_id_sdram_emc_quse_extra, - nvbct_lib_id_sdram_emc_fbio_cfg1, - nvbct_lib_id_sdram_emc_fbio_dqsib_dly, - nvbct_lib_id_sdram_emc_fbio_dqsib_dly_msb, - nvbct_lib_id_sdram_emc_fbio_quse_dly, - nvbct_lib_id_sdram_emc_fbio_quse_dly_msb, - nvbct_lib_id_sdram_emc_fbio_cfg5, - nvbct_lib_id_sdram_emc_fbio_cfg6, - nvbct_lib_id_sdram_emc_fbio_spare, - nvbct_lib_id_sdram_emc_mrs, - nvbct_lib_id_sdram_emc_emrs, - nvbct_lib_id_sdram_emc_mrw1, - nvbct_lib_id_sdram_emc_mrw2, - nvbct_lib_id_sdram_emc_mrw3, - nvbct_lib_id_sdram_emc_mrw_reset_command, - nvbct_lib_id_sdram_emc_mrw_reset_ninit_wait, - nvbct_lib_id_sdram_emc_adr_cfg, - nvbct_lib_id_sdram_emc_adr_cfg1, - nvbct_lib_id_sdram_mc_emem_Cfg, - nvbct_lib_id_sdram_mc_lowlatency_config, - nvbct_lib_id_sdram_emc_cfg, - nvbct_lib_id_sdram_emc_cfg2, - nvbct_lib_id_sdram_emc_dbg, - nvbct_lib_id_sdram_ahb_arbitration_xbar_ctrl, - nvbct_lib_id_sdram_emc_cfg_dig_dll, - nvbct_lib_id_sdram_emc_dll_xform_dqs, - nvbct_lib_id_sdram_emc_dll_xform_quse, - nvbct_lib_id_sdram_warm_boot_wait, - nvbct_lib_id_sdram_emc_ctt_term_ctrl, - nvbct_lib_id_sdram_emc_odt_write, - nvbct_lib_id_sdram_emc_odt_read, - nvbct_lib_id_sdram_emc_zcal_ref_cnt, - nvbct_lib_id_sdram_emc_zcal_wait_cnt, - nvbct_lib_id_sdram_emc_zcal_mrw_cmd, - nvbct_lib_id_sdram_emc_mrs_reset_dll, - nvbct_lib_id_sdram_emc_mrw_zq_init_dev0, - nvbct_lib_id_sdram_emc_mrw_zq_init_dev1, - nvbct_lib_id_sdram_emc_mrw_zq_init_wait, - nvbct_lib_id_sdram_emc_mrs_reset_dll_wait, - nvbct_lib_id_sdram_emc_emrs_emr2, - nvbct_lib_id_sdram_emc_emrs_emr3, - nvbct_lib_id_sdram_emc_emrs_ddr2_dll_enable, - nvbct_lib_id_sdram_emc_mrs_ddr2_dll_reset, - nvbct_lib_id_sdram_emc_emrs_ddr2_ocd_calib, - nvbct_lib_id_sdram_emc_ddr2_wait, - nvbct_lib_id_sdram_emc_cfg_clktrim0, - nvbct_lib_id_sdram_emc_cfg_clktrim1, - nvbct_lib_id_sdram_emc_cfg_clktrim2, - nvbct_lib_id_sdram_pmc_ddr_pwr, - nvbct_lib_id_sdram_apb_misc_gp_xm2cfga_pad_ctrl, - nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl, - nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl2, - nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl, - nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl2, - nvbct_lib_id_sdram_apb_misc_gp_xm2clkcfg_Pad_ctrl, - nvbct_lib_id_sdram_apb_misc_gp_xm2comp_pad_ctrl, - nvbct_lib_id_sdram_apb_misc_gp_xm2vttgen_pad_ctrl, - - nvbct_lib_id_max, - - nvbct_lib_id_force32 = 0x7fffffff - -} nvbct_lib_id; - -typedef int (*nvbct_lib_get_dev_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct); -typedef int (*nvbct_lib_set_dev_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t data, - u_int8_t *bct); - -typedef int (*nvbct_lib_get_sdram_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct); -typedef int (*nvbct_lib_set_sdram_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t data, - u_int8_t *bct); - -typedef int (*nvbct_lib_get_bl_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct); -typedef int (*nvbct_lib_set_bl_param)(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct); - -typedef int (*nvbct_lib_get_value)(nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct); -typedef int (*nvbct_lib_set_value)(nvbct_lib_id id, - u_int32_t data, - u_int8_t *bct); - -/* - * Note: On input, *length is the size of data. On output, *length is the - * actual size used. - */ -typedef int (*nvbct_lib_get_data)(nvbct_lib_id id, - u_int8_t *data, - u_int32_t *length, - u_int8_t *bct); -typedef int (*nvbct_lib_set_data)(nvbct_lib_id id, - u_int8_t *data, - u_int32_t length, - u_int8_t *bct); - -/* - * Structure of function pointers used to access a specific BCT variant. - */ -typedef struct nvbct_lib_fns_rec -{ - nvbct_lib_get_value get_value; - nvbct_lib_set_value set_value; - - nvbct_lib_get_data get_data; - nvbct_lib_set_data set_data; - - nvbct_lib_get_bl_param getbl_param; - nvbct_lib_set_bl_param setbl_param; - - nvbct_lib_get_dev_param getdev_param; - nvbct_lib_set_dev_param setdev_param; - - nvbct_lib_get_sdram_param get_sdram_params; - nvbct_lib_set_sdram_param set_sdram_params; -} nvbct_lib_fns; - -void nvbct_lib_get_fns(nvbct_lib_fns *fns); - -#endif /* #ifndef INCLUDED_NVBCTLIB_H */ diff --git a/nvboot_sdram_param.h b/nvboot_sdram_param.h deleted file mode 100644 index 03f2762..0000000 --- a/nvboot_sdram_param.h +++ /dev/null @@ -1,328 +0,0 @@ -/** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. - */ - -#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H -#define INCLUDED_NVBOOT_SDRAM_PARAM_H - -#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 - -typedef enum -{ - /// Specifies the memory type to be undefined - nvboot_memory_type_none = 0, - - /// Specifies the memory type to be DDR SDRAM - nvboot_memory_type_ddr, - - /// Specifies the memory type to be LPDDR SDRAM - nvboot_memory_type_lpddr, - - /// Specifies the memory type to be DDR2 SDRAM - nvboot_memory_type_ddr2, - - /// Specifies the memory type to be LPDDR2 SDRAM - nvboot_memory_type_lpddr2, - - nvboot_memory_type_num, - nvboot_memory_type_force32 = 0x7FFFFFF -} nvboot_memory_type; - - -/** - * Defines the SDRAM parameter structure - */ -typedef struct nvboot_sdram_params_rec -{ - /// Specifies the type of memory device - nvboot_memory_type memory_type; - - /// Specifies the CPCON value for PllM - u_int32_t pllm_charge_pump_setup_ctrl; - /// Specifies the LPCON value for PllM - u_int32_t pllm_loop_filter_setup_ctrl; - /// Specifies the M value for PllM - u_int32_t pllm_input_divider; - /// Specifies the N value for PllM - u_int32_t pllm_feedback_divider; - /// Specifies the P value for PllM - u_int32_t pllm_post_divider; - /// Specifies the time to wait for PLLM to lock (in microseconds) - u_int32_t pllm_stable_time; - - /// Specifies the divider for the EMC Clock Source - u_int32_t emc_clock_divider; - - /// - /// Auto-calibration of EMC pads - /// - /// Specifies the value for EMC_AUTO_CAL_INTERVAL - u_int32_t emc_auto_cal_interval; - /// Specifies the value for EMC_AUTO_CAL_CONFIG - /// Note: Trigger bits are set by the SDRAM code. - u_int32_t emc_auto_cal_config; - /// Specifies the time for the calibration to - /// stabilize (in microseconds) - u_int32_t emc_auto_cal_wait; - - /// Specifies the time to wait after pin programming (in microseconds) - /// Dram vendors require at least 200us. - u_int32_t emc_pin_program_wait; - - /// - /// Timing parameters required for the SDRAM - /// - /// Specifies the value for EMC_RC - u_int32_t emc_rc; - /// Specifies the value for EMC_RFC - u_int32_t emc_rfc; - /// Specifies the value for EMC_RAS - u_int32_t emc_ras; - /// Specifies the value for EMC_RP - u_int32_t emc_rp; - /// Specifies the value for EMC_R2W - u_int32_t emc_r2w; - /// Specifies the value for EMC_R2W - u_int32_t emc_w2r; - /// Specifies the value for EMC_R2P - u_int32_t emc_r2p; - /// Specifies the value for EMC_W2P - u_int32_t emc_w2p; - /// Specifies the value for EMC_RD_RCD - u_int32_t emc_rd_rcd; - /// Specifies the value for EMC_WR_RCD - u_int32_t emc_wr_rcd; - /// Specifies the value for EMC_RRD - u_int32_t emc_rrd; - /// Specifies the value for EMC_REXT - u_int32_t emc_rext; - /// Specifies the value for EMC_WDV - u_int32_t emc_wdv; - /// Specifies the value for EMC_QUSE - u_int32_t emc_quse; - /// Specifies the value for EMC_QRST - u_int32_t emc_qrst; - /// Specifies the value for EMC_QSAFE - u_int32_t emc_qsafe; - /// Specifies the value for EMC_RDV - u_int32_t emc_rdv; - /// Specifies the value for EMC_REFRESH - u_int32_t emc_refresh; - /// Specifies the value for EMC_BURST_REFRESH_NUM - u_int32_t emc_burst_refresh_num; - /// Specifies the value for EMC_PDEX2WR - u_int32_t emc_pdex2wr; - /// Specifies the value for EMC_PDEX2RD - u_int32_t emc_pdex2rd; - /// Specifies the value for EMC_PCHG2PDEN - u_int32_t emc_pchg2pden; - /// Specifies the value for EMC_ACT2PDEN - u_int32_t emc_act2pden; - /// Specifies the value for EMC_AR2PDEN - u_int32_t emc_ar2pden; - /// Specifies the value for EMC_RW2PDEN - u_int32_t emc_rw2pden; - /// Specifies the value for EMC_TXSR - u_int32_t emc_txsr; - /// Specifies the value for EMC_TCKE - u_int32_t emc_tcke; - /// Specifies the value for EMC_TFAW - u_int32_t emc_tfaw; - /// Specifies the value for EMC_TRPAB - u_int32_t emc_trpab; - /// Specifies the value for EMC_TCLKSTABLE - u_int32_t emc_tclkstable; - /// Specifies the value for EMC_TCLKSTOP - u_int32_t emc_tclkstop; - /// Specifies the value for EMC_TREFBW - u_int32_t emc_trefbw; - /// Specifies the value for EMC_QUSE_EXTRA - u_int32_t emc_quse_extra; - - /// - /// FBIO configuration values - /// - /// Specifies the value for EMC_FBIO_CFG1 - u_int32_t emc_fbio_cfg1; - /// Specifies the value for EMC_FBIO_DQSIB_DLY - u_int32_t emc_fbio_dqsib_dly; - /// Specifies the value for EMC_FBIO_DQSIB_DLY_MSB - u_int32_t emc_fbio_dqsib_dly_msb; - /// Specifies the value for EMC_FBIO_QUSE_DLY - u_int32_t emc_fbio_quse_dly; - /// Specifies the value for EMC_FBIO_QUSE_DLY_MSB - u_int32_t emc_fbio_quse_dly_msb; - /// Specifies the value for EMC_FBIO_CFG5 - u_int32_t emc_fbio_cfg5; - /// Specifies the value for EMC_FBIO_CFG6 - u_int32_t emc_fbio_cfg6; - /// Specifies the value for EMC_FBIO_SPARE - u_int32_t emc_fbio_spare; - - /// - /// MRS command values - /// - /// Specifies the value for EMC_MRS - u_int32_t emc_mrs; - /// Specifies the value for EMC_EMRS - u_int32_t emc_emrs; - /// Specifies the first of a sequence of three values for EMC_MRW - u_int32_t emc_mrw1; - /// Specifies the second of a sequence of three values for EMC_MRW - u_int32_t emc_mrw2; - /// Specifies the third of a sequence of three values for EMC_MRW - u_int32_t emc_mrw3; - - /// Specifies the EMC_MRW reset command value - u_int32_t emc_mrw_reset_command; - /// Specifies the EMC Reset wait time (in microseconds) - u_int32_t emc_mrw_reset_ninit_wait; - - /// Specifies the value for EMC_ADR_CFG - /// The same value is also used for MC_EMC_ADR_CFG - u_int32_t emc_adr_cfg; - /// Specifies the value for EMC_ADR_CFG_1 - u_int32_t emc_adr_cfg1; - - /// Specifies the value for MC_EMEM_CFG which holds the external memory - /// size (in KBytes) - /// EMEM_SIZE_KB must be <= (Device size in KB * Number of Devices) - u_int32_t mc_emem_Cfg; - - /// Specifies the value for MC_LOWLATENCY_CONFIG - /// Mainly for LL_DRAM_INTERLEAVE: Some DRAMs do not support interleave - /// mode. If so, turn off this bit to get the correct low-latency path - /// behavior. Reset is ENABLED. - u_int32_t mc_lowlatency_config; - /// Specifies the value for EMC_CFG - u_int32_t emc_cfg; - /// Specifies the value for EMC_CFG_2 - u_int32_t emc_cfg2; - /// Specifies the value for EMC_DBG - u_int32_t emc_dbg; - - /// Specifies the value for AHB_ARBITRATION_XBAR_CTRL. - /// This is used to set the Memory Inid done - u_int32_t ahb_arbitration_xbar_ctrl; - - /// Specifies the value for EMC_CFG_DIG_DLL - /// Note: Trigger bits are set by the SDRAM code. - u_int32_t emc_cfg_dig_dll; - /// Specifies the value for EMC_DLL_XFORM_DQS - u_int32_t emc_dll_xform_dqs; - /// Specifies the value for EMC_DLL_XFORM_QUSE - u_int32_t emc_dll_xform_quse; - - /// Specifies the delay after prgramming the PIN/NOP register during a - /// WarmBoot0 sequence (in microseconds) - u_int32_t warm_boot_wait; - - /// Specifies the value for EMC_CTT_TERM_CTRL - u_int32_t emc_ctt_term_ctrl; - - /// Specifies the value for EMC_ODT_WRITE - u_int32_t emc_odt_write; - /// Specifies the value for EMC_ODT_WRITE - u_int32_t emc_odt_read; - - /// Specifies the value for EMC_ZCAL_REF_CNT - /// Only meaningful for LPDDR2. Set to 0 for all other memory types. - u_int32_t emc_zcal_ref_cnt; - /// Specifies the value for EMC_ZCAL_WAIT_CNT - /// Only meaningful for LPDDR2. Set to 0 for all other memory types. - u_int32_t emc_zcal_wait_cnt; - /// Specifies the value for EMC_ZCAL_MRW_CMD - /// Only meaningful for LPDDR2. Set to 0 for all other memory types. - u_int32_t emc_zcal_mrw_cmd; - - /// Specifies the MRS command value for initilizing the mode register. - u_int32_t emc_mrs_reset_dll; - /// Specifies the MRW command for ZQ initialization of device 0 - u_int32_t emc_mrw_zq_init_dev0; - /// Specifies the MRW command for ZQ initialization of device 1 - u_int32_t emc_mrw_zq_init_dev1; - /// Specifies the wait time after programming a ZQ initialization - /// command (in microseconds) - u_int32_t emc_mrw_zq_init_wait; - /// Specifies the wait time after sending an MRS DLL reset command - /// (in microseconds) - u_int32_t emc_mrs_reset_dll_wait; - /// Specifies the first of two EMRS commands to initialize mode - /// registers - u_int32_t emc_emrs_emr2; - /// Specifies the second of two EMRS commands to initialize mode - /// registers - u_int32_t emc_emrs_emr3; - /// Specifies the EMRS command to enable the DDR2 DLL - u_int32_t emc_emrs_ddr2_dll_enable; - /// Specifies the MRS command to reset the DDR2 DLL - u_int32_t emc_mrs_ddr2_dll_reset; - /// Specifies the EMRS command to set OCD calibration - u_int32_t emc_emrs_ddr2_ocd_calib; - /// Specifies the wait between initializing DDR and setting OCD - /// calibration (in microseconds) - u_int32_t emc_ddr2_wait; - - /// - /// Clock trimmers - /// - /// Specifies the value for EMC_CFG_CLKTRIM_0 - u_int32_t emc_cfg_clktrim0; - /// Specifies the value for EMC_CFG_CLKTRIM_1 - u_int32_t emc_cfg_clktrim1; - /// Specifies the value for EMC_CFG_CLKTRIM_2 - u_int32_t emc_cfg_clktrim2; - - /// - /// Pad controls - /// - /// Specifies the value for PMC_DDR_PWR - u_int32_t pmc_ddr_pwr; - /// Specifies the value for APB_MISC_GP_XM2CFGAPADCTRL - u_int32_t apb_misc_gp_xm2cfga_pad_ctrl; - /// Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL - u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl; - /// Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL2 - u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl2; - /// Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL - u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl; - /// Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL2 - u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl2; - /// Specifies the value for APB_MISC_GP_XM2CLKCFGPADCTRL - u_int32_t apb_misc_gp_xm2clkcfg_Pad_ctrl; - /// Specifies the value for APB_MISC_GP_XM2COMPPADCTRL - u_int32_t apb_misc_gp_xm2comp_pad_ctrl; - /// Specifies the value for APB_MISC_GP_XM2VTTGENPADCTRL - u_int32_t apb_misc_gp_xm2vttgen_pad_ctrl; - - /// Specifies storage for arbitration configuration registers - /// Data passed through to the Bootloader but not used by the Boot ROM - u_int32_t arbitration_config[NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS]; -} nvboot_sdram_params; - -#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H */ - @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -24,17 +24,7 @@ * parse.c - Parsing support for the cbootimage tool */ -/* - * TODO / Notes - * - Add doxygen commentary - * - Do we have endian issues to deal with? - * - Add support for device configuration data - * - Add support for bad blocks - * - Add support for different allocation modes/strategies - * - Add support for multiple BCTs in journal block - * - Add support for other missing features. - */ - +#include <ctype.h> #include "parse.h" #include "cbootimage.h" #include "data_layout.h" @@ -51,11 +41,16 @@ * A SetXXX() function may not call any parseing functions. */ -static char *parse_u32(char *statement, u_int32_t *val); -static char *parse_u8(char *statement, u_int32_t *val); -static char *parse_filename(char *statement, char *name, int chars_remaining); +static int +set_array(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); +static char *parse_u32(char *str, u_int32_t *val); +static char *parse_u8(char *str, u_int32_t *val); +static char *parse_filename(char *str, char *name, int chars_remaining); static char *parse_enum(build_image_context *context, - char *statement, + char *str, enum_item *table, u_int32_t *val); static char @@ -73,269 +68,28 @@ static int parse_value_u32(build_image_context *context, parse_token token, char *rest); static int parse_bct_file(build_image_context *context, parse_token token, char *rest); -static int -parse_addon(build_image_context *context, parse_token token, char *rest); -static char *parse_string(char *statement, char *uname, int chars_remaining); static char -*parse_end_state(char *statement, char *uname, int chars_remaining); +*parse_end_state(char *str, char *uname, int chars_remaining); static int parse_dev_param(build_image_context *context, parse_token token, char *rest); static int parse_sdram_param(build_image_context *context, parse_token token, char *rest); -static int process_statement(build_image_context *context, char *statement); - -enum_item s_devtype_table[] = -{ - { "NvBootDevType_Sdmmc", nvbct_lib_id_dev_type_sdmmc }, - { "NvBootDevType_Spi", nvbct_lib_id_dev_type_spi }, - { "NvBootDevType_Nand", nvbct_lib_id_dev_type_nand }, - { "Sdmmc", nvbct_lib_id_dev_type_sdmmc }, - { "Spi", nvbct_lib_id_dev_type_spi }, - { "Nand", nvbct_lib_id_dev_type_nand }, - - { NULL, 0 } -}; - -enum_item s_sdmmc_data_width_table[] = -{ - { - "NvBootSdmmcDataWidth_4Bit", - nvbct_lib_id_sdmmc_data_width_4bit - }, - { - "NvBootSdmmcDataWidth_8Bit", - nvbct_lib_id_sdmmc_data_width_8bit - }, - { "4Bit", nvbct_lib_id_sdmmc_data_width_4bit }, - { "8Bit", nvbct_lib_id_sdmmc_data_width_8bit }, - { NULL, 0 } -}; - -enum_item s_spi_clock_source_table[] = -{ - { - "NvBootSpiClockSource_PllPOut0", - nvbct_lib_id_spi_clock_source_pllp_out0 - }, - { - "NvBootSpiClockSource_PllCOut0", - nvbct_lib_id_spi_clock_source_pllc_out0 - }, - { - "NvBootSpiClockSource_PllMOut0", - nvbct_lib_id_spi_clock_source_pllm_out0 - }, - { - "NvBootSpiClockSource_ClockM", - nvbct_lib_id_spi_clock_source_clockm - }, - - { "ClockSource_PllPOut0", nvbct_lib_id_spi_clock_source_pllp_out0 }, - { "ClockSource_PllCOut0", nvbct_lib_id_spi_clock_source_pllc_out0 }, - { "ClockSource_PllMOut0", nvbct_lib_id_spi_clock_source_pllm_out0 }, - { "ClockSource_ClockM", nvbct_lib_id_spi_clock_source_clockm }, - - - { "PllPOut0", nvbct_lib_id_spi_clock_source_pllp_out0 }, - { "PllCOut0", nvbct_lib_id_spi_clock_source_pllc_out0 }, - { "PllMOut0", nvbct_lib_id_spi_clock_source_pllm_out0 }, - { "ClockM", nvbct_lib_id_spi_clock_source_clockm }, - - { NULL, 0 } -}; - -enum_item s_nvboot_memory_type_table[] = -{ - { "NvBootMemoryType_None", nvbct_lib_id_memory_type_none }, - { "NvBootMemoryType_Ddr2", nvbct_lib_id_memory_type_ddr2 }, - { "NvBootMemoryType_Ddr", nvbct_lib_id_memory_type_ddr }, - { "NvBootMemoryType_LpDdr2", nvbct_lib_id_memory_type_lpddr2 }, - { "NvBootMemoryType_LpDdr", nvbct_lib_id_memory_type_lpddr }, - - { "None", nvbct_lib_id_memory_type_none }, - { "Ddr2", nvbct_lib_id_memory_type_ddr2 }, - { "Ddr", nvbct_lib_id_memory_type_ddr }, - { "LpDdr2", nvbct_lib_id_memory_type_lpddr2 }, - { "LpDdr", nvbct_lib_id_memory_type_lpddr }, - - { NULL, 0 } -}; - -#define TOKEN(name) \ - token_##name, nvbct_lib_id_sdram_##name, field_type_u32, NULL - -field_item s_sdram_field_table[] = -{ - { "MemoryType", token_memory_type, nvbct_lib_id_sdram_memory_type, - field_type_enum, s_nvboot_memory_type_table }, - - { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, - { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, - { "PllMInputDivider", TOKEN(pllm_input_divider) }, - { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, - { "PllMPostDivider", TOKEN(pllm_post_divider) }, - { "PllMStableTime", TOKEN(pllm_stable_time) }, - { "EmcClockDivider", TOKEN(emc_clock_divider) }, - { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, - { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, - { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, - { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, - { "EmcRc", TOKEN(emc_rc) }, - { "EmcRfc", TOKEN(emc_rfc) }, - { "EmcRas", TOKEN(emc_ras) }, - { "EmcRp", TOKEN(emc_rp) }, - { "EmcR2w", TOKEN(emc_r2w) }, - { "EmcW2r", TOKEN(emc_w2r) }, - { "EmcR2p", TOKEN(emc_r2p) }, - { "EmcW2p", TOKEN(emc_w2p) }, - { "EmcRrd", TOKEN(emc_rrd) }, - { "EmcRdRcd", TOKEN(emc_rd_rcd) }, - { "EmcWrRcd", TOKEN(emc_wr_rcd) }, - { "EmcRext", TOKEN(emc_rext) }, - { "EmcWdv", TOKEN(emc_wdv) }, - { "EmcQUseExtra", TOKEN(emc_quse_extra) }, - { "EmcQUse", TOKEN(emc_quse) }, - { "EmcQRst", TOKEN(emc_qrst) }, - { "EmcQSafe", TOKEN(emc_qsafe) }, - { "EmcRdv", TOKEN(emc_rdv) }, - { "EmcRefresh", TOKEN(emc_refresh) }, - { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, - { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, - { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, - { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, - { "EmcAct2Pden", TOKEN(emc_act2pden) }, - { "EmcAr2Pden", TOKEN(emc_ar2pden) }, - { "EmcRw2Pden", TOKEN(emc_rw2pden) }, - { "EmcTxsr", TOKEN(emc_txsr) }, - { "EmcTcke", TOKEN(emc_tcke) }, - { "EmcTfaw", TOKEN(emc_tfaw) }, - { "EmcTrpab", TOKEN(emc_trpab) }, - { "EmcTClkStable", TOKEN(emc_tclkstable) }, - { "EmcTClkStop", TOKEN(emc_tclkstop) }, - { "EmcTRefBw", TOKEN(emc_trefbw) }, - { "EmcFbioCfg1", TOKEN(emc_fbio_cfg1) }, - { "EmcFbioDqsibDlyMsb", TOKEN(emc_fbio_dqsib_dly_msb) }, - { "EmcFbioDqsibDly", TOKEN(emc_fbio_dqsib_dly) }, - { "EmcFbioQuseDlyMsb", TOKEN(emc_fbio_quse_dly_msb) }, - { "EmcFbioQuseDly", TOKEN(emc_fbio_quse_dly) }, - { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, - { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, - { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, - { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, - { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, - { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, - { "EmcMrs", TOKEN(emc_mrs) }, - { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, - { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, - { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, - { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, - { "EmcEmrs", TOKEN(emc_emrs) }, - { "EmcMrw1", TOKEN(emc_mrw1) }, - { "EmcMrw2", TOKEN(emc_mrw2) }, - { "EmcMrw3", TOKEN(emc_mrw3) }, - { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, - { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, - { "EmcAdrCfg1", TOKEN(emc_adr_cfg1) }, - { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, - { "McEmemCfg", TOKEN(mc_emem_Cfg) }, - { "McLowLatencyConfig", TOKEN(mc_lowlatency_config) }, - { "EmcCfg2", TOKEN(emc_cfg2) }, - { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, - { "EmcCfgClktrim0", TOKEN(emc_cfg_clktrim0) }, - { "EmcCfgClktrim1", TOKEN(emc_cfg_clktrim1) }, - { "EmcCfgClktrim2", TOKEN(emc_cfg_clktrim2) }, - { "EmcCfg", TOKEN(emc_cfg) }, - { "EmcDbg", TOKEN(emc_dbg) }, - { "AhbArbitrationXbarCtrl", TOKEN(ahb_arbitration_xbar_ctrl) }, - { "EmcDllXformDqs", TOKEN(emc_dll_xform_dqs) }, - { "EmcDllXformQUse", TOKEN(emc_dll_xform_quse) }, - { "WarmBootWait", TOKEN(warm_boot_wait) }, - { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, - { "EmcOdtWrite", TOKEN(emc_odt_write) }, - { "EmcOdtRead", TOKEN(emc_odt_read) }, - { "EmcZcalRefCnt", TOKEN(emc_zcal_ref_cnt) }, - { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, - { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, - { "EmcMrwZqInitDev0", TOKEN(emc_mrw_zq_init_dev0) }, - { "EmcMrwZqInitDev1", TOKEN(emc_mrw_zq_init_dev1) }, - { "EmcMrwZqInitWait", TOKEN(emc_mrw_zq_init_wait) }, - { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, - { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, - { "ApbMiscGpXm2CfgAPadCtrl", TOKEN(apb_misc_gp_xm2cfga_pad_ctrl) }, - { "ApbMiscGpXm2CfgCPadCtrl2", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl2) }, - { "ApbMiscGpXm2CfgCPadCtrl", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl) }, - { "ApbMiscGpXm2CfgDPadCtrl2", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl2) }, - { "ApbMiscGpXm2CfgDPadCtrl", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl) }, - { "ApbMiscGpXm2ClkCfgPadCtrl", TOKEN(apb_misc_gp_xm2clkcfg_Pad_ctrl)}, - { "ApbMiscGpXm2CompPadCtrl", TOKEN(apb_misc_gp_xm2comp_pad_ctrl) }, - { "ApbMiscGpXm2VttGenPadCtrl", TOKEN(apb_misc_gp_xm2vttgen_pad_ctrl)}, - { NULL, 0, 0, 0, NULL } -}; - -#undef TOKEN -#define TOKEN(name) \ - token_##name, nvbct_lib_id_nand_##name, field_type_u32, NULL +static int process_statement(build_image_context *context, + char *str, + u_int8_t simple_parse); -field_item s_nand_table[] = +static parse_item parse_simple_items[] = { - { "ClockDivider", TOKEN(clock_divider) }, - /* Note: NandTiming2 must appear before NandTiming, because NandTiming - * is a prefix of NandTiming2 and would otherwise match first. - */ - { "NandTiming2", TOKEN(nand_timing2) }, - { "NandTiming", TOKEN(nand_timing) }, - { "BlockSizeLog2", TOKEN(block_size_log2) }, - { "PageSizeLog2", TOKEN(page_size_log2) }, - { NULL, 0, 0, 0, NULL } -}; - -#undef TOKEN -#define TOKEN(name) \ - token_##name, nvbct_lib_id_sdmmc_##name, field_type_u32, NULL - -field_item s_sdmmc_table[] = -{ - { "ClockDivider", TOKEN(clock_divider) }, - { "DataWidth", - token_data_width, - nvbct_lib_id_sdmmc_data_width, - field_type_enum, - s_sdmmc_data_width_table }, - { "MaxPowerClassSupported", TOKEN(max_power_class_supported) }, - { NULL, 0, 0, 0, NULL } -}; - -#undef TOKEN -#define TOKEN(name) \ - token_##name, nvbct_lib_id_spiflash_##name, field_type_u8, NULL - -field_item s_spiflash_table[] = -{ - { "ReadCommandTypeFast", TOKEN(read_command_type_fast) }, - { "ClockDivider", TOKEN(clock_divider) }, - { "ClockSource", - token_clock_source, - nvbct_lib_id_spiflash_clock_source, - field_type_enum, - s_spi_clock_source_table }, - { NULL, 0, 0, 0, NULL } -}; - -static parse_subfield_item s_device_type_table[] = -{ - { "NandParams.", token_nand_params, - s_nand_table, set_nand_param }, - { "SdmmcParams.", token_sdmmc_params, - s_sdmmc_table, set_sdmmc_param }, - { "SpiFlashParams.", token_spiflash_params, - s_spiflash_table, set_spiflash_param }, - - { NULL, 0, NULL } + { "Bctfile=", token_bct_file, parse_bct_file }, + { "BootLoader=", token_bootloader, parse_bootloader }, + { "Redundancy=", token_redundancy, parse_value_u32 }, + { "Bctcopy=", token_bct_copy, parse_value_u32 }, + { "Version=", token_version, parse_value_u32 }, + { NULL, 0, NULL } /* Must be last */ }; -static parse_item s_top_level_items[] = -{ +static parse_item s_top_level_items[] = { { "Bctfile=", token_bct_file, parse_bct_file }, { "Attribute=", token_attribute, parse_value_u32 }, { "Attribute[", token_attribute, parse_array }, @@ -349,56 +103,59 @@ static parse_item s_top_level_items[] = { "Redundancy=", token_redundancy, parse_value_u32 }, { "Bctcopy=", token_bct_copy, parse_value_u32 }, { "Version=", token_version, parse_value_u32 }, - { "AddOn[", token_addon, parse_addon }, { NULL, 0, NULL } /* Must be last */ }; /* Macro to simplify parser code a bit. */ #define PARSE_COMMA(x) if (*rest != ',') return (x); rest++ -/* This parsing code was initially borrowed from nvcamera_config_parse.c. */ -/* Returns the address of the character after the parsed data. */ +/* + * Parse the given string and find the u32 dec/hex number. + * + * @param str String to parse + * @param val Returns value that was parsed + * @return the remainder of the string after the number was parsed + */ static char * -parse_u32(char *statement, u_int32_t *val) +parse_u32(char *str, u_int32_t *val) { u_int32_t value = 0; + u_int32_t digit; - while (*statement=='0') { - statement++; - } + while (*str == '0') + str++; - if (*statement=='x' || *statement=='X') { - statement++; - while (((*statement >= '0') && (*statement <= '9')) || - ((*statement >= 'a') && (*statement <= 'f')) || - ((*statement >= 'A') && (*statement <= 'F'))) { + if (tolower(*str) == 'x') { + str++; + while (isxdigit(*str)) { value *= 16; - if ((*statement >= '0') && (*statement <= '9')) { - value += (*statement - '0'); - } else if ((*statement >= 'A') && - (*statement <= 'F')) { - value += ((*statement - 'A')+10); - } else { - value += ((*statement - 'a')+10); - } - statement++; + digit = tolower(*str); + value += digit <= '9' ? digit - '0' : digit - 'a' + 10; + str++; } } else { - while (*statement >= '0' && *statement <= '9') { - value = value*10 + (*statement - '0'); - statement++; + while (*str >= '0' && *str <= '9') { + value = value*10 + (*str - '0'); + str++; } } *val = value; - return statement; + return str; } -char * -parse_u8(char *statement, u_int32_t *val) +/* + * Parse the given string and find the u8 dec/hex number. + * + * @param str String to parse + * @param val Returns value that was parsed + * @return the remainder of the string after the number was parsed + */ +static char * +parse_u8(char *str, u_int32_t *val) { char *retval; - retval = parse_u32(statement, val); + retval = parse_u32(str, val); if (*val > 0xff) { printf("Warning: Parsed 8-bit value that exceeded 8-bits.\n"); @@ -410,38 +167,46 @@ parse_u8(char *statement, u_int32_t *val) } -/* This parsing code was initially borrowed from nvcamera_config_parse.c. */ -/* Returns the address of the character after the parsed data. */ +/* + * Parse the given string and find the file name then + * return the rest of the string. + * + * @param str String to parse + * @param name Returns the filename that was parsed + * @param chars_remaining The maximum length of filename + * @return the remainder of the string after the name was parsed + */ static char * -parse_filename(char *statement, char *name, int chars_remaining) +parse_filename(char *str, char *name, int chars_remaining) { - while (((*statement >= '0') && (*statement <= '9')) || - ((*statement >= 'a') && (*statement <= 'z')) || - ((*statement >= 'A') && (*statement <= 'Z')) || - (*statement == '\\') || - (*statement == '/' ) || - (*statement == '~' ) || - (*statement == '_' ) || - (*statement == '-' ) || - (*statement == '+' ) || - (*statement == ':' ) || - (*statement == '.' )) { - /* Check if the filename buffer is out of space, preserving one - * character to null terminate the string. - */ + /* + * Check if the filename buffer is out of space, preserving one + * character to null terminate the string. + */ + while (isalnum(*str) || strchr("\\/~_-+:.", *str)) { + chars_remaining--; if (chars_remaining < 1) return NULL; - *name++ = *statement++; + *name++ = *str++; } /* Null terminate the filename. */ *name = '\0'; - return statement; + return str; } +/* + * Parse the given string and find the match field name listed + * in field table. + * + * @param rest String to parse + * @param field_table The field table to parse + * @param field Returns the field item that was parsed + * @return NULL or the remainder of the string after the field item was parsed + */ static char *parse_field_name(char *rest, field_item *field_table, field_item **field) { @@ -452,7 +217,7 @@ static char assert(rest != NULL); assert(field != NULL); - while(*(rest + field_name_len) != '=') + while (rest[field_name_len] != '=') field_name_len++; /* Parse the field name. */ @@ -472,8 +237,17 @@ static char return NULL; } +/* + * Parse the value based on the field table + * + * @param context The main context pointer + * @param rest String to parse + * @param field Field item to parse + * @param value Returns the value that was parsed + * @return the remainder of the string after the value was parsed + */ static char -*parse_field_value(build_image_context *context, +*parse_field_value(build_image_context *context, char *rest, field_item *field, u_int32_t *value) @@ -506,38 +280,45 @@ static char return rest; } +/* + * Parse the given string and find the match enum item listed + * in table. + * + * @param context The main context pointer + * @param str String to parse + * @param table Enum item table to parse + * @param value Returns the value that was parsed + * @return the remainder of the string after the item was parsed + */ static char * parse_enum(build_image_context *context, - char *statement, + char *str, enum_item *table, u_int32_t *val) { int i; char *rest; - int e; for (i = 0; table[i].name != NULL; i++) { - if (!strncmp(table[i].name, statement, + if (!strncmp(table[i].name, str, strlen(table[i].name))) { - /* Lookup the correct value for the token. */ - e = context->bctlib.get_value(table[i].value, - val, context->bct); - if (e) { - printf("Error looking up token %d.\n", table[i].value); - printf("\"%s\" is not valid for this chip.\n", - table[i].name); - *val = -1; - } - - rest = statement + strlen(table[i].name); - return rest; + *val = table[i].value; + rest = str + strlen(table[i].name); + return rest; } } - return parse_u32(statement, val); + return parse_u32(str, val); } + /* - * parse_bootloader(): Processes commands to set a bootloader. + * Parse the given string and find the bootloader file name, load address and + * entry point information then call set_bootloader function. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure */ static int parse_bootloader(build_image_context *context, parse_token token, @@ -586,7 +367,12 @@ static int parse_bootloader(build_image_context *context, } /* - * parse_array(): Processes commands to set an array value. + * Parse the given string and find the array items in config file. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure */ static int parse_array(build_image_context *context, parse_token token, char *rest) @@ -613,12 +399,15 @@ parse_array(build_image_context *context, parse_token token, char *rest) rest++; /* Parse the value based on the field table. */ - switch(token) { + switch (token) { case token_attribute: rest = parse_u32(rest, &value); break; case token_dev_type: - rest = parse_enum(context, rest, s_devtype_table, &value); + rest = parse_enum(context, + rest, + s_devtype_table_t20, + &value); break; default: @@ -630,11 +419,56 @@ parse_array(build_image_context *context, parse_token token, char *rest) return 1; /* Store the result. */ - return context_set_array(context, index, token, value); + return set_array(context, index, token, value); } /* - * parse_value_u32(): General handler for setting u_int32_t values in config files. + * Call hw interface to set the value for array item in bct such as device + * type and bootloader attribute. + * + * @param context The main context pointer + * @param index The index for array + * @param token The parse token value + * @param value The value to set + * @return 0 and -ENODATA for success and failure + */ + +static int +set_array(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + int err = 0; + + assert(context != NULL); + + switch (token) { + case token_attribute: + err = g_bct_parse_interf->setbl_param(index, + token_bl_attribute, + &value, + context->bct); + break; + case token_dev_type: + err = g_bct_parse_interf->set_dev_param(context, + index, + token_dev_type, + value); + break; + default: + break; + } + return err; +} + +/* + * General handler for setting u_int32_t values in config files. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure */ static int parse_value_u32(build_image_context *context, parse_token token, @@ -652,6 +486,14 @@ static int parse_value_u32(build_image_context *context, return context_set_value(context, token, value); } +/* + * Parse the given string and find the bct file name. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ static int parse_bct_file(build_image_context *context, parse_token token, char *rest) { @@ -669,120 +511,33 @@ parse_bct_file(build_image_context *context, parse_token token, char *rest) context->bct_filename = filename; /* Read the bct file to buffer */ read_bct_file(context); + update_context(context); return 0; } static char * -parse_string(char *statement, char *uname, int chars_remaining) -{ - memset(uname, 0, chars_remaining); - while (((*statement >= '0') && (*statement <= '9')) || - ((*statement >= 'A') && (*statement <= 'Z')) || - ((*statement >= 'a') && (*statement <= 'z'))) { - - *uname++ = *statement++; - if (--chars_remaining < 0) { - printf("String length beyond the boundary!!!"); - return NULL; - } - } - *uname = '\0'; - return statement; -} - -static char * -parse_end_state(char *statement, char *uname, int chars_remaining) +parse_end_state(char *str, char *uname, int chars_remaining) { - while (((*statement >= 'a') && (*statement <= 'z')) || - ((*statement >= 'A') && (*statement <= 'Z'))) { + while (isalpha(*str)) { - *uname++ = *statement++; + *uname++ = *str++; if (--chars_remaining < 0) return NULL; } *uname = '\0'; - return statement; -} - - -/* Parse the addon component */ -static int -parse_addon(build_image_context *context, parse_token token, char *rest) -{ - char filename[MAX_BUFFER]; - char u_name[4]; - char e_state[MAX_STR_LEN]; - u_int32_t index; - u_int32_t item_attr; - u_int32_t others; - char other_str[MAX_STR_LEN]; - - assert(context != NULL); - assert(rest != NULL); - - /* Parse the index. */ - rest = parse_u32(rest, &index); - if (rest == NULL) - return 1; - - /* Parse the closing bracket. */ - if (*rest != ']') - return 1; - rest++; - - /* Parse the equals sign.*/ - if (*rest != '=') - return 1; - rest++; - - rest = parse_filename(rest, filename, MAX_BUFFER); - if (rest == NULL) - return 1; - if (set_addon_filename(context, filename, index) != 0) - return 1; - - PARSE_COMMA(1); - - rest = parse_string(rest, u_name, 3); - if (rest == NULL) { - printf("Unique name should be 3 characters.\n"); - return 1; - } - if (set_unique_name(context, u_name, index) != 0) - return 1; - - PARSE_COMMA(1); - - rest = parse_u32(rest, &item_attr); - if (rest == NULL) - return 1; - if (set_addon_attr(context, item_attr, index) != 0) - return 1; - - PARSE_COMMA(1); - - if (*rest == '0' && (*(rest + 1) == 'x' ||*(rest + 1) == 'X')) { - rest = parse_u32(rest, &others); - if (set_other_field(context, NULL, others, index) != 0) - return 1; - } else { - rest = parse_string(rest, other_str, 16); - if (set_other_field(context, other_str, 0, index) != 0) - return 1; - } - if (rest == NULL) - return 1; - - PARSE_COMMA(1); - - rest = parse_end_state(rest, e_state, MAX_STR_LEN); - if (rest == NULL) - return 1; - if (strncmp(e_state, "Complete", strlen("Complete"))) - return 1; - return 0; + return str; } +/* + * Parse the given string and find device parameter listed in device table + * and value for this device parameter. If match, call the corresponding + * function in the table to set device parameter. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ static int parse_dev_param(build_image_context *context, parse_token token, char *rest) { @@ -790,11 +545,16 @@ parse_dev_param(build_image_context *context, parse_token token, char *rest) u_int32_t value; field_item *field; u_int32_t index; + parse_subfield_item *device_type_table; parse_subfield_item *device_item = NULL; - + assert(context != NULL); assert(rest != NULL); + if (context->boot_data_version == NVBOOT_BOOTDATA_VERSION(3, 1)) + device_type_table = s_device_type_table_t30; + else + device_type_table = s_device_type_table_t20; /* Parse the index. */ rest = parse_u32(rest, &index); if (rest == NULL) @@ -811,16 +571,16 @@ parse_dev_param(build_image_context *context, parse_token token, char *rest) rest++; /* Parse the device name. */ - for (i = 0; s_device_type_table[i].prefix != NULL; i++) { - if (!strncmp(s_device_type_table[i].prefix, - rest, strlen(s_device_type_table[i].prefix))) { + for (i = 0; device_type_table[i].prefix != NULL; i++) { + if (!strncmp(device_type_table[i].prefix, + rest, strlen(device_type_table[i].prefix))) { - device_item = &(s_device_type_table[i]); - rest = rest + strlen(s_device_type_table[i].prefix); + device_item = &(device_type_table[i]); + rest = rest + strlen(device_type_table[i].prefix); /* Parse the field name. */ rest = parse_field_name(rest, - s_device_type_table[i].field_table, + device_type_table[i].field_table, &field); if (rest == NULL) return 1; @@ -838,11 +598,18 @@ parse_dev_param(build_image_context *context, parse_token token, char *rest) index, field->token, value); } } - - return 1; - + return 1; } +/* + * Parse the given string and find sdram parameter and value in config + * file. If match, call the corresponding function set the sdram parameter. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ static int parse_sdram_param(build_image_context *context, parse_token token, char *rest) { @@ -869,7 +636,10 @@ parse_sdram_param(build_image_context *context, parse_token token, char *rest) rest++; /* Parse the field name. */ - rest = parse_field_name(rest, s_sdram_field_table, &field); + if (context->boot_data_version == NVBOOT_BOOTDATA_VERSION(3, 1)) + rest = parse_field_name(rest, s_sdram_field_table_t30, &field); + else + rest = parse_field_name(rest, s_sdram_field_table_t20, &field); if (rest == NULL) return 1; @@ -884,23 +654,42 @@ parse_sdram_param(build_image_context *context, parse_token token, char *rest) return 1; /* Store the result. */ - return set_sdram_param(context, index, field->token, value); - + return g_bct_parse_interf->set_sdram_param(context, + index, + field->token, + value); } -/* Return 0 on success, 1 on error */ + +/* + * Compare the given string with item listed in table. + * Execute the proper process function if match. + * + * @param context The main context pointer + * @param str String to parse + * @param simple_parse Simple parse flag + * @return 0 and 1 for success and failure + */ static int -process_statement(build_image_context *context, char *statement) +process_statement(build_image_context *context, + char *str, + u_int8_t simple_parse) { int i; char *rest; + parse_item *cfg_parse_item; + + if (simple_parse == 0) + cfg_parse_item = s_top_level_items; + else + cfg_parse_item = parse_simple_items; - for (i = 0; s_top_level_items[i].prefix != NULL; i++) { - if (!strncmp(s_top_level_items[i].prefix, statement, - strlen(s_top_level_items[i].prefix))) { - rest = statement + strlen(s_top_level_items[i].prefix); + for (i = 0; cfg_parse_item[i].prefix != NULL; i++) { + if (!strncmp(cfg_parse_item[i].prefix, str, + strlen(cfg_parse_item[i].prefix))) { + rest = str + strlen(cfg_parse_item[i].prefix); - return s_top_level_items[i].process(context, - s_top_level_items[i].token, + return cfg_parse_item[i].process(context, + cfg_parse_item[i].token, rest); } } @@ -909,13 +698,18 @@ process_statement(build_image_context *context, char *statement) return 1; } -/* Note: Basic parsing borrowed from nvcamera_config.c */ -void process_config_file(build_image_context *context) +/* + * The main function parse the config file. + * + * @param context The main context pointer + * @param simple_parse Simple parse flag + */ +void process_config_file(build_image_context *context, u_int8_t simple_parse) { char buffer[MAX_BUFFER]; int space = 0; char current; - u_int8_t c_eol_comment_start = 0; // True after first slash + u_int8_t c_eol_comment_start = 0; /* True after first slash */ u_int8_t comment = 0; u_int8_t string = 0; u_int8_t equal_encounter = 0; @@ -923,7 +717,7 @@ void process_config_file(build_image_context *context) assert(context != NULL); assert(context->config_file != NULL); - while ((current = fgetc(context->config_file)) !=EOF) { + while ((current = fgetc(context->config_file)) != EOF) { if (space >= (MAX_BUFFER-1)) { /* if we exceeded the max buffer size, it is likely due to a missing semi-colon at the end of a line */ @@ -950,30 +744,28 @@ void process_config_file(build_image_context *context) if (!string && !comment) { buffer[space++] = '\0'; - /* Process a statement. */ - if (process_statement(context, buffer)) { - goto error; - } + if (process_statement(context, + buffer, + simple_parse)) + goto error; space = 0; equal_encounter = 0; - } else if (string) { + } else if (string) buffer[space++] = current; - } break; case '/': if (!string && !comment) { if (c_eol_comment_start) { - /* EOL comment started. */ + /* EOL comment started. */ comment = 1; c_eol_comment_start = 0; } else { /* Potential start of eol comment. */ c_eol_comment_start = 1; } - } else if (!comment) { + } else if (!comment) buffer[space++] = current; - } break; /* ignore whitespace. uses fallthrough */ @@ -984,28 +776,25 @@ void process_config_file(build_image_context *context) c_eol_comment_start = 0; case ' ': case '\t': - if (string) { + if (string) buffer[space++] = current; - } break; case '#': - if (!string) { + if (!string) comment = 1; - } else { + else buffer[space++] = current; - } break; default: if (!comment) { buffer[space++] = current; if (current == '=') { - if (!equal_encounter) { + if (!equal_encounter) equal_encounter = 1; - } else { + else goto error; - } } } break; @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -53,7 +53,7 @@ typedef enum token_version, token_bct_file, token_bct_copy, - token_addon, + token_bct_size, token_nand_params, token_sdmmc_params, token_spiflash_params, @@ -62,11 +62,86 @@ typedef enum token_clock_source, token_read_command_type_fast, token_max_power_class_supported, + token_sd_controller, token_nand_timing2, token_nand_timing, token_block_size_log2, token_page_size_log2, + token_nand_async_timing0, + token_nand_async_timing1, + token_nand_async_timing2, + token_nand_async_timing3, + token_nand_sddr_timing0, + token_nand_sddr_timing1, + token_nand_tddr_timing0, + token_nand_tddr_timing1, + token_nand_fbio_dqsib_dly_byte, + token_nand_fbio_quse_dly_byte, + token_nand_fbio_cfg_quse_late, + token_async_timing0, + token_async_timing1, + token_async_timing2, + token_async_timing3, + token_sddr_timing0, + token_sddr_timing1, + token_tddr_timing0, + token_tddr_timing1, + token_fbio_dqsib_dly_byte, + token_fbio_quse_dly_byte, + token_fbio_cfg_quse_late, + token_disable_sync_ddr, + token_nand_disable_sync_ddr, token_sdram, + token_crypto_hash, + token_random_aes_blk, + token_boot_data_version, + token_bootloader_used, + token_bootloaders_max, + token_reserved, + token_reserved_size, + token_reserved_offset, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks, + token_num_param_sets, + token_dev_type_nand, + token_dev_type_sdmmc, + token_dev_type_spi, + token_num_sdram_sets, + + token_nand_clock_divider, + token_nand_nand_timing, + token_nand_nand_timing2, + token_nand_block_size_log2, + token_nand_page_size_log2, + token_sdmmc_clock_divider, + token_sdmmc_data_width, + token_sdmmc_sd_controller, + token_sdmmc_max_power_class_supported, + token_spiflash_read_command_type_fast, + token_spiflash_clock_source, + token_spiflash_clock_divider, + token_sdmmc_data_width_4bit, + token_sdmmc_data_width_8bit, + token_spi_clock_source_pllp_out0, + token_spi_clock_source_pllc_out0, + token_spi_clock_source_pllm_out0, + token_spi_clock_source_clockm, + token_memory_type_none, + token_memory_type_ddr, + token_memory_type_lpddr, + token_memory_type_ddr2, + token_memory_type_lpddr2, + + token_bl_version, + token_bl_start_blk, + token_bl_start_page, + token_bl_length, + token_bl_load_addr, + token_bl_entry_point, + token_bl_attribute, + token_bl_crypto_hash, token_memory_type, token_pllm_charge_pump_setup_ctrl, @@ -113,11 +188,6 @@ typedef enum token_emc_tclkstop, token_emc_trefbw, token_emc_quse_extra, - token_emc_fbio_cfg1, - token_emc_fbio_dqsib_dly, - token_emc_fbio_dqsib_dly_msb, - token_emc_fbio_quse_dly, - token_emc_fbio_quse_dly_msb, token_emc_fbio_cfg5, token_emc_fbio_cfg6, token_emc_fbio_spare, @@ -129,16 +199,12 @@ typedef enum token_emc_mrw_reset_command, token_emc_mrw_reset_ninit_wait, token_emc_adr_cfg, - token_emc_adr_cfg1, - token_mc_emem_Cfg, - token_mc_lowlatency_config, + token_mc_emem_cfg, token_emc_cfg, token_emc_cfg2, token_emc_dbg, - token_ahb_arbitration_xbar_ctrl, token_emc_cfg_dig_dll, - token_emc_dll_xform_dqs, - token_emc_dll_xform_quse, + token_emc_cfg_dig_dll_period, token_warm_boot_wait, token_emc_ctt_term_ctrl, token_emc_odt_write, @@ -147,9 +213,6 @@ typedef enum token_emc_zcal_wait_cnt, token_emc_zcal_mrw_cmd, token_emc_mrs_reset_dll, - token_emc_mrw_zq_init_dev0, - token_emc_mrw_zq_init_dev1, - token_emc_mrw_zq_init_wait, token_emc_mrs_reset_dll_wait, token_emc_emrs_emr2, token_emc_emrs_emr3, @@ -157,10 +220,24 @@ typedef enum token_emc_mrs_ddr2_dll_reset, token_emc_emrs_ddr2_ocd_calib, token_emc_ddr2_wait, + token_pmc_ddr_pwr, + + token_emc_fbio_cfg1, + token_emc_fbio_dqsib_dly, + token_emc_fbio_dqsib_dly_msb, + token_emc_fbio_quse_dly, + token_emc_fbio_quse_dly_msb, + token_emc_adr_cfg1, + token_mc_lowlatency_config, token_emc_cfg_clktrim0, token_emc_cfg_clktrim1, token_emc_cfg_clktrim2, - token_pmc_ddr_pwr, + token_ahb_arbitration_xbar_ctrl, + token_emc_dll_xform_dqs, + token_emc_dll_xform_quse, + token_emc_mrw_zq_init_dev0, + token_emc_mrw_zq_init_dev1, + token_emc_mrw_zq_init_wait, token_apb_misc_gp_xm2cfga_pad_ctrl, token_apb_misc_gp_xm2cfgc_pad_ctrl, token_apb_misc_gp_xm2cfgc_pad_ctrl2, @@ -170,6 +247,122 @@ typedef enum token_apb_misc_gp_xm2comp_pad_ctrl, token_apb_misc_gp_xm2vttgen_pad_ctrl, + token_emc_clock_source, + token_emc_clock_use_pll_mud, + token_emc_pin_extra_wait, + token_emc_timing_control_wait, + token_emc_wext, + token_emc_ctt, + token_emc_ctt_duration, + token_emc_prerefresh_req_cnt, + token_emc_txsr_dll, + token_emc_cfg_rsv, + token_emc_mrw_extra, + token_emc_warm_boot_mrw1, + token_emc_warm_boot_mrw2, + token_emc_warm_boot_mrw3, + token_emc_warm_boot_mrw_extra, + token_emc_warm_boot_extramode_reg_write_enable, + token_emc_extramode_reg_write_enable, + token_emc_mrs_wait_cnt, + token_emc_cmd_q, + token_emc_mc2emc_q, + token_emc_dyn_self_ref_control, + token_ahb_arbitration_xbar_ctrl_meminit_done, + token_emc_dev_select, + token_emc_sel_dpd_ctrl, + token_emc_dll_xform_dqs0, + token_emc_dll_xform_dqs1, + token_emc_dll_xform_dqs2, + token_emc_dll_xform_dqs3, + token_emc_dll_xform_dqs4, + token_emc_dll_xform_dqs5, + token_emc_dll_xform_dqs6, + token_emc_dll_xform_dqs7, + token_emc_dll_xform_quse0, + token_emc_dll_xform_quse1, + token_emc_dll_xform_quse2, + token_emc_dll_xform_quse3, + token_emc_dll_xform_quse4, + token_emc_dll_xform_quse5, + token_emc_dll_xform_quse6, + token_emc_dll_xform_quse7, + token_emc_dli_trim_tx_dqs0, + token_emc_dli_trim_tx_dqs1, + token_emc_dli_trim_tx_dqs2, + token_emc_dli_trim_tx_dqs3, + token_emc_dli_trim_tx_dqs4, + token_emc_dli_trim_tx_dqs5, + token_emc_dli_trim_tx_dqs6, + token_emc_dli_trim_tx_dqs7, + token_emc_dll_xform_dq0, + token_emc_dll_xform_dq1, + token_emc_dll_xform_dq2, + token_emc_dll_xform_dq3, + token_emc_zcal_interval, + token_emc_zcal_init_dev0, + token_emc_zcal_init_dev1, + token_emc_zcal_init_wait, + token_emc_zcal_cold_boot_enable, + token_emc_zcal_warm_boot_enable, + token_emc_mrw_lpddr2zcal_warm_boot, + token_emc_zqcal_ddr3_warm_boot, + token_emc_zcal_warm_boot_wait, + token_emc_mrs_warm_boot_enable, + token_emc_mrs_extra, + token_emc_warm_boot_mrs, + token_emc_warm_boot_emrs, + token_emc_warm_boot_emr2, + token_emc_warm_boot_emr3, + token_emc_warm_boot_mrs_extra, + token_emc_clken_override, + token_emc_extra_refresh_num, + token_emc_clken_override_allwarm_boot, + token_mc_clken_override_allwarm_boot, + token_emc_cfg_dig_dll_period_warm_boot, + token_pmc_vddp_sel, + token_pmc_ddr_cfg, + token_pmc_io_dpd_req, + token_pmc_eno_vtt_gen, + token_pmc_no_io_power, + token_emc_xm2cmd_pad_ctrl, + token_emc_xm2cmd_pad_ctrl2, + token_emc_xm2dqs_pad_ctrl, + token_emc_xm2dqs_pad_ctrl2, + token_emc_xm2dqs_pad_ctrl3, + token_emc_xm2dq_pad_ctrl, + token_emc_xm2dq_pad_ctrl2, + token_emc_xm2clk_pad_ctrl, + token_emc_xm2comp_pad_ctrl, + token_emc_xm2vttgen_pad_ctrl, + token_emc_xm2vttgen_pad_ctrl2, + token_emc_xm2quse_pad_ctrl, + token_mc_emem_adr_cfg, + token_mc_emem_adr_cfg_dev0, + token_mc_emem_adr_cfg_dev1, + token_mc_emem_arb_cfg, + token_mc_emem_arb_outstanding_req, + token_mc_emem_arb_timing_rcd, + token_mc_emem_arb_timing_rp, + token_mc_emem_arb_timing_rc, + token_mc_emem_arb_timing_ras, + token_mc_emem_arb_timing_faw, + token_mc_emem_arb_timing_rrd, + token_mc_emem_arb_timing_rap2pre, + token_mc_emem_arb_timing_wap2pre, + token_mc_emem_arb_timing_r2r, + token_mc_emem_arb_timing_w2w, + token_mc_emem_arb_timing_r2w, + token_mc_emem_arb_timing_w2r, + token_mc_emem_arb_da_turns, + token_mc_emem_arb_da_covers, + token_mc_emem_arb_misc0, + token_mc_emem_arb_misc1, + token_mc_emem_arb_ring1_throttle, + token_mc_emem_arb_override, + token_mc_emem_arb_rsv, + token_mc_clken_override, + token_force32 = 0x7fffffff } parse_token; @@ -203,11 +396,11 @@ typedef struct { char *name; u_int32_t token; - u_int32_t enum_value; field_type type; enum_item *enum_table; } field_item; + typedef struct { char *prefix; @@ -224,22 +417,201 @@ typedef struct } parse_item; /* - * Provide access to enum and field tables. These tables are useful when - * pretty printing a BCT file using bct_dump. + * Set of function pointers to be used to access the different hardware + * interface for setting/getting bct information. */ -extern enum_item s_devtype_table[]; -extern enum_item s_sdmmc_data_width_table[]; -extern enum_item s_spi_clock_source_table[]; -extern enum_item s_nvboot_memory_type_table[]; -extern field_item s_sdram_field_table[]; -extern field_item s_nand_table[]; -extern field_item s_sdmmc_table[]; -extern field_item s_spiflash_table[]; +typedef struct bct_parse_interface_rec { + /* + * Set device parameters in bct according to the value listed + * + * @param context The main context pointer + * @param index The device index in bct field + * @param token The parse token value + * @param value Value to set + * @return 0 and -ENODATA for success and failure + */ + int (*set_dev_param)(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); + /* + * Get the specified device parameters from bct data stored + * in context. + * + * @param context The main context pointer + * @param index The device index in bct field + * @param token The parse token value + * @param value Return value get from bct field + * @return 0 and -ENODATA for success and failure + */ + int (*get_dev_param)(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); + /* + * Set sdram parameters in bct according to the value listed + * in config file. + * + * @param context The main context pointer + * @param index The sdram index in bct field + * @param token The parse token value + * @param value Value to set + * @return 0 and 1 for success and failure + */ + int (*set_sdram_param)(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); + /* + * Get the specified sdram parameters from bct data stored + * in context. + * + * @param context The main context pointer + * @param index The sdram index in bct field + * @param token The parse token value + * @param value Return value get from bct field + * @return 0 and 1 for success and failure + */ + int (*get_sdram_param)(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); + /* + * Set bootloader parameters in bct according to the value listed + * in config file. + * + * @param set Bootloader index + * @param id The parse token value + * @param data Value to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*setbl_param)(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct); + /* + * Get the specified bootloader parameters from bct data stored + * in context. + * + * @param set Bootloader index + * @param id The parse token value + * @param data Return value get from bct data + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*getbl_param)(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct); + /* + * Set the specified bct value stored in context bct data structure. + * + * @param id The parse token value + * @param data Value to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*set_value)(parse_token id, + u_int32_t data, + u_int8_t *bct); + /* + * Get the specified bct value or some constant value of clocks and + * hw type. + * + * @param id The parse token value + * @param data Return value get from bct data + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*get_value)(parse_token id, + u_int32_t *data, + u_int8_t *bct); + /* + * Set the bct crypto hash data. + * + * @param id The parse token value + * @param data Value to set + * @param length Length of data to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*set_data)(parse_token id, + u_int8_t *data, + u_int32_t length, + u_int8_t *bct); + + void (*init_bad_block_table)(build_image_context *context); +} bct_parse_interface; + +void process_config_file(build_image_context *context, u_int8_t simple_parse); +void t20_get_cbootimage_interf(bct_parse_interface *cbootimage_bct_interf); +void t30_get_cbootimage_interf(bct_parse_interface *cbootimage_bct_interf); +int +t30_get_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); +int +t30_set_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); +int +t30_get_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); +int +t30_set_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); +int +t20_get_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); +int +t20_set_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); + +int +t20_get_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value); +int +t20_set_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value); +u_int32_t iceil_log2(u_int32_t a, u_int32_t b); + +/* Returns the smallest power of 2 >= a */ +u_int32_t ceil_log2(u_int32_t a); + +extern bct_parse_interface *g_bct_parse_interf; /* - * Function prototypes + * Provide access to enum and field tables. These tables are useful when + * pretty printing a BCT file using bct_dump. */ -void process_config_file(build_image_context *context); - +extern enum_item s_devtype_table_t20[]; +extern enum_item s_sdmmc_data_width_table_t20[]; +extern enum_item s_spi_clock_source_table_t20[]; +extern enum_item s_nvboot_memory_type_table_t20[]; +extern enum_item s_nvboot_memory_type_table_t30[]; +extern field_item s_sdram_field_table_t20[]; +extern field_item s_sdram_field_table_t30[]; +extern field_item s_nand_table_t20[]; +extern field_item s_nand_table_t30[]; +extern field_item s_sdmmc_table_t20[]; +extern field_item s_sdmmc_table_t30[]; +extern field_item s_spiflash_table_t20[]; +extern parse_subfield_item s_device_type_table_t30[]; +extern parse_subfield_item s_device_type_table_t20[]; #endif /* #ifndef INCLUDED_PARSE_H */ @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -38,23 +38,6 @@ * A ParseXXX() function may call other parse functions and set functions. * A SetXXX() function may not call any parseing functions. */ - -#define CASE_DEVICE_VALUE(prefix, id) \ - case token_##id: \ - (void)context->bctlib.setdev_param(index, \ - nvbct_lib_id_##prefix##_##id, \ - value, \ - context->bct); \ - break - -#define CASE_SDRAM_VALUE(id) \ - case token_##id: \ - (void)context->bctlib.set_sdram_params(index, \ - nvbct_lib_id_sdram_##id, \ - value, \ - context->bct); \ - break - #define DEFAULT() \ default: \ printf("Unexpected token %d at line %d\n", \ @@ -63,9 +46,7 @@ int read_from_image(char *filename, - u_int32_t page_size, u_int8_t **image, - u_int32_t *storage_size, u_int32_t *actual_size, file_type f_type) { @@ -87,35 +68,20 @@ read_from_image(char *filename, } *actual_size = (u_int32_t)stats.st_size; - *storage_size = - (u_int32_t)(ICEIL(stats.st_size, page_size) * page_size); - - if (f_type == file_type_bl) { - if (stats.st_size > MAX_BOOTLOADER_SIZE) { - printf("Error: Bootloader file %s is too large.\n", - filename); - result = 1; - goto cleanup; - } - - /* Workaround for a bug in release 1.0 of the boot rom. - * Any BL whose padded size is an integral multiple of page size - * has its length extended by 16 bytes to bump it to end on a - * partial page. - */ - if ((*storage_size - *actual_size) < 16) { - *actual_size += 16; - *storage_size += page_size; - } + if (f_type == file_type_bl && *actual_size > MAX_BOOTLOADER_SIZE) { + printf("Error: Bootloader file %s is too large.\n", + filename); + result = 1; + goto cleanup; } - *image = malloc(*storage_size); + *image = malloc(*actual_size); if (*image == NULL) { result = 1; goto cleanup; } - memset(*image, 0, *storage_size); + memset(*image, 0, *actual_size); if (fread(*image, 1, (size_t)stats.st_size, fp) != stats.st_size) { result = 1; @@ -127,9 +93,14 @@ cleanup: return result; } - /* - * set_bootloader(): Processes commands to set a bootloader. + * Processes commands to set a bootloader. + * + * @param context The main context pointer + * @param filename The file name of bootloader + * @param load_addr The load address value for bootloader + * @param entry_point The entry point value for bootloader + * @return 0 and 1 for success and failure */ int set_bootloader(build_image_context *context, @@ -150,39 +121,12 @@ set_bootloader(build_image_context *context, return 1 /* - * context_set_array(): Sets an array value. - */ -int -context_set_array(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value) -{ - assert(context != NULL); - assert(context->bct != NULL); - - switch (token) { - case token_attribute: - (void)context->bctlib.setbl_param(index, - nvbct_lib_id_bl_attribute, - &value, - context->bct); - break; - - case token_dev_type: - (void)context->bctlib.setdev_param(index, - nvbct_lib_id_dev_type, - value, - context->bct); - break; - - DEFAULT(); - } - return 0; -} - -/* - * context_set_value(): General handler for setting values in config files. + * General handler for setting values in config files. + * + * @param context The main context pointer + * @param token The parse token value + * @param value The value to set + * @return 0 for success */ int context_set_value(build_image_context *context, parse_token token, @@ -210,7 +154,8 @@ int context_set_value(build_image_context *context, } context->pages_per_blk= 1 << (context->block_size_log2- context->page_size_log2); - SET_VALUE(block_size_log2, context->block_size_log2); + g_bct_parse_interf->set_value(token_block_size_log2, + context->block_size_log2, context->bct); break; case token_partition_size: @@ -220,7 +165,8 @@ int context_set_value(build_image_context *context, } context->partition_size= value; - SET_VALUE(partition_size, value); + g_bct_parse_interf->set_value(token_partition_size, + value, context->bct); break; case token_page_size: @@ -229,7 +175,8 @@ int context_set_value(build_image_context *context, context->pages_per_blk= 1 << (context->block_size_log2- context->page_size_log2); - SET_VALUE(page_size_log2, context->page_size_log2); + g_bct_parse_interf->set_value(token_page_size_log2, + context->page_size_log2, context->bct); break; case token_redundancy: context->redundancy = value; @@ -248,333 +195,3 @@ int context_set_value(build_image_context *context, return 0; } - -int -set_addon_filename(build_image_context *context, - char *filename, - int index) -{ - - struct addon_item_rec **current; - int i; - - current = &(context->addon_tbl.addon_item_list); - - for(i = 0; i <= index; i++) { - if (*current == NULL) { - (*current) = malloc(sizeof(struct addon_item_rec)); - if (*current == NULL) - return -ENOMEM; - memset((*current), 0, sizeof(struct addon_item_rec)); - memcpy((*current)->addon_filename, - filename, MAX_BUFFER); - (*current)->item_index = index; - (*current)->next = NULL; - context->addon_tbl.addon_item_no++; - } else if ((*current)->item_index == index) { - memcpy((*current)->addon_filename, - filename, MAX_BUFFER); - } else - current = &((*current)->next); - } - return 0; -} - -int set_addon_attr(build_image_context *context, - u_int32_t file_attr, - int index) -{ - struct addon_item_rec **current; - int i; - - current = &(context->addon_tbl.addon_item_list); - - for(i = 0; i <= index; i++) { - if (*current == NULL) { - (*current) = malloc(sizeof(struct addon_item_rec)); - if (*current == NULL) - return -ENOMEM; - memset((*current), 0, sizeof(struct addon_item_rec)); - (*current)->item.attribute= file_attr; - (*current)->item_index = index; - (*current)->next = NULL; - context->addon_tbl.addon_item_no++; - } else if ((*current)->item_index == index) { - (*current)->item.attribute= file_attr; - } else - current = &((*current)->next); - } - return 0; -} - -int set_unique_name(build_image_context *context, char *uname, int index) -{ - struct addon_item_rec **current; - int i; - - current = &(context->addon_tbl.addon_item_list); - - for(i = 0; i <= index; i++) { - if (*current == NULL) { - (*current) = malloc(sizeof(struct addon_item_rec)); - if (*current == NULL) - return -ENOMEM; - memset((*current), 0, sizeof(struct addon_item_rec)); - memcpy((*current)->item.unique_name, uname, 4); - (*current)->item_index = index; - (*current)->next = NULL; - context->addon_tbl.addon_item_no++; - } else if ((*current)->item_index == index) { - memcpy((*current)->item.unique_name, uname, 4); - } else - current = &((*current)->next); - } - return 0; -} - -int -set_other_field(build_image_context *context, - char *other_str, - int other, - int index) -{ - struct addon_item_rec **current; - int i; - - current = &(context->addon_tbl.addon_item_list); - - for(i = 0; i <= index; i++) { - if (*current == NULL) { - (*current) = malloc(sizeof(struct addon_item_rec)); - if (*current == NULL) - return -ENOMEM; - memset((*current), 0, sizeof(struct addon_item_rec)); - if (other_str == NULL) - (*current)->item.reserve[0] = other; - else - memcpy((*current)->item.reserve, - other_str, 16); - (*current)->item_index = index; - (*current)->next = NULL; - context->addon_tbl.addon_item_no++; - } else if ((*current)->item_index == index) { - if (other_str == NULL) - (*current)->item.reserve[0] = other; - else - memcpy((*current)->item.reserve, - other_str, 16); - } else - current = &((*current)->next); - } - return 0; - -} - -static void -update_num_param_sets(build_image_context *context, u_int32_t index) -{ - u_int32_t num_params; - - GET_VALUE(num_param_sets, &num_params); - num_params = NV_MAX(num_params, index + 1); - SET_VALUE(num_param_sets, num_params); -} - -/* - * set_nand_param(): Processes commands to set Nand parameters. - */ -int -set_nand_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value) -{ - assert(context != NULL); - assert(context->bct != NULL); - - update_num_param_sets(context, index); - - switch (token) { - CASE_DEVICE_VALUE(nand, clock_divider); - CASE_DEVICE_VALUE(nand, nand_timing); - CASE_DEVICE_VALUE(nand, nand_timing2); - CASE_DEVICE_VALUE(nand, block_size_log2); - CASE_DEVICE_VALUE(nand, page_size_log2); - DEFAULT(); - } - - return 0; -} - -/* - * set_sdmmc_param(): Processes commands to set MoviNand parameters. - */ -int -set_sdmmc_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value) -{ - assert(context != NULL); - assert(context->bct != NULL); - - update_num_param_sets(context, index); - - switch (token) { - CASE_DEVICE_VALUE(sdmmc, clock_divider); - CASE_DEVICE_VALUE(sdmmc, data_width); - CASE_DEVICE_VALUE(sdmmc, max_power_class_supported); - DEFAULT(); - } - - return 0; -} - -/* - * set_spiflash_param(): Processes commands to set SpiFlash parameters. - */ -int -set_spiflash_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value) -{ - assert(context != NULL); - assert(context->bct != NULL); - - update_num_param_sets(context, index); - - switch (token) { - CASE_DEVICE_VALUE(spiflash, clock_divider); - CASE_DEVICE_VALUE(spiflash, clock_source); - CASE_DEVICE_VALUE(spiflash, read_command_type_fast); - DEFAULT(); - } - - return 0; -} - -int -set_sdram_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value) -{ - u_int32_t num_sdram_sets; - - assert(context != NULL); - assert(context->bct != NULL); - - // Update the number of SDRAM parameter sets. - GET_VALUE(num_sdram_sets, &num_sdram_sets); - num_sdram_sets = NV_MAX(num_sdram_sets, index + 1); - SET_VALUE(num_sdram_sets, num_sdram_sets); - - switch (token) { - - CASE_SDRAM_VALUE(memory_type); - CASE_SDRAM_VALUE(pllm_charge_pump_setup_ctrl); - CASE_SDRAM_VALUE(pllm_loop_filter_setup_ctrl); - CASE_SDRAM_VALUE(pllm_input_divider); - CASE_SDRAM_VALUE(pllm_feedback_divider); - CASE_SDRAM_VALUE(pllm_post_divider); - CASE_SDRAM_VALUE(pllm_stable_time); - CASE_SDRAM_VALUE(emc_clock_divider); - CASE_SDRAM_VALUE(emc_auto_cal_interval); - CASE_SDRAM_VALUE(emc_auto_cal_config); - CASE_SDRAM_VALUE(emc_auto_cal_wait); - CASE_SDRAM_VALUE(emc_pin_program_wait); - CASE_SDRAM_VALUE(emc_rc); - CASE_SDRAM_VALUE(emc_rfc); - CASE_SDRAM_VALUE(emc_ras); - CASE_SDRAM_VALUE(emc_rp); - CASE_SDRAM_VALUE(emc_r2w); - CASE_SDRAM_VALUE(emc_w2r); - CASE_SDRAM_VALUE(emc_r2p); - CASE_SDRAM_VALUE(emc_w2p); - CASE_SDRAM_VALUE(emc_rd_rcd); - CASE_SDRAM_VALUE(emc_wr_rcd); - CASE_SDRAM_VALUE(emc_rrd); - CASE_SDRAM_VALUE(emc_rext); - CASE_SDRAM_VALUE(emc_wdv); - CASE_SDRAM_VALUE(emc_quse); - CASE_SDRAM_VALUE(emc_qrst); - CASE_SDRAM_VALUE(emc_qsafe); - CASE_SDRAM_VALUE(emc_rdv); - CASE_SDRAM_VALUE(emc_refresh); - CASE_SDRAM_VALUE(emc_burst_refresh_num); - CASE_SDRAM_VALUE(emc_pdex2wr); - CASE_SDRAM_VALUE(emc_pdex2rd); - CASE_SDRAM_VALUE(emc_pchg2pden); - CASE_SDRAM_VALUE(emc_act2pden); - CASE_SDRAM_VALUE(emc_ar2pden); - CASE_SDRAM_VALUE(emc_rw2pden); - CASE_SDRAM_VALUE(emc_txsr); - CASE_SDRAM_VALUE(emc_tcke); - CASE_SDRAM_VALUE(emc_tfaw); - CASE_SDRAM_VALUE(emc_trpab); - CASE_SDRAM_VALUE(emc_tclkstable); - CASE_SDRAM_VALUE(emc_tclkstop); - CASE_SDRAM_VALUE(emc_trefbw); - CASE_SDRAM_VALUE(emc_quse_extra); - CASE_SDRAM_VALUE(emc_fbio_cfg1); - CASE_SDRAM_VALUE(emc_fbio_dqsib_dly); - CASE_SDRAM_VALUE(emc_fbio_dqsib_dly_msb); - CASE_SDRAM_VALUE(emc_fbio_quse_dly); - CASE_SDRAM_VALUE(emc_fbio_quse_dly_msb); - CASE_SDRAM_VALUE(emc_fbio_cfg5); - CASE_SDRAM_VALUE(emc_fbio_cfg6); - CASE_SDRAM_VALUE(emc_fbio_spare); - CASE_SDRAM_VALUE(emc_mrs); - CASE_SDRAM_VALUE(emc_emrs); - CASE_SDRAM_VALUE(emc_mrw1); - CASE_SDRAM_VALUE(emc_mrw2); - CASE_SDRAM_VALUE(emc_mrw3); - CASE_SDRAM_VALUE(emc_mrw_reset_command); - CASE_SDRAM_VALUE(emc_mrw_reset_ninit_wait); - CASE_SDRAM_VALUE(emc_adr_cfg); - CASE_SDRAM_VALUE(emc_adr_cfg1); - CASE_SDRAM_VALUE(mc_emem_Cfg); - CASE_SDRAM_VALUE(mc_lowlatency_config); - CASE_SDRAM_VALUE(emc_cfg); - CASE_SDRAM_VALUE(emc_cfg2); - CASE_SDRAM_VALUE(emc_dbg); - CASE_SDRAM_VALUE(ahb_arbitration_xbar_ctrl); - CASE_SDRAM_VALUE(emc_cfg_dig_dll); - CASE_SDRAM_VALUE(emc_dll_xform_dqs); - CASE_SDRAM_VALUE(emc_dll_xform_quse); - CASE_SDRAM_VALUE(warm_boot_wait); - CASE_SDRAM_VALUE(emc_ctt_term_ctrl); - CASE_SDRAM_VALUE(emc_odt_write); - CASE_SDRAM_VALUE(emc_odt_read); - CASE_SDRAM_VALUE(emc_zcal_ref_cnt); - CASE_SDRAM_VALUE(emc_zcal_wait_cnt); - CASE_SDRAM_VALUE(emc_zcal_mrw_cmd); - CASE_SDRAM_VALUE(emc_mrs_reset_dll); - CASE_SDRAM_VALUE(emc_mrw_zq_init_dev0); - CASE_SDRAM_VALUE(emc_mrw_zq_init_dev1); - CASE_SDRAM_VALUE(emc_mrw_zq_init_wait); - CASE_SDRAM_VALUE(emc_mrs_reset_dll_wait); - CASE_SDRAM_VALUE(emc_emrs_emr2); - CASE_SDRAM_VALUE(emc_emrs_emr3); - CASE_SDRAM_VALUE(emc_emrs_ddr2_dll_enable); - CASE_SDRAM_VALUE(emc_mrs_ddr2_dll_reset); - CASE_SDRAM_VALUE(emc_emrs_ddr2_ocd_calib); - CASE_SDRAM_VALUE(emc_ddr2_wait); - CASE_SDRAM_VALUE(emc_cfg_clktrim0); - CASE_SDRAM_VALUE(emc_cfg_clktrim1); - CASE_SDRAM_VALUE(emc_cfg_clktrim2); - CASE_SDRAM_VALUE(pmc_ddr_pwr); - CASE_SDRAM_VALUE(apb_misc_gp_xm2cfga_pad_ctrl); - CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgc_pad_ctrl); - CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgc_pad_ctrl2); - CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgd_pad_ctrl); - CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgd_pad_ctrl2); - CASE_SDRAM_VALUE(apb_misc_gp_xm2clkcfg_Pad_ctrl); - CASE_SDRAM_VALUE(apb_misc_gp_xm2comp_pad_ctrl); - CASE_SDRAM_VALUE(apb_misc_gp_xm2vttgen_pad_ctrl); - - DEFAULT(); - } - return 0; -} @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -33,12 +33,6 @@ #include "sys/stat.h" int -context_set_array(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value); - -int set_bootloader(build_image_context *context, char *filename, u_int32_t load_addr, @@ -50,55 +44,8 @@ context_set_value(build_image_context *context, u_int32_t value); int -set_addon_filename(build_image_context *context, - char *filename, - int index); - -int -set_addon_attr(build_image_context *context, - u_int32_t file_attr, - int index); - -int -set_unique_name(build_image_context *context, - char *uname, - int index); - -int -set_other_field(build_image_context *context, - char *other_str, - int other, - int index); - -int -set_nand_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value); - -int -set_sdmmc_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value); - -int -set_spiflash_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value); - -int -set_sdram_param(build_image_context *context, - u_int32_t index, - parse_token token, - u_int32_t value); - -int read_from_image(char *filename, - u_int32_t page_size, u_int8_t **Image, - u_int32_t *storage_size, u_int32_t *actual_size, file_type f_type); diff --git a/nvbctlib_ap20.c b/t20/nvbctlib_t20.c index c2ba2c2..ec2fd3d 100644 --- a/nvbctlib_ap20.c +++ b/t20/nvbctlib_t20.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -20,218 +20,180 @@ * MA 02111-1307 USA */ -#include "nvbctlib.h" -#include "nvboot_bct.h" +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t20.h" #include "string.h" -#include "cbootimage.h" -/* nvbctlib_ap20.c: The implementation of the nvbctlib API for AP20. */ +/* nvbctlib_t20.c: The implementation of the nvbctlib API for t20. */ /* Definitions that simplify the code which follows. */ #define CASE_GET_SDRAM_PARAM(x) \ -case nvbct_lib_id_sdram_##x:\ - *data = bct_ptr->sdram_params[set].x; \ +case token_##x:\ + *value = params->x; \ break #define CASE_SET_SDRAM_PARAM(x) \ -case nvbct_lib_id_sdram_##x:\ - bct_ptr->sdram_params[set].x = data; \ +case token_##x:\ + params->x = value; \ break #define CASE_GET_DEV_PARAM(dev, x) \ -case nvbct_lib_id_##dev##_##x:\ - *data = bct_ptr->dev_params[set].dev##_params.x; \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ break #define CASE_SET_DEV_PARAM(dev, x) \ -case nvbct_lib_id_##dev##_##x:\ - bct_ptr->dev_params[set].dev##_params.x = data; \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ break #define CASE_GET_BL_PARAM(x) \ -case nvbct_lib_id_bl_##x:\ +case token_bl_##x:\ *data = bct_ptr->bootloader[set].x; \ break #define CASE_SET_BL_PARAM(x) \ -case nvbct_lib_id_bl_##x:\ +case token_bl_##x:\ bct_ptr->bootloader[set].x = *data; \ break #define CASE_GET_NVU32(id) \ -case nvbct_lib_id_##id:\ +case token_##id:\ if (bct == NULL) return -ENODATA; \ *data = bct_ptr->id; \ break #define CASE_GET_CONST(id, val) \ -case nvbct_lib_id_##id:\ +case token_##id:\ *data = val; \ break #define CASE_GET_CONST_PREFIX(id, val_prefix) \ -case nvbct_lib_id_##id:\ +case token_##id:\ *data = val_prefix##_##id; \ break #define CASE_SET_NVU32(id) \ -case nvbct_lib_id_##id:\ +case token_##id:\ bct_ptr->id = data; \ break #define CASE_GET_DATA(id, size) \ -case nvbct_lib_id_##id:\ +case token_##id:\ if (*length < size) return -ENODATA;\ memcpy(data, &(bct_ptr->id), size); \ *length = size;\ break #define CASE_SET_DATA(id, size) \ -case nvbct_lib_id_##id:\ +case token_##id:\ if (length < size) return -ENODATA;\ memcpy(&(bct_ptr->id), data, size); \ break -static int -get_sdram_params(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct) +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +int +t20_set_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct = NULL; - if (set >= NVBOOT_BCT_MAX_SDRAM_SETS) - return ENODATA; - if (data == NULL || bct == NULL) - return -ENODATA; + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); - switch (id) { + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); - CASE_GET_SDRAM_PARAM(memory_type); - CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); - CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); - CASE_GET_SDRAM_PARAM(pllm_input_divider); - CASE_GET_SDRAM_PARAM(pllm_feedback_divider); - CASE_GET_SDRAM_PARAM(pllm_post_divider); - CASE_GET_SDRAM_PARAM(pllm_stable_time); - CASE_GET_SDRAM_PARAM(emc_clock_divider); - CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); - CASE_GET_SDRAM_PARAM(emc_auto_cal_config); - CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); - CASE_GET_SDRAM_PARAM(emc_pin_program_wait); - CASE_GET_SDRAM_PARAM(emc_rc); - CASE_GET_SDRAM_PARAM(emc_rfc); - CASE_GET_SDRAM_PARAM(emc_ras); - CASE_GET_SDRAM_PARAM(emc_rp); - CASE_GET_SDRAM_PARAM(emc_r2w); - CASE_GET_SDRAM_PARAM(emc_w2r); - CASE_GET_SDRAM_PARAM(emc_r2p); - CASE_GET_SDRAM_PARAM(emc_w2p); - CASE_GET_SDRAM_PARAM(emc_rd_rcd); - CASE_GET_SDRAM_PARAM(emc_wr_rcd); - CASE_GET_SDRAM_PARAM(emc_rrd); - CASE_GET_SDRAM_PARAM(emc_rext); - CASE_GET_SDRAM_PARAM(emc_wdv); - CASE_GET_SDRAM_PARAM(emc_quse); - CASE_GET_SDRAM_PARAM(emc_qrst); - CASE_GET_SDRAM_PARAM(emc_qsafe); - CASE_GET_SDRAM_PARAM(emc_rdv); - CASE_GET_SDRAM_PARAM(emc_refresh); - CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); - CASE_GET_SDRAM_PARAM(emc_pdex2wr); - CASE_GET_SDRAM_PARAM(emc_pdex2rd); - CASE_GET_SDRAM_PARAM(emc_pchg2pden); - CASE_GET_SDRAM_PARAM(emc_act2pden); - CASE_GET_SDRAM_PARAM(emc_ar2pden); - CASE_GET_SDRAM_PARAM(emc_rw2pden); - CASE_GET_SDRAM_PARAM(emc_txsr); - CASE_GET_SDRAM_PARAM(emc_tcke); - CASE_GET_SDRAM_PARAM(emc_tfaw); - CASE_GET_SDRAM_PARAM(emc_trpab); - CASE_GET_SDRAM_PARAM(emc_tclkstable); - CASE_GET_SDRAM_PARAM(emc_tclkstop); - CASE_GET_SDRAM_PARAM(emc_trefbw); - CASE_GET_SDRAM_PARAM(emc_quse_extra); - CASE_GET_SDRAM_PARAM(emc_fbio_cfg1); - CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly); - CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); - CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly); - CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb); - CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); - CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); - CASE_GET_SDRAM_PARAM(emc_fbio_spare); - CASE_GET_SDRAM_PARAM(emc_mrs); - CASE_GET_SDRAM_PARAM(emc_emrs); - CASE_GET_SDRAM_PARAM(emc_mrw1); - CASE_GET_SDRAM_PARAM(emc_mrw2); - CASE_GET_SDRAM_PARAM(emc_mrw3); - CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); - CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); - CASE_GET_SDRAM_PARAM(emc_adr_cfg); - CASE_GET_SDRAM_PARAM(emc_adr_cfg1); - CASE_GET_SDRAM_PARAM(mc_emem_Cfg); - CASE_GET_SDRAM_PARAM(mc_lowlatency_config); - CASE_GET_SDRAM_PARAM(emc_cfg); - CASE_GET_SDRAM_PARAM(emc_cfg2); - CASE_GET_SDRAM_PARAM(emc_dbg); - CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); - CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); - CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs); - CASE_GET_SDRAM_PARAM(emc_dll_xform_quse); - CASE_GET_SDRAM_PARAM(warm_boot_wait); - CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); - CASE_GET_SDRAM_PARAM(emc_odt_write); - CASE_GET_SDRAM_PARAM(emc_odt_read); - CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt); - CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); - CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); - CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); - CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0); - CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1); - CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait); - CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); - CASE_GET_SDRAM_PARAM(emc_emrs_emr2); - CASE_GET_SDRAM_PARAM(emc_emrs_emr3); - CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); - CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); - CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); - CASE_GET_SDRAM_PARAM(emc_ddr2_wait); - CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0); - CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1); - CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2); - CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); - CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + switch (token) { + CASE_SET_DEV_PARAM(nand, clock_divider); + CASE_SET_DEV_PARAM(nand, nand_timing); + CASE_SET_DEV_PARAM(nand, nand_timing2); + CASE_SET_DEV_PARAM(nand, block_size_log2); + CASE_SET_DEV_PARAM(nand, page_size_log2); + + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + bct->dev_type[index] = value; + break; default: return -ENODATA; } return 0; - } -static int -set_sdram_params(u_int32_t set, - nvbct_lib_id id, - u_int32_t data, - u_int8_t *bct) +int +t20_get_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct = NULL; - if (set >= NVBOOT_BCT_MAX_SDRAM_SETS) - return ENODATA; - if (bct == NULL) + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(nand, clock_divider); + CASE_GET_DEV_PARAM(nand, nand_timing); + CASE_GET_DEV_PARAM(nand, nand_timing2); + CASE_GET_DEV_PARAM(nand, block_size_log2); + CASE_GET_DEV_PARAM(nand, page_size_log2); + + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: return -ENODATA; + } - switch (id) { + return 0; +} + +int +t20_set_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + switch (token) { CASE_SET_SDRAM_PARAM(memory_type); CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); @@ -241,7 +203,7 @@ set_sdram_params(u_int32_t set, CASE_SET_SDRAM_PARAM(pllm_stable_time); CASE_SET_SDRAM_PARAM(emc_clock_divider); CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); - CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); CASE_SET_SDRAM_PARAM(emc_pin_program_wait); CASE_SET_SDRAM_PARAM(emc_rc); @@ -294,7 +256,7 @@ set_sdram_params(u_int32_t set, CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); CASE_SET_SDRAM_PARAM(emc_adr_cfg); CASE_SET_SDRAM_PARAM(emc_adr_cfg1); - CASE_SET_SDRAM_PARAM(mc_emem_Cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); CASE_SET_SDRAM_PARAM(mc_lowlatency_config); CASE_SET_SDRAM_PARAM(emc_cfg); CASE_SET_SDRAM_PARAM(emc_cfg2); @@ -334,94 +296,139 @@ set_sdram_params(u_int32_t set, CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); - default: - return -ENODATA; + DEFAULT(); } - return 0; } -static int -getdev_param(u_int32_t set, - nvbct_lib_id id, - u_int32_t *data, - u_int8_t *bct) -{ - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; - if (data == NULL || bct == NULL) - return -ENODATA; - - switch (id) { - CASE_GET_DEV_PARAM(nand, clock_divider); - CASE_GET_DEV_PARAM(nand, nand_timing); - CASE_GET_DEV_PARAM(nand, nand_timing2); - CASE_GET_DEV_PARAM(nand, block_size_log2); - CASE_GET_DEV_PARAM(nand, page_size_log2); - - CASE_GET_DEV_PARAM(sdmmc, clock_divider); - CASE_GET_DEV_PARAM(sdmmc, data_width); - CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); - - CASE_GET_DEV_PARAM(spiflash, clock_source); - CASE_GET_DEV_PARAM(spiflash, clock_divider); - CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); - - case nvbct_lib_id_dev_type: - *data = bct_ptr->dev_type[set]; - break; - - default: - return -ENODATA; - } - - return 0; -} - -static int -setdev_param(u_int32_t set, - nvbct_lib_id id, - u_int32_t data, - u_int8_t *bct) +int +t20_get_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; - - if (bct == NULL) - return -ENODATA; - - switch (id) { - CASE_SET_DEV_PARAM(nand, clock_divider); - CASE_SET_DEV_PARAM(nand, nand_timing); - CASE_SET_DEV_PARAM(nand, nand_timing2); - CASE_SET_DEV_PARAM(nand, block_size_log2); - CASE_SET_DEV_PARAM(nand, page_size_log2); - - CASE_SET_DEV_PARAM(sdmmc, clock_divider); - CASE_SET_DEV_PARAM(sdmmc, data_width); - CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; - CASE_SET_DEV_PARAM(spiflash, clock_source); - CASE_SET_DEV_PARAM(spiflash, clock_divider); - CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); - case nvbct_lib_id_dev_type: - bct_ptr->dev_type[set] = data; - break; - - default: - return -ENODATA; + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_post_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(emc_clock_divider); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg1); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(emc_adr_cfg1); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(mc_lowlatency_config); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_emr2); + CASE_GET_SDRAM_PARAM(emc_emrs_emr3); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + DEFAULT(); } - return 0; - } -static int -getbl_param(u_int32_t set, - nvbct_lib_id id, +int +t20_getbl_param(u_int32_t set, + parse_token id, u_int32_t *data, u_int8_t *bct) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; if (set >= NVBOOT_MAX_BOOTLOADERS) return -ENODATA; @@ -437,7 +444,7 @@ getbl_param(u_int32_t set, CASE_GET_BL_PARAM(entry_point); CASE_GET_BL_PARAM(attribute); - case nvbct_lib_id_bl_crypto_hash: + case token_bl_crypto_hash: memcpy(data, &(bct_ptr->bootloader[set].crypto_hash), sizeof(nvboot_hash)); @@ -450,14 +457,13 @@ getbl_param(u_int32_t set, return 0; } -/* Note: The *Data argument is to support hash data. */ -static int -setbl_param(u_int32_t set, - nvbct_lib_id id, +int +t20_setbl_param(u_int32_t set, + parse_token id, u_int32_t *data, u_int8_t *bct) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; if (set >= NVBOOT_MAX_BOOTLOADERS) return -ENODATA; @@ -473,7 +479,7 @@ setbl_param(u_int32_t set, CASE_SET_BL_PARAM(entry_point); CASE_SET_BL_PARAM(attribute); - case nvbct_lib_id_bl_crypto_hash: + case token_bl_crypto_hash: memcpy(&(bct_ptr->bootloader[set].crypto_hash), data, sizeof(nvboot_hash)); @@ -486,11 +492,10 @@ setbl_param(u_int32_t set, return 0; } - -static int -bct_get_value(nvbct_lib_id id, u_int32_t *data, u_int8_t *bct) +int +t20_bct_get_value(parse_token id, u_int32_t *data, u_int8_t *bct) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; nvboot_config_table samplebct; /* Used for computing offsets. */ /* @@ -519,24 +524,24 @@ bct_get_value(nvbct_lib_id id, u_int32_t *data, u_int8_t *bct) CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); - case nvbct_lib_id_reserved_offset: - *data = (u_int8_t*)&(samplebct.reserved) - - (u_int8_t*)&samplebct; + case token_reserved_offset: + *data = (u_int8_t *)&(samplebct.reserved) + - (u_int8_t *)&samplebct; break; - case nvbct_lib_id_bct_size: + case token_bct_size: *data = sizeof(nvboot_config_table); break; CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); - case nvbct_lib_id_crypto_offset: + case token_crypto_offset: /* Offset to region in BCT to encrypt & sign */ - *data = (u_int8_t*)&(samplebct.random_aes_blk) - - (u_int8_t*)&samplebct; + *data = (u_int8_t *)&(samplebct.random_aes_blk) + - (u_int8_t *)&samplebct; break; - case nvbct_lib_id_crypto_length: + case token_crypto_length: /* size of region in BCT to encrypt & sign */ *data = sizeof(nvboot_config_table) - sizeof(nvboot_hash); break; @@ -565,10 +570,10 @@ bct_get_value(nvbct_lib_id id, u_int32_t *data, u_int8_t *bct) return 0; } -static int -bct_set_value(nvbct_lib_id id, u_int32_t data, u_int8_t *bct) +int +t20_bct_set_value(parse_token id, u_int32_t data, u_int8_t *bct) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; if (bct == NULL) return -ENODATA; @@ -587,33 +592,18 @@ bct_set_value(nvbct_lib_id id, u_int32_t data, u_int8_t *bct) default: return -ENODATA; - } - - return 0; -} - - + } -/* - * Note: On input, *length is the size of Data. On output, *length is the - * actual size used. - */ -static int -bct_get_data(nvbct_lib_id id, - u_int8_t *data, - u_int32_t *length, - u_int8_t *bct) -{ return 0; } -static int -bct_set_data(nvbct_lib_id id, +int +t20_bct_set_data(parse_token id, u_int8_t *data, u_int32_t length, u_int8_t *bct) { - nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; if (data == NULL || bct == NULL) return -ENODATA; @@ -629,22 +619,38 @@ bct_set_data(nvbct_lib_id id, return 0; } - -void -nvbct_lib_get_fns(nvbct_lib_fns *fns) +void t20_init_bad_block_table(build_image_context *context) { - fns->get_value = bct_get_value; - fns->set_value = bct_set_value; + u_int32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); - fns->get_data = bct_get_data; - fns->set_data = bct_set_data; + assert(context != NULL); + assert(bct != NULL); - fns->getbl_param = getbl_param; - fns->setbl_param = setbl_param; + table = &bct->badblock_table; - fns->getdev_param = getdev_param; - fns->setdev_param = setdev_param; + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} - fns->get_sdram_params = get_sdram_params; - fns->set_sdram_params = set_sdram_params; +void t20_get_cbootimage_interf(bct_parse_interface *cbootimage_bct_interf) +{ + cbootimage_bct_interf->init_bad_block_table = t20_init_bad_block_table; + cbootimage_bct_interf->set_dev_param = t20_set_dev_param; + cbootimage_bct_interf->get_dev_param = t20_get_dev_param; + cbootimage_bct_interf->set_sdram_param = t20_set_sdram_param; + cbootimage_bct_interf->get_sdram_param = t20_get_sdram_param; + cbootimage_bct_interf->setbl_param = t20_setbl_param; + cbootimage_bct_interf->getbl_param = t20_getbl_param; + cbootimage_bct_interf->set_value = t20_bct_set_value; + cbootimage_bct_interf->get_value = t20_bct_get_value; + cbootimage_bct_interf->set_data = t20_bct_set_data; } diff --git a/nvboot_bct.h b/t20/nvboot_bct_t20.h index 94f9625..5102629 100644 --- a/nvboot_bct.h +++ b/t20/nvboot_bct_t20.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -24,7 +24,7 @@ #define INCLUDED_NVBOOT_BCT_H #include <sys/types.h> -#include "nvboot_sdram_param.h" +#include "nvboot_sdram_param_t20.h" /** * Defines the number of 32-bit words in the customer_data area of the BCT. @@ -35,7 +35,7 @@ * Defines the number of bytes in the customer_data area of the BCT. */ #define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ - (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) /** * Defines the number of bytes in the reserved area of the BCT. @@ -99,13 +99,12 @@ enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; /** * Defines the storage for a hash value (128 bits). */ -typedef struct nvboot_hash_rec -{ +typedef struct nvboot_hash_rec { u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; } nvboot_hash; -/// Defines the params that can be configured for NAND devices. -typedef struct nvboot_nand_params_rec{ +/* Defines the params that can be configured for NAND devices. */ +typedef struct nvboot_nand_params_rec { /** * Specifies the clock divider for the PLL_P 432MHz source. * If it is set to 18, then clock source to Nand controller is @@ -113,22 +112,21 @@ typedef struct nvboot_nand_params_rec{ */ u_int8_t clock_divider; - /// Specifies the value to be programmed to Nand Timing Register 1 + /* Specifies the value to be programmed to Nand Timing Register 1 */ u_int32_t nand_timing; - /// Specifies the value to be programmed to Nand Timing Register 2 + /* Specifies the value to be programmed to Nand Timing Register 2 */ u_int32_t nand_timing2; - /// Specifies the block size in log2 bytes + /* Specifies the block size in log2 bytes */ u_int8_t block_size_log2; - /// Specifies the page size in log2 bytes + /* Specifies the page size in log2 bytes */ u_int8_t page_size_log2; } nvboot_nand_params; -/// Defines various data widths supported. -typedef enum -{ +/* Defines various data widths supported. */ +typedef enum { /** * Specifies a 1 bit interface to eMMC. * Note that 1-bit data width is only for the driver's internal use. @@ -140,19 +138,18 @@ typedef enum */ nvboot_sdmmc_data_width_1bit = 0, - /// Specifies a 4 bit interface to eMMC. + /* Specifies a 4 bit interface to eMMC. */ nvboot_sdmmc_data_width_4bit = 1, - /// Specifies a 8 bit interface to eMMC. + /* Specifies a 8 bit interface to eMMC. */ nvboot_sdmmc_data_width_8bit = 2, nvboot_sdmmc_data_width_num, nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF } nvboot_sdmmc_data_width; -/// Defines the parameters that can be changed after BCT is read. -typedef struct nvboot_sdmmc_params_rec -{ +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { /** * Specifies the clock divider for the SDMMC controller's clock source, * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC @@ -160,10 +157,10 @@ typedef struct nvboot_sdmmc_params_rec */ u_int8_t clock_divider; - /// Specifies the data bus width. Supported data widths are 4/8 bits. + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ nvboot_sdmmc_data_width data_width; - /** + /** * Max Power class supported by the target board. * The driver determines the best data width and clock frequency * supported within the power class range (0 to Max) if the selected @@ -172,18 +169,17 @@ typedef struct nvboot_sdmmc_params_rec u_int8_t max_power_class_supported; } nvboot_sdmmc_params; -typedef enum -{ - /// Specifies SPI clock source to be PLLP. +typedef enum { + /* Specifies SPI clock source to be PLLP. */ nvboot_spi_clock_source_pllp_out0 = 0, - /// Specifies SPI clock source to be PLLC. + /* Specifies SPI clock source to be PLLC. */ nvboot_spi_clock_source_pllc_out0, - /// Specifies SPI clock source to be PLLM. + /* Specifies SPI clock source to be PLLM. */ nvboot_spi_clock_source_pllm_out0, - /// Specifies SPI clock source to be ClockM. + /* Specifies SPI clock source to be ClockM. */ nvboot_spi_clock_source_clockm, nvboot_spi_clock_source_num, @@ -194,8 +190,7 @@ typedef enum /** * Defines the parameters SPI FLASH devices. */ -typedef struct nvboot_spiflash_params_rec -{ +typedef struct nvboot_spiflash_params_rec { /** * Specifies the clock source to use. */ @@ -224,12 +219,12 @@ typedef struct nvboot_spiflash_params_rec /** * Defines the union of the parameters required by each device. */ -typedef union{ - /// Specifies optimized parameters for NAND +typedef union { + /* Specifies optimized parameters for NAND */ nvboot_nand_params nand_params; - /// Specifies optimized parameters for eMMC and eSD + /* Specifies optimized parameters for eMMC and eSD */ nvboot_sdmmc_params sdmmc_params; - /// Specifies optimized parameters for SPI NOR + /* Specifies optimized parameters for SPI NOR */ nvboot_spiflash_params spiflash_params; } nvboot_dev_params; @@ -239,25 +234,24 @@ typedef union{ * @note These no longer match the fuse API device values (for * backward compatibility with AP15). */ -typedef enum -{ - /// Specifies a default (unset) value. +typedef enum { + /* Specifies a default (unset) value. */ nvboot_dev_type_none = 0, - /// Specifies NAND. + /* Specifies NAND. */ nvboot_dev_type_nand, - /// Specifies SPI NOR. + /* Specifies SPI NOR. */ nvboot_dev_type_spi = 3, - /// Specifies SDMMC (either eMMC or eSD). + /* Specifies SDMMC (either eMMC or eSD). */ nvboot_dev_type_sdmmc, nvboot_dev_type_max, - /// Ignore -- Forces compilers to make 32-bit enums. + /* Ignore -- Forces compilers to make 32-bit enums. */ nvboot_dev_type_force32 = 0x7FFFFFFF - } nvboot_dev_type; +} nvboot_dev_type; /** * Stores information needed to locate and verify a boot loader. @@ -265,8 +259,7 @@ typedef enum * There is one \c nv_bootloader_info structure for each copy of a BL stored on * the device. */ -typedef struct nv_bootloader_info_rec -{ +typedef struct nv_bootloader_info_rec { u_int32_t version; u_int32_t start_blk; u_int32_t start_page; @@ -280,8 +273,7 @@ typedef struct nv_bootloader_info_rec /** * Defines the bad block table structure stored in the BCT. */ -typedef struct nvboot_badblock_table_rec -{ +typedef struct nvboot_badblock_table_rec { u_int32_t entries_used; u_int8_t virtual_blk_size_log2; u_int8_t block_size_log2; @@ -296,8 +288,7 @@ typedef struct nvboot_badblock_table_rec * - The \c random_aes_blk member exists to increase the difficulty of * key attacks based on knowledge of this structure. */ -typedef struct nvboot_config_table_rec -{ +typedef struct nvboot_config_table_rec { nvboot_hash crypto_hash; nvboot_hash random_aes_blk; u_int32_t boot_data_version; @@ -316,5 +307,4 @@ typedef struct nvboot_config_table_rec u_int8_t enable_fail_back; u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; } nvboot_config_table; - #endif /* #ifndef INCLUDED_NVBOOT_BCT_H */ diff --git a/t20/nvboot_sdram_param_t20.h b/t20/nvboot_sdram_param_t20.h new file mode 100644 index 0000000..fdf1631 --- /dev/null +++ b/t20/nvboot_sdram_param_t20.h @@ -0,0 +1,366 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* Specifies the CPCON value for PllM */ + u_int32_t pllm_charge_pump_setup_ctrl; + /* Specifies the LPCON value for PllM */ + u_int32_t pllm_loop_filter_setup_ctrl; + /* Specifies the M value for PllM */ + u_int32_t pllm_input_divider; + /* Specifies the N value for PllM */ + u_int32_t pllm_feedback_divider; + /* Specifies the P value for PllM */ + u_int32_t pllm_post_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + u_int32_t pllm_stable_time; + + /* Specifies the divider for the EMC Clock Source */ + u_int32_t emc_clock_divider; + + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + u_int32_t emc_auto_cal_interval; + /** + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + u_int32_t emc_auto_cal_config; + /** + * Specifies the time for the calibration to + * stabilize (in microseconds) + */ + u_int32_t emc_auto_cal_wait; + + /** + * Specifies the time to wait after pin programming (in microseconds) + * Dram vendors require at least 200us. + */ + u_int32_t emc_pin_program_wait; + + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + u_int32_t emc_rc; + /* Specifies the value for EMC_RFC */ + u_int32_t emc_rfc; + /* Specifies the value for EMC_RAS */ + u_int32_t emc_ras; + /* Specifies the value for EMC_RP */ + u_int32_t emc_rp; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + u_int32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + u_int32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + u_int32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + u_int32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + u_int32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + u_int32_t emc_rext; + /* Specifies the value for EMC_WDV */ + u_int32_t emc_wdv; + /* Specifies the value for EMC_QUSE */ + u_int32_t emc_quse; + /* Specifies the value for EMC_QRST */ + u_int32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + u_int32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + u_int32_t emc_rdv; + /* Specifies the value for EMC_REFRESH */ + u_int32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + u_int32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PDEX2WR */ + u_int32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + u_int32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + u_int32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + u_int32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + u_int32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + u_int32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + u_int32_t emc_txsr; + /* Specifies the value for EMC_TCKE */ + u_int32_t emc_tcke; + /* Specifies the value for EMC_TFAW */ + u_int32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + u_int32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + u_int32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + u_int32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + u_int32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + u_int32_t emc_quse_extra; + + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG1 */ + u_int32_t emc_fbio_cfg1; + /* Specifies the value for EMC_FBIO_DQSIB_DLY */ + u_int32_t emc_fbio_dqsib_dly; + /* Specifies the value for EMC_FBIO_DQSIB_DLY_MSB */ + u_int32_t emc_fbio_dqsib_dly_msb; + /* Specifies the value for EMC_FBIO_QUSE_DLY */ + u_int32_t emc_fbio_quse_dly; + /* Specifies the value for EMC_FBIO_QUSE_DLY_MSB */ + u_int32_t emc_fbio_quse_dly_msb; + /* Specifies the value for EMC_FBIO_CFG5 */ + u_int32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + u_int32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + u_int32_t emc_fbio_spare; + + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + u_int32_t emc_mrs; + /* Specifies the value for EMC_EMRS */ + u_int32_t emc_emrs; + /* Specifies the first of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw1; + /* Specifies the second of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw2; + /* Specifies the third of a sequence of three values for EMC_MRW */ + u_int32_t emc_mrw3; + + /* Specifies the EMC_MRW reset command value */ + u_int32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + u_int32_t emc_mrw_reset_ninit_wait; + + /** + * Specifies the value for EMC_ADR_CFG + * The same value is also used for MC_EMC_ADR_CFG + */ + u_int32_t emc_adr_cfg; + /* Specifies the value for EMC_ADR_CFG_1 */ + u_int32_t emc_adr_cfg1; + + /** + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + * EMEM_SIZE_KB must be <= (Device size in KB * Number of Devices) + */ + u_int32_t mc_emem_cfg; + + /** + * Specifies the value for MC_LOWLATENCY_CONFIG + * Mainly for LL_DRAM_INTERLEAVE: Some DRAMs do not support interleave + * mode. If so, turn off this bit to get the correct low-latency path + * behavior. Reset is ENABLED. + */ + u_int32_t mc_lowlatency_config; + /* Specifies the value for EMC_CFG */ + u_int32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + u_int32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + u_int32_t emc_dbg; + + /* + * Specifies the value for AHB_ARBITRATION_XBAR_CTRL. + * This is used to set the Memory Inid done + */ + u_int32_t ahb_arbitration_xbar_ctrl; + + /* + * Specifies the value for EMC_CFG_DIG_DLL + * Note: Trigger bits are set by the SDRAM code. + */ + u_int32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_DLL_XFORM_DQS */ + u_int32_t emc_dll_xform_dqs; + /* Specifies the value for EMC_DLL_XFORM_QUSE */ + u_int32_t emc_dll_xform_quse; + + /* + * Specifies the delay after prgramming the PIN/NOP register during a + * WarmBoot0 sequence (in microseconds) + */ + u_int32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + u_int32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_read; + + /* + * Specifies the value for EMC_ZCAL_REF_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_ref_cnt; + /* + * Specifies the value for EMC_ZCAL_WAIT_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_wait_cnt; + /* + * Specifies the value for EMC_ZCAL_MRW_CMD + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + u_int32_t emc_zcal_mrw_cmd; + + /* + * Specifies the MRS command value for initilizing + * the mode register. + */ + u_int32_t emc_mrs_reset_dll; + /* Specifies the MRW command for ZQ initialization of device 0 */ + u_int32_t emc_mrw_zq_init_dev0; + /* Specifies the MRW command for ZQ initialization of device 1 */ + u_int32_t emc_mrw_zq_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + u_int32_t emc_mrw_zq_init_wait; + /* + * Specifies the wait time after sending an MRS DLL reset command + * (in microseconds) + */ + u_int32_t emc_mrs_reset_dll_wait; + /* + * Specifies the first of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr2; + /* + * Specifies the second of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr3; + /* Specifies the EMRS command to enable the DDR2 DLL */ + u_int32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + u_int32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + u_int32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + u_int32_t emc_ddr2_wait; + + + /* Clock trimmers */ + + /* Specifies the value for EMC_CFG_CLKTRIM_0 */ + u_int32_t emc_cfg_clktrim0; + /* Specifies the value for EMC_CFG_CLKTRIM_1 */ + u_int32_t emc_cfg_clktrim1; + /* Specifies the value for EMC_CFG_CLKTRIM_2 */ + u_int32_t emc_cfg_clktrim2; + + + /* Pad controls */ + + /* Specifies the value for PMC_DDR_PWR */ + u_int32_t pmc_ddr_pwr; + /* Specifies the value for APB_MISC_GP_XM2CFGAPADCTRL */ + u_int32_t apb_misc_gp_xm2cfga_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL */ + u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL2 */ + u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL */ + u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL2 */ + u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CLKCFGPADCTRL */ + u_int32_t apb_misc_gp_xm2clkcfg_Pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2COMPPADCTRL */ + u_int32_t apb_misc_gp_xm2comp_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2VTTGENPADCTRL */ + u_int32_t apb_misc_gp_xm2vttgen_pad_ctrl; + + /* + * Specifies storage for arbitration configuration registers + * Data passed through to the Bootloader but not used by + * the Boot ROM + */ + u_int32_t arbitration_config[NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS]; +} nvboot_sdram_params; + +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H */ + diff --git a/t20/parse_t20.c b/t20/parse_t20.c new file mode 100644 index 0000000..b24f9fc --- /dev/null +++ b/t20/parse_t20.c @@ -0,0 +1,254 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * parse_t20.c - Parsing code for t20 + */ + +#include "../parse.h" +#include "nvboot_bct_t20.h" + +enum_item s_devtype_table_t20[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "NvBootDevType_Nand", nvboot_dev_type_nand }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { "Nand", nvboot_dev_type_nand }, + + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t20[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t20[] = { + { + "NvBootSpiClockSource_PllPOut0", + nvboot_spi_clock_source_pllp_out0 + }, + { + "NvBootSpiClockSource_PllCOut0", + nvboot_spi_clock_source_pllc_out0 + }, + { + "NvBootSpiClockSource_PllMOut0", + nvboot_spi_clock_source_pllm_out0 + }, + { + "NvBootSpiClockSource_ClockM", + nvboot_spi_clock_source_clockm + }, + + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + + + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t20[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t20[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t20 }, + + { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, + { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "EmcClockDivider", TOKEN(emc_clock_divider) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg1", TOKEN(emc_fbio_cfg1) }, + { "EmcFbioDqsibDlyMsb", TOKEN(emc_fbio_dqsib_dly_msb) }, + { "EmcFbioDqsibDly", TOKEN(emc_fbio_dqsib_dly) }, + { "EmcFbioQuseDlyMsb", TOKEN(emc_fbio_quse_dly_msb) }, + { "EmcFbioQuseDly", TOKEN(emc_fbio_quse_dly) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, + { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg1", TOKEN(emc_adr_cfg1) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "McLowLatencyConfig", TOKEN(mc_lowlatency_config) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgClktrim0", TOKEN(emc_cfg_clktrim0) }, + { "EmcCfgClktrim1", TOKEN(emc_cfg_clktrim1) }, + { "EmcCfgClktrim2", TOKEN(emc_cfg_clktrim2) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "AhbArbitrationXbarCtrl", TOKEN(ahb_arbitration_xbar_ctrl) }, + { "EmcDllXformDqs", TOKEN(emc_dll_xform_dqs) }, + { "EmcDllXformQUse", TOKEN(emc_dll_xform_quse) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalRefCnt", TOKEN(emc_zcal_ref_cnt) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcMrwZqInitDev0", TOKEN(emc_mrw_zq_init_dev0) }, + { "EmcMrwZqInitDev1", TOKEN(emc_mrw_zq_init_dev1) }, + { "EmcMrwZqInitWait", TOKEN(emc_mrw_zq_init_wait) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "ApbMiscGpXm2CfgAPadCtrl", TOKEN(apb_misc_gp_xm2cfga_pad_ctrl) }, + { "ApbMiscGpXm2CfgCPadCtrl2", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl2) }, + { "ApbMiscGpXm2CfgCPadCtrl", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl) }, + { "ApbMiscGpXm2CfgDPadCtrl2", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl2) }, + { "ApbMiscGpXm2CfgDPadCtrl", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl) }, + { "ApbMiscGpXm2ClkCfgPadCtrl", TOKEN(apb_misc_gp_xm2clkcfg_Pad_ctrl)}, + { "ApbMiscGpXm2CompPadCtrl", TOKEN(apb_misc_gp_xm2comp_pad_ctrl) }, + { "ApbMiscGpXm2VttGenPadCtrl", TOKEN(apb_misc_gp_xm2vttgen_pad_ctrl)}, + { NULL, 0, 0, NULL } +}; + +field_item s_nand_table_t20[] = { + { "ClockDivider", TOKEN(nand_clock_divider) }, + /* Note: NandTiming2 must appear before NandTiming, because NandTiming + * is a prefix of NandTiming2 and would otherwise match first. + */ + { "NandTiming2", TOKEN(nand_nand_timing2) }, + { "NandTiming", TOKEN(nand_nand_timing) }, + { "BlockSizeLog2", TOKEN(nand_block_size_log2) }, + { "PageSizeLog2", TOKEN(nand_page_size_log2) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t20[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t20 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t20[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t20 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t20[] = { + { "NandParams.", token_nand_params, + s_nand_table_t20, t20_set_dev_param }, + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t20, t20_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t20, t20_set_dev_param }, + + { NULL, 0, NULL } +}; diff --git a/t30/nvbctlib_t30.c b/t30/nvbctlib_t30.c new file mode 100644 index 0000000..da05ede --- /dev/null +++ b/t30/nvbctlib_t30.c @@ -0,0 +1,863 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t30.h" +#include "string.h" + +/* nvbctlib_t30.c: The implementation of the nvbctlib API for t30. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) return -ENODATA; \ + *data = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *data = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *data = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = data; \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +int +t30_set_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(nand, clock_divider); + CASE_SET_DEV_PARAM(nand, block_size_log2); + CASE_SET_DEV_PARAM(nand, page_size_log2); + CASE_SET_DEV_PARAM(nand, async_timing0); + CASE_SET_DEV_PARAM(nand, async_timing1); + CASE_SET_DEV_PARAM(nand, async_timing2); + CASE_SET_DEV_PARAM(nand, async_timing3); + CASE_SET_DEV_PARAM(nand, sddr_timing0); + CASE_SET_DEV_PARAM(nand, sddr_timing1); + CASE_SET_DEV_PARAM(nand, tddr_timing0); + CASE_SET_DEV_PARAM(nand, tddr_timing1); + CASE_SET_DEV_PARAM(nand, fbio_dqsib_dly_byte); + CASE_SET_DEV_PARAM(nand, fbio_quse_dly_byte); + CASE_SET_DEV_PARAM(nand, fbio_cfg_quse_late); + CASE_SET_DEV_PARAM(nand, disable_sync_ddr); + + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, sd_controller); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_get_dev_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(nand, clock_divider); + CASE_GET_DEV_PARAM(nand, block_size_log2); + CASE_GET_DEV_PARAM(nand, page_size_log2); + CASE_GET_DEV_PARAM(nand, async_timing0); + CASE_GET_DEV_PARAM(nand, async_timing1); + CASE_GET_DEV_PARAM(nand, async_timing2); + CASE_GET_DEV_PARAM(nand, async_timing3); + CASE_GET_DEV_PARAM(nand, sddr_timing0); + CASE_GET_DEV_PARAM(nand, sddr_timing1); + CASE_GET_DEV_PARAM(nand, tddr_timing0); + CASE_GET_DEV_PARAM(nand, tddr_timing1); + CASE_GET_DEV_PARAM(nand, fbio_dqsib_dly_byte); + CASE_GET_DEV_PARAM(nand, fbio_quse_dly_byte); + CASE_GET_DEV_PARAM(nand, fbio_cfg_quse_late); + CASE_GET_DEV_PARAM(nand, disable_sync_ddr); + + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, sd_controller); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_get_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_post_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(emc_clock_divider); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_emr2); + CASE_GET_SDRAM_PARAM(emc_emrs_emr3); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_clock_use_pll_mud); + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + CASE_GET_SDRAM_PARAM(emc_wext); + CASE_GET_SDRAM_PARAM(emc_ctt); + CASE_GET_SDRAM_PARAM(emc_ctt_duration); + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw1); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw2); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw3); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_cmd_q); + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_GET_SDRAM_PARAM(emc_dev_select); + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_GET_SDRAM_PARAM(emc_zcal_cold_boot_enable); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emrs); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emr2); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emr3); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_clken_override); + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_GET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_GET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2quse_pad_ctrl); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_GET_SDRAM_PARAM(mc_clken_override); + + DEFAULT(); + } + return 0; +} + +int +t30_set_sdram_param(build_image_context *context, + u_int32_t index, + parse_token token, + u_int32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_post_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(emc_clock_divider); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_quse_extra); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_emr2); + CASE_SET_SDRAM_PARAM(emc_emrs_emr3); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_clock_use_pll_mud); + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + CASE_SET_SDRAM_PARAM(emc_wext); + CASE_SET_SDRAM_PARAM(emc_ctt); + CASE_SET_SDRAM_PARAM(emc_ctt_duration); + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw1); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw2); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw3); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_cmd_q); + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_SET_SDRAM_PARAM(emc_dev_select); + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_SET_SDRAM_PARAM(emc_zcal_cold_boot_enable); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emrs); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emr2); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emr3); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_clken_override); + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_SET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_SET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2quse_pad_ctrl); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_SET_SDRAM_PARAM(mc_clken_override); + + DEFAULT(); + } + return 0; +} + +int +t30_getbl_param(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_setbl_param(u_int32_t set, + parse_token id, + u_int32_t *data, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_bct_get_value(parse_token id, u_int32_t *data, u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_reserved_offset: + *data = (u_int8_t *)&(samplebct.reserved) + - (u_int8_t *)&samplebct; + break; + + case token_bct_size: + *data = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *data = (u_int8_t *)&(samplebct.random_aes_blk) + - (u_int8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *data = sizeof(nvboot_config_table) - sizeof(nvboot_hash); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t30_bct_set_value(parse_token id, u_int32_t data, u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_bct_set_data(parse_token id, + u_int8_t *data, + u_int32_t length, + u_int8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + CASE_SET_DATA(crypto_hash, sizeof(nvboot_hash)); + + default: + return -ENODATA; + } + + return 0; +} + +void t30_init_bad_block_table(build_image_context *context) +{ + u_int32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +void t30_get_cbootimage_interf(bct_parse_interface *cbootimage_bct_interf) +{ + cbootimage_bct_interf->init_bad_block_table = t30_init_bad_block_table; + cbootimage_bct_interf->set_dev_param = t30_set_dev_param; + cbootimage_bct_interf->get_dev_param = t30_get_dev_param; + cbootimage_bct_interf->set_sdram_param = t30_set_sdram_param; + cbootimage_bct_interf->get_sdram_param = t30_get_sdram_param; + cbootimage_bct_interf->setbl_param = t30_setbl_param; + cbootimage_bct_interf->getbl_param = t30_getbl_param; + cbootimage_bct_interf->set_value = t30_bct_set_value; + cbootimage_bct_interf->get_value = t30_bct_get_value; + cbootimage_bct_interf->set_data = t30_bct_set_data; +} diff --git a/t30/nvboot_bct_t30.h b/t30/nvboot_bct_t30.h new file mode 100644 index 0000000..e2cf1c0 --- /dev/null +++ b/t30/nvboot_bct_t30.h @@ -0,0 +1,374 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef INCLUDED_NVBOOT_BCT_H +#define INCLUDED_NVBOOT_BCT_H + +#include <sys/types.h> +#include "nvboot_sdram_param_t30.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 506 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 3 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/** + * Defines the params that can be configured for NAND devices. + */ +typedef struct nvboot_nand_params_rec { + /** + * Specifies the clock divider for the PLL_P 432MHz source. + * If it is set to 18, then clock source to Nand controller is + * 432 / 18 = 24MHz. + */ + u_int8_t clock_divider; + + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 0 + */ + u_int32_t async_timing0; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 1 + */ + u_int32_t async_timing1; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 2 + */ + u_int32_t async_timing2; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 3 + */ + u_int32_t async_timing3; + /** + * Specifies the value to be programmed to Nand Sync DDR Timing + * Register 0 + */ + u_int32_t sddr_timing0; + /** + * Specifies the value to be programmed to Nand Sync DDR Timing + * Register 1 + */ + u_int32_t sddr_timing1; + /** + * Specifies the value to be programmed to Nand Toggle DDR Timing + * Register 0 + */ + u_int32_t tddr_timing0; + /** + * Specifies the value to be programmed to Nand Toggle DDR Timing + * Register 1 + */ + u_int32_t tddr_timing1; + /* Specifies the value to be programmed to FBIO_DQSIB_DELAY register */ + u_int8_t fbio_dqsib_dly_byte; + /* Specifies the value to be programmed to FBIO_DQUSE_DELAY register */ + u_int8_t fbio_quse_dly_byte; + /* Specifies the CFG_QUSE_LATE value to be programmed to FBIO + * configuration register */ + u_int8_t fbio_cfg_quse_late; + /* Specifies whether to enable sync DDR more or not */ + u_int8_t disable_sync_ddr; + + /* Specifies the block size in log2 bytes */ + u_int8_t block_size_log2; + + /* Specifies the page size in log2 bytes */ + u_int8_t page_size_log2; +} nvboot_nand_params; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines various sd controllers supported. */ +typedef enum { + /* Specifies Sdmmc 4 controller interface */ + nvboot_sdmmc_cntrl_4 = 0, + /* Specifies Sdmmc 3 controller interface */ + nvboot_sdmmc_cntrl_3 = 1, + nvboot_sdmmc_cntrl_num, + nvboot_sdmmc_cntrl_force32 = 0x7FFFFFFF +} nvboot_sdmmc_cntrl; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC + * controller runs at 432/18 = 24MHz. + */ + u_int8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + u_int8_t max_power_class_supported; + + /* Specifies the SD controller to be selected */ + nvboot_sdmmc_cntrl sd_controller; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be PLLC. */ + nvboot_spi_clock_source_pllc_out0, + + /* Specifies SPI clock source to be PLLM. */ + nvboot_spi_clock_source_pllm_out0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + nvboot_spi_clock_source clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + u_int8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + u_int8_t read_command_type_fast; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + u_int8_t size[64]; + /* Specifies optimized parameters for NAND */ + nvboot_nand_params nand_params; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies NAND. */ + nvboot_dev_type_nand, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + u_int32_t version; + u_int32_t start_blk; + u_int32_t start_page; + u_int32_t length; + u_int32_t load_addr; + u_int32_t entry_point; + u_int32_t attribute; + nvboot_hash crypto_hash; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + u_int32_t entries_used; + u_int8_t virtual_blk_size_log2; + u_int8_t block_size_log2; + u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_hash crypto_hash; + nvboot_hash random_aes_blk; + u_int32_t boot_data_version; + u_int32_t block_size_log2; + u_int32_t page_size_log2; + u_int32_t partition_size; + u_int32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + u_int32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + nvboot_badblock_table badblock_table; + u_int32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + u_int8_t enable_fail_back; + u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_H */ diff --git a/t30/nvboot_sdram_param_t30.h b/t30/nvboot_sdram_param_t30.h new file mode 100644 index 0000000..0979e69 --- /dev/null +++ b/t30/nvboot_sdram_param_t30.h @@ -0,0 +1,571 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the CPCON value for PllM */ + u_int32_t pllm_charge_pump_setup_ctrl; + /* Specifies the LPCON value for PllM */ + u_int32_t pllm_loop_filter_setup_ctrl; + /* Specifies the M value for PllM */ + u_int32_t pllm_input_divider; + /* Specifies the N value for PllM */ + u_int32_t pllm_feedback_divider; + /* Specifies the P value for PllM */ + u_int32_t pllm_post_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + u_int32_t pllm_stable_time; + + /* Specifies the divider for the EMC Clock Source */ + u_int32_t emc_clock_divider; + /* Specifies the PLL source for the EMC Clock Source */ + u_int32_t emc_clock_source; + /* + * Specifies the enable for using low jitter clock for + * the EMC Clock Source + */ + u_int32_t emc_clock_use_pll_mud; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + u_int32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + u_int32_t emc_auto_cal_config; + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + u_int32_t emc_auto_cal_wait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + u_int32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + u_int32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + u_int32_t emc_pin_extra_wait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + u_int32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + u_int32_t emc_rc; + /* Specifies the value for EMC_RFC */ + u_int32_t emc_rfc; + /* Specifies the value for EMC_RAS */ + u_int32_t emc_ras; + /* Specifies the value for EMC_RP */ + u_int32_t emc_rp; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + u_int32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + u_int32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + u_int32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + u_int32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + u_int32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + u_int32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + u_int32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + u_int32_t emc_wext; + /* Specifies the value for EMC_WDV */ + u_int32_t emc_wdv; + /* Specifies the value for EMC_QUSE */ + u_int32_t emc_quse; + /* Specifies the value for EMC_QRST */ + u_int32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + u_int32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + u_int32_t emc_rdv; + /* Specifies the value for EMC_CTT */ + u_int32_t emc_ctt; + /* Specifies the value for EMC_CTT_DURATION */ + u_int32_t emc_ctt_duration; + /* Specifies the value for EMC_REFRESH */ + u_int32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + u_int32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + u_int32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + u_int32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + u_int32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + u_int32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + u_int32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + u_int32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + u_int32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + u_int32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + u_int32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + u_int32_t emc_tcke; + /* Specifies the value for EMC_TFAW */ + u_int32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + u_int32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + u_int32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + u_int32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + u_int32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + u_int32_t emc_quse_extra; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + u_int32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + u_int32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + u_int32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + u_int32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + u_int32_t emc_mrs; + /* Specifies the value for EMC_EMRS */ + u_int32_t emc_emrs; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + u_int32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + u_int32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + u_int32_t emc_mrw3; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + u_int32_t emc_mrw_extra; + /* Specifies the programming to LPDDR2 Mode Register 1 at warm boot */ + u_int32_t emc_warm_boot_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at warm boot */ + u_int32_t emc_warm_boot_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at warm boot */ + u_int32_t emc_warm_boot_mrw3; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + u_int32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + u_int32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + u_int32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + u_int32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + u_int32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + u_int32_t emc_mrs_wait_cnt; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + u_int32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + u_int32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + u_int32_t emc_dbg; + /* Specifies the value for EMC_CMDQ */ + u_int32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + u_int32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + u_int32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + u_int32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + u_int32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + u_int32_t emc_cfg_dig_dll_period; + /* Specifies the vlaue of *DEV_SELECTN of various EMC registers */ + u_int32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + u_int32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + u_int32_t emc_dll_xform_dqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + u_int32_t emc_dll_xform_dqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + u_int32_t emc_dll_xform_dqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + u_int32_t emc_dll_xform_dqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + u_int32_t emc_dll_xform_dqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + u_int32_t emc_dll_xform_dqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + u_int32_t emc_dll_xform_dqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + u_int32_t emc_dll_xform_dqs7; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + u_int32_t emc_dll_xform_quse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + u_int32_t emc_dll_xform_quse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + u_int32_t emc_dll_xform_quse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + u_int32_t emc_dll_xform_quse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + u_int32_t emc_dll_xform_quse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + u_int32_t emc_dll_xform_quse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + u_int32_t emc_dll_xform_quse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + u_int32_t emc_dll_xform_quse7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + u_int32_t emc_dli_trim_tx_dqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + u_int32_t emc_dli_trim_tx_dqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + u_int32_t emc_dli_trim_tx_dqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + u_int32_t emc_dli_trim_tx_dqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + u_int32_t emc_dli_trim_tx_dqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + u_int32_t emc_dli_trim_tx_dqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + u_int32_t emc_dli_trim_tx_dqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + u_int32_t emc_dli_trim_tx_dqs7; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + u_int32_t emc_dll_xform_dq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + u_int32_t emc_dll_xform_dq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + u_int32_t emc_dll_xform_dq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + u_int32_t emc_dll_xform_dq3; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + u_int32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + u_int32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + u_int32_t emc_odt_read; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + u_int32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + u_int32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + u_int32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + u_int32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + u_int32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + u_int32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + u_int32_t emc_zcal_init_wait; + /* Specifies the enable for ZQ calibration at cold boot */ + u_int32_t emc_zcal_cold_boot_enable; + /* Specifies the enable for ZQ calibration at warm boot */ + u_int32_t emc_zcal_warm_boot_enable; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + *on warmboot + */ + /* Is issued to both devices separately */ + u_int32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + u_int32_t emc_zqcal_ddr3_warm_boot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + u_int32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + u_int32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + u_int32_t emc_mrs_reset_dll_wait; + /* + * Specifies the first of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr2; + /* + * Specifies the second of two EMRS commands to initialize mode + * registers + */ + u_int32_t emc_emrs_emr3; + /* Specifies the extra MRS command to initialize mode registers */ + u_int32_t emc_mrs_extra; + /* Specifies the programming to DDR3 Mode Register 0 at warm boot */ + u_int32_t emc_warm_boot_mrs; + /* Specifies the programming to DDR3 Mode Register 1 at warm boot */ + u_int32_t emc_warm_boot_emrs; + /* Specifies the programming to DDR3 Mode Register 2 at warm boot */ + u_int32_t emc_warm_boot_emr2; + /* Specifies the programming to DDR3 Mode Register 3 at warm boot */ + u_int32_t emc_warm_boot_emr3; + /* Specifies the extra MRS command at warm boot */ + u_int32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + u_int32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + u_int32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + u_int32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + u_int32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + u_int32_t emc_clken_override; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + u_int32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + u_int32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + u_int32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + u_int32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + u_int32_t pmc_vddp_sel; + /* Specifies the value for PMC_DDR_PWR */ + u_int32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + u_int32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD_REQ */ + u_int32_t pmc_io_dpd_req; + /* Specifies the value for PMC_E_NO_VTTGEN */ + u_int32_t pmc_eno_vtt_gen; + /* Specifies the value for PMC_NO_IOPOWER */ + u_int32_t pmc_no_io_power; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + u_int32_t emc_xm2cmd_pad_ctrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + u_int32_t emc_xm2cmd_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + u_int32_t emc_xm2dqs_pad_ctrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + u_int32_t emc_xm2dqs_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + u_int32_t emc_xm2dqs_pad_ctrl3; + /* Specifies the value for EMC_XM2DQPADCTRL */ + u_int32_t emc_xm2dq_pad_ctrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + u_int32_t emc_xm2dq_pad_ctrl2; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + u_int32_t emc_xm2clk_pad_ctrl; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + u_int32_t emc_xm2comp_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + u_int32_t emc_xm2vttgen_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + u_int32_t emc_xm2vttgen_pad_ctrl2; + /* Specifies the value for EMC_XM2QUSEPADCTRL */ + u_int32_t emc_xm2quse_pad_ctrl; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + u_int32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + u_int32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + u_int32_t mc_emem_adr_cfg_dev1; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + u_int32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + u_int32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + u_int32_t mc_emem_arb_outstanding_req; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + u_int32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + u_int32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + u_int32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + u_int32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + u_int32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + u_int32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + u_int32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + u_int32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + u_int32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + u_int32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + u_int32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + u_int32_t mc_emem_arb_timing_w2r; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + u_int32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + u_int32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + u_int32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + u_int32_t mc_emem_arb_misc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + u_int32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + u_int32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_RSV */ + u_int32_t mc_emem_arb_rsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + u_int32_t mc_clken_override; + + /* End of generated code by warmboot_code_gen */ +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H */ + diff --git a/t30/parse_t30.c b/t30/parse_t30.c new file mode 100644 index 0000000..94cedc2 --- /dev/null +++ b/t30/parse_t30.c @@ -0,0 +1,363 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * parse_t30.h - Definitions for the dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t30.h" + +enum_item s_devtype_table_t30[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "NvBootDevType_Nand", nvboot_dev_type_nand }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { "Nand", nvboot_dev_type_nand }, + + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t30[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t30[] = { + { + "NvBootSpiClockSource_PllPOut0", + nvboot_spi_clock_source_pllp_out0 + }, + { + "NvBootSpiClockSource_PllCOut0", + nvboot_spi_clock_source_pllc_out0 + }, + { + "NvBootSpiClockSource_PllMOut0", + nvboot_spi_clock_source_pllm_out0 + }, + { + "NvBootSpiClockSource_ClockM", + nvboot_spi_clock_source_clockm + }, + + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + + + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t30[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t30[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t30 }, + + { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, + { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "EmcClockDivider", TOKEN(emc_clock_divider) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, + { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcClockUsePllMUD", TOKEN(emc_clock_use_pll_mud) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcCtt", TOKEN(emc_ctt) }, + { "EmcCttDuration", TOKEN(emc_ctt_duration) }, + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrw1", TOKEN(emc_warm_boot_mrw1) }, + { "EmcWarmBootMrw2", TOKEN(emc_warm_boot_mrw2) }, + { "EmcWarmBootMrw3", TOKEN(emc_warm_boot_mrw3) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + { "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) }, + { "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) }, + { "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) }, + { "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) }, + { "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) }, + { "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) }, + { "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) }, + { "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) }, + { "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) }, + { "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) }, + { "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) }, + { "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) }, + { "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) }, + { "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) }, + { "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) }, + { "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) }, + { "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) }, + { "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) }, + { "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) }, + { "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) }, + { "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) }, + { "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) }, + { "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) }, + { "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) }, + { "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) }, + { "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) }, + { "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) }, + { "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalColdBootEnable", TOKEN(emc_zcal_cold_boot_enable) }, + { "EmcZcalWarmBootEnable", TOKEN(emc_zcal_warm_boot_enable) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrs", TOKEN(emc_warm_boot_mrs) }, + { "EmcWarmBootEmrs", TOKEN(emc_warm_boot_emrs) }, + { "EmcWarmBootEmr2", TOKEN(emc_warm_boot_emr2) }, + { "EmcWarmBootEmr3", TOKEN(emc_warm_boot_emr3) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpdReq", TOKEN(pmc_io_dpd_req) }, + { "PmcENoVttGen", TOKEN(pmc_eno_vtt_gen) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + { "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) }, + { "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) }, + { "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) }, + { "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) }, + { "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) }, + { "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) }, + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) }, + { "EmcXm2QUsePadCtrl", TOKEN(emc_xm2quse_pad_ctrl) }, + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + { "McClkenOverride", TOKEN(mc_clken_override) }, + { NULL, 0, 0, NULL } +}; + +field_item s_nand_table_t30[] = { + + /* Note: NandTiming2 must appear before NandTiming, because NandTiming + * is a prefix of NandTiming2 and would otherwise match first. + */ + { "ClockDivider", TOKEN(nand_clock_divider) }, + { "BlockSizeLog2", TOKEN(nand_block_size_log2) }, + { "PageSizeLog2", TOKEN(nand_page_size_log2) }, + { "NandAsyncTiming3", TOKEN(nand_async_timing3) }, + { "NandAsyncTiming2", TOKEN(nand_async_timing2) }, + { "NandAsyncTiming1", TOKEN(nand_async_timing1) }, + { "NandAsyncTiming0", TOKEN(nand_async_timing0) }, + { "DisableSyncDDR", TOKEN(nand_disable_sync_ddr) }, + { "NandSDDRTiming1", TOKEN(nand_sddr_timing1) }, + { "NandSDDRTiming0", TOKEN(nand_sddr_timing0) }, + { "NandTDDRTiming1", TOKEN(nand_tddr_timing1) }, + { "NandTDDRTiming0", TOKEN(nand_tddr_timing0) }, + { "NandFbioDqsibDlyByte", TOKEN(nand_fbio_dqsib_dly_byte) }, + { "NandFbioQuseDlyByte", TOKEN(nand_fbio_quse_dly_byte) }, + { "NandFbioCfgQuseLate", TOKEN(nand_fbio_cfg_quse_late) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t30[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t30 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "SdController", TOKEN(sdmmc_sd_controller) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t30[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t30 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t30[] = { + { "NandParams.", token_nand_params, + s_nand_table_t30, t30_set_dev_param }, + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t30, t30_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t30, t30_set_dev_param }, + + { NULL, 0, NULL } +}; |