Add the SDRAM parameters support for cbootimage.

Change-Id: I15a6cacbf8b19b16b4bcccd6ea0e2740cacadee3

BUG=None.
TEST=Test with config file.

Review URL: http://codereview.chromium.org/6625006
Patch from Peer Chen <pchen@nvidia.com>.

6 files changed, 904 insertions, 0 deletions

diff --git a/nvbctlib.h b/nvbctlib.h
index 51bb3bb..9138b42 100644
--- a/nvbctlib.h
+++ b/nvbctlib.h
@@ -65,6 +65,7 @@ typedef enum {
 	nvbct_lib_id_dev_type_nand,
 	nvbct_lib_id_dev_type_sdmmc,
 	nvbct_lib_id_dev_type_spi,
+	nvbct_lib_id_num_sdram_sets,
 
 	nvbct_lib_id_nand_clock_divider,
 	nvbct_lib_id_nand_nand_timing,
@@ -93,6 +94,114 @@ typedef enum {
 	nvbct_lib_id_bl_attribute,
 	nvbct_lib_id_bl_crypto_hash,
 
+	nvbct_lib_id_memory_type_none,
+	nvbct_lib_id_memory_type_ddr2,
+	nvbct_lib_id_memory_type_ddr,
+	nvbct_lib_id_memory_type_lpddr2,
+	nvbct_lib_id_memory_type_lpddr,
+
+	nvbct_lib_id_sdram_memory_type,
+	nvbct_lib_id_sdram_pllm_charge_pump_setup_ctrl,
+	nvbct_lib_id_sdram_pllm_loop_filter_setup_ctrl,
+	nvbct_lib_id_sdram_pllm_input_divider,
+	nvbct_lib_id_sdram_pllm_feedback_divider,
+	nvbct_lib_id_sdram_pllm_post_divider,
+	nvbct_lib_id_sdram_pllm_stable_time,
+	nvbct_lib_id_sdram_emc_clock_divider,
+	nvbct_lib_id_sdram_emc_auto_cal_interval,
+	nvbct_lib_id_sdram_emc_auto_cal_config,   
+	nvbct_lib_id_sdram_emc_auto_cal_wait,
+	nvbct_lib_id_sdram_emc_pin_program_wait,
+	nvbct_lib_id_sdram_emc_rc,
+	nvbct_lib_id_sdram_emc_rfc,
+	nvbct_lib_id_sdram_emc_ras,
+	nvbct_lib_id_sdram_emc_rp,
+	nvbct_lib_id_sdram_emc_r2w,
+	nvbct_lib_id_sdram_emc_w2r,
+	nvbct_lib_id_sdram_emc_r2p,
+	nvbct_lib_id_sdram_emc_w2p,
+	nvbct_lib_id_sdram_emc_rd_rcd,
+	nvbct_lib_id_sdram_emc_wr_rcd,
+	nvbct_lib_id_sdram_emc_rrd,
+	nvbct_lib_id_sdram_emc_rext,
+	nvbct_lib_id_sdram_emc_wdv,
+	nvbct_lib_id_sdram_emc_quse,
+	nvbct_lib_id_sdram_emc_qrst,
+	nvbct_lib_id_sdram_emc_qsafe,
+	nvbct_lib_id_sdram_emc_rdv,
+	nvbct_lib_id_sdram_emc_refresh,
+	nvbct_lib_id_sdram_emc_burst_refresh_num,
+	nvbct_lib_id_sdram_emc_pdex2wr,
+	nvbct_lib_id_sdram_emc_pdex2rd,
+	nvbct_lib_id_sdram_emc_pchg2pden,
+	nvbct_lib_id_sdram_emc_act2pden,
+	nvbct_lib_id_sdram_emc_ar2pden,
+	nvbct_lib_id_sdram_emc_rw2pden,
+	nvbct_lib_id_sdram_emc_txsr,
+	nvbct_lib_id_sdram_emc_tcke,
+	nvbct_lib_id_sdram_emc_tfaw,
+	nvbct_lib_id_sdram_emc_trpab,
+	nvbct_lib_id_sdram_emc_tclkstable,
+	nvbct_lib_id_sdram_emc_tclkstop,
+	nvbct_lib_id_sdram_emc_trefbw,
+	nvbct_lib_id_sdram_emc_quse_extra,
+	nvbct_lib_id_sdram_emc_fbio_cfg1,
+	nvbct_lib_id_sdram_emc_fbio_dqsib_dly,
+	nvbct_lib_id_sdram_emc_fbio_dqsib_dly_msb,
+	nvbct_lib_id_sdram_emc_fbio_quse_dly,
+	nvbct_lib_id_sdram_emc_fbio_quse_dly_msb,
+	nvbct_lib_id_sdram_emc_fbio_cfg5,
+	nvbct_lib_id_sdram_emc_fbio_cfg6,
+	nvbct_lib_id_sdram_emc_fbio_spare,
+	nvbct_lib_id_sdram_emc_mrs,
+	nvbct_lib_id_sdram_emc_emrs,
+	nvbct_lib_id_sdram_emc_mrw1,
+	nvbct_lib_id_sdram_emc_mrw2,
+	nvbct_lib_id_sdram_emc_mrw3,
+	nvbct_lib_id_sdram_emc_mrw_reset_command,
+	nvbct_lib_id_sdram_emc_mrw_reset_ninit_wait,
+	nvbct_lib_id_sdram_emc_adr_cfg,
+	nvbct_lib_id_sdram_emc_adr_cfg1,
+	nvbct_lib_id_sdram_mc_emem_Cfg,
+	nvbct_lib_id_sdram_mc_lowlatency_config,
+	nvbct_lib_id_sdram_emc_cfg,
+	nvbct_lib_id_sdram_emc_cfg2,
+	nvbct_lib_id_sdram_emc_dbg,
+	nvbct_lib_id_sdram_ahb_arbitration_xbar_ctrl,
+	nvbct_lib_id_sdram_emc_cfg_dig_dll,
+	nvbct_lib_id_sdram_emc_dll_xform_dqs,
+	nvbct_lib_id_sdram_emc_dll_xform_quse,
+	nvbct_lib_id_sdram_warm_boot_wait,
+	nvbct_lib_id_sdram_emc_ctt_term_ctrl,
+	nvbct_lib_id_sdram_emc_odt_write,
+	nvbct_lib_id_sdram_emc_odt_read,
+	nvbct_lib_id_sdram_emc_zcal_ref_cnt,
+	nvbct_lib_id_sdram_emc_zcal_wait_cnt,
+	nvbct_lib_id_sdram_emc_zcal_mrw_cmd,
+	nvbct_lib_id_sdram_emc_mrs_reset_dll,
+	nvbct_lib_id_sdram_emc_mrw_zq_init_dev0,
+	nvbct_lib_id_sdram_emc_mrw_zq_init_dev1,
+	nvbct_lib_id_sdram_emc_mrw_zq_init_wait,
+	nvbct_lib_id_sdram_emc_mrs_reset_dll_wait,
+	nvbct_lib_id_sdram_emc_emrs_emr2,
+	nvbct_lib_id_sdram_emc_emrs_emr3,
+	nvbct_lib_id_sdram_emc_emrs_ddr2_dll_enable,
+	nvbct_lib_id_sdram_emc_mrs_ddr2_dll_reset,
+	nvbct_lib_id_sdram_emc_emrs_ddr2_ocd_calib,
+	nvbct_lib_id_sdram_emc_ddr2_wait,
+	nvbct_lib_id_sdram_emc_cfg_clktrim0,
+	nvbct_lib_id_sdram_emc_cfg_clktrim1,
+	nvbct_lib_id_sdram_emc_cfg_clktrim2,
+	nvbct_lib_id_sdram_pmc_ddr_pwr,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2cfga_pad_ctrl,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl2,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl2,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2clkcfg_Pad_ctrl,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2comp_pad_ctrl,
+	nvbct_lib_id_sdram_apb_misc_gp_xm2vttgen_pad_ctrl,
+
 	nvbct_lib_id_max,
 
 	nvbct_lib_id_force32 = 0x7fffffff
@@ -108,6 +217,15 @@ typedef int  (*nvbct_lib_set_dev_param)(u_int32_t set,
 					u_int32_t data,
 					u_int8_t *bct);
 
+typedef int  (*nvbct_lib_get_sdram_param)(u_int32_t set,
+					nvbct_lib_id id,
+					u_int32_t *data,
+					u_int8_t *bct);
+typedef int  (*nvbct_lib_set_sdram_param)(u_int32_t set,
+					nvbct_lib_id id,
+					u_int32_t data,
+					u_int8_t *bct);
+
 typedef int (*nvbct_lib_get_bl_param)(u_int32_t set,
 					nvbct_lib_id id,
 					u_int32_t *data,
@@ -153,6 +271,9 @@ typedef struct nvbct_lib_fns_rec
 
 	nvbct_lib_get_dev_param getdev_param;
 	nvbct_lib_set_dev_param setdev_param;
+
+	nvbct_lib_get_sdram_param get_sdram_params;
+	nvbct_lib_set_sdram_param set_sdram_params;
 } nvbct_lib_fns;
 
 void nvbct_lib_get_fns(nvbct_lib_fns *fns);
diff --git a/nvbctlib_ap20.c b/nvbctlib_ap20.c
index b1a9024..c2ba2c2 100644
--- a/nvbctlib_ap20.c
+++ b/nvbctlib_ap20.c
@@ -28,6 +28,16 @@
 /* nvbctlib_ap20.c: The implementation of the nvbctlib API for AP20. */
 
 /* Definitions that simplify the code which follows. */
+#define CASE_GET_SDRAM_PARAM(x) \
+case nvbct_lib_id_sdram_##x:\
+	*data = bct_ptr->sdram_params[set].x; \
+	break
+
+#define CASE_SET_SDRAM_PARAM(x) \
+case nvbct_lib_id_sdram_##x:\
+	bct_ptr->sdram_params[set].x = data; \
+	break
+
 #define CASE_GET_DEV_PARAM(dev, x) \
 case nvbct_lib_id_##dev##_##x:\
 	*data = bct_ptr->dev_params[set].dev##_params.x; \
@@ -83,6 +93,254 @@ case nvbct_lib_id_##id:\
 	break
 
 static int
+get_sdram_params(u_int32_t set,
+		nvbct_lib_id id,
+		u_int32_t *data,
+		u_int8_t *bct)
+{
+	nvboot_config_table *bct_ptr = (nvboot_config_table*)bct;
+
+	if (set >= NVBOOT_BCT_MAX_SDRAM_SETS)
+		return ENODATA;
+	if (data == NULL || bct == NULL)
+		return -ENODATA;
+
+	switch (id) {
+
+	CASE_GET_SDRAM_PARAM(memory_type);
+	CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl);
+	CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl);
+	CASE_GET_SDRAM_PARAM(pllm_input_divider);
+	CASE_GET_SDRAM_PARAM(pllm_feedback_divider);
+	CASE_GET_SDRAM_PARAM(pllm_post_divider);
+	CASE_GET_SDRAM_PARAM(pllm_stable_time);
+	CASE_GET_SDRAM_PARAM(emc_clock_divider);
+	CASE_GET_SDRAM_PARAM(emc_auto_cal_interval);
+	CASE_GET_SDRAM_PARAM(emc_auto_cal_config);   
+	CASE_GET_SDRAM_PARAM(emc_auto_cal_wait);
+	CASE_GET_SDRAM_PARAM(emc_pin_program_wait);
+	CASE_GET_SDRAM_PARAM(emc_rc);
+	CASE_GET_SDRAM_PARAM(emc_rfc);
+	CASE_GET_SDRAM_PARAM(emc_ras);
+	CASE_GET_SDRAM_PARAM(emc_rp);
+	CASE_GET_SDRAM_PARAM(emc_r2w);
+	CASE_GET_SDRAM_PARAM(emc_w2r);
+	CASE_GET_SDRAM_PARAM(emc_r2p);
+	CASE_GET_SDRAM_PARAM(emc_w2p);
+	CASE_GET_SDRAM_PARAM(emc_rd_rcd);
+	CASE_GET_SDRAM_PARAM(emc_wr_rcd);
+	CASE_GET_SDRAM_PARAM(emc_rrd);
+	CASE_GET_SDRAM_PARAM(emc_rext);
+	CASE_GET_SDRAM_PARAM(emc_wdv);
+	CASE_GET_SDRAM_PARAM(emc_quse);
+	CASE_GET_SDRAM_PARAM(emc_qrst);
+	CASE_GET_SDRAM_PARAM(emc_qsafe);
+	CASE_GET_SDRAM_PARAM(emc_rdv);
+	CASE_GET_SDRAM_PARAM(emc_refresh);
+	CASE_GET_SDRAM_PARAM(emc_burst_refresh_num);
+	CASE_GET_SDRAM_PARAM(emc_pdex2wr);
+	CASE_GET_SDRAM_PARAM(emc_pdex2rd);
+	CASE_GET_SDRAM_PARAM(emc_pchg2pden);
+	CASE_GET_SDRAM_PARAM(emc_act2pden);
+	CASE_GET_SDRAM_PARAM(emc_ar2pden);
+	CASE_GET_SDRAM_PARAM(emc_rw2pden);
+	CASE_GET_SDRAM_PARAM(emc_txsr);
+	CASE_GET_SDRAM_PARAM(emc_tcke);
+	CASE_GET_SDRAM_PARAM(emc_tfaw);
+	CASE_GET_SDRAM_PARAM(emc_trpab);
+	CASE_GET_SDRAM_PARAM(emc_tclkstable);
+	CASE_GET_SDRAM_PARAM(emc_tclkstop);
+	CASE_GET_SDRAM_PARAM(emc_trefbw);
+	CASE_GET_SDRAM_PARAM(emc_quse_extra);
+	CASE_GET_SDRAM_PARAM(emc_fbio_cfg1);
+	CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly);
+	CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb);
+	CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly);
+	CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb);
+	CASE_GET_SDRAM_PARAM(emc_fbio_cfg5);
+	CASE_GET_SDRAM_PARAM(emc_fbio_cfg6);
+	CASE_GET_SDRAM_PARAM(emc_fbio_spare);
+	CASE_GET_SDRAM_PARAM(emc_mrs);
+	CASE_GET_SDRAM_PARAM(emc_emrs);
+	CASE_GET_SDRAM_PARAM(emc_mrw1);
+	CASE_GET_SDRAM_PARAM(emc_mrw2);
+	CASE_GET_SDRAM_PARAM(emc_mrw3);
+	CASE_GET_SDRAM_PARAM(emc_mrw_reset_command);
+	CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
+	CASE_GET_SDRAM_PARAM(emc_adr_cfg);
+	CASE_GET_SDRAM_PARAM(emc_adr_cfg1);
+	CASE_GET_SDRAM_PARAM(mc_emem_Cfg);
+	CASE_GET_SDRAM_PARAM(mc_lowlatency_config);
+	CASE_GET_SDRAM_PARAM(emc_cfg);
+	CASE_GET_SDRAM_PARAM(emc_cfg2);
+	CASE_GET_SDRAM_PARAM(emc_dbg);
+	CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl);
+	CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll);
+	CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs);
+	CASE_GET_SDRAM_PARAM(emc_dll_xform_quse);
+	CASE_GET_SDRAM_PARAM(warm_boot_wait);
+	CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl);
+	CASE_GET_SDRAM_PARAM(emc_odt_write);
+	CASE_GET_SDRAM_PARAM(emc_odt_read);
+	CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt);
+	CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt);
+	CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd);
+	CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll);
+	CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0);
+	CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1);
+	CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait);
+	CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
+	CASE_GET_SDRAM_PARAM(emc_emrs_emr2);
+	CASE_GET_SDRAM_PARAM(emc_emrs_emr3);
+	CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
+	CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
+	CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
+	CASE_GET_SDRAM_PARAM(emc_ddr2_wait);
+	CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0);
+	CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1);
+	CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2);
+	CASE_GET_SDRAM_PARAM(pmc_ddr_pwr);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl);
+	CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl);
+
+	default:
+		return -ENODATA;
+	}
+
+	return 0;
+
+}
+
+static int
+set_sdram_params(u_int32_t set,
+		nvbct_lib_id id,
+		u_int32_t data,
+		u_int8_t *bct)
+{
+	nvboot_config_table *bct_ptr = (nvboot_config_table*)bct;
+
+	if (set >= NVBOOT_BCT_MAX_SDRAM_SETS)
+		return ENODATA;
+	if (bct == NULL)
+		return -ENODATA;
+
+	switch (id) {
+
+	CASE_SET_SDRAM_PARAM(memory_type);
+	CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl);
+	CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl);
+	CASE_SET_SDRAM_PARAM(pllm_input_divider);
+	CASE_SET_SDRAM_PARAM(pllm_feedback_divider);
+	CASE_SET_SDRAM_PARAM(pllm_post_divider);
+	CASE_SET_SDRAM_PARAM(pllm_stable_time);
+	CASE_SET_SDRAM_PARAM(emc_clock_divider);
+	CASE_SET_SDRAM_PARAM(emc_auto_cal_interval);
+	CASE_SET_SDRAM_PARAM(emc_auto_cal_config);   
+	CASE_SET_SDRAM_PARAM(emc_auto_cal_wait);
+	CASE_SET_SDRAM_PARAM(emc_pin_program_wait);
+	CASE_SET_SDRAM_PARAM(emc_rc);
+	CASE_SET_SDRAM_PARAM(emc_rfc);
+	CASE_SET_SDRAM_PARAM(emc_ras);
+	CASE_SET_SDRAM_PARAM(emc_rp);
+	CASE_SET_SDRAM_PARAM(emc_r2w);
+	CASE_SET_SDRAM_PARAM(emc_w2r);
+	CASE_SET_SDRAM_PARAM(emc_r2p);
+	CASE_SET_SDRAM_PARAM(emc_w2p);
+	CASE_SET_SDRAM_PARAM(emc_rd_rcd);
+	CASE_SET_SDRAM_PARAM(emc_wr_rcd);
+	CASE_SET_SDRAM_PARAM(emc_rrd);
+	CASE_SET_SDRAM_PARAM(emc_rext);
+	CASE_SET_SDRAM_PARAM(emc_wdv);
+	CASE_SET_SDRAM_PARAM(emc_quse);
+	CASE_SET_SDRAM_PARAM(emc_qrst);
+	CASE_SET_SDRAM_PARAM(emc_qsafe);
+	CASE_SET_SDRAM_PARAM(emc_rdv);
+	CASE_SET_SDRAM_PARAM(emc_refresh);
+	CASE_SET_SDRAM_PARAM(emc_burst_refresh_num);
+	CASE_SET_SDRAM_PARAM(emc_pdex2wr);
+	CASE_SET_SDRAM_PARAM(emc_pdex2rd);
+	CASE_SET_SDRAM_PARAM(emc_pchg2pden);
+	CASE_SET_SDRAM_PARAM(emc_act2pden);
+	CASE_SET_SDRAM_PARAM(emc_ar2pden);
+	CASE_SET_SDRAM_PARAM(emc_rw2pden);
+	CASE_SET_SDRAM_PARAM(emc_txsr);
+	CASE_SET_SDRAM_PARAM(emc_tcke);
+	CASE_SET_SDRAM_PARAM(emc_tfaw);
+	CASE_SET_SDRAM_PARAM(emc_trpab);
+	CASE_SET_SDRAM_PARAM(emc_tclkstable);
+	CASE_SET_SDRAM_PARAM(emc_tclkstop);
+	CASE_SET_SDRAM_PARAM(emc_trefbw);
+	CASE_SET_SDRAM_PARAM(emc_quse_extra);
+	CASE_SET_SDRAM_PARAM(emc_fbio_cfg1);
+	CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly);
+	CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb);
+	CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly);
+	CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly_msb);
+	CASE_SET_SDRAM_PARAM(emc_fbio_cfg5);
+	CASE_SET_SDRAM_PARAM(emc_fbio_cfg6);
+	CASE_SET_SDRAM_PARAM(emc_fbio_spare);
+	CASE_SET_SDRAM_PARAM(emc_mrs);
+	CASE_SET_SDRAM_PARAM(emc_emrs);
+	CASE_SET_SDRAM_PARAM(emc_mrw1);
+	CASE_SET_SDRAM_PARAM(emc_mrw2);
+	CASE_SET_SDRAM_PARAM(emc_mrw3);
+	CASE_SET_SDRAM_PARAM(emc_mrw_reset_command);
+	CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
+	CASE_SET_SDRAM_PARAM(emc_adr_cfg);
+	CASE_SET_SDRAM_PARAM(emc_adr_cfg1);
+	CASE_SET_SDRAM_PARAM(mc_emem_Cfg);
+	CASE_SET_SDRAM_PARAM(mc_lowlatency_config);
+	CASE_SET_SDRAM_PARAM(emc_cfg);
+	CASE_SET_SDRAM_PARAM(emc_cfg2);
+	CASE_SET_SDRAM_PARAM(emc_dbg);
+	CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl);
+	CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll);
+	CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs);
+	CASE_SET_SDRAM_PARAM(emc_dll_xform_quse);
+	CASE_SET_SDRAM_PARAM(warm_boot_wait);
+	CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl);
+	CASE_SET_SDRAM_PARAM(emc_odt_write);
+	CASE_SET_SDRAM_PARAM(emc_odt_read);
+	CASE_SET_SDRAM_PARAM(emc_zcal_ref_cnt);
+	CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt);
+	CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd);
+	CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll);
+	CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev0);
+	CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev1);
+	CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_wait);
+	CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
+	CASE_SET_SDRAM_PARAM(emc_emrs_emr2);
+	CASE_SET_SDRAM_PARAM(emc_emrs_emr3);
+	CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
+	CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
+	CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
+	CASE_SET_SDRAM_PARAM(emc_ddr2_wait);
+	CASE_SET_SDRAM_PARAM(emc_cfg_clktrim0);
+	CASE_SET_SDRAM_PARAM(emc_cfg_clktrim1);
+	CASE_SET_SDRAM_PARAM(emc_cfg_clktrim2);
+	CASE_SET_SDRAM_PARAM(pmc_ddr_pwr);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl);
+	CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl);
+
+	default:
+		return -ENODATA;
+	}
+
+	return 0;
+}
+static int
 getdev_param(u_int32_t set,
 		nvbct_lib_id id,
 		u_int32_t *data,
@@ -251,6 +509,7 @@ bct_get_value(nvbct_lib_id id, u_int32_t *data, u_int8_t *bct)
 	CASE_GET_NVU32(page_size_log2);
 	CASE_GET_NVU32(partition_size);
 	CASE_GET_NVU32(num_param_sets);
+	CASE_GET_NVU32(num_sdram_sets);
 	CASE_GET_NVU32(bootloader_used);
 
 	/*
@@ -294,6 +553,12 @@ bct_get_value(nvbct_lib_id id, u_int32_t *data, u_int8_t *bct)
 	CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot);
 	CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot);
 
+	CASE_GET_CONST_PREFIX(memory_type_none, nvboot);
+	CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot);
+	CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot);
+	CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot);
+	CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot);
+
 	default:
 		return -ENODATA;
 	}
@@ -317,6 +582,7 @@ bct_set_value(nvbct_lib_id id, u_int32_t  data, u_int8_t *bct)
 	CASE_SET_NVU32(page_size_log2);
 	CASE_SET_NVU32(partition_size);
 	CASE_SET_NVU32(num_param_sets);
+	CASE_SET_NVU32(num_sdram_sets);
 	CASE_SET_NVU32(bootloader_used);
 
 	default:
@@ -379,4 +645,6 @@ nvbct_lib_get_fns(nvbct_lib_fns *fns)
 	fns->getdev_param = getdev_param;
 	fns->setdev_param = setdev_param;
 
+	fns->get_sdram_params = get_sdram_params;
+	fns->set_sdram_params = set_sdram_params;
 }
diff --git a/parse.c b/parse.c
index babda04..49d7b4a 100644
--- a/parse.c
+++ b/parse.c
@@ -80,6 +80,8 @@ static char
 *parse_end_state(char *statement, char *uname, int chars_remaining);
 static int
 parse_dev_param(build_image_context *context, parse_token token, char *rest);
+static int
+parse_sdram_param(build_image_context *context, parse_token token, char *rest);
 
 static int process_statement(build_image_context *context, char *statement);
 
@@ -143,6 +145,231 @@ static enum_item s_spi_clock_source_table[] =
 	{ NULL, 0 }
 };
 
+static enum_item s_nvboot_memory_type_table[] =
+{
+	{ "NvBootMemoryType_None", nvbct_lib_id_memory_type_none },
+	{ "NvBootMemoryType_Ddr2", nvbct_lib_id_memory_type_ddr2 },
+	{ "NvBootMemoryType_Ddr", nvbct_lib_id_memory_type_ddr },
+	{ "NvBootMemoryType_LpDdr2", nvbct_lib_id_memory_type_lpddr2 },
+	{ "NvBootMemoryType_LpDdr", nvbct_lib_id_memory_type_lpddr },
+
+	{ "None", nvbct_lib_id_memory_type_none },
+	{ "Ddr2", nvbct_lib_id_memory_type_ddr2 },
+	{ "Ddr", nvbct_lib_id_memory_type_ddr },
+	{ "LpDdr2", nvbct_lib_id_memory_type_lpddr2 },
+	{ "LpDdr", nvbct_lib_id_memory_type_lpddr },
+
+	{ NULL, 0 }
+};
+
+static field_item s_sdram_field_table[] = 
+{
+	{ "MemoryType", token_memory_type,
+		field_type_enum,  s_nvboot_memory_type_table },
+	{ "PllMChargePumpSetupControl", token_pllm_charge_pump_setup_ctrl,
+		field_type_u32,  NULL },
+	{ "PllMLoopFilterSetupControl", token_pllm_loop_filter_setup_ctrl,
+		field_type_u32,  NULL },
+	{ "PllMInputDivider", token_pllm_input_divider,
+		field_type_u32,  NULL },
+	{ "PllMFeedbackDivider", token_pllm_feedback_divider,
+		field_type_u32,  NULL },
+	{ "PllMPostDivider", token_pllm_post_divider,
+		field_type_u32,  NULL },
+	{ "PllMStableTime", token_pllm_stable_time,
+		field_type_u32,  NULL },
+	{ "EmcClockDivider", token_emc_clock_divider,
+		field_type_u32,  NULL },
+	{ "EmcAutoCalInterval", token_emc_auto_cal_interval,
+		field_type_u32,  NULL },
+	{ "EmcAutoCalConfig", token_emc_auto_cal_config,
+		field_type_u32,  NULL },
+	{ "EmcAutoCalWait", token_emc_auto_cal_wait,
+		field_type_u32,  NULL },
+	{ "EmcPinProgramWait", token_emc_pin_program_wait,
+		field_type_u32,  NULL },
+	{ "EmcRc", token_emc_rc,
+		field_type_u32,  NULL },
+	{ "EmcRfc", token_emc_rfc,
+		field_type_u32,  NULL },
+	{ "EmcRas", token_emc_ras,
+		field_type_u32,  NULL },
+	{ "EmcRp", token_emc_rp,
+		field_type_u32,  NULL },
+	{ "EmcR2w", token_emc_r2w,
+		field_type_u32,  NULL },
+	{ "EmcW2r", token_emc_w2r,
+		field_type_u32,  NULL },
+	{ "EmcR2p", token_emc_r2p,
+		field_type_u32,  NULL },
+	{ "EmcW2p", token_emc_w2p,
+		field_type_u32,  NULL },
+	{ "EmcRrd", token_emc_rrd,
+		field_type_u32,  NULL },
+	{ "EmcRdRcd", token_emc_rd_rcd,
+		field_type_u32,  NULL },
+	{ "EmcWrRcd", token_emc_wr_rcd,
+		field_type_u32,  NULL },
+	{ "EmcRext", token_emc_rext,
+		field_type_u32,  NULL },
+	{ "EmcWdv", token_emc_wdv,
+		field_type_u32,  NULL },
+	{ "EmcQUseExtra", token_emc_quse_extra,
+		field_type_u32,  NULL },
+	{ "EmcQUse", token_emc_quse,
+		field_type_u32,  NULL },
+	{ "EmcQRst", token_emc_qrst,
+		field_type_u32,  NULL },
+	{ "EmcQSafe", token_emc_qsafe,
+		field_type_u32,  NULL },
+	{ "EmcRdv", token_emc_rdv,
+		field_type_u32,  NULL },
+	{ "EmcRefresh", token_emc_refresh,
+		field_type_u32,  NULL },
+	{ "EmcBurstRefreshNum", token_emc_burst_refresh_num,
+		field_type_u32,  NULL },
+	{ "EmcPdEx2Wr", token_emc_pdex2wr,
+		field_type_u32,  NULL },
+	{ "EmcPdEx2Rd", token_emc_pdex2rd,
+		field_type_u32,  NULL },
+	{ "EmcPChg2Pden", token_emc_pchg2pden,
+		field_type_u32,  NULL },
+	{ "EmcAct2Pden", token_emc_act2pden,
+		field_type_u32,  NULL },
+	{ "EmcAr2Pden", token_emc_ar2pden,
+		field_type_u32,  NULL },
+	{ "EmcRw2Pden", token_emc_rw2pden,
+		field_type_u32,  NULL },
+	{ "EmcTxsr", token_emc_txsr,
+		field_type_u32,  NULL },
+	{ "EmcTcke", token_emc_tcke,
+		field_type_u32,  NULL },
+	{ "EmcTfaw", token_emc_tfaw,
+		field_type_u32,  NULL },
+	{ "EmcTrpab", token_emc_trpab,
+		field_type_u32,  NULL },
+	{ "EmcTClkStable", token_emc_tclkstable,
+		field_type_u32,  NULL },
+	{ "EmcTClkStop", token_emc_tclkstop,
+		field_type_u32,  NULL },
+	{ "EmcTRefBw", token_emc_trefbw,
+		field_type_u32,  NULL },
+	{ "EmcFbioCfg1", token_emc_fbio_cfg1,
+		field_type_u32,  NULL },
+	{ "EmcFbioDqsibDlyMsb", token_emc_fbio_dqsib_dly_msb,
+		field_type_u32,  NULL },
+	{ "EmcFbioDqsibDly", token_emc_fbio_dqsib_dly,
+		field_type_u32,  NULL },
+	{ "EmcFbioQuseDlyMsb", token_emc_fbio_quse_dly_msb,
+		field_type_u32,  NULL },
+	{ "EmcFbioQuseDly", token_emc_fbio_quse_dly,
+		field_type_u32,  NULL },
+	{ "EmcFbioCfg5", token_emc_fbio_cfg5,
+		field_type_u32,  NULL },
+	{ "EmcFbioCfg6", token_emc_fbio_cfg6,
+		field_type_u32,  NULL },
+	{ "EmcFbioSpare", token_emc_fbio_spare,
+		field_type_u32,  NULL },
+	{ "EmcMrsResetDllWait", token_emc_mrs_reset_dll_wait,
+		field_type_u32,  NULL },
+	{ "EmcMrsResetDll", token_emc_mrs_reset_dll,
+		field_type_u32,  NULL },
+	{ "EmcMrsDdr2DllReset", token_emc_mrs_ddr2_dll_reset,
+		field_type_u32,  NULL },
+	{ "EmcMrs", token_emc_mrs,
+		field_type_u32,  NULL },
+	{ "EmcEmrsEmr2", token_emc_emrs_emr2,
+		field_type_u32,  NULL },
+	{ "EmcEmrsEmr3", token_emc_emrs_emr3,
+		field_type_u32,  NULL },
+	{ "EmcEmrsDdr2DllEnable", token_emc_emrs_ddr2_dll_enable,
+		field_type_u32,  NULL },
+	{ "EmcEmrsDdr2OcdCalib", token_emc_emrs_ddr2_ocd_calib,
+		field_type_u32,  NULL },
+	{ "EmcEmrs", token_emc_emrs,
+		field_type_u32,  NULL },
+	{ "EmcMrw1", token_emc_mrw1,
+		field_type_u32,  NULL },
+	{ "EmcMrw2", token_emc_mrw2,
+		field_type_u32,  NULL },
+	{ "EmcMrw3", token_emc_mrw3,
+		field_type_u32,  NULL },
+	{ "EmcMrwResetCommand", token_emc_mrw_reset_command,
+		field_type_u32,  NULL },
+	{ "EmcMrwResetNInitWait", token_emc_mrw_reset_ninit_wait,
+		field_type_u32,  NULL },
+	{ "EmcAdrCfg1", token_emc_adr_cfg1,
+		field_type_u32,  NULL },
+	{ "EmcAdrCfg", token_emc_adr_cfg,
+		field_type_u32,  NULL },
+	{ "McEmemCfg", token_mc_emem_Cfg,
+		field_type_u32,  NULL },
+	{ "McLowLatencyConfig", token_mc_lowlatency_config,
+		field_type_u32,  NULL },
+	{ "EmcCfg2", token_emc_cfg2,
+		field_type_u32,  NULL },
+	{ "EmcCfgDigDll", token_emc_cfg_dig_dll,
+		field_type_u32,  NULL },
+	{ "EmcCfgClktrim0", token_emc_cfg_clktrim0,
+		field_type_u32,  NULL },
+	{ "EmcCfgClktrim1", token_emc_cfg_clktrim1,
+		field_type_u32,  NULL },
+	{ "EmcCfgClktrim2", token_emc_cfg_clktrim2,
+		field_type_u32,  NULL },
+	{ "EmcCfg", token_emc_cfg,
+		field_type_u32,  NULL },
+	{ "EmcDbg", token_emc_dbg,
+		field_type_u32,  NULL },
+	{ "AhbArbitrationXbarCtrl", token_ahb_arbitration_xbar_ctrl,
+		field_type_u32,  NULL },
+	{ "EmcDllXformDqs", token_emc_dll_xform_dqs,
+		field_type_u32,  NULL },
+	{ "EmcDllXformQUse", token_emc_dll_xform_quse,
+		field_type_u32,  NULL },
+	{ "WarmBootWait", token_warm_boot_wait,
+		field_type_u32,  NULL },
+	{ "EmcCttTermCtrl", token_emc_ctt_term_ctrl,
+		field_type_u32,  NULL },
+	{ "EmcOdtWrite", token_emc_odt_write,
+		field_type_u32,  NULL },
+	{ "EmcOdtRead", token_emc_odt_read,
+		field_type_u32,  NULL },
+	{ "EmcZcalRefCnt", token_emc_zcal_ref_cnt,
+		field_type_u32,  NULL },
+	{ "EmcZcalWaitCnt", token_emc_zcal_wait_cnt,
+		field_type_u32,  NULL },
+	{ "EmcZcalMrwCmd", token_emc_zcal_mrw_cmd,
+		field_type_u32,  NULL },
+	{ "EmcMrwZqInitDev0", token_emc_mrw_zq_init_dev0,
+		field_type_u32,  NULL },
+	{ "EmcMrwZqInitDev1", token_emc_mrw_zq_init_dev1,
+		field_type_u32,  NULL },
+	{ "EmcMrwZqInitWait", token_emc_mrw_zq_init_wait,
+		field_type_u32,  NULL },
+	{ "EmcDdr2Wait", token_emc_ddr2_wait,
+		field_type_u32,  NULL },
+	{ "PmcDdrPwr", token_pmc_ddr_pwr,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CfgAPadCtrl", token_apb_misc_gp_xm2cfga_pad_ctrl,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CfgCPadCtrl2", token_apb_misc_gp_xm2cfgc_pad_ctrl2,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CfgCPadCtrl", token_apb_misc_gp_xm2cfgc_pad_ctrl,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CfgDPadCtrl2", token_apb_misc_gp_xm2cfgd_pad_ctrl2,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CfgDPadCtrl", token_apb_misc_gp_xm2cfgd_pad_ctrl,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2ClkCfgPadCtrl", token_apb_misc_gp_xm2clkcfg_Pad_ctrl,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2CompPadCtrl", token_apb_misc_gp_xm2comp_pad_ctrl,
+		field_type_u32,  NULL },
+	{ "ApbMiscGpXm2VttGenPadCtrl", token_apb_misc_gp_xm2vttgen_pad_ctrl
+		,field_type_u32,  NULL },
+
+	{ NULL, 0, 0, NULL }
+};
+
 static field_item s_nand_table[] = 
 {
 	{ "ClockDivider", token_clock_divider, field_type_u32,  NULL },
@@ -200,6 +427,7 @@ static parse_item s_top_level_items[] =
 	{ "PartitionSize=", token_partition_size,	parse_value_u32 },
 	{ "DevType[",       token_dev_type,		parse_array },
 	{ "DeviceParam[",   token_dev_param,		parse_dev_param },
+	{ "SDRAM[",         token_sdram,		parse_sdram_param },
 	{ "BootLoader=",    token_bootloader,		parse_bootloader },
 	{ "Redundancy=",    token_redundancy,		parse_value_u32 },
 	{ "Version=",       token_version,		parse_value_u32 },
@@ -696,6 +924,51 @@ parse_dev_param(build_image_context *context, parse_token token, char *rest)
     return 1;
 
 }
+
+static int
+parse_sdram_param(build_image_context *context, parse_token token, char *rest)
+{
+	u_int32_t value;
+	field_item *field;
+	u_int32_t index;
+
+	assert(context != NULL);
+	assert(rest != NULL);
+
+	/* Parse the index. */
+	rest = parse_u32(rest, &index);
+	if (rest == NULL)
+		return 1;
+
+	/* Parse the closing bracket. */
+	if (*rest != ']')
+		return 1;
+	rest++;
+
+	/* Parse the following '.' */
+	if (*rest != '.')
+		return 1;
+	rest++;
+
+	/* Parse the field name. */
+	rest = parse_field_name(rest, s_sdram_field_table, &field);
+	if (rest == NULL)
+		return 1;
+
+	/* Parse the equals sign.*/
+	if (*rest != '=')
+		return 1;
+	rest++;
+
+	/* Parse the value based on the field table. */
+	rest = parse_field_value(context, rest, field, &value);
+	if (rest == NULL)
+		return 1;
+
+	/* Store the result. */
+	return set_sdram_param(context, index, field->token, value);
+
+}
 /* Return 0 on success, 1 on error */
 static int
 process_statement(build_image_context *context, char *statement)
diff --git a/parse.h b/parse.h
index e755c60..e4ec1e5 100644
--- a/parse.h
+++ b/parse.h
@@ -65,6 +65,109 @@ typedef enum
 	token_nand_timing,
 	token_block_size_log2,
 	token_page_size_log2,
+	token_sdram,
+
+	token_memory_type,
+	token_pllm_charge_pump_setup_ctrl,
+	token_pllm_loop_filter_setup_ctrl,
+	token_pllm_input_divider,
+	token_pllm_feedback_divider,
+	token_pllm_post_divider,
+	token_pllm_stable_time,
+	token_emc_clock_divider,
+	token_emc_auto_cal_interval,
+	token_emc_auto_cal_config,   
+	token_emc_auto_cal_wait,
+	token_emc_pin_program_wait,
+	token_emc_rc,
+	token_emc_rfc,
+	token_emc_ras,
+	token_emc_rp,
+	token_emc_r2w,
+	token_emc_w2r,
+	token_emc_r2p,
+	token_emc_w2p,
+	token_emc_rd_rcd,
+	token_emc_wr_rcd,
+	token_emc_rrd,
+	token_emc_rext,
+	token_emc_wdv,
+	token_emc_quse,
+	token_emc_qrst,
+	token_emc_qsafe,
+	token_emc_rdv,
+	token_emc_refresh,
+	token_emc_burst_refresh_num,
+	token_emc_pdex2wr,
+	token_emc_pdex2rd,
+	token_emc_pchg2pden,
+	token_emc_act2pden,
+	token_emc_ar2pden,
+	token_emc_rw2pden,
+	token_emc_txsr,
+	token_emc_tcke,
+	token_emc_tfaw,
+	token_emc_trpab,
+	token_emc_tclkstable,
+	token_emc_tclkstop,
+	token_emc_trefbw,
+	token_emc_quse_extra,
+	token_emc_fbio_cfg1,
+	token_emc_fbio_dqsib_dly,
+	token_emc_fbio_dqsib_dly_msb,
+	token_emc_fbio_quse_dly,
+	token_emc_fbio_quse_dly_msb,
+	token_emc_fbio_cfg5,
+	token_emc_fbio_cfg6,
+	token_emc_fbio_spare,
+	token_emc_mrs,
+	token_emc_emrs,
+	token_emc_mrw1,
+	token_emc_mrw2,
+	token_emc_mrw3,
+	token_emc_mrw_reset_command,
+	token_emc_mrw_reset_ninit_wait,
+	token_emc_adr_cfg,
+	token_emc_adr_cfg1,
+	token_mc_emem_Cfg,
+	token_mc_lowlatency_config,
+	token_emc_cfg,
+	token_emc_cfg2,
+	token_emc_dbg,
+	token_ahb_arbitration_xbar_ctrl,
+	token_emc_cfg_dig_dll,
+	token_emc_dll_xform_dqs,
+	token_emc_dll_xform_quse,
+	token_warm_boot_wait,
+	token_emc_ctt_term_ctrl,
+	token_emc_odt_write,
+	token_emc_odt_read,
+	token_emc_zcal_ref_cnt,
+	token_emc_zcal_wait_cnt,
+	token_emc_zcal_mrw_cmd,
+	token_emc_mrs_reset_dll,
+	token_emc_mrw_zq_init_dev0,
+	token_emc_mrw_zq_init_dev1,
+	token_emc_mrw_zq_init_wait,
+	token_emc_mrs_reset_dll_wait,
+	token_emc_emrs_emr2,
+	token_emc_emrs_emr3,
+	token_emc_emrs_ddr2_dll_enable,
+	token_emc_mrs_ddr2_dll_reset,
+	token_emc_emrs_ddr2_ocd_calib,
+	token_emc_ddr2_wait,
+	token_emc_cfg_clktrim0,
+	token_emc_cfg_clktrim1,
+	token_emc_cfg_clktrim2,
+	token_pmc_ddr_pwr,
+	token_apb_misc_gp_xm2cfga_pad_ctrl,
+	token_apb_misc_gp_xm2cfgc_pad_ctrl,
+	token_apb_misc_gp_xm2cfgc_pad_ctrl2,
+	token_apb_misc_gp_xm2cfgd_pad_ctrl,
+	token_apb_misc_gp_xm2cfgd_pad_ctrl2,
+	token_apb_misc_gp_xm2clkcfg_Pad_ctrl,
+	token_apb_misc_gp_xm2comp_pad_ctrl,
+	token_apb_misc_gp_xm2vttgen_pad_ctrl,
 
 	token_force32 = 0x7fffffff
 } parse_token;
diff --git a/set.c b/set.c
index 1b16c21..3623788 100644
--- a/set.c
+++ b/set.c
@@ -50,6 +50,14 @@
 			context->bct);              \
 	break
 
+#define CASE_SDRAM_VALUE(id)                                          \
+	case token_##id:                                              \
+		(void)context->bctlib.set_sdram_params(index,            \
+			nvbct_lib_id_sdram_##id,      \
+			value,                      \
+			context->bct);              \
+            break
+
 #define DEFAULT()                                                     \
 	default:                                                      \
 		printf("Unexpected token %d at line %d\n",            \
@@ -444,3 +452,128 @@ set_spiflash_param(build_image_context *context,
 
 	return 0;
 }
+
+int
+set_sdram_param(build_image_context *context,
+		u_int32_t index,
+		parse_token token,
+		u_int32_t value)
+{
+	u_int32_t num_sdram_sets;
+
+	assert(context != NULL);
+	assert(context->bct != NULL);
+
+	// Update the number of SDRAM parameter sets.
+	GET_VALUE(num_sdram_sets, &num_sdram_sets);
+	num_sdram_sets = NV_MAX(num_sdram_sets, index + 1);
+	SET_VALUE(num_sdram_sets, num_sdram_sets);
+
+	switch (token) {
+
+	CASE_SDRAM_VALUE(memory_type);
+	CASE_SDRAM_VALUE(pllm_charge_pump_setup_ctrl);
+	CASE_SDRAM_VALUE(pllm_loop_filter_setup_ctrl);
+	CASE_SDRAM_VALUE(pllm_input_divider);
+	CASE_SDRAM_VALUE(pllm_feedback_divider);
+	CASE_SDRAM_VALUE(pllm_post_divider);
+	CASE_SDRAM_VALUE(pllm_stable_time);
+	CASE_SDRAM_VALUE(emc_clock_divider);
+	CASE_SDRAM_VALUE(emc_auto_cal_interval);
+	CASE_SDRAM_VALUE(emc_auto_cal_config);   
+	CASE_SDRAM_VALUE(emc_auto_cal_wait);
+	CASE_SDRAM_VALUE(emc_pin_program_wait);
+	CASE_SDRAM_VALUE(emc_rc);
+	CASE_SDRAM_VALUE(emc_rfc);
+	CASE_SDRAM_VALUE(emc_ras);
+	CASE_SDRAM_VALUE(emc_rp);
+	CASE_SDRAM_VALUE(emc_r2w);
+	CASE_SDRAM_VALUE(emc_w2r);
+	CASE_SDRAM_VALUE(emc_r2p);
+	CASE_SDRAM_VALUE(emc_w2p);
+	CASE_SDRAM_VALUE(emc_rd_rcd);
+	CASE_SDRAM_VALUE(emc_wr_rcd);
+	CASE_SDRAM_VALUE(emc_rrd);
+	CASE_SDRAM_VALUE(emc_rext);
+	CASE_SDRAM_VALUE(emc_wdv);
+	CASE_SDRAM_VALUE(emc_quse);
+	CASE_SDRAM_VALUE(emc_qrst);
+	CASE_SDRAM_VALUE(emc_qsafe);
+	CASE_SDRAM_VALUE(emc_rdv);
+	CASE_SDRAM_VALUE(emc_refresh);
+	CASE_SDRAM_VALUE(emc_burst_refresh_num);
+	CASE_SDRAM_VALUE(emc_pdex2wr);
+	CASE_SDRAM_VALUE(emc_pdex2rd);
+	CASE_SDRAM_VALUE(emc_pchg2pden);
+	CASE_SDRAM_VALUE(emc_act2pden);
+	CASE_SDRAM_VALUE(emc_ar2pden);
+	CASE_SDRAM_VALUE(emc_rw2pden);
+	CASE_SDRAM_VALUE(emc_txsr);
+	CASE_SDRAM_VALUE(emc_tcke);
+	CASE_SDRAM_VALUE(emc_tfaw);
+	CASE_SDRAM_VALUE(emc_trpab);
+	CASE_SDRAM_VALUE(emc_tclkstable);
+	CASE_SDRAM_VALUE(emc_tclkstop);
+	CASE_SDRAM_VALUE(emc_trefbw);
+	CASE_SDRAM_VALUE(emc_quse_extra);
+	CASE_SDRAM_VALUE(emc_fbio_cfg1);
+	CASE_SDRAM_VALUE(emc_fbio_dqsib_dly);
+	CASE_SDRAM_VALUE(emc_fbio_dqsib_dly_msb);
+	CASE_SDRAM_VALUE(emc_fbio_quse_dly);
+	CASE_SDRAM_VALUE(emc_fbio_quse_dly_msb);
+	CASE_SDRAM_VALUE(emc_fbio_cfg5);
+	CASE_SDRAM_VALUE(emc_fbio_cfg6);
+	CASE_SDRAM_VALUE(emc_fbio_spare);
+	CASE_SDRAM_VALUE(emc_mrs);
+	CASE_SDRAM_VALUE(emc_emrs);
+	CASE_SDRAM_VALUE(emc_mrw1);
+	CASE_SDRAM_VALUE(emc_mrw2);
+	CASE_SDRAM_VALUE(emc_mrw3);
+	CASE_SDRAM_VALUE(emc_mrw_reset_command);
+	CASE_SDRAM_VALUE(emc_mrw_reset_ninit_wait);
+	CASE_SDRAM_VALUE(emc_adr_cfg);
+	CASE_SDRAM_VALUE(emc_adr_cfg1);
+	CASE_SDRAM_VALUE(mc_emem_Cfg);
+	CASE_SDRAM_VALUE(mc_lowlatency_config);
+	CASE_SDRAM_VALUE(emc_cfg);
+	CASE_SDRAM_VALUE(emc_cfg2);
+	CASE_SDRAM_VALUE(emc_dbg);
+	CASE_SDRAM_VALUE(ahb_arbitration_xbar_ctrl);
+	CASE_SDRAM_VALUE(emc_cfg_dig_dll);
+	CASE_SDRAM_VALUE(emc_dll_xform_dqs);
+	CASE_SDRAM_VALUE(emc_dll_xform_quse);
+	CASE_SDRAM_VALUE(warm_boot_wait);
+	CASE_SDRAM_VALUE(emc_ctt_term_ctrl);
+	CASE_SDRAM_VALUE(emc_odt_write);
+	CASE_SDRAM_VALUE(emc_odt_read);
+	CASE_SDRAM_VALUE(emc_zcal_ref_cnt);
+	CASE_SDRAM_VALUE(emc_zcal_wait_cnt);
+	CASE_SDRAM_VALUE(emc_zcal_mrw_cmd);
+	CASE_SDRAM_VALUE(emc_mrs_reset_dll);
+	CASE_SDRAM_VALUE(emc_mrw_zq_init_dev0);
+	CASE_SDRAM_VALUE(emc_mrw_zq_init_dev1);
+	CASE_SDRAM_VALUE(emc_mrw_zq_init_wait);
+	CASE_SDRAM_VALUE(emc_mrs_reset_dll_wait);
+	CASE_SDRAM_VALUE(emc_emrs_emr2);
+	CASE_SDRAM_VALUE(emc_emrs_emr3);
+	CASE_SDRAM_VALUE(emc_emrs_ddr2_dll_enable);
+	CASE_SDRAM_VALUE(emc_mrs_ddr2_dll_reset);
+	CASE_SDRAM_VALUE(emc_emrs_ddr2_ocd_calib);
+	CASE_SDRAM_VALUE(emc_ddr2_wait);
+	CASE_SDRAM_VALUE(emc_cfg_clktrim0);
+	CASE_SDRAM_VALUE(emc_cfg_clktrim1);
+	CASE_SDRAM_VALUE(emc_cfg_clktrim2);
+	CASE_SDRAM_VALUE(pmc_ddr_pwr);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2cfga_pad_ctrl);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgc_pad_ctrl);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgc_pad_ctrl2);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgd_pad_ctrl);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2cfgd_pad_ctrl2);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2clkcfg_Pad_ctrl);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2comp_pad_ctrl);
+	CASE_SDRAM_VALUE(apb_misc_gp_xm2vttgen_pad_ctrl);
+
+	DEFAULT();
+    	}
+	return 0;
+}
diff --git a/set.h b/set.h
index e7ee055..e2368c0 100644
--- a/set.h
+++ b/set.h
@@ -89,6 +89,12 @@ set_spiflash_param(build_image_context *context,
 		u_int32_t value);
 
 int
+set_sdram_param(build_image_context *context,
+		u_int32_t index,
+		parse_token token,
+		u_int32_t value);
+
+int
 read_from_image(char *filename,
 		u_int32_t	page_size,
 		u_int8_t	**Image,