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authorPatrick Rudolph <siro@das-labor.org>2017-06-20 17:54:53 +0200
committerPatrick Rudolph <siro@das-labor.org>2017-07-12 16:04:55 +0000
commitbdae93571b4d54a149023ac1e208cfdee7561411 (patch)
tree4414e8a87940a57ab2afd5c4aad79ed03d26bcb4 /src/northbridge
parentfa47042e1c4fc028a46e870c574e58b446475b91 (diff)
downloadcoreboot-bdae93571b4d54a149023ac1e208cfdee7561411.tar.gz
nb/intel/common/gma_opregion: Use new method to update ASLS
Use new GMA driver method to set ASLS. Change-Id: I872ff86a778497df76ad7f9b1b6910c4e7c5941f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/common/gma_opregion.c15
1 files changed, 2 insertions, 13 deletions
diff --git a/src/northbridge/intel/common/gma_opregion.c b/src/northbridge/intel/common/gma_opregion.c
index 7d4c3f1c05..43e7c16d3f 100644
--- a/src/northbridge/intel/common/gma_opregion.c
+++ b/src/northbridge/intel/common/gma_opregion.c
@@ -79,8 +79,6 @@ static enum cb_err init_opregion_vbt(igd_opregion_t *opregion)
enum cb_err init_igd_opregion(igd_opregion_t *opregion)
{
enum cb_err ret;
- device_t igd;
- u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
@@ -119,17 +117,8 @@ enum cb_err init_igd_opregion(igd_opregion_t *opregion)
if (ret != CB_SUCCESS)
return ret;
- /* TODO This needs to happen in S3 resume, too.
- * Maybe it should move to the finalize handler
- */
- igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
- pci_write_config32(igd, ASLS, (u32)opregion);
-
- /* Intel's Windows driver relies on this: */
- reg16 = pci_read_config16(igd, SWSCI);
- reg16 &= ~GSSCIE;
- reg16 |= SMISCISEL;
- pci_write_config16(igd, SWSCI, reg16);
+ /* Write ASLS PCI register and prepare SWSCI register. */
+ intel_gma_opregion_register((uintptr_t)opregion);
return CB_SUCCESS;
}