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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-20 14:34:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 15:51:11 +0000 |
| commit | 40c5f74ae9c83893f4cccb28d869c862ed60b8d1 (patch) | |
| tree | 06f83da3ed9afd8555a3eb754461619d0f976728 | |
| parent | 69ababcbf61915456888a480f9d73b67e47e4a84 (diff) | |
| download | coreboot-40c5f74ae9c83893f4cccb28d869c862ed60b8d1.tar.gz | |
cpu/amd/pi/00730F01/fixme: replace some magic numbers
TEST=Timeless build for pcengines/apu2 results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
| -rw-r--r-- | src/cpu/amd/pi/00730F01/fixme.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index d36f507114..9724133ab7 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -3,6 +3,7 @@ #include <amdblocks/pci_devs.h> #include <arch/hpet.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -16,13 +17,14 @@ void amd_initcpuio(void) * set to non-posted regions. Last address before processor local APIC * at FEE00000, set NP (non-posted) bit. */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7)); + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, + ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7)); /* lowest NP address is HPET at FED00000 */ pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last - address before non-posted range */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00); + /* Map the remaining PCI hole as posted MMIO. */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, + ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); /* Send all IO (0000-FFFF) to southbridge. */ |