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# Copyright 2022 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
menuconfig AP_PWRSEQ
bool "AP Power sequencing support"
select HAS_TASK_POWERBTN
help
Enables AP power sequencing support with
embedded controller. This includes normal shutdown, critical
shutdown and reset handling.
Enabling this automatically enables HAS_TASK_POWERBTN since this task
is required to handle power button pressed/released by user.
if AP_PWRSEQ
module = AP_PWRSEQ
module-str = AP power sequencing
source "subsys/logging/Kconfig.template.log_config"
config AP_PWRSEQ_AUTOSTART
bool "Start the power sequence thread automatically"
default n
help
This option starts the AP power sequence task
at initialisation. If not set, ap_pwrseq_thread_start()
needs to be called to start the task.
Disable this option if there is other board or module
initialization that must occur before the AP power sequence
thread is started.
config AP_PWRSEQ_STACK_SIZE
int "AP pwrseq stack size (in bytes)"
help
This option specifies the size of the stack used by the
AP power sequencing state machine thread handler.
This must be set in a board configuration. If a default
is set here, it cannot be overridden (if necessary), since
this Kconfig appears before the EC chip specific stack
sizes.
config X86_NON_DSX_PWRSEQ
bool
default n
help
This option enables Non Deep Sleep Well power sequencing for
Intel x86 chips.
config X86_NON_DSX_PWRSEQ_ADL
bool "x86 Non Deep Sx power sequencing on ADL"
depends on AP_X86_INTEL_ADL
select X86_NON_DSX_PWRSEQ
default n
help
This enables AP power sequecing support for Intel Alderlake
family of chipset.
config X86_NON_DSX_PWRSEQ_CONSOLE
bool "Console commands for x86 Non Deep Sx power sequencing"
depends on X86_NON_DSX_PWRSEQ
default n
help
This option enables Non Deep Sleep Well power sequencing shell
console commands to debug.
config AP_PWRSEQ_S0IX
bool "Enable S0ix power state"
default n
help
This option enables power state S0ix for Intel x86 chipset.
endif
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