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# Copyright 2021 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
# Zephyr Kernel Configuration
CONFIG_SOC_SERIES_NPCX7=y
# Platform Configuration
CONFIG_SOC_NPCX7M6FC=y
CONFIG_BOARD_TROGDOR=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Pinmux Driver
CONFIG_PINMUX=y
# GPIO Controller
CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# PLL configuration
CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
# Code RAM base for NPCX797FC
CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10070000
CONFIG_CROS_EC_RAM_BASE=0x200c0000
CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000
CONFIG_CROS_EC_RAM_SIZE=0x0000f800
# ADC
# The resolution and oversamplig values are fixed by the NPCX ADC driver
CONFIG_PLATFORM_EC_ADC_RESOLUTION=10
CONFIG_PLATFORM_EC_ADC_OVERSAMPLING=0
CONFIG_FLASH_SIZE=512
CONFIG_CROS_EC_RO_MEM_OFF=0x0
CONFIG_CROS_EC_RO_SIZE=0x40000
# (CONFIG_CROS_EC_RO_MEM_OFF + CONFIG_CROS_EC_RO_SIZE)
CONFIG_CROS_EC_RW_MEM_OFF=0x0
# (CONFIG_CROS_EC_FLASH_SIZE - CONFIG_CROS_EC_RW_MEM_OFF -
# CONFIG_CROS_EC_RO_MEM_OFF)
CONFIG_CROS_EC_RW_SIZE=0x40000
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