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# Copyright 2021 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
# Zephyr Kernel Configuration
CONFIG_SOC_SERIES_NPCX7=y
# Platform Configuration
CONFIG_SOC_NPCX7M6FB=y # Actually NPCX7M6FC; C just has 512K Flash
CONFIG_BOARD_KOHAKU=y
# NPCX BootLoader Table Configuration
CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50=y
CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Pinmux Driver
CONFIG_PINMUX=y
# GPIO Controller
CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# WATCHDOG configuration
CONFIG_WATCHDOG=y
# Set the delay time for printing panic data.
# 1 cycle is about 32ms. 500ms is about 16 cycles.
CONFIG_WDT_NPCX_DELAY_CYCLES=16
# PLL configuration
CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
# The following are valid for all:
# npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m6g
CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10090000
CONFIG_CROS_EC_RAM_BASE=0x200c0000
CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000
CONFIG_CROS_EC_RAM_SIZE=0x0000f800
CONFIG_FLASH_SIZE=512
CONFIG_CROS_EC_RO_MEM_OFF=0x0
# (44*1024)
CONFIG_CROS_EC_RO_SIZE=0x30000
# (CONFIG_CROS_EC_RO_MEM_OFF + CONFIG_CROS_EC_RO_SIZE)
CONFIG_CROS_EC_RW_MEM_OFF=0x30000
# (CONFIG_CROS_EC_FLASH_SIZE - CONFIG_CROS_EC_RW_MEM_OFF -
# CONFIG_CROS_EC_RO_MEM_OFF)
CONFIG_CROS_EC_RW_SIZE=0x30000
CONFIG_FLASH_SIZE=512
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