1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
|
/* Copyright 2022 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* ANX7483: Active redriver with linear equilzation
*/
#include "anx7483.h"
#include "chipset.h"
#include "common.h"
#include "console.h"
#include "i2c.h"
#include "retimer/anx7483_public.h"
#include "timer.h"
#include "usb_mux.h"
#include "util.h"
/*
* Programming guide specifies it may be as much as 30ms after chip power on
* before it's ready for i2c
*/
#define ANX7483_I2C_WAKE_TIMEOUT_MS 30
#define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
const test_export_static struct anx7483_tuning_set anx7483_usb_enabled[] = {
{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
};
const test_export_static struct anx7483_tuning_set anx7483_dp_enabled[] = {
{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
};
const test_export_static struct anx7483_tuning_set anx7483_dock_noflip[] = {
{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
};
const test_export_static struct anx7483_tuning_set anx7483_dock_flip[] = {
{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
};
const size_t anx7483_usb_enabled_count = ARRAY_SIZE(anx7483_usb_enabled);
const size_t anx7483_dp_enabled_count = ARRAY_SIZE(anx7483_dp_enabled);
const size_t anx7483_dock_noflip_count = ARRAY_SIZE(anx7483_dock_noflip);
const size_t anx7483_dock_flip_count = ARRAY_SIZE(anx7483_dock_flip);
test_export_static int anx7483_read(const struct usb_mux *me, uint8_t reg,
int *val)
{
return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
}
test_export_static int anx7483_write(const struct usb_mux *me, uint8_t reg,
uint8_t val)
{
return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
}
test_export_static int anx7483_init(const struct usb_mux *me)
{
timestamp_t start;
int rv;
int val;
if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
return EC_ERROR_NOT_POWERED;
/* Keep reading control register until mux wakes up or times out */
start = get_time();
do {
rv = anx7483_read(me, ANX7483_ANALOG_STATUS_CTRL_REG, &val);
if (!rv)
break;
usleep(ANX7483_I2C_WAKE_RETRY_DELAY_US);
} while (time_since32(start) < ANX7483_I2C_WAKE_TIMEOUT_MS * MSEC);
if (rv) {
CPRINTS("ANX7483: Failed to wake mux rv:%d", rv);
return EC_ERROR_TIMEOUT;
}
/* Configure for i2c control */
val |= ANX7483_CTRL_REG_EN;
RETURN_ERROR(anx7483_write(me, ANX7483_ANALOG_STATUS_CTRL_REG, val));
return EC_SUCCESS;
}
test_export_static int anx7483_set(const struct usb_mux *me,
mux_state_t mux_state, bool *ack_required)
{
int reg;
int val;
/* This driver does not use host command ACKs */
*ack_required = false;
/* This driver treats safe mode as none */
if (mux_state == USB_PD_MUX_SAFE_MODE)
mux_state = USB_PD_MUX_NONE;
/*
* Mux is not powered in Z1
*/
if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
return EC_ERROR_NOT_POWERED;
/*
* Always ensure i2c control is set and state machine is enabled
* (setting ANX7483_CTRL_REG_BYPASS_EN disables state machine)
* Not recommend because it turns off whole low power function
*/
/*
* Modify LFPS_TIMER to prevent going USB SLUMBER state too early
*/
RETURN_ERROR(anx7483_read(me, ANX7483_LFPS_TIMER_REG, &val));
val &= ~ANX7483_LFPS_TIMER_MASK;
val |= ANX7483_LFPS_TIMER_SLUMBER_TIME_H << ANX7483_LFPS_TIMER_SHIFT;
RETURN_ERROR(anx7483_write(me, ANX7483_LFPS_TIMER_REG, val));
reg = ANX7483_CTRL_REG_EN;
if (mux_state & USB_PD_MUX_USB_ENABLED)
reg |= ANX7483_CTRL_USB_EN;
if (mux_state & USB_PD_MUX_DP_ENABLED)
reg |= ANX7483_CTRL_DP_EN;
if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
reg |= ANX7483_CTRL_FLIP_EN;
return anx7483_write(me, ANX7483_ANALOG_STATUS_CTRL_REG, reg);
}
test_export_static int anx7483_get(const struct usb_mux *me,
mux_state_t *mux_state)
{
int reg;
/* Mux is not powered in Z1 */
if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
return USB_PD_MUX_NONE;
*mux_state = 0;
RETURN_ERROR(anx7483_read(me, ANX7483_ANALOG_STATUS_CTRL_REG, ®));
if (reg & ANX7483_CTRL_USB_EN)
*mux_state |= USB_PD_MUX_USB_ENABLED;
if (reg & ANX7483_CTRL_DP_EN)
*mux_state |= USB_PD_MUX_DP_ENABLED;
if (reg & ANX7483_CTRL_FLIP_EN)
*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
return EC_SUCCESS;
}
/* Helper to apply entire array of tuning registers, returning on first error */
static enum ec_error_list
anx7483_apply_tuning(const struct usb_mux *me,
const struct anx7483_tuning_set *reg, int num)
{
int i;
for (i = 0; i < num; i++) {
RETURN_ERROR(anx7483_write(me, reg[i].addr, reg[i].value));
}
return EC_SUCCESS;
}
int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state)
{
bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
/* Remove flipped from the state for easier compraisons */
mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
/* Enable i2c configuration of tuning registers */
RETURN_ERROR(anx7483_write(me, ANX7483_ENABLE_EQ_FLAT_SWING_REG,
ANX7483_ENABLE_EQ_FLAT_SWING_EN));
if (mux_state == USB_PD_MUX_USB_ENABLED) {
return anx7483_apply_tuning(me, anx7483_usb_enabled,
ARRAY_SIZE(anx7483_usb_enabled));
} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
return anx7483_apply_tuning(me, anx7483_dp_enabled,
ARRAY_SIZE(anx7483_dp_enabled));
} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
return anx7483_apply_tuning(me, anx7483_dock_noflip,
ARRAY_SIZE(anx7483_dock_noflip));
} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
return anx7483_apply_tuning(me, anx7483_dock_flip,
ARRAY_SIZE(anx7483_dock_flip));
}
return EC_SUCCESS;
}
enum ec_error_list anx7483_set_eq(const struct usb_mux *me,
enum anx7483_tune_pin pin,
enum anx7483_eq_setting eq)
{
int reg, value;
if (pin == ANX7483_PIN_UTX1)
reg = ANX7483_UTX1_PORT_CFG0_REG;
else if (pin == ANX7483_PIN_UTX2)
reg = ANX7483_UTX2_PORT_CFG0_REG;
else if (pin == ANX7483_PIN_URX1)
reg = ANX7483_URX1_PORT_CFG0_REG;
else if (pin == ANX7483_PIN_URX2)
reg = ANX7483_URX2_PORT_CFG0_REG;
else if (pin == ANX7483_PIN_DRX1)
reg = ANX7483_DRX1_PORT_CFG0_REG;
else if (pin == ANX7483_PIN_DRX2)
reg = ANX7483_DRX2_PORT_CFG0_REG;
else
return EC_ERROR_INVAL;
RETURN_ERROR(anx7483_read(me, reg, &value));
value &= ~ANX7483_CFG0_EQ_MASK;
value |= eq << ANX7483_CFG0_EQ_SHIFT;
return anx7483_write(me, reg, value);
}
enum ec_error_list anx7483_set_fg(const struct usb_mux *me,
enum anx7483_tune_pin pin,
enum anx7483_fg_setting fg)
{
int reg, value;
if (pin == ANX7483_PIN_UTX1)
reg = ANX7483_UTX1_PORT_CFG2_REG;
else if (pin == ANX7483_PIN_UTX2)
reg = ANX7483_UTX2_PORT_CFG2_REG;
else if (pin == ANX7483_PIN_URX1)
reg = ANX7483_URX1_PORT_CFG2_REG;
else if (pin == ANX7483_PIN_URX2)
reg = ANX7483_URX2_PORT_CFG2_REG;
else if (pin == ANX7483_PIN_DRX1)
reg = ANX7483_DRX1_PORT_CFG2_REG;
else if (pin == ANX7483_PIN_DRX2)
reg = ANX7483_DRX2_PORT_CFG2_REG;
else
return EC_ERROR_INVAL;
RETURN_ERROR(anx7483_read(me, reg, &value));
value &= ~ANX7483_CFG2_FG_MASK;
value |= fg << ANX7483_CFG2_FG_SHIFT;
return anx7483_write(me, reg, value);
}
const struct usb_mux_driver anx7483_usb_retimer_driver = {
.init = anx7483_init,
.set = anx7483_set,
.get = anx7483_get,
};
|
