1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "dma.h"
#include "registers.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
/**
* Get a pointer to a DMA channel.
*
* @param channel Channel number to read (DMAC_...)
* @return pointer to DMA channel registers
*/
static struct dma_channel *get_channel(int channel)
{
struct dma_channel *chan;
struct dma_ctlr *dma;
/* Get a pointer to the correct controller and channel */
ASSERT(channel < DMA_NUM_CHANNELS);
if (channel < DMA1_NUM_CHANNELS) {
dma = (struct dma_ctlr *)STM32L_DMA1_BASE;
chan = &dma->chan[channel];
} else {
dma = (struct dma_ctlr *)STM32L_DMA2_BASE;
chan = &dma->chan[channel - DMA1_NUM_CHANNELS];
}
return chan;
}
void dma_disable(unsigned channel)
{
struct dma_channel *chan;
chan = get_channel(channel);
if (REG32(&chan->ccr) & DMA_EN)
REG32(&chan->ccr) &= ~DMA_EN;
}
/**
* Prepare a channel for use and start it
*
* @param channel Channel number to read (DMAC_...)
* @param count Number of bytes to transfer
* @param periph Pointer to peripheral data register
* @param memory Pointer to memory address
* @param flags DMA flags for the control register, normally:
* DMA_DIR_FROM_MEM_MASK for tx
* 0 for rx
* @return 0 if ok, -1 on error
*/
static int prepare_channel(unsigned channel, unsigned count, void *periph,
const void *memory, unsigned flags)
{
struct dma_channel *chan;
uint32_t ctrl;
chan = get_channel(channel);
if (REG32(&chan->ccr) & DMA_EN)
REG32(&chan->ccr) &= ~DMA_EN;
/* Following the order in Doc ID 15965 Rev 5 p194 */
REG32(&chan->cpar) = (uint32_t)periph;
REG32(&chan->cmar) = (uint32_t)memory;
REG32(&chan->cndtr) = count;
ctrl = DMA_PL_VERY_HIGH << DMA_PL_SHIFT;
REG32(&chan->ccr) = ctrl;
ctrl |= DMA_MINC_MASK | flags;
ctrl |= 0 << 10; /* MSIZE (memory size in bytes) */
ctrl |= 1 << 8; /* PSIZE (16-bits for now) */
REG32(&chan->ccr) = ctrl;
/* Fire it up */
ctrl |= DMA_EN;
REG32(&chan->ccr) = ctrl;
return 0;
}
int dma_start_tx(unsigned channel, unsigned count, void *periph,
const void *memory)
{
return prepare_channel(channel, count, periph, memory,
DMA_DIR_FROM_MEM_MASK);
}
int dma_start_rx(unsigned channel, unsigned count, void *periph,
const void *memory)
{
return prepare_channel(channel, count, periph, memory, 0);
}
/* Hide this code behind an undefined CONFIG for now */
#ifdef CONFIG_DMA_TEST
void dma_check(int channel, char *buff)
{
struct dma_channel *chan;
int count;
int i;
chan = get_channel(channel);
count = REG32(&chan->cndtr);
uart_printf("c=%d\n", count);
udelay(1000 * 100);
uart_printf("c=%d\n",
REG32(&chan->cndtr));
for (i = 0; i < count; i++)
uart_printf("%02x ", buff[i]);
udelay(1000 * 100);
uart_printf("c=%d\n",
REG32(&chan->cndtr));
for (i = 0; i < count; i++)
uart_printf("%02x ", buff[i]);
}
/* Run a check of memory-to-memory DMA */
void dma_test(void)
{
unsigned channel = 3;
struct dma_channel *chan;
uint32_t ctrl;
char periph[16], memory[16];
unsigned count = sizeof(periph);
int i;
chan = get_channel(channel);
memset(memory, '\0', sizeof(memory));
for (i = 0; i < count; i++)
periph[i] = 10 + i;
/* Following the order in Doc ID 15965 Rev 5 p194 */
REG32(&chan->cpar) = (uint32_t)periph;
REG32(&chan->cmar) = (uint32_t)memory;
REG32(&chan->cndtr) = count;
ctrl = DMA_PL_MEDIUM << DMA_PL_SHIFT;
REG32(&chan->ccr) = ctrl;
ctrl |= DMA_MINC_MASK; /* | DMA_DIR_FROM_MEM_MASK */;
ctrl |= 1 << 14; /* MEM2MEM */
ctrl |= 1 << 6; /* PINC */
/* ctrl |= 2 << 10; */
/* ctrl |= 2 << 8; */
REG32(&chan->ccr) = ctrl;
ctrl |= DMA_EN;
REG32(&chan->ccr) = ctrl;
for (i = 0; i < count; i++)
uart_printf("%d/%d ", periph[i], memory[i]);
uart_printf("\ncount=%d\n", REG32(&chan->cndtr));
}
#endif /* CONFIG_TEST */
void dma_init(void)
{
/* Enable DMA1, we don't support DMA2 yet */
STM32L_RCC_AHBENR |= 1 << 24;
}
|
