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* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: rename HOSTCMD_ESPI_* to HOST_INTERFACE_ESPI_*Michał Barnaś2022-09-091-1/+1
| | | | | | | | | | | | | | | Rename ESPI additional configs to match the name of base config that selects ESPI as HOST_INTERFACE. BUG=b:195416058 BRANCH=main TEST=zmake testall && make buildall Change-Id: I137449a1a58b1ea0d9794ebc0900e1b68413819d Signed-off-by: Michał Barnaś <mb@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3291744 Reviewed-by: Sam Hurst <shurst@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* zephyr: Remove gpio_map.h legacy include fileAndrew McRae2022-07-071-2/+2
| | | | | | | | | | | | | Remove gpio_map.h and update Kconfig references to it. BUG=b:237716584 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: I4b21b53a4a63c6a934f9ab3bef3707e225bd01b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750267 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: allow only one power sequencing option via kconfigPeter Marheine2022-06-151-0/+1
| | | | | | | | | | | | | | PLATFORM_EC_POWERSEQ and AP_PWRSEQ implement the same subsystem, so update the kconfig to prevent both from being enabled at the same time. BUG=b:233681784 TEST=zmake testall BRANCH=none Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Ied6ffdd8b541acb343ac4e36ea901f9d252717c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703088 Reviewed-by: Keith Short <keithshort@chromium.org>
* Zephyr: Allow S0ix to be configured on non-Intel boardsDiana Z2022-06-091-8/+8
| | | | | | | | | | | | | | | Boards besides Intel may allow S0ix, so move that configuration out of the Intel-specific section of the power sequencing Kconfig. BRANCH=None BUG=b:234499465 TEST=zmake testall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I05ce493aeed002576809dc6fc45997ca47d6bcae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3693866 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* throttle_ap: Add option to gate PROCHOT based on C10Keith Short2022-04-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some x86 boards, the PROCHOT signal is not valid once the AP enters the C10 state. Add an option to gate PROCHOT detection if the C10 state is asserted. When the AP exits C10, the EC rechecks the PROCHOT state. Note that only the Volteer baseboard enables the PROCHOT interrupt, so it is the only board that is updated to call throttle_ap_config_prochot(). All gpio.inc files that connect to throttle_ap_prochot_input_interrupt() all use the pin name EC_PROCHOT_IN_L. Confirmed with these searches: $ grep -r "GPIO_INT.*throttle_ap_prochot_input_interrupt" . \ | wc -l 31 $ grep -r "EC_PROCHOT_IN_L.*throttle_ap_prochot_input_interrupt" . \ | wc -l 31 $ grep -r "gpio_enable_interrupt.*EC_PROCHOT_IN_L" . ./baseboard/volteer/power.c: \ gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L); BUG=b:185810479 BRANCH=volteer TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I73fb328675d9faade13fe0192570dc838de028a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3615479 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Zephyr: Correct adlrvp and intelrvp baseboard to select correct configBrandon Breitenstein2022-03-171-1/+1
| | | | | | | | | | | | | | | Since there are now multiple intelrvp boards no longer select the power sequencing in the baseboard and move the selection to the specific rvp. Also set the default for icelake to n to avoid always pulling it. BUG=none BRANCH=none TEST=zmake testall and verify that there are no build issues with new prj.conf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Change-Id: I266d74b75628156668ec9d40f6ffec7315c53224 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516596 Reviewed-by: Keith Short <keithshort@chromium.org>
* power: Add base code for Meteorlake power sequencingVijay Hiremath2022-03-151-0/+9
| | | | | | | | | | | | | | | | Added base code for Meteorlake power sequencing. Implementation closely follows Intel Icelake power sequencing as reference and modified the logic based on Meteorlake Platform Development Guide. BUG=b:223985632 BRANCH=none TEST=Able to boot MTLRVP to S0 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Change-Id: Ia551a1e226c648d9f23aff05ad3d44c3735a2495 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516600 Reviewed-by: Keith Short <keithshort@chromium.org>
* intel_x86: Add config to configure S5 exit timerSugnan Prabhu S2022-03-091-0/+11
| | | | | | | | | | | | | | | | | | | | On enabling Delayed Authentication Mode(DAM) in the coreboot for latest platforms, system takes more time to exit from S5 than the current wait time(4secs). Due to which EC forces the system to G3 after few retries. This patch adds a new config to allow configuration of this timeout value for which EC has to wait for S5 exit before performing RTC reset and forcing the system to G3. BRANCH=None BUG=b:191742284 TEST=Boot test on Brya with the DAM enabled coreboot Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Change-Id: I78821280fa5928682c9c0c742a4e00299ac49db0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3432445 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
* Zephyr: Allow RSMRST delay to be set for AMDDiana Z2022-02-141-7/+8
| | | | | | | | | | | | | | | AMD platforms also use the RSMRST delay configuration, so allow it to be set for either AMD or Intel. BRANCH=None BUG=b:218867363 TEST=zmake testall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib399640023b7091ddfbc2a79e3a9127f80cd895f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3456684 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Power: Add fake S0 console commandDiana Z2022-02-051-0/+9
| | | | | | | | | | | | | | | | Add a console command which can be used to sequence into S0, even when the SoC isn't populated. The bulk of the work is performed in the chip's power code, as the implementation will need to be chipset-specific. BRANCH=None BUG=b:209613841 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If7f1467a314ef9ab299bb8ad1a153a1e82bfe758 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3430300 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: add mt8186 power sequenceTing Shen2022-01-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT8186 power sequence is a simplified version of 8192/95. EC does not lie between AP and PMIC, so there's no need to forward the signals. Other logics are almost the same. BUG=b:206338930 TEST=Test following items on krabby CL:3233784 * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control 'ec_uart_cmd:powerbtn 200' Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=none Cq-Depend: chromium:3366102 Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iebfe77c8f6d127ee4d0685903b67afd215ca6682 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3233783 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* Add EC feature flag for S4 residencyEvan Green2021-12-011-0/+10
| | | | | | | | | | | | | | | | | | On systems with Intel Key Locker, the AP must hibernate to S4 in order to preserve active Key Locker state. Until recently, the EC did not support camping out in S4. Add a feature bit so the AP can distinguish EC versions which are capable of going to S4 from those that are not. BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I9d01c689e90cd479d8d3f06a224ef7f9ed309fc4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3290310 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* zephyr: mtk power sequence code refactorTing Shen2021-11-161-13/+2
| | | | | | | | | | | | | | | | | | | | | | | Minor refactor before landing mt8186 power seq: 1) remove PLATFORM_EC_POWERSEQ_IT8XXX2, we don't have common power code for it8xxx2 devices currently. 2) rename mediatek,power-signal-list dts binding to mt8192. Powerseq for MTK platform should infer from AP_ARM_MTK_MTxxxx, not from the EC chip. BUG=b:206338930 TEST=1) zmake -j32 configure -b zephyr/projects/asurada/hayato/ 2) zmake -j32 configure -b zephyr/projects/corsola/krabby/ BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I3ce8aeb6f2745b6aef9980a7cda5eadbafbfdcc4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3281631 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: brya: Add power sequencing support using shimDivya Sasidharan2021-11-121-2/+10
| | | | | | | | | | | | | | Add required configs for power sequencing brya. BUG=b:200975143 BRANCH=main TEST=zmake testall; check AP power state transitions to S0, verify booting up to kernel. Change-Id: Ib02cc4dc1be11af024f485efd5b73c613a4d1ac2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3176402 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: guybrush: Bringup power sequencingJack Rosenthal2021-09-171-0/+20
| | | | | | | | | | | | | | | | | Bringup power sequencing for AMD and enable for guybrush. Note that at the moment we had to copy-paste the power signals and related funcitons, the code was a bit too far from shimming without extensive editing. We can try and merge together later. BUG=b:195137794 BRANCH=none TEST=power sequence to S0, nothing useful on ap console (yet!) Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I9a577e24d80fe0ff992af4b847e14695b82f871d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169568 Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr: add support for CONFIG_CMD_S5_TIMEOUTKeith Short2021-07-121-0/+8
| | | | | | | | | | | | | | | Add a Kconfig option to control the CONFIG_CMD_S5_TIMEOUT option. BUG=b:193195946 BRANCH=none TEST=zmake testall TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2f4b8c74a9b710f68d8e07e04d9cb95ca2e39dea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3015869 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: asurada: Enable power button and sequencingDenis Brockus2021-05-191-0/+18
| | | | | | | | | | | | | BUG=b:180980668 BRANCH=none TEST=get powerbtn command in shell Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I1af4673b7eff84149e3aabad7ff09445a1f96e1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2895306 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* qcom: Create new configs for SC7280Wai-Hong Tam2021-05-181-0/+8
| | | | | | | | | | | | | | | Create new configs (Chromium EC namespace and Zephyr namespace) for SC7280. In this state, SC7280 power sequence has no difference from SC7180. BRANCH=None BUG=b:187980397 TEST=Built all the Chromium EC images and Zephyr EC images. TEST=Modify a board to use the new CONFIG. Change-Id: I178b8ffa5d79d3828baf222ac77906ab2262cf76 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893069
* zephyr: lazor: enable power sequencingJack Rosenthal2021-03-221-0/+8
| | | | | | | | | | | | | | | | | | | | Enable SC7180 power sequencing code. Currently, depthcharge starts and then times out on some host commands, and the AP issues a reboot. We're going to need the SPI host interface up and going in Zephyr to get any further, so may as well submit this for now. BUG=b:183054226 BRANCH=none TEST=used serial firmware to verify that depthcharge starts, times out on some host commands, and then reboots Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I860088360480946b644fd1bb276a29266c57c614 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774368 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* zephyr: make PLATFORM_EC_POWERSEQ_PP5000_CONTROL available to ARMJack Rosenthal2021-03-181-7/+7
| | | | | | | | | | | | | | | | | The PLATFORM_EC_POWERSEQ_PP5000_CONTROL config option was previously guarded under a PLATFORM_EC_POWERSEQ_INTEL dependency, however the config option is used in the ARM world as well. Drop the Intel dependency. BUG=b:182398910 BRANCH=none TEST=zmake testall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ica512cbbd9fb0735ab07192543e95ef27bc0e03f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774359 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* zephyr: move select on HAS_TASK_POWERBTN to PLATFORM_EC_POWERSEQ_INTELJack Rosenthal2021-02-171-0/+1
| | | | | | | | | | | | | | | | | | | | | common/power_button.c (enabled by PLATFORM_EC_POWER_BUTTON) does not use or require the POWERBTN task. The POWERBTN task is required by common/power_button_x86.c instead, which is enabled by PLATFORM_EC_POWERSEQ_INTEL. Thus, there should not be a reverse dependency on the POWERBTN task for PLATFORM_EC_POWER_BUTTON, and this select was moved to the correct location. BUG=b:180410072 BRANCH=none TEST=compile for delbin with follow-up CL (enables the power button) Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Icf7c89ad006c2c32cdc1f0f77ecff0c42fa6dab2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699530 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Support the EC_CMD_AP_RESET host commandSimon Glass2021-02-081-0/+10
| | | | | | | | | | | | | | | Add support for this in Zephyr so the AP can request a reset from the EC. Don't enable it by default as it is not widely used and is quite dangerous. BUG=b:178099673 BRANCH=none TEST=build zephyr and see that host_command_apreset is now compiled in Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I6aefc6c60ab316bd2445ceb06fd59a90d6c576b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678789 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Support POWER_SLEEP_FAILURE_DETECTIONSimon Glass2021-02-051-0/+10
| | | | | | | | | | | | | | Add support for this feature which is used on some x86 systems. BUG=b:178099673 BRANCH=none TEST=build volteer for zephyr make BOARD=volteer -j8 Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I607a96cd79496534da08b050f2e43fd82c351e58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2643619 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: power: add shim option for S0ixJack Rosenthal2021-01-221-0/+15
| | | | | | | | | | | | | Add a shim option for enabling S0ix and host sleep tracking. BUG=b:177609422 BRANCH=none TEST=power sequence kohaku Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I2a41ec509339879c6a372bdc7d2d6d2e2bb651ae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2633821 Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: add comet lake power sequencing optionsJack Rosenthal2021-01-161-0/+7
| | | | | | | | | | | | | Add Kconfig options to enable cometlake power sequencing. BUG=b:177609422 BRANCH=none TEST=with kohaku CLs Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ib40873f623a4860e83bd4692e0d2ade1abbecb99 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2633164 Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: Make HAS_TASK_CHIPSET a Kconfig optionSimon Glass2021-01-061-8/+6
| | | | | | | | | | | | | | | | This option is implied so we may as well create it. Set it to be visible (and automatically enabled) only if PLATFORM_EC_POWERSEQ is enabled. This mostly mimics the current behaviour. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_CHIPSET and PLATFORM_EC_POWERSEQ Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I7dc698c15fa65eb16ec40724a06b67d7e4ddc27d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606573 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Convert the sub-Kconfig files into menusSimon Glass2020-12-301-1/+1
| | | | | | | | | | | | | | | | | | | Use a menu for each of these since it produces a tidier top-level view for the EC. Put the function as the first word to make it easier to follow. For battery and USB-C, use menuconfig so that it works the same way as power sequencing. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig See that the menus appear Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I57e58f94aeaa0783ca69b0c948b7760c2e42adbf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606571 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: fix build for keyboard shimYuval Peress2020-12-051-0/+7
| | | | | | | | | | | | | | | | | | | | | See platform/ec/common/build.mk for reference. The use of keyboard_scan.c should only be allowed when HAS_TASK_KEYSCAN is defined. As such, we should always set HAS_TASK_KEYSCAN to 1 if CONFIG_PLATFORM_EC_KEYBOARD is defined. Further, CROS_EC_TASK_LIST was defined per project and it doesn't need to be, we can instead define it once for all boards depending on which tasks are set to 1 in shimmed_tasks.h Note that shimmed_tasks.h can still be used in tests. BRANCH=none BUG=none TEST=zmake testall Cq-Depend: chromium:2566421 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Id0ed49dd49e3c4eb2ac23184cf943c91dcd261eb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567560
* zephyr: shim in power sequencingJack Rosenthal2020-11-201-0/+80
Enable shimming of power sequencing code. BUG=b:171312361 BRANCH=none TEST=With zephyr-chrome CL... https://screenshot.googleplex.com/4m6N6vd2Nx5FpiD.png Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I8fb96019c8c636010d2cd136c0116df41fc9f148 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2548308
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