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* power/skylake: Add option to reset pmic using LDO_ENFurquan Shaikh2017-01-231-0/+37
| | | | | | | | | | | | | | | | | Add a config option that can be used by chipset to provide PMIC reset using LDO_EN. This is required for ensuring that the AP is power cycled properly. Implement the special pmic reset for skylake chipsets. BUG=chrome-os-partner:61883 BRANCH=None TEST=Verified that reboot on EC console resets the AP and does not get stuck in G3 on poppy. Change-Id: I5f680fede5cb4effa86243f51edfdea09db4d975 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/431192 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* intel_x86: Handle unexpected power loss in S0iXVijay Hiremath2017-01-211-4/+12
| | | | | | | | | | | | | | | | | | Picked the code from Glados branch. Change-Id: I0f24f717f712dcd46e3ddca2a8c86888739f3deb Reviewed-on: https://chromium-review.googlesource.com/390343 BUG=chrome-os-partner:61645 BRANCH=none TEST=Manually tested on Reef. Reef exits from S0iX upon issuing 'apreset warm' & 'apreset cold' from the ec console. Change-Id: Ie5fa4ad79b7c78344e99fcbf4ba2b5b800f9934c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427393 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel_x86: Handle RSMRST signal in Intel x86 common codeVijay Hiremath2017-01-214-73/+58
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427018 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel_x86: Make common code for LPC S0 <-> S0ix transitionsVijay Hiremath2017-01-211-2/+48
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=Manually tested on Reef. System can enter and exit from S0iX when LID is closed & opened respectively. Change-Id: I5892da327c2dcdd400d5a7ade867bec1b80cbaa4 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407047 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Group Intel x86 power sequencing common codeVijay Hiremath2017-01-206-530/+301
| | | | | | | | | | | | | | | | | | | Grouping the Intel x86 power sequencing common code so that the future chipset power sequencing implementation can make use of the existing code. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Manually tested on Reef & Chell. System can boot to OS. S3, S5, hibernate are working. Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/402272 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Extract Intel x86 power sequencing common codeVijay Hiremath2017-01-077-178/+202
| | | | | | | | | | | | | | | | | Extracted Intel x86 power sequencing common code from skylake.c and apollolake.c to implement common code for power sequencing. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/406486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* apollolake: Add support to enable eSPI signalsVijay Hiremath2017-01-061-6/+32
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I6d90d647a6e19c627aa68ddd8a203d6be8b2e32d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425820 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Reuse the sleep event code from the common codeVijay Hiremath2017-01-061-51/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I881b92215f24ea047ec4fc3109b174ff1615de29 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: rk3399: Wake from S3 on power button press rather than shutdownShawn Nematbakhsh2016-12-011-7/+1
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:58599 BRANCH=gru TEST=Boot kevin, go to S3, verify power button wakes. Hold power button in S3, verify device wakes and then shuts down. Go to S3, close lid, press power button, and verify no wake occurs. Change-Id: I4fa2e4967babc18cea9b5ffc7cec264b6f2fa8e3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399518 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 97bdf83b41834c072c5d1be516c8186c7911cee3) Reviewed-on: https://chromium-review.googlesource.com/415489 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Use longer SYS_RST hold time on chipset resetShawn Nematbakhsh2016-12-011-1/+5
| | | | | | | | | | | | | | | | | BUG=chrome-os-partner:57990 BRANCH=gru TEST=On kevin, verify `apreset` and kernel panic cause successful AP reset. Change-Id: Ic5ad2fd2d2d08ae32a60314e30f4cdff061da164 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395533 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 8fb0dedd8daebeca3757bc341d0a5355d3b26ba5) Reviewed-on: https://chromium-review.googlesource.com/396136 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Apollolake: Enter/exit from S0ix based on host commands from kernelArchana Patni2016-11-172-61/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the entry/exit model for S0ix from a PCH SLP_S0 signal based model to a hybrid host event/direct interrupt model. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. The assertion of SLP_S0 comes later than HC(suspend) and deasserion of SLP_S0 comes earlier than HC(resume). ________ ________ SLP_S0 |______________________| _____ ________ HC |___________________________| BRANCH=none BUG=chrome-os-partner:58740 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify idle state transitions during display off and periodic wakes from S0ix do not lead to state transitions in EC. Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/401072 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-2/+2
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* skylake: Add support to S0iX based on host commands from KernelVijay Hiremath2016-11-132-58/+53
| | | | | | | | | | | | | | | | | | Picked the code from Glados branch. Change-Id: I4bf114235c4d542dd7cf0dad6427c771e54d4611 https://chromium-review.googlesource.com/#/c/331358/ BUG=chrome-os-partner:59742 BRANCH=none TEST=make buildall -j Change-Id: Ib79f1209dfd9e6a9de0438cb1866bba2939e5393 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410036 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* kevin: Add Sensor in S3, disable keyboard wakeup in tablet mode.Gwendal Grignou2016-11-041-6/+6
| | | | | | | | | | | | | | | | | | | | Let sensor be powered on in S3. It is useful for Android and if we want to disable keyboard wakeup based on lid angle. Allow EC to disable touchpad and not send keyboard events when lid angle is greater than 180. BUG=chrome-os-partner:57510,chromium:620633 BRANCH=gru TEST=In S3, check the sensors are readable. Check that when in S3 and lid angle is < 180 EC sends keyboard events. Check that when in S3 and lid angle is > 180 EC does not send keyboard events. Change-Id: I4e7959ed37bc5dfdf9c105ecae94c314b253d77f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/406739 Commit-Ready: Gwendal Grignou <gwendal@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: rk3399: Decrease max. latency for aborted suspendShawn Nematbakhsh2016-10-281-20/+20
| | | | | | | | | | | | | | | | Make several calls to msleep() rather than one single call. BUG=chrome-os-partner:58474 BRANCH=gru TEST=S/R stress test on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Icdc8f221c51519e0f2b95d273aa0523ea3a4eeee Reviewed-on: https://chromium-review.googlesource.com/401930 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403460 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Adjust power-down sequencing delaysShawn Nematbakhsh2016-10-281-12/+10
| | | | | | | | | | | | | | BUG=chrome-os-partner:58474 BRANCH=gru TEST=suspend_stress_test on kevin for 50 cycles. Change-Id: Ice721e04c6d4389520f40c4ca72f5bec0e1bdb5b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399992 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403459 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* power: rk3399: turn off the center logic in s3Caesar Wang2016-10-271-5/+6
| | | | | | | | | | | | | CQ-DEPEND=CL:386537 BUG=chrome-os-partner:54291 TEST=turn off the center-logic BRANCH=None Change-Id: I73577e15cc0a8474d8eb2ed1a48f5aba59e54c6a Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/381158 Reviewed-by: Catherine Xu <caxu@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* lpc: Add function for host reset without RCIN GPIODuncan Laurie2016-10-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Prior x86 boards have had GPIO for toggling RCIN directly on the PCH, although many likely had HW-assisted methods as well. With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality software control over RCIN Virtual Wire is not available with the npcx EC, so the legacy LPC interface for pulsing KBRST must be used instead as this is the only way to generate RCIN. This method will likely vary on different EC chips, but for skylake it can just be abstracted into the LPC module. BUG=chrome-os-partner:58666 BRANCH=none TEST=successful 'apreset warm' on eve EC console Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400037 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add board callback before RSMRST# state changeDuncan Laurie2016-10-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | This board function allows workarounds to be applied to a board after all power rails are up but before the AP is out of reset. Most workarounds for power sequencing can go in board init hooks, but for devices where the power sequencing is driven by external PMIC the EC may not get interrupts in time to handle workarounds. For x86 platforms and boards which support RSMRST# passthrough this board callback will allow workarounds to be applied despite the PMIC sequencing by ensuring that the function is executed before RSMRST# deassertion. BUG=chrome-os-partner:58666 BRANCH=none TEST=test IMVP8 workaround on multiple eve boards Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/402591 Reviewed-by: Shawn N <shawnn@chromium.org>
* include: Add default state for ESPI and VW_SIGNALSDuncan Laurie2016-10-252-4/+4
| | | | | | | | | | | | | | Add the default undefined state for CONFIG_ESPI and rename CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS. BUG=chrome-os-partner:58666 BRANCH=none TEST=pass presubmit checks Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400032 Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Debounce PGOOD_SYS signalShawn Nematbakhsh2016-10-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | PGOOD_SYS may glitch for a period not to exceed 1ms. When PGOOD_SYS or PGOOD_AP are deasserted, wait for up to 100ms for both signals return before transitioning out of S0. BUG=chrome-os-partner:56822 BRANCH=gru TEST=Manual on kevin, boot device and verify it remains in S0 without spurious transitions to S3. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I95ccae54fc5939c835f00dc9b7cf88b9d0553c11 Reviewed-on: https://chromium-review.googlesource.com/393148 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit b867d3fc9dea04ac65f5288fb99d3ed65c127644) Reviewed-on: https://chromium-review.googlesource.com/396139 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Enable PP900_PCIE earlier to prevent leakageShawn Nematbakhsh2016-09-301-2/+2
| | | | | | | | | | | | | | | | | | Enable PP90_PCIE along with PPVAR_LOGIC and PP900_AP to avoid leakage. BUG=chrome-os-partner:57952 BRANCH=Gru TEST=Verify kevin powers up / down successfully. Change-Id: I6fa47edcdde482d3fa2f249cfdff6e060a445f42 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/390896 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit b41006ba84bc86e453c241296309fadf9a864032) Reviewed-on: https://chromium-review.googlesource.com/391037 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: common: Prevent console spam.Aseda Aboagye2016-09-261-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The power state driver would print out the current power state along with its signals everytime a power signal interrupt was fired. On some systems, a signal may briefly go low and then come back before our chipset module has a chance to notice. This causes what appears to be duplicate prints. This commit tries to only print out the current power state when something has actually changed. If the input power signals or state differs from the last time it checked, then the information will be printed. BUG=None BRANCH=gru TEST=Find a kevin where PGOOD goes away quite frequently. Build and flash; Verify that significantly less "power state S0" console spam is emitted. TEST=Verify that all state transitions are still printed. Change-Id: I9d66c04e2ed79ab203c54f0a8dad82f32856bbf0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388761 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power: common: Print RTC when changing states.Aseda Aboagye2016-09-231-0/+3
| | | | | | | | | | | | | | | | | | In order to help correlate EC logs with those from the kernel, it was suggested that the EC could periodically print the RTC time. This commit prints out the RTC time when changing power states. BUG=chrome-os-partner:57731 BRANCH=gru TEST=Build and flash kevin. Boot system up and suspend. Verify that RTC times are logged to the EC console. Change-Id: Ia1ee1ec88c6733f863a703fb3f841ab74b80fcb9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388802 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Print RTC when resetting chipset.Aseda Aboagye2016-09-231-0/+3
| | | | | | | | | | | | | | | | | | In order to help correlate EC logs with those from the kernel, it was suggested that the EC could periodically print the RTC time. This commit prints out the RTC time when a chipset reset is requested. BUG=chrome-os-partner:57731 BRANCH=gru TEST=Build and flash kevin. Trigger watchdog from kernel and verify that RTC time is printed when the chipset is reset. Change-Id: Idc9a815c3337f720d41d16e0d844b4c1ea6728d8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388857 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: common: uint64divmod() for host_command_hibernation_delay()Dino Li2016-09-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | This change is implemented so we won't need the 64 bit division for nds32 core(__udivdi3). Please have a look at CL:314400. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Issue the host command by "ectool hibdelay xx" and check if hibernation delay was updated. Change-Id: Ia2f08381e464563d954a6bf5998688cd9298fd38 Reviewed-on: https://chromium-review.googlesource.com/384436 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: rk3399: Minimize resume latency on short suspendShawn Nematbakhsh2016-09-081-0/+25
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:56605 BRANCH=None TEST=Manual on kevin, modify code to force CHECK_ABORTED_SUSPEND() condition to be true for each respective case, verify AP resumes successfully. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib3ec3c287c14ea2b9b410171a173c38c9385a90f Reviewed-on: https://chromium-review.googlesource.com/378078 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* power: rk3399: Hold SYS_RST low before powering on P1.8_PMUShawn Nematbakhsh2016-08-291-8/+12
| | | | | | | | | | | | | | | | | | | Holding SYS_RST low will keep the TPM in reset, and prevent a reset-too-soon-after-power-on case that put the TPM into a bad state. BUG=chrome-os-partner:56414 BRANCH=None TEST=Manual on kevin rev5, verify board still seqences from G3->S0 and back, S0->S5 and back, S0->S3 and back. Change-Id: I07671079deedb757314679608d848b1620aa67d6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374899 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Catherine Xu <caxu@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* power: rk3399: Debounce PGOOD_AP signalShawn Nematbakhsh2016-08-252-7/+39
| | | | | | | | | | | | | | | | | PGOOD_AP may go low for a period < 100ms during regulator output voltage transitions, so ignore such pulses. BRANCH=None BUG=chrome-os-partner:54814 TEST=On kevin, verify suspend / resume succeeds for 10 cycles. Change-Id: I5b6240a570472e1ea74de6e5f2341472ea7afe6b Reviewed-on: https://chromium-review.googlesource.com/374524 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-245-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* apollolake: Do not power-on AP till sufficient power is providedVijay Hiremath2016-08-241-3/+3
| | | | | | | | | | | | | | | | | Do not power-on the AP unless battery can provide sufficient power or the charger is negotiated to sufficient power. BUG=chrome-os-partner:56494 BRANCH=none TEST=Manually tested on Reef. Device can boot to OS without the battery & cut-off battery. Change-Id: Ib22bad81a29ccbb2fecc8e835148b627dd722988 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/374023 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rk3399: Remove useless calls to wireless_set_state()Shawn Nematbakhsh2016-08-241-17/+0
| | | | | | | | | | | | | | | | | rk3399 doesn't use AP-controlled wireless power state and CONFIG_WIRELESS isn't defined, so wireless_set_set() is in fact an empty useless function. BUG=None BRANCH=None TEST=Verify basic EC functionality on Kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6e3631012ca1f356555a847793050ebdef8eee52 Reviewed-on: https://chromium-review.googlesource.com/373643 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: rk3399: Implement latest power sequencingShawn Nematbakhsh2016-08-241-33/+40
| | | | | | | | | | | | | | BUG=chrome-os-partner:55981,chrome-os-partner:56105 BRANCH=None TEST=Verify kevin rev5 sequences up from S5, down to S3, and back to S0. Change-Id: I65b73e4a0a46c631c6e40f154cf92810f5aabb72 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366951 Commit-Ready: Derek Basehore <dbasehore@chromium.org> Tested-by: Catherine Xu <caxu@google.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org>
* power: Add virtual-wire power signals support for skylake.Mulin Chao2016-08-132-7/+54
| | | | | | | | | | | | | | | | | | | Add virtual wire power signals support for skylake. By adding CONFIG_VW_SIGNALS definition in board level driver, we can save three GPIOs (SLP_S3/SLP_S4/CLK_RUN) on skylake platform. Modified sources: 1. common.c: Add support for VW power signals. 2. skylake.c: Add upper func to get system sleep state through GPIOs or VWs. BRANCH=none BUG=none TEST=make buildall; test boot up and shut down on eSPI POC of wheatley. Change-Id: I0eae363dad8cec011eb32929a40701f19fde7e1a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366711 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mkbp_event: Allow host to report sleep state for non-wake event skippingShawn Nematbakhsh2016-08-121-0/+21
| | | | | | | | | | | | | | | | | | | | | | Allow the host to self-report its sleep state through EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND param when the host begins its sleep process. While the host has self-reported that it is in SUSPEND, don't assert the interrupt line, except for designated wake events. BUG=chrome-os-partner:56156 BRANCH=None TEST=On kevin, run 'ectool hostsleepstate suspend', verify that interrupt assertion is skipped for battery host event. Run 'ectool hostsleepstate resume' and verify interrupt is again asserted by the battery host event. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I74288465587ccf7185cec717f7c1810602361b8c Reviewed-on: https://chromium-review.googlesource.com/368391 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin: increase the delay in chipset_resetMary Ruthven2016-07-281-1/+1
| | | | | | | | | | | | | | | | | Cr50 has sys_rst_l as a wake source, but it can't tell which pin woke it on resume. To know the source it has to check the value of the pin on resume. This change makes the delay long enough for Cr50 to resume and check that sys_rst_is asserted. BUG=chrome-os-partner:55674 BUG=b:30308276 BRANCH=none TEST=enable sleep on cr50 and verify apreset still reset it Change-Id: I8e088c5f13a4222142161d8b79550dfc6eb529d6 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364170 Reviewed-by: Shawn N <shawnn@chromium.org>
* rk3399: Start 'force shutdown' timer on initial power pressShawn Nematbakhsh2016-07-261-5/+6
| | | | | | | | | | | | | | | | | | On a power press that will bring the system to S0, start our 8 sec timeout in case the power button is never released. BUG=chrome-os-partner:55666 BRANCH=None TEST=Press and hold power button on kevin to bring device to S0, verify device boots in normal mode and powers down ~8 seconds after initial press. Change-Id: I1cbb52974bcc09d23a130df13815cee07968467a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363592 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rk3399: Transition to / from S3 based upon GPIO_AP_EC_S3_S0_LShawn Nematbakhsh2016-07-211-5/+18
| | | | | | | | | | | | | | | | BRANCH=None TEST=Set GPIO_AP_EC_S3_S0_L high from sysfs, verify EC power state machine enters S3. BUG=chrome-os-partner:54328 CQ-DEPEND=CL:*270114 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0fbd49775c245f3d747ddb46801ed89085829e12 Reviewed-on: https://chromium-review.googlesource.com/352651 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* rk3399: kevin: Inhibit booting w/ insufficient pwrAseda Aboagye2016-07-181-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Before, as soon as the EC started booting, it would unconditionally boot the AP (unless explicitly told not to. ie: "reboot ap-off"). However, we weren't waiting for our power to settle which was causing some brownouts. This would happen when trying to boot without the battery. This commit causes the EC to inhibit powering on the AP until we have sufficient power. BUG=chrome-os-partner:55289 BRANCH=None TEST=Flash EVT2; verify can boot normally. TEST=Remove battery and insert charger. Verify that DUT can boot up. TEST=Insert drained battery. Verify power on is inhbited. Plug in charger and verify that DUT can power on. Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/361005 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: mediatek: Do not block power state by waiting for power button releaseKoro Chen2016-07-111-13/+2
| | | | | | | | | | | | | | | | | | | The firmware needs to talk to the EC while the power button is pressed. If the EC did not even leave the S5->S3 state this is not possible. Seems like the piece of code is not even necessary, check_for_power_off_event will catch the long press asynchronously later on anyway. BRANCH=none BUG=chrome-os-partner:54781 TEST=power up by power button and hold it, there should be no error logs during EC sync, and screen turns on for a short time then off Change-Id: Ic0cccb6cfc5ddd389c1111a77ec06530a9e429ef Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/359152 Reviewed-by: Rong Chang <rongchang@chromium.org>
* power: rk3399: Control power state properly on power button / lid toggleShawn Nematbakhsh2016-06-241-10/+45
| | | | | | | | | | | | | | | | | | | | | | | | - Power up the AP automatically on initial EC power-on. - In S0, wait for 8s power button hold before powering down. - In S3 and lower, power down immediately on power press. - In G3 / S5, power up on lid open. BUG=chrome-os-partner:54582,chrome-os-partner:54511 BRANCH=None TEST=Manual on gru. Verify the following: - AP powers up when battery initially attached. - `reboot` powers up AP after EC reset. - `reboot ap-off` doesn't power up AP. - `apshutdown` + `lidclose` + `lidopen` causes AP power-up. - Holding power for 4s in S0 does not change power state. - Holding power for 8s in S0 causes AP power down. Change-Id: I588056549a972212c28b9aa6a83fe2e0b179baa9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355650 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* gru/kevin: Turn PP1800_PMU on earlier in sequenceDavid Schneider2016-06-141-2/+2
| | | | | | | | | | | | | | | PP1800_PMU impacts the initial centerlogic voltage due to DVS circuitry. Since there's no other sequencing dependency, turn it on earlier. This fixes centerlogic from initially starting too high (1.5V). BUG=none BRANCH=none TEST=Watch PPVAR_CENTERLOGIC and confirm that it starts at the target voltage Change-Id: Icac076a7e8aef978401452a98d9f6bc8b373d94f Signed-off-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/352247 Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Enable charging of USB-A devices in S3Shawn Nematbakhsh2016-06-141-15/+0
| | | | | | | | | | | | | | | | | Leave USB-A charging enabled in S3, and move gru-specific code into board hooks, out of the power state driver. BUG=chrome-os-partner:54159 BRANCH=None TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and deasserted in G3. Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/351670 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: rk3399: Add power-down sequencingShawn Nematbakhsh2016-06-141-51/+37
| | | | | | | | | | | | | | | | | Power-down sequence in reverse order of power-up, with delays extended to 10ms, to allow rails extra time to decay. BUG=chrome-os-partner:54159 BRANCH=None TEST=Manual on gru. Verify repeated `powerbtn` commands on console boot + power-down the SOC. Change-Id: I2e8fb39f8f900e56deef6b386bae1c336aa1f963 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/351520 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* apollolake: modify PMIC_EN and RSMRST_N handlingKevin K Wong2016-05-271-19/+38
| | | | | | | | | | | | | | | | | | | | | | Move power rail and pmic enable control to be handled at board level due to specific board design. Modify rsmrst where assertion is pass-through at all time and de-assertion is only pass-through at power up. BUG=chrome-os-partner:53666 BRANCH=none TEST=amenia is able to handle apreset warm/cold, pmic shutdown, soc reset/shutdown. Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/347370 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* reef: Initial commitDavid Hendricks2016-05-201-4/+10
| | | | | | | | | | | | | | | | This adds the basic framework for Reef including full GPIO listing, board config file, and rudimentary functionality. It has not been fully tested and still has several TODOs/FIXMEs. For now we just need something that will build and can be incrementally improved. BUG=chrome-os-partner:53035 BRANCH=none TEST=EC and AP both boot, seems reasonably stable for now Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339292 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* gru: Initial mainboard commitShawn Nematbakhsh2016-05-041-0/+15
| | | | | | | | | | | | | | | | Clone of kevin w/ minor GPIO / LED changes. BUG=chrome-os-partner:52736 BRANCH=None TEST=Verify image boots + sequences on kevin p1. Change-Id: I7d3f3ce97a8b080516b635a3d2b7bc3c6515c6d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340542 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* rk3399: Set power state based on input signalsShawn Nematbakhsh2016-05-041-9/+49
| | | | | | | | | | | | | | | | | | | | | Use input signals to verify power state and determine power state after sysjump. BUG=chrome-os-partner:52878 BRANCH=None TEST=Manual on kevin. - Verify AP powers up on 'powerbtn'. - AP shuts down on 'apshutdown'. - AP re-powers / resets on 'powerbtn' + 'apreset'. - AP doesn't shutdown on 'sysjump rw' while in S0. Change-Id: Id24feb0f8490aa7cb73c46178085ff2e46f8d0a6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341704 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: ignore PLTRST# from SOC unless RSMRST# is deassertedKevin K Wong2016-05-031-0/+15
| | | | | | | | | | | | | add optional chipset specific function to check if PLTRST# is valid BUG=chrome-os-partner:52656 BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341732 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: GPIO changes for new proto buildShawn Nematbakhsh2016-04-291-6/+3
| | | | | | | | | | | | | BUG=chrome-os-partner:52171 TEST=Verify old kevin boards still boot + power sequence. BRANCH=None Change-Id: Iacc02beba05ef3e80ffa59aa7fc5718c12bae20c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338043 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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