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* system: Remember if reset was due to AP watchdog triggeringNicolas Boichat2018-10-301-1/+6
| | | | | | | | | | | | | | | | | | | | On MT8183, when EC detects a watchdog reset, EC needs to reboot itself in preparation for the next boot. This means that AP loses the reset cause (as AP system reset is toggled), and, therefore, we need to save the reset reason in the EC. BRANCH=none BUG=b:109900671 TEST=apshutdown, powerb, see that reset reason is: reset-pin TEST=Use test-wd from bug. Reset reason: reset-pin ap-watchdog Change-Id: I2e30306db5727a22de930f00dc30de40b9695bef Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1295890 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1309037 Reviewed-by: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org>
* power: add chipset_in_or_transitioning_to_stateJett Rink2018-09-181-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need a method that we can call from the chipset notify hooks that can clearly distinguish which state you are about to be in. This is made evident by the child CL for putting a MUX into low power mode in S5. Without this method, we have to put chipset state into the PD task variable and use that instead (since chipset_in_state won't work because we are in the S3S5 state) BRANCH=none BUG=b:112136208,b:111196155,chromium:736508 TEST=On Phaser the 3300_pd_a drops from 92mW to 32 mW when the charger is plugged into C1 and the SoC is in S5. The rail also says at 32mW after removing and plugging the power back in while the SoC is in S5. Also ensured that power is low upon first insertion and AP does not come on automatically. Change-Id: I93cce2aa319c9689efce222919e5389471001a00 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1211368 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1230981 Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org>
* power/mt8183: Keep PMIC_WATCHDOG_L low in S5/S3Nicolas Boichat2018-08-311-2/+3
| | | | | | | | | | | | | | | | Instead of pulsing the watchdog to PMIC, keep it low in S5/G3. This avoids leaking power from EC to PMIC in S5/G3, when the PMIC is off. BRANCH=none BUG=b:113559677 TEST=In G3, pp1800_ec_mw power consumption drops from ~23mW to <1mW. Change-Id: I37bc8e5e6954834e1ae2bc1206919f342273b888 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1195300 Reviewed-by: Yilun Lin <yllin@chromium.org>
* power/mt8183: Fix power sequencingNicolas Boichat2018-08-311-6/+32
| | | | | | | | | | | | | | | | | | | | | | Fix power sequencing: 1. Replace power_has_signals(...) with power_get_signals() & ... to reduce unwanted noise during boot 2. PMIC_FORCE_RESET only takes about 5ms to work. 3. In G3, switch back to S5->G3 if the PMIC happens to be on again. 4. On boot, start from S5 instead of G3 if the PMIC is on. 5. In S5->S3, retry to turn on PMIC if the first attempt fails (this is necessary after a force reset) BRANCH=none BUG=b:109850749 TEST=Cycles of apshutdown, powerbtn; EC reboot TEST=apshutdown, sysjump rw, powerbtn works properly Change-Id: I2e52e267eab9d45d30036f75cfd6b821d3b13638 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194546 Reviewed-by: Yilun Lin <yllin@chromium.org>
* cheza: Disable interrupts which are floating when switchcap offWai-Hong Tam2018-08-311-0/+9
| | | | | | | | | | | | | | | | The power signals, AP_RST_L and PMIC_FAULT_L, are floating when switchcap off. Disable their interrupts. The PS_HOLD and POWER_GOOD should be OK as they have pull-down. BRANCH=none BUG=b:78455067 TEST=Checked "power on", "power off", "apshutdown", and "apreset". Change-Id: I17e4c7e8f82e950b52d750961f4b5efc01c18ccf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180066 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Use POWER_GOOD signal instead of AP_RST_LWai-Hong Tam2018-08-311-21/+21
| | | | | | | | | | | | | | | | | | | | | | | The AP_RST_L is not a good signal to indicate power good. For an AP initiated warm reset (the Qualcomm way), AP pulls down PS_HOLD for a short pulse, and then PMIC pulls down AP_RST_L for another short pulse. This short pulse confuses EC from a power-lost. We use a confirmation logic to differentiate this case as a workaround. This CL uses another signal POWER_GOOD, which is SRC_PP1800_S4A from PMIC, as an indicator. CQ-DEPEND=CL:1169952 BRANCH=none BUG=b:78455067 TEST=Checked "power on", "power off", "apshutdown", and "apreset". Verifed the power-off sequence: * if the PMIC registers not programmed, it forces off switchcap. * if the PMIC registers programmed, it does graceful PMIC shutdown. Change-Id: I847eef5d4202485b70354b3f65ce24cd1ccb7ece Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1169953 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* Revert "cheza: Support confirmation of power lost"Wai-Hong Tam2018-08-311-51/+2
| | | | | | | | | | | | | | | | | This reverts commit 548e4d9708cc4402497ed290daf4df672114302c. The following CL uses the POWER_GOOD signal as an indicator, instead of the AP_RST_L which has a short low pulse during warm reset. So revert the confirmation logic for the AP_RST_L. BRANCH=none BUG=b:78455067 TEST=Check the following CL. Change-Id: Iec0a7592f8dd1686b1bce8304b42ad0407b6dfde Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1169952 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* kukui: Change FORCE_RESET to ODLNicolas Boichat2018-08-291-3/+3
| | | | | | | | | | | | | | Also, FORCE_RESET is open-drain, active-low. Also, set the default to high. BRANCH=none BUG=b:112616655 TEST=boot rev1 to coreboot Change-Id: I33bd4a97831313f7bc5c3f0044c5b44d88932060 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1192722 Reviewed-by: Yilun Lin <yllin@chromium.org>
* cheza: Add more power signals for informative purposeWai-Hong Tam2018-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | No power sequence logic is chanaged. Add PS_HOLD, PMIC_FAULT_L, and POWER_GOOD (the real one, not AP_RST_L) as power signals. If their states change, the EC console will show it and the timestamp. BRANCH=none BUG=b:78455067 TEST=Ran "gpioset SWITCHCAP_ON_L 0" and showed the signals changed: 7 signal changes: 750.164712 +0.000000 AP_RST_L => 0 750.164810 +0.000098 PMIC_FAULT_L => 0 750.165312 +0.000502 PS_HOLD => 0 750.166565 +0.001253 POWER_GOOD => 0 750.206345 +0.039780 PMIC_FAULT_L => 1 751.190869 +0.984524 PMIC_FAULT_L => 0 751.233388 +0.042519 PMIC_FAULT_L => 1 Change-Id: I1237f4fff20e2256f504d3c9d11ed26da5224ecd Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1169951 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* power/mt8183: Power sequence from S5, not G3Nicolas Boichat2018-08-241-19/+22
| | | | | | | | | | | | | | | | | | | The previous code was switching on the AP on G3 to S5 transition, this causes problems as there is a 10s timeout in the S5 to G3 transition, so we would not be able to boot the AP from S5. The only difference now between S5 and G3, is the case where the PMIC fails to shut down properly: we only enter G3 if the PMIC shuts down as expected. BRANCH=none BUG=b:109850749 TEST=make BOARD=kukui -j Change-Id: I260146e6d4622a76ad3a53d67fdde43a8669697c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1181008 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* ICL: Fix the timeout value for SUS_SLP_L in G3S5 stateScott Collyer2018-08-221-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | The function power_wait_signals_timeout() expects the timeout value to be in usec, but a value in msec was being passed in. In addition, measuring on a system shows that the signal wait is ~150 msec, so increased the timeout value to 250 mSec. BUG=b:112913718 BRANCH=none TEST=Verfied that with this change I no longer see the console message: SLP_SUS_L didn't go high! Assuming G3. powerinfo shows: > powerinfo [2470.263452 power state 3 = S0, in 0x003f] Change-Id: I6564cbab638b80234a2574f3f700d1f33c516de1 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1184330 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* cheza: Check switchcap GPIO0 which indicates outputting good voltageWai-Hong Tam2018-08-131-0/+43
| | | | | | | | | | | | | | | | | When turnning the switchcap on, wait its GPIO0 asserted. The GPIO0 is configured as PVC_PG. When the output voltage is over the threshold PVC_PG_ADJ (3.0V), the PVC_PG is asserted. BRANCH=none BUG=b:77957956 TEST=Run "power on" and "power off" on EC console. Adding debug messages, confirmed waiting the signal asserted. Change-Id: Iac72be5290c7ba9988b5861db1dbd84c24f93eda Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1145952 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* intel_x86: fix the build error when removing CONFIG_POWER_S0IXZhuohao Lee2018-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | The ec build error if the CONFIG_POWER_S0IX is removed from board.h This patch fixes the build error: power/intel_x86.c:515:13: error: 'lpc_s0ix_suspend_clear_masks' defined but not used [-Werror=unused-function] static void lpc_s0ix_suspend_clear_masks(void) ^ power/intel_x86.c:529:13: error: 'lpc_s0ix_resume_restore_masks' defined but not used [-Werror=unused-function] static void lpc_s0ix_resume_restore_masks(void) ^ BUG=none BRANCH=master TEST=1. make buildall -j 2. Removing CONFIG_POWER_S0IX from rammus/board.h, build pass Change-Id: I8c533736a7efb9f9f78ff71044431dd8a1698481 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1168271 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* icelake: Correct POWER_G3S5 exit statusVijay Hiremath2018-08-091-11/+4
| | | | | | | | | | | | | | | | | | For Icelake SLP_SUS_L deassertion is the exit state to go to POWER_S5 state hence corrected the logic to wait on SLP_SUS_L deassertion. BUG=b:111851944, b:111810925 BRANCH=none TEST=ICLRVP & Dragonegg can boot to S0 Change-Id: I65a04a448bb97223589f6d1338249c87ab395f42 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1162661 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* icelake: Add power sequencing support for icelakeScott Collyer2018-07-274-1/+178
| | | | | | | | | | | | | | | | | This CL adds code to support x86 power sequencing for icelake. BRANCH=none CQ-DEPEND=I0bf29d69de471c64f905ee8aa070b15b4f34f2ba BUG=b:111121615,b:111853963 TEST=make buildall. Also tested on P0 and verified that AP gets to S0. Change-Id: I3513f2e598162b2362d56c33df76d16b63864bd3 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123318 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-272-6/+6
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cheza: Remove the switchcap hackWai-Hong Tam2018-07-261-1/+1
| | | | | | | | | | | | | Don't need it as the switchcap has been OTP'ed. BRANCH=none BUG=b:77957956 TEST=On the rev-1 board, power-on and power-off work. Change-Id: I318e658b34d2ebdd8cd169bc5690aa1edd669008 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1080998 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Change GPIO for the rev-1 boardWai-Hong Tam2018-07-261-5/+5
| | | | | | | | | | | | | Reflect the chanages on the rev-1 board. BRANCH=none BUG=b:79548010 TEST=Verified on the rev-1 board, power-on and off, USB boot to kernel. Change-Id: I933ff8dc171954dd6c44e0031016b300f15aa24e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1080995 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* reset: Log the reason for AP resets.Jonathan Brandmeyer2018-07-2611-55/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a new EC host command 'uptime info' which gathers up some information which may be useful for debugging spurious resets on the AP (was the EC reset recently? Why was the EC reset? If the EC reset the AP, why did it do so?, etc.). Provide ectool support for the same. Example results of `ectool uptimeinfo`: ``` localhost ~ # ectool uptimeinfo EC uptime: 475.368 seconds AP resets since EC boot: 2 Most recent AP reset causes: 315.903: reset: console command 363.507: reset: keyboard warm reboot EC reset flags at last EC boot: reset-pin | sysjump ``` BRANCH=none TEST=Perform some `apreset` commands from the EC console and observe their side-effects via the `ectool uptimeinfo` command on the AP side. Test sequences include no-resets through 5 resets, observing that the ring buffer handling was correct. BUG=b:110788201, b:79529789 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I0bf29d69de471c64f905ee8aa070b15b4f34f2ba Reviewed-on: https://chromium-review.googlesource.com/1139028 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power: Add power_get_state APIDaisuke Nojiri2018-07-251-0/+5
| | | | | | | | | | | | | | | | | This patch adds power_get_state API, which returns the low-level power chipset state. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=make buildall Change-Id: I104fdf9623f64416d8c27d583cd434920808afdb Reviewed-on: https://chromium-review.googlesource.com/1144447 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power/mt8183: Fix PMIC_EN_ODL polarity, watchdog signalNicolas Boichat2018-07-231-2/+2
| | | | | | | | | | | | | | | | Watchdog signal should on high by default (and only pulsed to shut down the PMIC). Also, PMIC_EN_ODL is active-low, fix polarity. BRANCH=none BUG=b:109850749 TEST=make BOARD=kukui -j => Boot to FW Change-Id: I3f69bfd75c02ae958785153593d4494c02f39172 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1146132 Reviewed-by: Yilun Lin <yllin@chromium.org>
* power/mt8183: Remove use of GPIO_PP1800_S0_EN.Yilun Lin2018-06-201-2/+0
| | | | | | | | | | | | | TEST=make BOARD=kukui BUG=None BRANCH=None Change-Id: I09b8efb1215abfc53904a8ceb8273d88ef9fbbb1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1105804 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Remove Kahlee boardMartin Roth2018-06-151-8/+0
| | | | | | | | | | | | | The Kahlee/CDX03 board is no longer used. BUG=b:77693343 TEST=None BRANCH=None Change-Id: I2e0495dc1895d03b54cd6d1b9e13e1b84efb5bad Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1091394 Reviewed-by: Jett Rink <jettrink@chromium.org>
* host_event: Handle SCI/SMI masks correctly when using S0ixFurquan Shaikh2018-06-151-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When host is using S0ix, BIOS is not involved during suspend or resume paths. Thus, until now, SCI and SMI masks were preserved across S0ix suspend/resume cycles. However, it was identified in b:78497503 that if SCI is generated after host enters S0ix, then it results in EC eSPI controller waiting for host controller to respond to the SCI virtual wire event. This prevents the EC from entering low power idle mode. In order to fix the above issue, this change ensures that SCI and SMI masks are cleared when host expresses its interest to enter S0ix. Since these masks are not re-programmed by the host on resume, EC maintains backup copies of both the masks. On resume from S0ix, backup copies are used to restore the masks for SCI and SMI. This change applies to both eSPI and LPC systems since SCI/SMI should not be generated (physical or virtual) when host is in S0ix. This implementation follows the design proposed in: https://docs.google.com/document/d/1J2VYeVXV-KZnIHvtDyOrcH4AXJipsSX6m8oZIDSdtv8/edit?usp=sharing BUG=b:78497503 BRANCH=None TEST=Verified following: 1. SCI and SMI masks are programmed correctly on boot-up. 2. SCI and SMI masks are set to 0 when host enters S0ix. 3. SCI and SMI masks are restored correctly on S0ix resume. Change-Id: Iaa3981e6545d2d3cff51649642f6926f0d4ec31f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1099968 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power/mt8183: Power sequencing logic for MT8183Nicolas Boichat2018-06-142-0/+329
| | | | | | | | | | | | | | | | | | | | | | | | | MT8183 uses a power sequencing inspired from RK3399, with fewer signals. We only have 1 signal from PMIC (PMIC_PWR_GOOD), active in S0/S3, and 1 signal from AP (AP_IN_S3_L), active in S3/S5. One particularity of this design is that we need to reboot the EC to RO on every single cold boot/reboot. For the forced transition to S5, we assert the WATCHDOG signal to PMIC to shut it down, which should usually work, if the PMIC was configured properly by AP. If not, we also assert power+home key (PMIC_EN_ODL) until the PMIC shuts down for good. BRANCH=none BUG=b:109850749 TEST=make BOARD=kukui -j Change-Id: Ibcde8b937d7f4cecb0f470b9a7e0809fc24efae6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1092402 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Add CONFIG_* option for PROCHOT polarity.Aseda Aboagye2018-06-083-0/+17
| | | | | | | | | | | | | | | | | | | The common x86 chipset code assumed that CPU_PROCHOT was active high, however on some boards it's actually active low. This commit simply adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts the places where the signal is used. BUG=b:109882953 BRANCH=poppy TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted by default. Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1092150 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Fizz: add CONFIG_BOARD_HAS_RTC_RESETRyan Zhang2018-06-071-0/+5
| | | | | | | | | | | | | | | | | | | | | This patch resets the RTC of the SoC when the system doesn't leave S5. If it fails 5 times, the system will go back to and stay in G3. BUG=b:79323716 BRANCH=fizz TEST=Boot Fizz differently: 1. AC plug-in 2. Power button press 3. reboot EC command 4. servo reset button 5. Recovery mode Change-Id: I728c99c342fb888600599acbe25f72a478ccf948 Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020583 Reviewed-on: https://chromium-review.googlesource.com/1089035 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* power: Rename rockchip to rk3288Nicolas Boichat2018-06-072-1/+1
| | | | | | | | | | | | | Get rid of a TODO. BRANCH=none BUG=b:35569119 TEST=make buildall -j Change-Id: Ia918c90519220a348f8c65b6b6f14b6d3129a63a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090523 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Rename mediatek to mt817xNicolas Boichat2018-06-072-2/+2
| | | | | | | | | | | BRANCH=none BUG=b:109850749 TEST=make buildall -j Change-Id: I69538a210f9b2198614720537faa3ee75bc0600e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090522 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stoney: Rename GPIO_PCH_RCIN_L to GPIO_SYS_RESET_LJonathan Brandmeyer2018-06-051-2/+2
| | | | | | | | | | | | | | Pin rename only; no functional changes. See also b/72426192 for earlier functional changes. BUG=b:77301519 TEST=make -j buildall BRANCH=none Change-Id: I18e71118e584a5b36ba001bac24951929d2c93ff Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1087207 Reviewed-by: Edward Hill <ecgh@chromium.org>
* stoney: strip unused forcing_coldreset path.Jonathan Brandmeyer2018-06-041-12/+2
| | | | | | | | | | | | | | This is just a dead code elimination; no functional changes. See also b/72426192 for functional changes. BUG=b:77301519 TEST=power cycle on grunt EVT BRANCH=none Change-Id: Id9f60d14eb2a7df9013f779b05a54638ad62971f Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1083317 Reviewed-by: Edward Hill <ecgh@chromium.org>
* APL/GLK: Clean up UART buffer before shutdownVijay Hiremath2018-05-231-0/+8
| | | | | | | | | | | | | | | | | | | | UART buffer gets overwritten by other tasks if it is not explicitly flushed before printing it on the console by same task. Hence, clean up the UART buffer so that all the debug messages are printed on the UART console before doing shutdown. BUG=b:79950369 BRANCH=none TEST=Manually tested on BIP, observed that UART logs are not lost on the terminal when apshutdown is issued. Change-Id: I420e9de9e2e71913ee3168267a6f3a2728b2690b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1064977 Commit-Ready: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-232-6/+6
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cheza: Check power enough and enable PP5000 when power-on APWai-Hong Tam2018-05-221-0/+51
| | | | | | | | | | | | | | | | | | | | | | | Remove the previous hack of force increasing the adapter current. The PP5000 rail is now turned on/off during power-on/off AP. Add a check to ensure it has enough power to enable the 5V rail and boot AP. If the battery is in low level or unplugged and the charger adapter doesn't supply enough power, don't boot AP and transition back to S5. The check may wait a while for PD negoiation. BRANCH=none BUG=b:79353631 TEST=On battery plugged and unplugged cases, checked the device can source VBUS to USB port-0 and port-1. TEST=Unplug battery and use a low-power adapter, can't boot up AP. See the "Not enough power to boot" message and transition to S5. Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050607
* cheza: Support confirmation of power lostTom Wai-Hong Tam2018-05-081-2/+51
| | | | | | | | | | | | | | | | | | | | | | Keep the timestamp of the latest power lost. Add a handler to wake the chipset task to check if power lost stays low for a while (the time between now and the latest power lost is longer than a period). BRANCH=none BUG=b:78455067 TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset sequence and verified AP reset but not a transition S0 -> S5. TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse (see power_off function) to execute PMIC shutdown sequence and verified a power-lost transition S0 -> S5. Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028831 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Enable AP_RST_REQ as a request from AP to reset itselfWai-Hong Tam2018-05-081-1/+27
| | | | | | | | | | | | | | | | | | | | | | | This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising edge interrupts to trigger a hook to call chipset_reset(). As the hook task will be preempted by the chipset task, it adds a flag bypass_power_lost_trigger to avoid triggering to S5 as the chipset state machines sees power lost during the reset. So far the chipset_reset() implementation is to do a cold reset; will be revised to a warm reset after the PMIC registers are reprogrammed. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran 'reboot' on AP console which toggles the GPIO. Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1023986 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Make sure switchcap is configured rightAlexandru M Stan2018-05-041-1/+1
| | | | | | | | | | | | | | | | | | Configure switchcap every time we're about to change the signal, just in case it forgot. Feel free to revert this after b/77957956 is fixed. BRANCH=none BUG=b:77957956 TEST="i2cxfer r 0 0xd0 0x2" never shows 0x70, even after a bad brownout (like "gpioset EN_PP5000_A 1" on an unreworked board) Change-Id: I8994cd402ce96d8bf4e436dadfc0e572e7f77a85 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024501 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Add SDM845 power sequence for rev-0 boardWai-Hong Tam2018-05-042-0/+641
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the power sequence for rev-0 board. Confirmed the behavior of reprogramming the PMIC registers to enable the instant reset and shutdown. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control pwr_button:press sleep:0.2 pwr_button:release Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0 * Console command: power off Result: S0 -> S5 -> G3 * Console command: power on Result: G3 -> S0 * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969702
* power/rk3399: Check aborted suspend for s0s3_usb_wake_power_seqPhilip Chen2018-04-201-1/+5
| | | | | | | | | | | | | BUG=b:78321971 BRANCH=scarlet TEST=build kevin and scarlet Change-Id: I9e0c842cd8f4186147fa8e6d001b1c21ddad7e89 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1022746 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org>
* power/common: Preserve 5v enable across sysjumpJustin TerAvest2018-04-191-0/+25
| | | | | | | | | | | | | | | | | | | | | | The value of pwr_5v_en_req needs to be preserved when the EC performs a sysjump, otherwise any task calling power_5v_enable(tid, 0) will drop the 5v rail for the entire system. I've scheduled this at HOOK_PRIO_FIRST for restoring the value to ensure that no other init hooks read a stale value, but I'm not sure if that's necessary. BUG=b:78275296 BRANCH=none TEST=Booted yorp with power only connected to USB-C port 0 Change-Id: I3a9ed24a5fde02b60163ad2c5e3252759f8c1c5b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020066 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stoney: Use chipset_pre_init callbackFurquan Shaikh2018-04-191-2/+7
| | | | | | | | | | | | | | | | Similar to intel_x86, move chipset stoney to using chipset_pre_init callback. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I995bbda01ec78ecd28c302f269cf15739913ecd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018738 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-191-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Get rid of CHIPSET_PRE_INIT hookFurquan Shaikh2018-04-191-3/+0
| | | | | | | | | | | | | | | | | Now that all boards are moved to using chipset_pre_init_callback, get rid of hook notification for CHIPSET_PRE_INIT from x86 power state machine. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018736 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chipset: Add callback for chipset pre-initializationFurquan Shaikh2018-04-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a callback for chipset_pre_init_callback which is made by x86 common power state machine when in G3S5 state. Until now, there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by chipset task when in G3S5 state. However, there are at least following reasons why this should be a callback and not a hook notification: 1. The initialization that is done as part of pre-init could be essential for the power state machine to make progress. Though the chipset task goes to sleep waiting for power signals after the hook notification, pre-initialization can all be done as part of a callback since it is mostly board-specific code that is doing work to initialize PMIC. 2. Typically, boards use I2C transactions to setup PMIC on getting chipset pre-init notification. However, since i2c transfers are not encouraged in hook task, they have to be deferred anyways. 3. Since the initialization is being done as part of hook task, use of any constructs e.g. pwr_5v_en_req which allows multiple consumers to enable/disable power rails will use task id for hook task. Instead it is better to provide correct information about the task by letting chipset task perform this request. Thus, this change adds a callback chipset_pre_init_callback in G3S5 state for x86 power state machine. This callback is guarded by CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK. The hook notification is left as is for now until all x86 boards are moved over to using the newly added callback. BUG=b:78259506 BRANCH=None TEST=None Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018733 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Code cleanup: Remove cold reset logicVijay Hiremath2018-04-036-85/+37
| | | | | | | | | | | | | | | | | | | | | Majority of the chipsets do not have a dedicated GPIO to trigger AP cold reset. Current code either ignores cold reset or does a warm reset instead or have a work around to put AP in S5 and then bring back to S0. In order to avoid the confusion, removed the cold reset logic and only apreset is used hence forth. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually tested on GLKRVP, apreset EC command can reset AP. Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/991052 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stoney: Rename PGOOD GPIOsEdward Hill2018-03-261-14/+14
| | | | | | | | | | | | | | | Rename stoney power signals for clarity: SPOK -> S5_PGOOD VGATE -> S0_PGOOD BUG=none BRANCH=none TEST=power grunt on and off Change-Id: Iee8307138600c10868981a22971beace2de1ca91 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978952 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-254-50/+31
| | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* apollolake: Remove AP cold reset logicVijay Hiremath2018-03-251-29/+8
| | | | | | | | | | | | | | | | | | | | | In APL & GLK, cold reset code does a AP force shutdown (with board specific AP shutdown code) by power sequencing the SOC all the way to S5 and bring it back to S0. However there is no separate GPIO in APL & GLK for doing AP cold reset hence removed the AP cold reset logic. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually verified on GLKRVP, apreset cold & warm behave same Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974107 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-2/+2
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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