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* motionsense: Convert in_spoof_mode to a more generic flagsYuval Peress2019-05-231-3/+8
| | | | | | | | | | | | BUG=b:129159505 BRANCH=arcada TEST=I ran `make buildall` since this change isn't used yet it doesn't affect run-time behavior. Change-Id: I01857d679b800f9b53762c659ebd9a018cbf16db Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1612251 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
* flash_log: add vendor command, timestamp base accessorVadim Bendebury2019-05-231-0/+2
| | | | | | | | | | | | | | | | The new vendor command allows to get and increase the flash log timestamp base. BRANCH=cr50, cr50-mp BUG=b:132287488 TEST=verified in the next patch in the series. Change-Id: Idc76012b7e7894b95cd70eeffeb50562a91b9656 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1610720 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* flash_log: add api for setting base timestampVadim Bendebury2019-05-231-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | The Cr50 environment does not have a wall clock, which makes it impossible to associate flash log entries with real time. This patch provides an API which allows to set a base time value and then use it plus current Cr50 uptime to generate more sensible flash log timestamps. Care is taken to ensure that attempts to set timestamp base such that it would cause a log timestamps rollback do not succeed. A unit test is being added to verify this behavior. BRANCH=none BUG=b:132287488 TEST='make buildall -j' (which runs the new tests) succeeds. Change-Id: I7521df1bac5aef67e0cf634c183bf1618655f48d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1610719 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* PI3USB9281: Serialize mux setting and BC12 detectionDaisuke Nojiri2019-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Currently a PD task and a USB charger task can talk to PI3USB9281 to update mux setting and to get BC12 information interleavingly. We suspect this causes unreliable BC12 detection including detach detection. This patch makes the usb_charger_set_switches API schedule a mux update instead of changing the mux setting by itself wakes up a USB charger task. A USB charger task solely handles BC12 detection and mux setting. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/125176293 BRANCH=nami TEST=Verify BC1.2 and PD charger can be detected correctly and power_supply_info prints 'Discharging' when they're disconnected on Syndra. Change-Id: Iadaf9087be74a4ba0412dd08b95a40eac4e69ce1 Reviewed-on: https://chromium-review.googlesource.com/1622293 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* bq25710: Allow IDCHG to be used as a prochot triggerScott Collyer2019-05-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kohaku units are currently using a 2S+1P battery back which is not able to provide sufficient power for peak CPU load when running on battery only. The bq25710 has various triggers for prochot and one of those is IDCHG (battery discharge current). This CL adds a new config option CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA to enable this feature in the bq25710. For prochot to be active, the bq25710 must remain in performance mode. Chispet hooks are used to request the bq25710 in/out of performace mode when the IDCHG prochot feature is active. BUG=b:132285560 BRANCH=none TEST=Manual Connected wires to VBAT, PPVAR_SYS, PROCHOT_ODL signals and had a current probe connected to measure IBAT. Verfied that without this CL, VBAT shuts off when IBAT spikes. With this CL, then verified that prochot gets asserted whenever the current spikes to values specified by CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA. In addition verified that with this CL, the system can successfully boot and remain powered on even as CPU load gets increased. Change-Id: If13d16f561b76289936d0d75a2b984d2b71b3c37 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1613797 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* USB-PD: Consolidate tcpc_config declarations in usb_pd_tcpm.hDaisuke Nojiri2019-05-211-0/+6
| | | | | | | | | | | | | | | | | | Currently, tcpc_config is declared in two places. This patch consolidates declarations in usb_pd_tcpm.h. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I4f30d06b1eaeb6a83b664de76116d85d65a9fc97 Reviewed-on: https://chromium-review.googlesource.com/1616007 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: add __maybe_unused attributeJack Rosenthal2019-05-201-0/+11
| | | | | | | | | | | | | | | | | | | | | Functions which might go unused under a particular set of CONFIG_ options have historically been wrapped in an ifdef to clear up compiler warnings about unused functions. Since we are trying to reduce conditional compilation in favor of macros like IS_ENABLED, the Linux kernel style guide suggests using __maybe_unused for these functions. This adds the __maybe_unused macro. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ia8239ad566b5aa518c258eaab0e4dceada790da4 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1602489 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tabletmode: ignore lid angle if hall sensor activeJett Rink2019-05-182-0/+15
| | | | | | | | | | | | | | | | | | | | If the 360 degree hall sensor is active, then we should remain in tablet mode even if the lid angle says we are 1 degree since an angle of 360 could wrap around to 1 degree. Also ensure that tablet mode always gets initialized to the correct state at startup (by setting initial value to -1) BRANCH=R75 BUG=b:131785573,b:132178305 TEST=NB_MODE# on arcada does not flutter when the device is at 360 degrees with CL stack. Change-Id: I962a9c23205766080a65d741c6c425452d9de608 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1597189 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common: chip_save_reset_flags takes uint32_tJack Rosenthal2019-05-171-1/+1
| | | | | | | | | | | | | | | The getters and setters for the reset flags should take and return the same type. `uint32_t' seems the more appropraiate type than `int', so change the setter to take `uint32_t'. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I50928a114858dd51034a048520efa849f5182bd0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615648 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: add i2clookup host commandJett Rink2019-05-161-0/+29
| | | | | | | | | | | | | | | Add a new host command that will allow you to lookup a well known device on the EC. This is useful for FAFT tests that want to talk directly with i2c devices but don't know the physical address for each platform. BRANCH=octopus BUG=b:119065537 TEST=Used this with new faft test in CL:1601300 Change-Id: I82c2d5462fcb4edbc92ea60765971190fed7ae81 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1601060 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: common: Make IS_ENABLED fail on unknown valuesRaul E Rangel2019-05-151-16/+36
| | | | | | | | | | | | | | | | | If IS_ENABLED is called with any unknown values, a compiler error will be thrown. This change requires that the optimizer always be enabled, otherwise errors will be thrown when a value is not defined. BUG=none BRANCH=none TEST=make runtests TEST_LIST_HOST="is_enabled_error is_enabled" Change-Id: I1b166311f81d07e48b3665f4bc0e9502d2ccc4c6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592728 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* charge_manager: Revisit charge supplier priority.stabilize-12206.BYilun Lin2019-05-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to USB-C spec 1.3 Table 4-17 "Precedence of power source usage", the supplier's priority should be: USB-C 3.0A/1.5A > BC1.2 > USB-C under 1.5A. This CL propose to raise the BC1.2 priority to fix that charge_manager won't choose BC1.2 when the port reports it can supply both TYPEC 500ma and BC1.2 supplier. According to the spec mentioned aboved, we should prefer BC1.2 rather than TYPEC. Besdies, charge_manager is able to pick the supplier which provides the higheste power. The CL simplifies the supplier priority a bit by taking advantage of the feature. TEST=Charge kukui with 5V/2A charger and see it can drain 1.34A (DCP current bound of mt6370 is 1.5A) rather than 0.5A. TEST=Charge kukui with Type-C 5V3A/CDP/DCP/SDP/PD charger randomly and see that the current it drains is reasonable. TEST=Charge soraka with 'A', and plug another port with 'B', and see it can transist the sinking port from A to B. Here (A, B) are: 1. (SDP 5V0.5A, Type-C 5V3A) 2. (CDP 5V1.5A, PD) 3. (SDP 5V0.5A, CDP 5V1.5A) 4. (CDP 5V1.5A, Type-C 5V3A) 5. (Type-C 5V3A, PD) BUG=b:131126720 BRANCH=None Change-Id: I46384e09d764aa926129358657d0593fca4923c2 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1581859 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* retimer: Add driver support for Intel Burnside Bridge retimerVijay Hiremath2019-05-143-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Burnside Bridge is a Type-C multi-protocol retimer to be used in on-board applications. Burnside Bridge offers the ability to latch protocol signals into on-chip memory before retransmitting them onwards. It can be used to extend the physical length of the system without increasing high frequency jitter. Burnside Bridge supports spec compliant retimer of following protocols: 1. Display Port: four unidirectional DP lanes 2. USB3.1 Gen1/2: one bi-directional USB lane 3. Thunderbolt: two bi-directional CIO lanes 4. Multifunction Display (MFD): two unidirectional lanes of DP and one bi-directional lane of USB3.1 Gen1/2 Note: Only item 1, 2 & 4 are supported in this CL. Item 3 support will be added in follow on CLs. BUG=b:127623438 BRANCH=none TEST=Manually verified on ICLRVP, able to configure the registers Change-Id: I2d60dbcaf8fe7a1503f09a2f16007409f059f54e Signed-off-by: Ayushee <ayushee.shah@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1594170 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
* queue.h: Check at compile time if queue size is power of 2Nicolas Boichat2019-05-141-1/+1
| | | | | | | | | | | | | | | | | Replace the runtime assertion with a compile time one, saves a bit of space (~64 bytes on many boards), and warn users earlier of potential issues. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I7df70b7166dd447a8b1dd8e10710c8bc7ab213e3 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1600943 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* charger/rt946x,krane: Enable backlight power.Yilun Lin2019-05-121-0/+6
| | | | | | | | | | | | | | | Krane's backlight power and PWM is controlled by mt6370. TEST=See the backlight is enabled on krane. BUG=b:131125903 BRANCH=None Change-Id: I9276a73d1a36e6b1eb64b39d7e9e988cda164ada Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1575051 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32: Decouple printf logic from directly calling USB console driverWai-Hong Tam2019-05-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling printf functions, it was to call the USB console driver directly, i.e. copying all the bytes to USB package buffer and enabling the transmission. If the next printf is called immediately before the USB transmission is done, it will wait (polling the EP_TX_VALID status). This implementation limited each printf function can only transmit 64 bytes, i.e. the USB max package size. The remaining bytes will be dropped silently. To fix this issue, this CL puts a queue between the printf logic and the driver. The size of the queue is 2048-byte (no overflow happened on a normal boot and console commands). The printf logic now fills the queue and schedules a deferred hook to handle the transmission. When the transmission is done, an interrupt will be triggered that schedules the deferred hook again to check any remaining bytes need to be transmitted. For the incoming bytes, replace the circular buffer to a queue structure for better reusability. No major logic changes. BRANCH=servo BUG=b:129423678 TEST=Manually added a printf call to show >64 bytes and verified it. TEST=Manually added a printf call to show >2048 bytes and the bytes after the 2048-th dropped silently. Change-Id: Icb2310421d7bcbbff8d7cd753c732390acc43ab8 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1597960 Commit-Ready: Todd Broch <tbroch@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: rebuild board image if essential make variables changeVadim Bendebury2019-05-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When building Cr50 board image, some make variables get converted into compilation flags, which affect image composition. Changes of these variables go unnoticed as they do not directly affect make dependencies. Let's define the set of essential variables in ENV_VARS, and save the state of these variables at build time in a generated .h file, updating it only if any of the variables' values changed since the previous make run. The generated .h file is included in board.h, which guarantees that files dependent on board.h are recompiled if the generated .h file changes. BRANCH=cr50 BUG=none TEST=verified that changing of CR50_DEV and/or H1_RED_BOARD or CR50_SQA values triggers full rebuild of the Cr50 image. Verified that 'emerge-atlas ec-utils' also succeeds. Change-Id: Id0589a3b6a66fe4da90a9aea894bc83eb6337c8c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707915 Reviewed-by: Keith Short <keithshort@chromium.org>
* tcs3400: rename tcs3400_drv_data_t to als_drv_data_tNick Vaccaro2019-05-091-0/+10
| | | | | | | | | | | | | | | | | | | - rename tsc3400_drv_data_t to als_drv_data_t - change tcs3400 driver to use common als_drv_data_t - change flapjack config to use common als_drv_data_t - rename TSC3400_SCALE() macro to ALS_CHANNEL_SCALE() - create and use new I2C_PORT_ALS definition - fix a couple nits BUG=b:124512628 BRANCH=master TEST=build and flash to flapjack, verify ALS and RGB still work. Change-Id: I9a45d255ff77794ef34026406c9b702a04e09c11 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://chromium-review.googlesource.com/1601052 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* MAX17055: Add the full model driverYH Lin2019-05-081-0/+6
| | | | | | | | | | | | | | | | | This patch adds the full model driver for MAX17055. The full model of MAX17055 provides more accurate soc estimation than the short model or ez model. BUG=b:130979269 BRANCH=none TEST=Do a full charge test Change-Id: I4cf249cf0c47fd30f75f4e38b74c7995285603e6 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1577387 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power: Manipulate wake mask during s0ix timeoutsEvan Green2019-05-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | When S0ix failure detection is enabled and a timeout occurs such that the SLP_S0 line never actually toggles, then s0ix_transition_timeout() sets the HANG_DETECT event bit. This doesn't quite work in this scenario, since the wake mask is only enabled when the power state transitions to S0ix, which happens when the SLP_S0 line toggles. So the AP never sees the event, since it's not in the wake mask and so never causes the EC->AP interrupt line to change. Detect this situation in the timeout function, and explicitly move the wake mask to its S0ix value so that when the event bit is set, (if it is in the wake mask), the system will wake up. Doing this forcefully gets the wake mask out of sync with the power state. So upon resume, explicitly restore the wake mask to its S0 state. BUG=b:131434497 BRANCH=none TEST=suspend_stress_test -c1 --suspend_min=60 with a firmware where S0ix fails. Change-Id: Id2e67c6933a7895fba85ccfdff9b336629eabf24 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592469 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* makefile: don't build ro if EC_INCLUDE_RO not setTing Shen2019-05-081-1/+1
| | | | | | | | | | | | | | BUG=b:121406695 TEST=make BRANCH=None Change-Id: Ib678678330837fefffd12a7ac445038661639e8c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1595929 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* USB-PD: Add hook for PD connect eventDaisuke Nojiri2019-05-082-3/+8
| | | | | | | | | | | | | | | | This patch adds a hook for USB PD connect event. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/127228934 BRANCH=none TEST=buildall. Verify a hook is called on BC12 charger connection. Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3 Reviewed-on: https://chromium-review.googlesource.com/1597794 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd_protocol.c: exiting from try.src to attach.srcRuibin Chang2019-05-071-0/+8
| | | | | | | | | | | | | | | | | | | | The port shall transition to Attached.SRC when the SRC.Rd state is detected on exactly "one of the CC1 or CC2 pins" for at least tTryCCDebounce. See TypeC v1.4 spec 4.5.2.2.10.2 Exiting from Try.SRC State. BRANCH=None BUG=b:130615676 TEST=1.Ampton with apple type-c adapter 2.Ellisys USB-PD test Change-Id: I461c53e2b8d9189f290956964754ae5b1a11a950 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1564499 Commit-Ready: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver: add tcs3400 RGB channel sensor driverNick Vaccaro2019-05-071-0/+12
| | | | | | | | | | | | | | | | | | | Implements a MOTIONSENSE_TYPE_LIGHT_RGB sensor using the tcs3400. BUG=b:129419982 BRANCH=master CQ-DEPEND=CL:1541955 TEST=cherry-pick CLs to enable tcs3400 for flapjack and to add alslog, build and flash to flapjack; boot flapjack, from ec console, execute 'sysjump rw', then execute "alslog" to enable logging of als data. Verify als data is generated and logged to ec console. Change-Id: Ia8000d27ff4f9683ceb4c9522bc7f0fed20c2045 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551748 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* driver: add tcs3400 ALS sensor chip driverNick Vaccaro2019-05-062-0/+17
| | | | | | | | | | | | | | | | | | | Implements a MOTIONSENSE_TYPE_LIGHT sensor using the clear channel of the tcs3400. BUG=b:124512628 BRANCH=master TEST=cherry-pick CLs to enable tcs3400 for flapjack and to add alslog, build and flash to flapjack; boot flapjack, from ec console, execute 'sysjump rw', then execute "alslog" to enable logging of als data. Verify als data is generated and logged to ec console. Change-Id: I918cbf5513fb5eba20a27705c47545d3c0b3ca91 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://chromium-review.googlesource.com/1541955 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: add MOTIONSENSE_CHIP_TCS3400Nick Vaccaro2019-05-041-0/+1
| | | | | | | | | | | | | | Add new chip definition for AMS TCS3400 light sensor. BUG=b:129419982 BRANCH=master TEST=none Change-Id: Ic66a0922f3c48775f2eaeff0c5ac37a09624a5d6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://chromium-review.googlesource.com/1541954 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: add new MOTIONSENSE_TYPE_LIGHT_RGB sensor typeNick Vaccaro2019-05-041-0/+1
| | | | | | | | | | | | | | Add a new light sensor type for color light sensors. BUG=b:129419982 BRANCH=master TEST=none Change-Id: I30cec56761b1f7f90544dda52a90415d39ded337 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://chromium-review.googlesource.com/1541953 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* ish: preserve panic data across resetJack Rosenthal2019-05-042-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit stores panic data across reset by storing panic data in the last 256 bytes of AON memory (before AON ROM). > crash divzero ========== PANIC ========== Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E Resetting system... =========================== ... ISH reset ... > panicinfo Saved panic data: (NEW) Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E BUG=b:129425206 BRANCH=none TEST=see console output above (on arcada_ish) Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1593418 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: ensure all CONFIGs are undef'ed in include/config.hJack Rosenthal2019-05-041-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some people have been bypassing the pre-submit checks: confs=($(grep -Eor "\bCONFIG_[A-Z_]*" chip/ish/config_chip.h | sort | uniq)) for opt in "${confs[@]}"; do grep "$opt" include/config.h >/dev/null || echo "$opt is not defined in include/config.h!" done >>> CONFIG_ISH_AON_SRAM_BASE_END is not defined in include/config.h! CONFIG_ISH_AON_SRAM_BASE_START is not defined in include/config.h! CONFIG_ISH_AON_SRAM_ROM_SIZE is not defined in include/config.h! CONFIG_ISH_AON_SRAM_ROM_START is not defined in include/config.h! CONFIG_ISH_AON_SRAM_SIZE is not defined in include/config.h! CONFIG_ISH_SRAM_BANKS is not defined in include/config.h! CONFIG_ISH_SRAM_BANK_SIZE is not defined in include/config.h! CONFIG_ISH_SRAM_BASE_END is not defined in include/config.h! CONFIG_ISH_SRAM_BASE_START is not defined in include/config.h! CONFIG_ISH_SRAM_SIZE is not defined in include/config.h! This is not good! This commit renames each of these to an existing option defined in include/config.h, or undefs the relevant option in include/config.h. BUG=b:131749055 BRANCH=none TEST=make buildall -j TEST=script above reports no options which weren't defined TEST=arcada_ish, (specifically power management, which was greatly affected by this commit) functions as normal Change-Id: Idfbd1105880174b5e160c47c4ec1d88c352d6bc6 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592420 Reviewed-by: Jett Rink <jettrink@chromium.org>
* 7-seg display: Add config to display port80 msg and power statesAyushee2019-05-031-0/+9
| | | | | | | | | | | | | | | | | Adding this CL to display port80 message and power states of EC & SOC on the 7-segment display. BRANCH=None BUG=b:130738086 TEST=Manually tested on intelrvp, able to verify the power states and port80 message displayed on the 7 segment display Change-Id: I4437cfcd60662c8637e406e425f98fad1a4ba7ed Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1575433 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add buffer_units_mask member into struct queueNamyoon Woo2019-05-021-0/+2
| | | | | | | | | | | | | | "q->buffer_units - 1" is performed many times to wrap head and/or tail. It should be calculated once. BUG=None BRANCH=cr50 TEST=None Change-Id: I9714147d5a97afd7aaba00d31a8b10bad50d0942 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1572444 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* usb: add inline helper method for CC linesJett Rink2019-05-022-5/+44
| | | | | | | | | | | | | | | | Expressing logic for CC lines can get very verbose. Add helper inline methods that logical describe the condition we are testing to clean up call sites. BRANCH=none BUG=none TEST=Builds, no functional change. Change-Id: I48c117437bc14f3c55473df7f7c778b55af2706d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1589906 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Sam Hurst <shurst@google.com>
* driver/max695x: Add 7 segment display driverAyushee2019-05-022-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Port80 information and power sequencing states can be displayed on the 7-segment so that we can observe its information without connecting a debugger. Adding this CL to initialize and write to the 7-segment display. For port80, 80(data) gets displayed on the seven segment, for the power states, EC(state) gets displayed on the seven segment. The MAX6958/MAX6959 is a compact multiplexed common - cathode display designed to interface microprocessors with seven - segment numerical LED digits or to discrete LEDs via a 2-wire serial interface compatible with SMBusTM and I2C. The 2-wire serial interface uses fixed logic thresholds of 0.8V/2.1V when the display driver is powered from a 5V supply for compatibility with 2.5V and 3.3V systems. BRANCH=None BUG=b:130738086 TEST=Manually tested on intelrvp, able to write to the 7 segment display Change-Id: I82ba3aca40640e094463669aa1ff106ce7b99b7b Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1574665 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nvmem: protect flash accesses with a mutexVadim Bendebury2019-05-022-8/+12
| | | | | | | | | | | | | | | | | | | Multiple tasks could be trying to modify NVMEM concurrently. To avoid data corruption add a mutex which guarantees that only one thread of execution has access to the flash storing NVMEM objects. Various paths accessing flash contents are now protected by the same mutex. Mutex control functions are put in wrappers, which makes it easier to add debugging code when needed. BRANCH=cr50, cr50-mp BUG=b:69907320, b:130828517 TEST=attempts to take a device through RMA open do not fail any more. Change-Id: I6424477dced20d00f6165006cd3b3968433be6d0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1584586 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-021-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* battery: Consolidate battery_manufacturer_nameDaisuke Nojiri2019-05-011-0/+11
| | | | | | | | | | | | | | | | | | | | | Currently, the battery_manufacturer_name API is implemented individually by each chip. This patch consolidate the definitions. It also allows a board to return custom manufacturer names. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129599895 BRANCH=none TEST=buildall Change-Id: Ib0f60c9be71fea31658ab284a915d73341b9145e Reviewed-on: https://chromium-review.googlesource.com/1590039 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nvmem: add logging and restart on app_cipher failuresVadim Bendebury2019-05-011-1/+2
| | | | | | | | | | | | | | | Just in case there is a failure when encrypting or decrypting NVMEM objects, add code which detects problems, reports them in the flash log and reboots. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST=none Change-Id: I22e55941f459b5b45bf4b23781b20601a56b40d8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1590042 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Flapjack: Disable charging from BC 1.2 charger as USB-C chargerDaisuke Nojiri2019-04-301-0/+7
| | | | | | | | | | | | | | | | | | | | | Currently, if a charger shows Rp=USB on USB-C port, the charge manager chooses it and sets the max current to 500 mA even if it can provide higher power as a BC 1.2 charger. This patch introduces CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF. When it's defined, a BC 1.2 charger won't be recognized as a USB-C charger. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/131353444 BRANCH=none TEST=Charge Flapjack from BC 1.2 charger on USB-C port. Change-Id: I50969973026185dd2aecdb768985cd116c1d32f7 Reviewed-on: https://chromium-review.googlesource.com/1586580 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion sense: Calculate loop time based on sensor needsMathew King2019-04-272-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the motion sense loop bases its sleep time based on the fastest active sensor. This method has several flaws: 1. It does not take into account any task switching overhead 2. With a mix of interrupt driven and forced sensors the sleep time gets recalculated every time there is an interrupt causing the loop to oversleep 3. If multiple sensors do not have rates that are in sync the timing of the slower sensor will be off. For example if there was a sensor running at 50 Hz and one running at 20 Hz the slower sensor would end up being sampled at about 16 Hz instead of 20 Hz This change calculates an ideal read time for every forced mode sensor and calculates the sleep time based on the nearest read time. Every time a sensor is read the next read time is calculated based on the ideal read time not the actual read time so that reading does not drift because of system load or other overhead. BUG=b:129159505 TEST=Ran sensor CTS tests on arcada, without this change the magnetometer was failing 50 Hz tests at about 38 Hz with 30% jitter with this change in place 50 Hz was spot on with about 10% jitter BRANCH=none Change-Id: Ia4fccb083713b490518d45e7398eb3be3b957eae Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1574786 Reviewed-by: Jett Rink <jettrink@chromium.org>
* charger: Add basic driver code for ISL9241Vijay Hiremath2019-04-261-1/+3
| | | | | | | | | | | | | | | | | | The ISL9241 is a digitally configurable buck-boost battery charger that can support both Narrow Voltage Direct Charging (NVDC) and Hybrid Power Buck Boost (HPBB/Bypass) charging and switch between the modes using firmware control. BUG=b:131123775 BRANCH=none TEST=Able to boot intelrvp with charger & battery is charging Change-Id: If0736136778cbe7650ed7f03d04f4e011eedd1f6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1579241 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* thermistor: Add STEINHART-HART lookup table for NCP15WB473F03RCVijay Hiremath2019-04-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lookup table is based off of a resistor divider circuit on 3.0V with a 22.6K resistor in series with a thermistor with nominal value of 47K (at 25C) and a B (25/100) value of 4050. Calculation: 1. Get the thermistor resistance for a given temperature from the datasheet. 2. Calculate the ADC input voltage. Vout = (Vdd * Rt) / (Rt + Rs) Where: Vdd - Source voltage (Constant) Vout - ADC value read on STEINHART-HART voltage divider circuit Rt - Resistance of thermistor at given temperature Rs - Series resistance value (constant) 3. Form a STEINHART-HART lookup table for 0 to 100 deg C 4. Add a scaling factor so that the STEINHART-HART lookup table data is 1-byte per pair. BUG=b:131060744 BRANCH=none TEST=Manually tested on ICLRVP, able to read correct temperature Change-Id: Ib0e7b1ab6d6d4c5bcb14ff4ab0e830881e9864e6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1577741 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec_commands: Move #ifdef to encompass more codeGwendal Grignou2019-04-261-1/+3
| | | | | | | | | | | | | | | To generate kernel ec_commands.h as lean as possible, include comments within #ifdef. BUG=chromium:945948 BRANCH=none TEST=compile Change-Id: I23e48aa68c456ac09e8418f80993e952043111f6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1559379 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_commands.h: Fix multi-line comments layoutGwendal Grignou2019-04-261-12/+17
| | | | | | | | | | | | | | | | | | | | checkpatch.pl found some comments that does not match the format: /* * line1 * line2 */ Fix some other minors errors in comments. BUG=chromium:945948 BRANCH=none TEST=Compile Change-Id: I34fddfc8db2a68431c114fd534278e80fa4b3b53 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1559378 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
* cr50: Support legacy U2F key handlesLouis Collard2019-04-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | The new U2F functions make use of a new key derivation scheme. This adds a flag clients can specify that allows the new functions to also sign requests using a legacy key handle. This will allow continued support of legacy key handles in Chrome OS whilst allowing the legacy code to be removed from cr50. BUG=b:112603199, b:123161715 TEST=with new cr50 and u2fd patched to send new param: - register legacy key handle with Google - restart u2fd with user keys and no fallback - check login fails - restart u2fd with user keys and fallback - check login succeeds Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: Ib3164e9c0856d51b958fa8db181153b5b2227850 Reviewed-on: https://chromium-review.googlesource.com/1580622 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* tests: make lighbar test easier to debugJett Rink2019-04-241-0/+3
| | | | | | | | | | | | | | | | | This test was failing and it is easier to comment out tests that are passing to debug. I needed to add a precondition so each test would pass on its own. I also needed to remove the static modifier to allow each test to be comment out. BRANCH=none BUG=none TEST=builds and passes Change-Id: Ib2a7c0948aee363e1552835222a9700225993e46 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570605 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tasks: convert TASK_EVENT_CUSTOM macro to bitJett Rink2019-04-244-22/+33
| | | | | | | | | | | | | | | | | | | | | We should ensure that all custom task definition are non-zero and fit with the globally defined events. Add compile time check and change semantics to specify bit number (instead of making all callers use the BIT macro). This also fixes an error with TASK_EVENT_PHY_TX_DONE for ITE being 0. The bug that made that happen hasn't landed on any firmware branches that use it though. BRANCH=none BUG=none TEST=builds Cq-Depend:chrome-internal:1178968,chrome-internal:1178952 Change-Id: I5e1d1312382d200280c548e9128e53f4eddd3e61 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570607 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-242-2/+2
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* driver: lis2mdl: add standalone supportYuval Peress2019-04-231-0/+1
| | | | | | | | | | | | | | BRANCH=None BUG=b:128619310 TEST=Created new console commands to directly trigger init, read, and set_data_rate for the sensor. Manually verified behavior and register values from the magnetometer using ISH console. Change-Id: Ie162827f596056ee4cfd96be5c457e08708a9b9b Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1534339 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* P9221: Add P9221 driverTony Zou2019-04-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds P9221 driver and enable it for Flapjack. The driver originates from https://android.googlesource.com/kernel /msm/+/android-msm-bluecross-4.9-pie-qpr1/drivers/power/supply/qcom /p9221_charger.c CQ-DEPEND=CL:1445133 CL:1551583 BRANCH=none BUG=b:126162615 TEST=Verify charging from PD and WPC as follows: 1. Charge with PD charger. Place DUT on WPC charger. -> PD charger continues to charge. 2. Unplug PD charger. -> WPC starts charging as GPP. 3. Plug PD charger. -> PD charger starts charging at 2A@9V TEST=Verify OTG and WPC functionality as follows: 1. Plug fan to USB port: -> Fan spins 2. Place DUT on WPC charger: -> WPC starts charging as GPP. Fan continues to spin. 3. Remove DUT from WPC charger: -> Fan continues to spin. 4. Do 1 and 2 then unplug USB fan: -> WPC starts charging. TEST=/sys/class/power_supply/CROS_USBPD_CHARGER0/usb_type is BrickID /sys/class/power_supply/sbs-12-000b/status is ok Change-Id: I5fbd0237cedd8095f98582c39973d432e733f2cd Signed-off-by: Tony Zou <zoutao@huaqin.corp-partner.google.com> Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1448193 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
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