summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeFilesLines
* Shuffle const aroundPatrick Georgi2019-05-242-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | gcc 8.1 complains about duplicate const, and while some of these really are duplicate, others look like they were supposed to tighten the API contract so that variables are "const pointer to const data", but didn't have that effect. BUG=b:65441143 BRANCH=none TEST=building Chrome EC as part of upstream coreboot's build with a gcc 8.1 compiler now works (better. there are other issues left) Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1039812 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 85ddb2ce533cb0276aab7780238ec98e1abec2fe) Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1621258 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* stm32: usb_hid_touchpad: add confidenceWei-Han Chen2018-11-191-9/+14
| | | | | | | | | | | | | | | | | | | | `confidence` is expected from a PTP-compliant touchpad BRANCH=none BUG=b:70482333 BUG=chromium:904711 TEST=manual Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: Ibe7166f43cae5fb36bbcc4e6dfd9ae6525a7225e Reviewed-on: https://chromium-review.googlesource.com/1188170 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1333949 Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_hid_touchpad: make max pressure configurableWei-Han Chen2018-11-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Maximum pressure is now defined by CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Z. `hammer` is the only board using usb_hid_touchpad, the board.h is updated to reflect the change (for old boards "HAMMER" and "STAFF", we keep the value 1023, so they should behave the same). BRANCH=none BUG=b:70482333 BUG=chromium:904711 TEST=make BOARD=whiskers TEST=make buildall -j TEST=manually on device Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I70b0a5b19dfbe3ac731ef2ead08578a7f7a1cb0b Reviewed-on: https://chromium-review.googlesource.com/1141676 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1333948 Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* motion: Change ODR only within the motion sensor taskGwendal Grignou2018-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | When changing ODR for one sensor, we insert a timestamp in the FIFO. That timestamp can be misinterpreted by other sensor while in batch mode, condensing all events in a small timezone. Also, it can lead the motionsense stack to insert timestamp from the past. BUG=b:111422556,chromium:562245 TEST=Check cheets_CTS_P.9.0_r2.x86.CtsSensorTestCases pass on eve. BRANCH=eve Change-Id: If76aa3abcedbe463321ccbb1c183dc16edda8693 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204692 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit f62f2ebbecb131956a5edc4bf60c094bc67972a1) Reviewed-on: https://chromium-review.googlesource.com/c/1259383 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Trybot-Ready: Philip Chen <philipchen@chromium.org>
* base_detect: Expose console command to force state.RaviChandra Sadineni2018-09-272-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an effort to test wake sources on any given platform, this CL exposes console command to set the base state. This console command can then be invoked by autottests from the uart interface. We have two implementations for managing base status. One is interrupt driven while the other is a polling via a task. Boards current implementations then are: interrupts: lux, soraka, cheza polling task: nocturne, zoombini For forcing base connect and disconnect, interrupts: Disable interrupts and set forced base state. polling task: Stop periodic task and set forced base state. On reset, interrupts: Schedule deferred task immediately and enable interrupts. polling task: Clear forced base state and begin rescheduling periodic task. Signed-off-by: RaviChandra Sadineni <ravisadineni@google.com> BRANCH=poppy,nocturne BUG=chromium:820668, b:37223093 TEST=Tested on lux, soraka and nocturne basestate a : attaches the lid, reflected in ui. basestate d : detaches the lid, reflected in ui. basestate r : resets to the correct state. Wakes the device up on lux and nocturne and soraka. orig-Change-Id: Iab698e103a50b8d22bf216a6f816998cb158e38a orig-Reviewed-on: https://chromium-review.googlesource.com/1184172 Change-Id: I13a12c302fb6c50b11a70f15c218eb72079f2c17 Reviewed-on: https://chromium-review.googlesource.com/1240456 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Trybot-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org>
* Revert "motion: remove load_fifo"Alexandru M Stan2018-07-161-0/+14
| | | | | | | | | | | | | | | | | | | | This reverts commit 1d89369b51135d979c5adcd8cc7b9c6d5853a467. A few EC CLs made some bad assumption and caused CTS to fail (without realizing it in time). This is a series to revert those bad CLs and other CLs that depend on it. They might reland back soon. BUG=b/111220617 TEST=With series, CTS passes once again Change-Id: I0b549d036a1bfd2126b50afe0da73c21188745e8 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1134057 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* Revert "motion: Lower jitter of Sensor->EC timestamp"Alexandru M Stan2018-07-161-7/+4
| | | | | | | | | | | | | | | | | | | | This reverts commit 05c410f34add5d4b2a50b248ab79c9436a0cf776. A few EC CLs made some bad assumption and caused CTS to fail (without realizing it in time). This is a series to revert those bad CLs and other CLs that depend on it. They might reland back soon. BUG=b/111220617 TEST=With series, CTS passes once again Change-Id: Id0d98eacf388d6e7778cf23c5dfcefca9e78a757 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1134056 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* Revert "sensors: Add driver for SYNC"Alexandru M Stan2018-07-161-8/+2
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2778b192f39ea01fc870153d4c21b42fc2149590. A few EC CLs made some bad assumption and caused CTS to fail (without realizing it in time). This is a series to revert those bad CLs and other CLs that depend on it. They might reland back soon. Conflicts: include/config.h BUG=b/111220617 TEST=With series, CTS passes once again Change-Id: Ieeb6515c12a544a99efcfc254bbdea520b7e05ee Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1134055 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* nautilus: change the reference value, NOISY_MAGNITUDE_DEVIATIONInno Park2018-06-081-0/+9
| | | | | | | | | | | | | | | | | | | | Changed NOISY_MAGNITUDE_DEVIATION from 1 to 1.5. Current value seems to be set too low. So ec could regard lid angle as unreliable even when sensors are at rest. BUG=b:79670788 BRANCH=firmware-poppy-10431.B TEST=Build & flash EC then ectool motionsense Change-Id: I07c3e5c2149e7dade567592a437d36d3a294b7af Signed-off-by: Inno Park <ih.yoo.park@samsung.com> Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1065954 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ih-Yoo Park <ih.yoo.park@samsung.corp-partner.google.com> Reviewed-by: Ih-Yoo Park <ih.yoo.park@samsung.corp-partner.google.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Ih-Yoo Park <ih.yoo.park@samsung.corp-partner.google.com>
* rsa: Further optimization of multiplications for Cortex-M0Nicolas Boichat2018-06-011-2/+14
| | | | | | | | | | | | | | | | | | | | | In RSA, we often need to actually compute (a*b)+c+d: provide some assembly optimized functions for that. With -O3, 3072-bit exponent, lower verification time from 104 ms to 88 ms on STM32F072 @48Mhz. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=make BOARD=hammer test-utils test-rsa3, test on board Change-Id: I80e8a7258d091e4f6adea11797729ac657dfd85d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071411 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080584
* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-06-012-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080583
* console_channel.inc: Add more ifdef to reduce number of channelsNicolas Boichat2018-06-012-0/+11
| | | | | | | | | | | | | | | | | | | There are still more ifdef than can be added: this just takes out the low hanging fruits. BRANCH=poppy BUG=b:35647963 TEST=make buildall -j, see that we gain from 0 to 64 bytes on many boards. Conflicts: board/nocturne/board.c => Does not exist on FW branch Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070948 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080582
* console_output: Clarify help text for CONFIG_CONSOLE_CHANNELNicolas Boichat2018-06-011-2/+5
| | | | | | | | | | | | BRANCH=poppy BUG=b:35647963 TEST=N/A Change-Id: I85dd6553cf3ebace4e19813a308d0a024eba2915 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071412 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080581
* timer: Allow disabling gettime console commandNicolas Boichat2018-06-011-0/+1
| | | | | | | | | | | | | | hammer does not need that command, let's just remove it. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, saves 112 bytes of flash Change-Id: I24ed979f8a9053128d4eb56fc5af00429f7ba0ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070950 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080579
* console_output: Add option to disable console channelsNicolas Boichat2018-06-011-0/+9
| | | | | | | | | | | | | | | On hammer, we do not need the console channels, so we can just disable them to save flash size. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, staff image size shrinks by 704 bytes Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070949 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080578
* usb_pd_protocol: Add PD_ROLE_DISCONNECTED for data role swapsDuncan Laurie2018-05-011-2/+3
| | | | | | | | | | | | | | | | | | | | | Add a state to indicate that a data role is actually disconnected and notify the board-level data swap function with this state when a cable is unplugged. This allows the board to clean up and restore any state that may have been set up with a data role swap. BUG=b:78308749 BRANCH=eve,poppy TEST=manual on eve: plug in C-to-C cable, execute data swap on port 0 with 'pd 0 swap data' and ensure the OTG pins are asserted. Then unplug the cable and ensure OTG pins are now deasserted. Change-Id: I7d8fff22dd5836b4b5af54f0ede71ee1b6e40b5c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/1036904 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* ec: add driver/touchpad_st.cWei-Han Chen2018-03-271-5/+12
| | | | | | | | | | | | | | | | | | | | | | | Initial commit for ST touchpad. This CL will support X/Y mode function. BRANCH=none BUG=none TEST=make BOARD=whiskers TEST=manually test touchpad function on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I1669286ca764fbbd4a691171193415dd4999673f Reviewed-on: https://chromium-review.googlesource.com/958894 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982348 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* lpc: remove lpc_host_resetJett Rink2018-03-271-5/+0
| | | | | | | | | | | | | | | | | | | | | | No one is using this method and it implies that all chipset should support the RCIN# Virtual Wire if using eSPI. Only large core chips use RCIN#; small core chips don't. This method was introduced for skylake and has since been replaced since CL:575947 was merged. BRANCH=none BUG=none TEST=build all Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/975904 Reviewed-on: https://chromium-review.googlesource.com/982347 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=none BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982340 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* keyboard: Add config option for refresh key rowDuncan Laurie2018-03-272-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | The keyboards that have an assistant key also move the row that the refresh key is on from 2 to 3. The row is hardcoded and used by the early boot key detection code to determine if boot keys should be honored. The fallout from not having the right refresh row defined was not seen on Eve because that board has a different quirk where it does not distinguish reset-pin vs power-on reset types so the test in check_boot_keys() was not failing. BUG=none BRANCH=none TEST=manual testing on Eve board Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979574 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982339 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* tcpc: rename CONFIG_USB_PD_TCPM_ANX74XX to CONFIG_USB_PD_TCPM_ANX3429Jett Rink2018-03-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for ANX3429, rename the option especially since the ANX7447 driver will not reuse the ANX74XX driver which is being introduced in CL:956790. Also adding the CONFIG_USB_PD_TCPM_ANX740X and CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the ANX chip the anx74xx.c driver applies to. BRANCH=none BUG=none TEST=build all Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/973558 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982331 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* yorp: Enable lid, base accel and gyro sensorDivya Sasidharan2018-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | This is initial configuration changes and enable motion sensor task. BUG=none BRANCH=none TEST=Verified "make buildall -j and make BOARD=yorp" Change-Id: Ia45d6434a2c034c0ec650d7b46d6f664848f9153 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/961459 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982328 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* usb_update: check touchpad_info size at build timeWei-Han Chen2018-03-271-0/+9
| | | | | | | | | | | | | | | | | | | | | Current protocol will not work if touchpad_info is more than 50 bytes. Assert this constrain at build time. BRANCH=none BUG=none TEST=make BOARD=hammer Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I9bf163f77f14c7d475fc8a2f422ce596dc89c61e Reviewed-on: https://chromium-review.googlesource.com/958893 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982321 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* ppc: Add driver for NX20P3483Scott Collyer2018-03-272-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NX20P3483 is a USB PD and Type C high voltage sink/source combo switch. This CL adds support for this PPC variant. Unlike the TI SN5S330, the NX20P3483 does not support VCONN and does not need to be informed of CC polarity by the TCPM. To account for these differences, 2 new PPC config options are added and the driver for the TI SN5S330 was modified to include these new options. The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO signals which may be connected the EC or directly to the TCPC. To handle both cases, the ppc_chips structure was modified with a flags, snk_gpio, and src_gpio elements. BUG=none BRANCH=none TEST=make -j buildall and verified there are no build errors. Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/966926 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982314 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Add vsnprintf function.Jeff Andersen2018-03-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | This function enables variadic functions to take advantage of functionality provided by snprintf. Signed-off-by: Jeff Andersen <jeffandersen@google.com> BRANCH=none BUG=none TEST=make buildall -j Change-Id: I0095a96339b374ef8030b87b5184fa4678b439eb Reviewed-on: https://chromium-review.googlesource.com/971761 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982313 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* power: create CONFIG_CHIPSET_GEMINILAKEJett Rink2018-03-271-9/+22
| | | | | | | | | | | | | | | | | | | | | | Geminilake uses the same power sequencing code as Apollolake. Instead of the board specifying the wrong chipset, we will make the correct chipset reuse the existing power code. This also gives us flexibility in the future if GLK needs to vary from ALK in any of shared code. BRANCH=none BUG=none TEST=build all Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969613 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982312 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* fpsensor: add enrollment and matching interfaceVincent Palatin2018-03-272-3/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the state machine and the interfacing to the enrollment and matching algorithm providing by the private driver part. Implement the host commands interface for it (based on MKBP event) along with the console debug commands to exercise it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=On ZerbleBarn console, use 'fpenroll' then 'fpmatch' for several fingers. TEST=With ZerbleBarn and a servo-v2, retrieve and upload templates with 'ectool_servo fptemplate'. TEST=On Meowth, exercise with the prototype of biod CrosFpBiometricsManager. CQ-DEPEND=CL:*555078 Change-Id: I10b0d76d3faa898a682cf9a2eb7fc7e212b0c20c Reviewed-on: https://chromium-review.googlesource.com/886401 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982310 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* driver: lsm6dsm: Add ectool support.Gwendal Grignou2018-03-271-0/+1
| | | | | | | | | | | | | | | | BUG=none BRANCH=master TEST=compile Change-Id: If914dfbf7bb30e934b711d8f89c46af2787f917c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924406 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982304 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* driver: accel_lis2dh: Fix interfaceGwendal Grignou2018-03-271-0/+1
| | | | | | | | | | | | | | | | | | Add support in ectool, expose min/max ODR. BUG=none BRANCH=master TEST=compile Change-Id: Ib09c06e17d7d73aaab91680672de4d5267299c7f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924405 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982303 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* common: Add hardware error codeGwendal Grignou2018-03-271-0/+2
| | | | | | | | | | | | | | | | | Add error code to indicate a piece of hardware is not working properly. BUG=none TEST=compile BRANCH=none Change-Id: I34eca8073a359aec1c559241654a1d0a7075cd44 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753968 Reviewed-on: https://chromium-review.googlesource.com/982279 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* i2c: Add option for calling board-specific functions before and after every ↵Furquan Shaikh2018-03-232-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | i2c transaction This change adds a new config option CONFIG_I2C_XFER_CALLBACK that makes i2c_xfer callback into board-provided functions before the start and after the end of every I2C transaction. This can be used by boards to implement any I2C device-specific quirks e.g. requiring minimum bus-free time between every I2C transaction when the slave device cannot actually do clock stretching. BUG=b:73147310 BRANCH=nautilus TEST=make -j buildall Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/956934 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit f1bd7040ee2c456b8278682926f9ac3b36a427b8) Reviewed-on: https://chromium-review.googlesource.com/974601 Reviewed-by: Philip Chen <philipchen@chromium.org> Tested-by: YongBeum Ha <ybha@samsung.com> Commit-Queue: YongBeum Ha <ybha@samsung.com>
* config: Put all sensor interrupt config events at a single locationGwendal Grignou2018-03-191-13/+5
| | | | | | | | | | | | | | | | | | | The number of interrupt events will increase with the ST sensors support. BUG=none BRANCH=none TEST=compile Change-Id: If375afa97ad664594f005a6b007aa7d9439e8ecb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767611 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 50728bc54748d95c94095c3f7c3579d4473034a9) Reviewed-on: https://chromium-review.googlesource.com/967330 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ec: Add /baseboard to EC projectScott Collyer2018-03-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This CL introduces /baseboard to the EC project which can contain config options and code which is specific to certain family, but can be shared among the board derivatives of that family. Only the infrastructure changes are included with an empty baseboard.c/.h for octopus. BRANCH=none BUG=b:74358864 TEST='make buildall' and ensure that all boards build successfully. In addition, temporarily moved config options for USB-C and charger to baseboard.h and tested that 'make BOARD=yorp' is successful. Change-Id: I16656574f835c56598a9d2bf49bc1e946d71fe76 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/954444 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 514c3b3e26edb3b05b466c5569894808cfdc4a91) Reviewed-on: https://chromium-review.googlesource.com/965427 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* sensors: Add driver for SYNCAlexandru M Stan2018-03-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Useful for recording the exact time a gpio interrupt happened in the context of sensors. Adding it for camera vsync purposes. BUG=b:67743747 TEST=With next patch see it work on scarlet. BRANCH=master Change-Id: Ic8e8fb444e08200e5d8daded8b4a5920b13431ac Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/850580 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit 4a1d2e3daf005766dc523216b8c3639fcd9595a2) Reviewed-on: https://chromium-review.googlesource.com/963742 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* motion: Lower jitter of Sensor->EC timestampAlexandru M Stan2018-03-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead getting the time for each sample in the task code, we should be getting it as soon as the sensor reported it added it to its fifo (so sensor just finished integration). Because of that each sensor should provide the time when it provides a sample, ideally from an accurate spot like an interrupt. Deprecate motion_sense_fifo_add_unit (without a timestamp) in favour of motion_sense_fifo_add_data (which adds the timestamps). Update all relevant sensors to use the new api. Note: for now I focused on the BMI160, where I actually made it get the time in the interrupt. The other sensors were made to use the new api, but still don't record the time in the right place (though it's not any worse than before). BUG=b:67743747 TEST=In the kernel, fifo_info->info.timestamp still has sane values. TEST=CTS should still pass BRANCH=master Change-Id: I9829343f8702e00cc19f9c88134fa1f258c9e1e9 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/807331 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit b63595258df33b0c31effe979feb4bfe884cc9fb) Reviewed-on: https://chromium-review.googlesource.com/963741 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* usbc: add config support for multiple (and no) vbus adc channelsJett Rink2018-03-122-0/+15
| | | | | | | | | | | | | | | | | | | | yorp measures each port's vbus separately on a deticated ADC. Also, add config to take care of ADV_VBUS -1 case too. BRANCH=none BUG=none TEST=none Change-Id: I6f4df96caffc3b527b69e67358631dd448172cde Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/956555 Reviewed-by: Edward Hill <ecgh@chromium.org> (cherry picked from commit ef4e70174ac2797f0c02753685b35d038a317a6a) Reviewed-on: https://chromium-review.googlesource.com/959114 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* motion: remove load_fifoGwendal Grignou2018-03-121-14/+0
| | | | | | | | | | | | | | | | | | | | | | To prevent invalid timestamping, call load_fifo only when we get a FIFO interrupt. In consequence, remove load_fifo entry point and only process fifo inside the IRQ. Add helper function to know when we are in forced mode (the EC needs to periodically read sensor data or interrupt driven). BUG=None BRANCH=master TEST=compile Change-Id: I959e476f3f7215be95424c07223f7421e8b13da1 (cherry picked from commit bc766130becff13136baa53070749899dce687f6) Reviewed-on: https://chromium-review.googlesource.com/959112 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* isl923x: Round up requested OTG currentNicolas Boichat2018-03-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, requesting 100mA or output current would be rounded down to zero. This would also cause other issues when doing base/lid and lid/base power transfers on lux/wand, as the input current has a much finer grain control, which could lead the input charger to brown out the output charger. BRANCH=none BUG=b:67920792 TEST=Flash lux/wand, lux can provide as little as 100mA of current successfully. Change-Id: Ibf170a6ee3c2dfbdbbc03948c3b0e6ab878eee47 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/956660 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 49f76d0c863146cce707e724fa79de629b912a65) Reviewed-on: https://chromium-review.googlesource.com/957930 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* motion: driver: Fix activity inclusion in accelgyro.hGwendal Grignou2018-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | list/add_activities should be include even when FIFO support is not compiled it, when the host is not asking for them, as it is needed for double tap support. BUG=b:73546254 BRANCH=master TEST=Compile when just CONFIG_GESTURE_DETECTION is defined. Change-Id: Icec7ccec7fd8463ea40afbe05ce1e177ae7d609d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924404 Commit-Ready: Gwendal Grignou <gwendal@google.com> Tested-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> (cherry picked from commit eb50aaded727acfaf6b8521bde325976f374a3a2) Reviewed-on: https://chromium-review.googlesource.com/957923 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* fan: Allow board to configure fans at run timeDaisuke Nojiri2018-03-071-7/+17
| | | | | | | | | | | | | | | | | | | | | | This patch splits struct fan_t into two parts: base configuration and RPM configuration. RPMs are expected to be different from model to model while a base configuration is most likely shared. BUG=b:73720175 BRANCH=none TEST=make buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 7f4018c41f875c7fbdff03ee4a489753d541b0a9) Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176 Reviewed-on: https://chromium-review.googlesource.com/953791 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* core: add chip-specific memory regions definition mechanismVincent Palatin2018-03-072-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a chip has special/non-contiguous SRAM physical memory region, rather than extending the generic linker file ad nauseam, define a mechanism to declare a chip specific list of those regions. To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS configuration and have a memory_regions.inc with the list of regions. The special-purpose preprocessed chip/<chip_name>/memory_regions.inc file has one region declaration per line using the following macro: REGION(name, attributes, start_address, size) Each region will get a proper MEMORY entry and a section in the linker file. the __SECTION(region_name) helper is provided as a convenience to declare variable in a specific region. Note: those 'special' regions are NOT cleared at startup contrary to .bss. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. Reviewed-on: https://chromium-review.googlesource.com/946368 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit b42dd73603844c03b44d88a4513df330ee168496) Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c Reviewed-on: https://chromium-review.googlesource.com/953785 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* config: Rename new key to assistant keyNicolas Boichat2018-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | Make it clearer what the new key is about. CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/950263 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 6d567bc45ffcc3b8df2c288f8347d00a250248fc) Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e Reviewed-on: https://chromium-review.googlesource.com/953784 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Cr50: Add LLSR (long long shift right) support.Allen Webb2018-03-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Cr50 lacks native instructions for 64-bit integers and an ABI function can be used by the compiler to take the place of the needed instructions. This CL adds support for a right bitwise shift of 64-bit integers. BRANCH=none BUG=chromium:794010 TEST=Set CONFIG_LLSR_TEST, build, update cr50, and run llsrtest on the console. Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/931932 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6719bdf3edef357c1a81e8ed48728b68e0ec0431) Change-Id: Iae66c86720c531454ba29f15b3cc6a07959f5ef2 Reviewed-on: https://chromium-review.googlesource.com/953782 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Allen Webb <allenwebb@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Introduce CONFIG_USB_PD_5V_CHARGER_CTRLPhilip Chen2018-03-052-0/+11
| | | | | | | | | | | | | | | | | | | | | | Add a new config for the boards using charger (e.g. rt946x) to report if VBUS source is enabled instead of using GPIO. BUG=b:65446459 BRANCH=none TEST=Charge Scarlet rev3 with SDP and DCP. Change-Id: Id0a07945f0f888b6a36c422c596b56c5aa5065c0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/905400 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 9896e428f72670562f73713456d5966ad3f2d491) Reviewed-on: https://chromium-review.googlesource.com/949620 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* stm32h7: enable the fast PLL on-demandVincent Palatin2018-03-051-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new module ID 'MODULE_FAST_CPU'. When it is enabled with clock_enable_module(MODULE_FAST_CPU, 1), switch the system clocking to the fast 400-Mhz PLL. For now, I consider that a single task/user is calling clock_enable_module(MODULE_FAST_CPU, x), so we don't need to count users (in a complicated atomic fashion). It's good enough for the current use-case and we can add the complexity later if we have a real need. BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, with follow-up CL setting clock_enable_module(MODULE_FAST_CPU,x) around the computation block, see that computations are fast and the clock goes back to HSI after. Change-Id: I2aef3ad673ddbffd6fc64c591c54297e94896fa6 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/945688 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 29c2aa329489eca44490a6445ef591d6c661b74e) Reviewed-on: https://chromium-review.googlesource.com/949619 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Nami: add keyboard backlight functionElmo_Lan2018-03-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Base on LM3509 chip. Add file LM3509.C and LM3509.H to control keyboard backlight when S0/LidOpen is turn on, others is turn off. BUG=b:73055990 BRANCH=none TEST=Verify keyboard backlight function in resume and suspend. S0/LidOpen is turn on; S4/S5/G3/LidClose is turn off. Change-Id: Ief9e385f969c9dfc9e8f0d4e47ea7803cee747aa Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/881081 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> (cherry picked from commit 6790a884a46f18e858a6b308d3b00f86ef915e3f) Reviewed-on: https://chromium-review.googlesource.com/949616 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* cortex-m: enable I-cache on ARMv7-MVincent Palatin2018-03-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit f23f45e74e4c0aff7116a832556d194747997ffe) Change-Id: I6bbd8ffb7877da13eb662345add252149da0aba0 Reviewed-on: https://chromium-review.googlesource.com/947458 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-03-033-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> (cherry picked from commit 5e614b1c98b73579d7f7975299a8be215f6ffd6d) Change-Id: I4e5948bdc8768fcd850d978b643c94a729a704a7 Reviewed-on: https://chromium-review.googlesource.com/947446 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* g: add CONFIG_USB_CONSOLE_CRCMarius Schilder2018-03-032-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | This option will cause usb console output to block and also compute a crc32. Signed-off-by: mschilder@google.com TEST=make buildall -j BRANCH=none BUG=none Reviewed-on: https://chromium-review.googlesource.com/936281 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit e5e1b7ea5dbc6a22e14c63ef9a6c4f00cfd1993f) Change-Id: I1d769c90bfb82a72a808772906ff54a03a374a1b Reviewed-on: https://chromium-review.googlesource.com/947430 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* ec: add crc32_ctx..() to take context parameter.Marius Schilder2018-03-031-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | Add crc32_ctx.. functions to take context parameter. This allows for multiple instances to exist in parallel. Signed-off-by: mschilder@google.com TEST=make buildall -j8 succeeds BRANCH=none BUG=b:73832883 Reviewed-on: https://chromium-review.googlesource.com/935825 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 3c4800e59452a7124c34f563d548e09849d59b8d) Change-Id: Ib31bb167b67bb6e80536e476f2797e93926b9891 Reviewed-on: https://chromium-review.googlesource.com/947429 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
View Lorry Controller Status