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* kukui/emmc: Disable eMMC emulation when not neededNicolas Boichat2018-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | When AP is off, or after it has booted, disable eMMC emulation, to save power. We also add a new sleepmask bit SLEEP_MASK_EMMC to make sure the EC does not deep sleep when emulating eMMC (timing is very critical). We only try to emulate for 5 seconds after boot, after which we shut down the SPI controller. 5 seconds is enough for multiple boot attempts by the AP. BRANCH=none BUG=b:110907438 TEST=Power up kukui, apshutdown, powerb, repeatedly, see that AP always boots up properly. TEST=EC power consumption in S5/G3 drops from ~6mW to 0.6mW. Change-Id: I32cc11418faa695ccf340784acbe7fa99bf74d8c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1181009 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* test: host_command_fuzz: fuzzing testNicolas Boichat2018-08-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Writing fuzzing tests is a little tricky, as clang takes over the main function. Instead, we start the test main function in a thread, and have LLVMFuzzerTestOneInput prepare the host command buffer, and wake the TEST_RUNNER task. To make fuzzing faster, we only send somehow correctly formed requests, with a valid checksum and length (this can be disabled with an option). We also make sure that the emulator does not hibernate, reboot or jump to a different image when fuzzing is enabled. BRANCH=none BUG=chromium:854975 TEST=make buildfuzztests -j ASAN_OPTIONS="log_path=stderr" \ build/host/host_command_fuzz/host_command_fuzz.exe -timeout=5 Change-Id: I27b25e44c405f118dfc1296247479245e15e54b4 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1107523 Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jonathan Metzman <metzman@chromium.org>
* npcx: adc: only enable ADC during conversion for power consumption.Mulin Chao2018-06-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | For better power consumption in npcx series ec, this CL only turns on ADC module before starting conversion and turns it off after the conversion is done. If ec enters deep sleep when ADC conversion is ongoing, the conveting process is suspended until next time ec wakes up from the deep sleep. Considering the frequency of ADC's source clock is up to 15MHz, it's more efficient to forbid ec enter deep sleep when the conversion is proceeding. (Each conversion time of ADC channel is ~200us based on this condition.) Forbidding ec enter deep sleep should have no harm. BRANCH=none BUG=b:110170824 TEST=No build errors for npcx7 series. The current of AVCC is reduced from 0.4mA to ~0.01mA on yorp if this patch is applied. Change-Id: Ie9226e942eeefaadbca7c17e45f0b9ee9a2364e9 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1090603 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32: low power idle for STM32H7Vincent Palatin2018-06-151-0/+1
| | | | | | | | | | | | | | | | | | | | | Enter STOP mode when possible. Use LPTIM1 clocked on the 32-Khz LSI as a time keeper / wake-up event during STOP mode. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:75105319 TEST=On ZerbleBarn, use on-board INAs to measure idle power consumption, w/o CONFIG_LOW_POWER_IDLE pp3300_h7_ma:14.0 with CONFIG_LOW_POWER_IDLE pp3300_h7_ma:1.84 Change-Id: I1b72a8f6964c7bc6174c07458f307dda57fe71f3 Reviewed-on: https://chromium-review.googlesource.com/1096767 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* system: Enable/Disable low power idle in run timePhilip Chen2018-05-301-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | We have enable_sleep()/disable_sleep() to enable/disable EC deep sleep mode in runtime. Here we introduce similar interfaces to enable/disable EC idle (sleep) mode. BUG=b:78792296 BRANCH=scarlet TEST=Confirm idle mode is enabled/disabled when enable_idle() and disable_idle() are called. Change-Id: I2484f08a066523441064968da99c47de9342ecf0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1072370 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> (cherry picked from commit c6b6626cdccef04b0ff203aaed0d84dbdcecf8b7) Reviewed-on: https://chromium-review.googlesource.com/1076708 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* npcx: Add BBRM idx for a 3rd PD port.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | | | | | Currently, there's only one board with 3 PD ports and it uses NPCX. Therefore, this commit just adds the index to NPCX which will be used to save the fact that there was an explicit contract in place. BUG=b:72838807 BRANCH=None TEST=make -j buildall CQ-DEPEND=CL:905390 Change-Id: Ic960f14a52f2a740adbe08bc340c45edfefbbf26 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/905922 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Allow hibernate to clear AP_OFF flagDaisuke Nojiri2017-12-051-1/+2
| | | | | | | | | | | | | | | | | | | After firmware update, cr50 toggles the EC's reset line, expecting the system will boot. This isn't the case for Chromebox because it sets AP_OFF flag on a clean shutdown (to restore the previous power state after power loss & restore). This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot command. It makes EC first clear AP_OFF then hibernate. BUG=b:69721737 BRANCH=none TEST=Verify Fizz reboot after cr50 update. Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/802632 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* system: Add wait-ext option to ec reboot commandScott Collyer2017-11-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_IN_RW signal is used to determine if the switch to dev mode can be safely made. However, EC_IN_RW needs the EC_RST_L line driven low in order to be reset. In faft tests that utilize crosEcSoftrecPower method, EC_RST_L is not being driven by servo to fix other test failures related to keeping EC and AC reboots in sync. This CL adds a new argument 'wait-ext' to the EC reboot command. When this option is used, instead of the EC generating a reset via it's system watchdog, it will wait 10 seconds for EC_RST_L to be driven. BUG=b:64603944 BRANCH=coral CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode" mutliple times and verified that it passes. Previoulsy, this test always fails when the EC is in RW before it starts. Also tested platform_ServoPowerStateController_USBPluggedin and verified it passed. Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/737524 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Mark reset and panic functions as noreturnPatrick Georgi2017-11-071-1/+1
| | | | | | | | | | | | | | | | | | | gcc 6.3 (as provided by coreboot-sdk) needs that to know which code paths end early. Also add a loop after the command that is "supposed" to reset the machine so that the compiler believes it (and in case that assumption fails). BRANCH=none BUG=b:65441143 TEST=none Change-Id: Idb87253ec7880d66ffec30d75f4d007f02f63aab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/742916 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* EFS: Switch active slot when current slot is invalidDaisuke Nojiri2017-09-211-9/+28
| | | | | | | | | | | | | | | | | | | | | | | When EFS finds the active slot is invalid, it tries the other slot. This patch makes the other slot active so that the following boots will try the other slot first. This patch also replaces enum flash_rw_slot with system_image_copy_t. The new APIs are therefore renamed from *_slot to *_copy. Basically, this makes vboot see slots as a conceptual place instead of physical spaces bound to flash storage. BUG=b:65028930 BRANCH=none TEST=On Fizz, verify: 1. RW_B is old and updated by soft sync. RW_B is activated and executed after reboot. System continues to boot to OS. 2. RW_A is old and updated by soft sync. RW_A is activated and executed after reboot. System continues to boot to OS. Change-Id: Icf97da13e651e7a931b9d507052b9422566eb16c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648449
* EFS: Add support for early firmware selectionDaisuke Nojiri2017-09-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chromebox ECs performs EFS: verifying firmware before the AP boots. This patch updates host commands which are required for the EFS. The change includes: * Update EC_CMD_FLASH_REGION_INFO to accept EC_FLASH_REGION_UPDATE * Update EC_CMD_VBOOT_HASH to accept EC_VBOOT_HASH_OFFSET_UPDATE When EC_FLASHS_REGION_UPDATE is specified, EC_CMD_FLASH_REGION_INFO returns the slot which currently is not hosting a running RW copy. When EC_VBOOT_HASH_OFFSET_UPDATE is specified, EC_CMD_VBOOT_HASH computs the hash of the update slot. This hash covers the entire region, including the signature at the end. This patch undefines CONFIG_CMD_USBMUX and CONFIG_CMD_TYPEC for gru to create space. BUG=b:65028930 BRANCH=none CQ-DEPEND=CL:648071 TEST=On Fizz, verify: 1. RW_B is old and updated by soft sync. RW_B is activated and executed after reboot. System continues to boot to OS. 2. RW_A is old and updated by soft sync. RW_A is activated and executed after reboot. System continues to boot to OS. Change-Id: I9ece907b764d07ce94054ba27996e048c665a80a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648448
* Treat SYSTEM_IMAGE_RW_B also as RW copyDaisuke Nojiri2017-09-091-0/+7
| | | | | | | | | | | | | | SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy. This change makes EC treat it also as a RW copy. BUG=none BRANCH=none TEST=make buildall Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656337 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* coral: Add host command to fetch SKU IDPatrick Georgi2017-08-151-0/+8
| | | | | | | | | | | | | | BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: Ibf307c6e46152b4b09e94d8dca6d49ae863cb3ad Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/608370 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add OTP supportGwendal Grignou2017-07-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One Time Programmable memory can be used to store permanent data like serial numbers. Reorganize the code to support writing serial number to OTP, in addition to pstate (if using its own memory bank) or autogenerate from unique id (hammer). + Add CONFIG_OTP to enable OTP code + Add CONFIG_SERIALNO_LEN to indicate the size of the serial number string. Currently set to 28, when USB serial number is needed. + Expose flash_read|write_pstate_serial and add otp_read|write_serail, remove more generic flash_read|write_serial. + Make board_read|write_serial generic, declared outside of USB subsystem. Priority order to read|write serial string: - board definition (like hammer) - pstate location, if stored in its private memory bank - otp area If none of these methods are available, a compilation error is raised. BUG=chromium:746471 BRANCH=none TEST=compile Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/580289 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cr50: Add physical presence state machineRandall Spangler2017-07-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used as part of case closed debugging configuration. Currently, this only adds the state machine, and a test command which is available when CR50_DEV=1. It also adds a new sleep mask flag for physical presence detect, instead of oveloading FORCE_NO_DSLEEP. The physical presence state machine supports both short (tap 5 times in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes apart) sequences. It will call a callback function at the end of the sequence, so that multiple things can each request physical presence in turn. This will be used by ccdopen / ccdunlock / testlab commands for CCD V1. Eventually, CCD config will replace the unlock sequence handling in wp.c. But for now, we don't touch that. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual Short sequence: pp short pp pp pp # See "Physical presence good" Timeout pp short pp # 15 sec later, get timeout error Long sequence: pp long pp pp pp (wait 2 sec) pp (wait 2 sec) pp # See "PP good" Long sequence, presses too fast: pp long pp pp pp pp # See "PP L too soon" (wait 2 sec) pp (wait 2 sec) pp # See "Physical presence good" Abort: pp short pp abort # See "Physical presence aborted" Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568796 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/stm32/pwm: Prevent sleeping while PWM output is activeNicolas Boichat2017-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | STM32F0 cannot keep PWM output active when chip is in deep sleep. The only other board that uses both CONFIG_LOW_POWER_IDLE and CONFIG_PWM on stm32 is jerry, and this logic should also apply to it. Also, switch using_pwm from array to bitmask to simplify handling. BRANCH=none BUG=b:36173380 TEST=On AP, tell it to autosuspend hammer: echo auto > /sys/bus/usb/devices/1-2/power/control Then see, using idlestats, that hammer does to deep sleep. In hammer console: pwm 0 50, see that PWM output is stable, idlestats shows EC does not sleep. In hammer console: pwm 0 -1, idlestats shows EC sleeps again. Change-Id: Ic74c1905364fe4335239da95a99193d0e3e979f7 Reviewed-on: https://chromium-review.googlesource.com/541115 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* vboot_ec:Read try slot from BBRAMDaisuke Nojiri2017-06-281-0/+1
| | | | | | | | | | | | | This patch makes EC read the slot to verify and jump to from the battery backed up RAM (BBRAM). BUG=b:38462249 BRANCH=none TEST=Boot Fizz Change-Id: I0c78861ea3ccdc45d0aa08e690e3a68f53658409 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/518255
* Add system_can_boot_ap APIDaisuke Nojiri2017-06-191-0/+8
| | | | | | | | | | | | | This API checks battery charge level and current power supply to determine whether the AP has enough power to boot or not. BUG=b:38462249 BRANCH=none TEST=make buildall Change-Id: I489f7ea92f230701b8f18c94d3e698aad90b4a03 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/517272
* g: show RW headers' Board ID fields in 'version' outputVadim Bendebury2017-06-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The contents of the board ID fields of the Cr50 image headers is an important piece of information which determines if an image can run on a particular H1 chip. This patch adds this information to the output of the 'version' command, printing both the contents of the fields of the RW images and if the image would run with the current INFO1 board ID contents (Yes or NO). The board_id feature is in fact g chipset specific, this is why board_id support files are being moved from the cr50 board scope to the g chip scope. BRANCH=cr50 BUG=b:35587387,b:35587053 TEST=observed expected output in the version command: > bid Board ID: 000000fa, flags 000000ff > vers Chip: g cr50 B2-C Board: 0 RO_A: * 0.0.10/29d77172 RO_B: 0.0.10/c2a3f8f9 RW_A: * 0.0.20/DBG/cr50_v1.1.6542-856c3aff4 RW_B: 0.0.20/DBG/cr50_v1.1.6543-2c68a2630+ BID A: 00000000:00000000:00000000 Yes BID B: 000000ea:0000fffc:000000ff No Build: 0.0.20/DBG/cr50_v1.1.6542-856c3aff4 tpm2:v0.0.289-cb2de5a cryptoc:v0.0.8-6283eee 2017-06-09 15:34:19 vbendeb@eskimo.mtv.corp.google.com > Change-Id: I5b283abf304a7408ca8f424407044fca238185e1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/530033 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32/usb: Add support for board-specific serial numberNicolas Boichat2017-06-131-0/+6
| | | | | | | | | | | | | | | | | | | By default, read USB serial number from flash, but provide a way for boards to override the function (e.g., to read serial number from unique chip id). BRANCH=none BUG=b:62280271 TEST=Flash hammer lsusb -d 18d1:5022 -v -v | grep iSerial shows different chip IDs on different boards. Change-Id: I0917752bb8e04c1eff4dffc0b3714f63dcd942b0 Reviewed-on: https://chromium-review.googlesource.com/523045 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Add function to fetch unique idNicolas Boichat2017-06-121-0/+9
| | | | | | | | | | | | | | BRANCH=none BUG=b:62280271 TEST=Flash hammer lsusb -d 18d1:5022 -v -v | grep iSerial shows different chip IDs on different boards. Change-Id: Id56b4509f184eb722d04fef94079c150dc2016e2 Reviewed-on: https://chromium-review.googlesource.com/523044 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-211-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* system: Shutdown AP before entering hibernate modePhilip Chen2017-04-141-0/+6
| | | | | | | | | | | | | | BUG=chromium:702451 BRANCH=none TEST=manually test on gru: confirm 'Alt+VolUp+h' puts gru in hibernate mode and AC plug-in wakes it up. Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 Reviewed-on: https://chromium-review.googlesource.com/470787 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Fixups in emulated sysrq codeNicolas Boichat2017-04-061-8/+0
| | | | | | | | | | | | | | | | Follow-up to CL:456520, addressing a few more comments. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I692afa7c911882f00d92b8e6d83889c52821e171 Reviewed-on: https://chromium-review.googlesource.com/468506 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add support for emulated sysrqNicolas Boichat2017-03-311-0/+8
| | | | | | | | | | | | | | | | | | | | On keyboard-less design, we will implement a special debug mode, based on button sequences, to transmit sysrq events to the AP. This implements the new MKBP event to send sysrq, and a console command to test it. Later CL will implement debug mode itself. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I71d3f77497baf8cc7fac65cd040ce20513b507bc Reviewed-on: https://chromium-review.googlesource.com/456520 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hostcmd: Remove EC_CMD_VBNV_CONTEXT handler for most boardsShawn Nematbakhsh2017-02-251-4/+0
| | | | | | | | | | | | | | | | | Most boards do not keep VBNV storage on the EC, so leave out the host command handler by default. BUG=chromium:693210 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia202ec7d73d1804d8430fe7516cc783afd86e89a Reviewed-on: https://chromium-review.googlesource.com/446716 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-241-6/+25
| | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Decrement retry counter on manual reboots.Aseda Aboagye2017-02-181-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, manually triggered reboots cause the retry counter to be incremented. However, if the system is responsive enough to process the reboot commands from either the console or TPM vendor command, we can assume that the image is "ok". This commit changes the Cr50 behaviour to decrement the retry counter when a reboot is issued on the console or the TPM vendor command is received. BUG=chrome-os-partner:62687 BRANCH=None TEST=Flash cr50. Flash an older image in the other slot. Enter the reboot command on the console over 10 times and verify that retry counter never exceeds RW_BOOT_MAX_RETRY_COUNT and older image is never executed. CQ-DEPEND=CL:444264 Change-Id: Ic35bdc63c4141834584a00a7ecceab2abe8dfc21 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/443330 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Move chip/g-specific system() prototypes to system_chip.hShawn Nematbakhsh2017-02-181-36/+0
| | | | | | | | | | | | | BUG=chromium:693148 BRANCH=None TEST=`make buildall -j` Change-Id: I7a758e6b5a04721d0422cfe8b767d85abddb1ad2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444264 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: consolidate chip shutdown and resume eventsVadim Bendebury2017-02-071-0/+11
| | | | | | | | | | | | | | | | | | | There is no point in keeping in one file multiple hooks task callbacks to handle chipset shutdown and resume conditions. Also, the policy of disabling deep sleep needs to be decided in the board level hooks. BRANCH=none BUG=chrome-os-partner:59007 TEST=ran reef through 200 cycles of suspend/resume Change-Id: I4d30cd04b986b243a5bea44c6978a5f82f8f62a7 Reviewed-on: https://chromium-review.googlesource.com/437729 Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Trybot-Ready: Vadim Bendebury <vbendeb@chromium.org>
* cr50: help battery disconnect to work on detachable devicesVadim Bendebury2017-01-121-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Detachable devices need firmware help to process battery disconnect requests promptly. The request happens when the user keeps pressed both power and "volume up" buttons and yanks the charger cable. Once this condition is detected a 5 s timeout is started, and if the charger cable is not plugged back in during this interval, the code initiates a low polarity pulse on both EC_RST_L and BAT_EN outputs. Lowering BAT_EN level will cause the battery cut off which is supposed to cause an immediate system power down. BRANCH=none BUG=chrome-os-partner:59833 TEST=verified desired behavior on an H1 dev board with a H1B2-D chip. Change-Id: Iecdcc93e228f4bc18734569bd896b0afa4bb752a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/426345 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: keep wp and console state through deep sleepMary Ruthven2016-12-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After every reboot, we were resetting the write protect and console lock states back to default. With this change the wp and lock states will be preserved through deep sleep. They will still be reset on any other type of reboot (like Power On reset or panic). The states are also cleared if the system detects a rollback even when booting from the deep sleep. With this patch it is going to be impossible to remove hardware write protection guarding writes into AP and EC firmware flash, unless the cr50 console is unlocked. Locking the console would reinstate hardware write protection automatically even if it was disabled when the console was unlocked. Two long life scratch register 1 bits are used to keep the console and write protect states over resets. To make code cleaner bitmap assignments of the long life scratch register is put in its own include file. BUG=chrome-os-partner:58961 BRANCH=none TEST=manual On prod/dev images verify that the default wp and console lock states are still correct. change the lock and write protect states from the default and verify they are preserved through deep sleep. reboot cr50 and make sure that they are reset. unlock the console and enable flash writes, then set fallback counter on cr50 to the value of 6 (rw 0x40000128 1; rw 0x4000012c 6) and put the AP into deep sleep by hitting Alt-H-VolUp. In five minutes press the power button on the device to bring it back from s5. Observe cr50 fall back to an older image and console lock and wp disabled. Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420812 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: keep board properties related code in board.cVadim Bendebury2016-12-201-30/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are plans to extend use of the LONG_LIFE_SCRATCH1 register for other purposes than keeping board properties. Just as the board properties, the new use is also very board specific. This patch moves the board properties code from chip/g to board/cr50, where it belongs. Instead of reading board properties bitmap and checking if various bits are set, api functions are now provided to allow determining various properties settings without actually looking at the properties bitmap. CQ-DEPEND=CL:*313057 BRANCH=none BUG=chrome-os-partner:58961 TEST=verified that both Gru and Reef boot with the new image, additionally, on Reef confirmed that it is possible to communicate with the H1 over USB, and that plt_reset signal is handled properly. Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547 Reviewed-on: https://chromium-review.googlesource.com/422081 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* g: remove sleep disable/enable in rddMary Ruthven2016-11-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Enabling and disabling sleep in the rdd interrupt is redundant because USB already takes care of that. When USB is initialized it will disable sleep. If it is released or suspended then it will re-enable sleep. This change removes the sleep enable and disable from the rdd interrupt. With this change now sleep can be enabled while suzyq is still plugged in using the command 'ccd disable'. BUG=none BRANCH=none TEST=manual The consoles still work Updating the EC, AP and Cr50 still works After running 'reboot ap-off' in the EC console and 'ccd disable' in the Cr50 console Cr50 will go to sleep. Change-Id: Ie8e6201e9fd611c514e93bc70d298d3b0d228611 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/413606 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Removed Reef EVT workaroundsScott2016-10-041-4/+1
| | | | | | | | | | | | | | | | | | | | | | - changed the pad assignment for plt_rst_l from DIOA13 to DIOM3; - removed the board property used to keep uart rx disabled, Uart0 is now enabled by default on Cr50. - removed resetting fallback counter on USB updates for reef boards, they are going to use the same mechanism as kevin and gru. BRANCH=none BUG=chrome-os-partner:56540 TEST=Tested on Reef Board ID 1 and Gru Board ID 1. Verfied that plt_rst_l signal is being detected and that there are no interrupt storms related to not having a pullup resistor on the uart rx line. Verified that both platforms successfully boot into chrome OS using cr50 TPM. Change-Id: I300a0c75e60acbecf93500b46aced303955a192a Signed-off-by: Scott <scollyer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/391140 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* system: Add print_system_rtc().Aseda Aboagye2016-09-231-0/+13
| | | | | | | | | | | | | | | | | This commit adds a function that allows the real-time clock to be printed on the EC console. This could be helpful in trying to correlate events between the EC's log and the kernel's. BUG=chrome-os-partner:57731 BRANCH=gru TEST=make -j buildall Change-Id: I5e20692a173bddea3dc5c20cc0f2061cc170ce7d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388856 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Add gpio input for platform reset (plt_rst_l)Scott2016-09-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | For TPM operation with Intel chipset APs, the signal PLT_RST_L needs to trigger a TPM reset. For current Reef boards, this signal is connected to DIOA13. The next version will have it on DIOM3. This CL adds support for platform reset connected on DIOA13 and uses a new board property so that it doesn't affect Kevin/Gru. BRANCH=none BUG=chrome-os-partner:55115 TEST=manual Used H1 dev board configured as Reef. Created high to low transisition on to verify that platform reset was detected. Tested on Kevin to ensure that resets were not occurring. Change-Id: I58f02b7ffa644a9197f4303ae6e640df181040bd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380336 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: correct a todo bug numberMary Ruthven2016-09-111-1/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I32bf88757b57b60f80e504dd5adb21cb824834ec Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383962 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: remove the pullup on sys_rst on kevinMary Ruthven2016-09-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | There is leakage on SYS_RST_ODL from the internal pullup cr50 has on DIOM0. This change removes the internal pullup on reef. On Kevin there is a bug preventing the EC from being able to pull sys_rst_l up high enoug for cr50 to detect that it is pulled high. This change adds an internal pullup back when cr50 detects that it is on a kevin or gru. BUG=chrome-os-partner:56945 BUG=chrome-os-partner:53544 BRANCH=none TEST=On gru and kevin remove servo verify when apreset is run on the EC it resets cr50 and the AP. Run pinmux and check that there is a pullup on diom0 on kevin but not on gru. Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/381322 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: usb update: clear fallback counter after update finishesVadim Bendebury2016-09-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | There is no point in waiting for a reset to clear the fallback counter, it can be cleared as soon as USB update is finished. BRANCH=none BUG=chrome-os-partner:56864 TEST=on a kevin-tpm2 device: set the reset counter to 7 by running > rw 0x40000128 1 > rw 0x4000012c 7 on the cr50 console. Then try uploading a new RW image over Suzy-Q and verify that it is running after reset. Then verify that cr50 can still be updated Change-Id: I098a87c48b2fe864143715b1e90d4bb2409b9eae Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383077 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: mark updated image as good once a usb request is receivedMary Ruthven2016-09-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is now a call to reset the retry counter before the hard reset after an update. Cr50 will use the updated image for the next 5 boots, but on the 6th it sees the retry counter is greater than 5 and then jumps back to the old image. Cr50 needs to call system_process_retry_counter to reset the counter and corrupt the old image header to prevent falling back to the old image. Normally the reset counter would be processed after it receives a TPM command. Reef does not have Cr50 TPM support. Until Cr50 has TPM support for Reef, Cr50 should have a different point to know when the update is good. This change adds a board property to mark the process the reset counter once the Cr50 USB controller receives a set address request from the host. On Reef the controller defaults to the AP PHY when suzyq is not connected, so it should have a connection to the AP or through suzyq after boot. The board property is only added to Reef. Behavior on Kevin and Gru is unchanged. BUG=chrome-os-partner:56864 BRANCH=none TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw 0x4000012c' and verify it is reset to 0. Change-Id: If517202f25a694cd70550e3be047ea502e7c5383 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380354
* cr50: unlock consoleMary Ruthven2016-09-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | UART0 RX only needs to be disabled on reef. This change uses a system property instead of a #define to disable UART0 RX that way it can just be done on Reef not Gru or the dev board. BUG=chrome-os-partner:55510 BRANCH=none TEST=manual rw 0x4060000c shows a value of 1 for reef and 3 for gru gru kevin and reef still boot. Connect DIOA13 to DIOA1 on the dev board and verify the console can be used. Change-Id: I5ee3559c2b35f959c0d67f233d1dfa40743b4064 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378336 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: connect to AP phy on reef when not in ccdMary Ruthven2016-08-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 needs to connect to the AP phy when not in ccd so cr50 can be updated and used as a gnubby. This change uses the strapping options to detect when it is on reef and modifies the ccd behavior to initialize usb on the AP phy when ccd is disabled. On gru the cr50 behavior is unchanged. In RDD this change removes the checks that the current_map is the correct one based on the detected debug state. rdd_init calls rdd_interrupt to set up the usb and ccd state correctly. Having that check prevents that initial rdd_interrupt from calling rdd_detached. Before rdd_detached just disabled usb and we knew during init it would already be disabled. Now we want to make sure it is called if a debug accessory is not attached to initialize usb on the AP PHY. BUG=chrome-os-partner:56098 BRANCH=none TEST=manual verify ccd still works on gru disconnect suzyq and reset reef. run lsusb on the AP and verify it shows cr50 as a device. connect suzyq and check that the AP no longer sees cr50. disconnect suzyq and verify the AP sees it again Change-Id: I3c1ccc54895835bce12302f3ea43fc2e751b4c97 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/372920 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Remove unused CONFIG_CONSOLE_RESTRICTED_INPUT optionBill Richardson2016-08-241-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nothing has used this config option since Spring and Skate, back in early 2014. There's nothing in ToT that uses it at all. I want to add something similar for other purposes, and having two similar-sounding options will just cause confusion. NOTE: Although the comments in include/system.h said that the two functions system_get_console_force_enabled() system_set_console_force_enabled() were only useful when CONFIG_CONSOLE_RESTRICTED_INPUT is defined, they were being used in chip/stm32/system.c. But since the bkpdata registers are only accessible to the EC, there was no way to initialize or modify the one relevant bit that those functions cared about, so they almost certainly had no effect. BUG=chrome-os-partner:55322 BRANCH=none TEST=make buildall Change-Id: Id41541193d4559f5c507bdd0268b049166af4497 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374525
* cr50: try recovering from rolling rebootsstabilize-8688.BVadim Bendebury2016-08-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes a perfectly sane image enters rolling reboot mode in case some data change triggered a bug which prevents the normal startup and causes a reset. The most likely task causing in in case of cr50 would be the tpm task. Let's add another check of the restart counter: should it reach the value of 50, do not start the TPM task. BRANCH=none BUG=chrome-os-partner:55708 TEST=with this code plus an unaligned access introduced in tpm initialization sequence in both RW_A and RW_B, program the full image on the dev board. Observe the device reset 50 time is rapid succession and then stop with the following message on the console: Bldr |511709 retry|50 Himg =4F992103..408D193E Hfss =384E4655..EE13EBD0 Hinf =44D21600..B70529BD jump @00044000 --- UART initialized after reboot --- [Reset cause: rtc-alarm] [Image: RW, cr50_v1.1.5044-8d6f7a2+ private-cr51:v0.0.68-633229c ... + cryptoc:v0.0.4-5319e83 2016-08-07 19:37:16 vbendeb@kvasha] [0.004130 Inits done] [0.006919 Active NVram partition set to 0] Console is enabled; type HELP for help. > system_rolling_reboot_suspected: roling reboots suspected. Try \ powercycling to clear this condition. [0.010502 Task 2 (TPM) exited!] Change-Id: I6b08c5c1a02da9edf9bdf394e57cc56d2e595ad1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366892 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: Decode more reasons for chip resetBill Richardson2016-08-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | There are few reasons why the SoC may reboot which we haven't been reporting (they just show up as "[Reset cause: other]"). This adds a bit of decoding to explain some of those "other" reasons. BUG=none BRANCH=none TEST=make buildall; try on Cr50 I tested one of the new reasons using "crash hang". It shows up correctly as "{Reset cause: security]". I haven't specifically tested all of the new reasons, but since this is basically just a change to console message they should work too. I'll double-check those cases once some blocking bugs are fixed. Change-Id: I46daed29d7e37bda9034a3486127bed0ea25f803 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366400 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Sample slave configuration pins at PORScott2016-08-031-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is just one version of Cr50 firmware for all boards that it's used on. However, on some boards the AP communicates to the TPM via a SPI interface (i.e. Kevin) and on others, the AP communicates via an I2C interface (i.e. Reef). In order to dynamically discover which interface to configure, there are strapping resistors added to the board which enables the Cr50 to detect which configuration to implement. This CL is a first pass and is only looking at DIOA1 which is pulled high for SPI and pulled low for I2C configurations. The strapping resistor should be read when the AP is in reset prior to it attempting to drive any of the lines used for strapping. To ensure this condition is met, Cr50 will only check the strapping options following a POR (power on reset). Once the configuration type is discovered, a 'long_life' register is used to hold the result so that the result can always be available. The long_life register contents remain unchanged until a subsequent power down event. BRANCH=none BUG=chrome-os-partner:50728 TEST=manual Tested on Kevin and Reef. Verfifed by reading the stored value that the SPI configuraiton is detected for Kevin and the I2C interface is detected on Reef. In addition, verified on Kevin that the Cr50 FW version is correctly reported to the AP which means that TPM register reads via the slave SPI are functioning. Change-Id: Ibd7624ad8e3b4126f6346dce0bc72f62a3cc6d18 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363014 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* HACK tpm: reset fallback counter when readyVadim Bendebury2016-07-291-0/+8
| | | | | | | | | | | | | | | | | | | As a temp measure until a proper solution is implemented, reset the restart counter when the PCR_Read command is issued by the host. This is a good indication that Chrome OS is through the boot process, as PCR value is used to determine the boot mode. BRANCH=none BUG=chrome-os-partner:55667 TEST=installed the new image on a Kevin cr50 and rebooted it in normal and recovery modes, observed on the cr50 console the message like > system_process_retry_counter:retry counter 1 Change-Id: Ib55e161d5edbf8f6e2d387fd756b94aa53c20ed8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364311 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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