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* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-06-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080583
* console_channel.inc: Add more ifdef to reduce number of channelsNicolas Boichat2018-06-011-0/+1
| | | | | | | | | | | | | | | | | | | There are still more ifdef than can be added: this just takes out the low hanging fruits. BRANCH=poppy BUG=b:35647963 TEST=make buildall -j, see that we gain from 0 to 64 bytes on many boards. Conflicts: board/nocturne/board.c => Does not exist on FW branch Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070948 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080582
* console_output: Clarify help text for CONFIG_CONSOLE_CHANNELNicolas Boichat2018-06-011-2/+5
| | | | | | | | | | | | BRANCH=poppy BUG=b:35647963 TEST=N/A Change-Id: I85dd6553cf3ebace4e19813a308d0a024eba2915 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071412 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080581
* timer: Allow disabling gettime console commandNicolas Boichat2018-06-011-0/+1
| | | | | | | | | | | | | | hammer does not need that command, let's just remove it. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, saves 112 bytes of flash Change-Id: I24ed979f8a9053128d4eb56fc5af00429f7ba0ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070950 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080579
* console_output: Add option to disable console channelsNicolas Boichat2018-06-011-0/+9
| | | | | | | | | | | | | | | On hammer, we do not need the console channels, so we can just disable them to save flash size. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, staff image size shrinks by 704 bytes Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070949 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080578
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=none BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982340 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* keyboard: Add config option for refresh key rowDuncan Laurie2018-03-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The keyboards that have an assistant key also move the row that the refresh key is on from 2 to 3. The row is hardcoded and used by the early boot key detection code to determine if boot keys should be honored. The fallout from not having the right refresh row defined was not seen on Eve because that board has a different quirk where it does not distinguish reset-pin vs power-on reset types so the test in check_boot_keys() was not failing. BUG=none BRANCH=none TEST=manual testing on Eve board Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979574 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982339 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* tcpc: rename CONFIG_USB_PD_TCPM_ANX74XX to CONFIG_USB_PD_TCPM_ANX3429Jett Rink2018-03-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for ANX3429, rename the option especially since the ANX7447 driver will not reuse the ANX74XX driver which is being introduced in CL:956790. Also adding the CONFIG_USB_PD_TCPM_ANX740X and CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the ANX chip the anx74xx.c driver applies to. BRANCH=none BUG=none TEST=build all Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/973558 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982331 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* ppc: Add driver for NX20P3483Scott Collyer2018-03-271-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NX20P3483 is a USB PD and Type C high voltage sink/source combo switch. This CL adds support for this PPC variant. Unlike the TI SN5S330, the NX20P3483 does not support VCONN and does not need to be informed of CC polarity by the TCPM. To account for these differences, 2 new PPC config options are added and the driver for the TI SN5S330 was modified to include these new options. The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO signals which may be connected the EC or directly to the TCPC. To handle both cases, the ppc_chips structure was modified with a flags, snk_gpio, and src_gpio elements. BUG=none BRANCH=none TEST=make -j buildall and verified there are no build errors. Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/966926 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982314 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* power: create CONFIG_CHIPSET_GEMINILAKEJett Rink2018-03-271-9/+22
| | | | | | | | | | | | | | | | | | | | | | Geminilake uses the same power sequencing code as Apollolake. Instead of the board specifying the wrong chipset, we will make the correct chipset reuse the existing power code. This also gives us flexibility in the future if GLK needs to vary from ALK in any of shared code. BRANCH=none BUG=none TEST=build all Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969613 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982312 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* i2c: Add option for calling board-specific functions before and after every ↵Furquan Shaikh2018-03-231-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | i2c transaction This change adds a new config option CONFIG_I2C_XFER_CALLBACK that makes i2c_xfer callback into board-provided functions before the start and after the end of every I2C transaction. This can be used by boards to implement any I2C device-specific quirks e.g. requiring minimum bus-free time between every I2C transaction when the slave device cannot actually do clock stretching. BUG=b:73147310 BRANCH=nautilus TEST=make -j buildall Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/956934 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit f1bd7040ee2c456b8278682926f9ac3b36a427b8) Reviewed-on: https://chromium-review.googlesource.com/974601 Reviewed-by: Philip Chen <philipchen@chromium.org> Tested-by: YongBeum Ha <ybha@samsung.com> Commit-Queue: YongBeum Ha <ybha@samsung.com>
* config: Put all sensor interrupt config events at a single locationGwendal Grignou2018-03-191-13/+5
| | | | | | | | | | | | | | | | | | | The number of interrupt events will increase with the ST sensors support. BUG=none BRANCH=none TEST=compile Change-Id: If375afa97ad664594f005a6b007aa7d9439e8ecb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767611 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 50728bc54748d95c94095c3f7c3579d4473034a9) Reviewed-on: https://chromium-review.googlesource.com/967330 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ec: Add /baseboard to EC projectScott Collyer2018-03-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This CL introduces /baseboard to the EC project which can contain config options and code which is specific to certain family, but can be shared among the board derivatives of that family. Only the infrastructure changes are included with an empty baseboard.c/.h for octopus. BRANCH=none BUG=b:74358864 TEST='make buildall' and ensure that all boards build successfully. In addition, temporarily moved config options for USB-C and charger to baseboard.h and tested that 'make BOARD=yorp' is successful. Change-Id: I16656574f835c56598a9d2bf49bc1e946d71fe76 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/954444 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 514c3b3e26edb3b05b466c5569894808cfdc4a91) Reviewed-on: https://chromium-review.googlesource.com/965427 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* sensors: Add driver for SYNCAlexandru M Stan2018-03-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Useful for recording the exact time a gpio interrupt happened in the context of sensors. Adding it for camera vsync purposes. BUG=b:67743747 TEST=With next patch see it work on scarlet. BRANCH=master Change-Id: Ic8e8fb444e08200e5d8daded8b4a5920b13431ac Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/850580 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit 4a1d2e3daf005766dc523216b8c3639fcd9595a2) Reviewed-on: https://chromium-review.googlesource.com/963742 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* usbc: add config support for multiple (and no) vbus adc channelsJett Rink2018-03-121-0/+5
| | | | | | | | | | | | | | | | | | | | yorp measures each port's vbus separately on a deticated ADC. Also, add config to take care of ADV_VBUS -1 case too. BRANCH=none BUG=none TEST=none Change-Id: I6f4df96caffc3b527b69e67358631dd448172cde Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/956555 Reviewed-by: Edward Hill <ecgh@chromium.org> (cherry picked from commit ef4e70174ac2797f0c02753685b35d038a317a6a) Reviewed-on: https://chromium-review.googlesource.com/959114 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* core: add chip-specific memory regions definition mechanismVincent Palatin2018-03-071-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a chip has special/non-contiguous SRAM physical memory region, rather than extending the generic linker file ad nauseam, define a mechanism to declare a chip specific list of those regions. To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS configuration and have a memory_regions.inc with the list of regions. The special-purpose preprocessed chip/<chip_name>/memory_regions.inc file has one region declaration per line using the following macro: REGION(name, attributes, start_address, size) Each region will get a proper MEMORY entry and a section in the linker file. the __SECTION(region_name) helper is provided as a convenience to declare variable in a specific region. Note: those 'special' regions are NOT cleared at startup contrary to .bss. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. Reviewed-on: https://chromium-review.googlesource.com/946368 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit b42dd73603844c03b44d88a4513df330ee168496) Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c Reviewed-on: https://chromium-review.googlesource.com/953785 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* config: Rename new key to assistant keyNicolas Boichat2018-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | Make it clearer what the new key is about. CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/950263 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 6d567bc45ffcc3b8df2c288f8347d00a250248fc) Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e Reviewed-on: https://chromium-review.googlesource.com/953784 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Cr50: Add LLSR (long long shift right) support.Allen Webb2018-03-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Cr50 lacks native instructions for 64-bit integers and an ABI function can be used by the compiler to take the place of the needed instructions. This CL adds support for a right bitwise shift of 64-bit integers. BRANCH=none BUG=chromium:794010 TEST=Set CONFIG_LLSR_TEST, build, update cr50, and run llsrtest on the console. Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/931932 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6719bdf3edef357c1a81e8ed48728b68e0ec0431) Change-Id: Iae66c86720c531454ba29f15b3cc6a07959f5ef2 Reviewed-on: https://chromium-review.googlesource.com/953782 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Allen Webb <allenwebb@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Introduce CONFIG_USB_PD_5V_CHARGER_CTRLPhilip Chen2018-03-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | Add a new config for the boards using charger (e.g. rt946x) to report if VBUS source is enabled instead of using GPIO. BUG=b:65446459 BRANCH=none TEST=Charge Scarlet rev3 with SDP and DCP. Change-Id: Id0a07945f0f888b6a36c422c596b56c5aa5065c0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/905400 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 9896e428f72670562f73713456d5966ad3f2d491) Reviewed-on: https://chromium-review.googlesource.com/949620 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Nami: add keyboard backlight functionElmo_Lan2018-03-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Base on LM3509 chip. Add file LM3509.C and LM3509.H to control keyboard backlight when S0/LidOpen is turn on, others is turn off. BUG=b:73055990 BRANCH=none TEST=Verify keyboard backlight function in resume and suspend. S0/LidOpen is turn on; S4/S5/G3/LidClose is turn off. Change-Id: Ief9e385f969c9dfc9e8f0d4e47ea7803cee747aa Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/881081 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> (cherry picked from commit 6790a884a46f18e858a6b308d3b00f86ef915e3f) Reviewed-on: https://chromium-review.googlesource.com/949616 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* cortex-m: enable I-cache on ARMv7-MVincent Palatin2018-03-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit f23f45e74e4c0aff7116a832556d194747997ffe) Change-Id: I6bbd8ffb7877da13eb662345add252149da0aba0 Reviewed-on: https://chromium-review.googlesource.com/947458 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* g: add CONFIG_USB_CONSOLE_CRCMarius Schilder2018-03-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This option will cause usb console output to block and also compute a crc32. Signed-off-by: mschilder@google.com TEST=make buildall -j BRANCH=none BUG=none Reviewed-on: https://chromium-review.googlesource.com/936281 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit e5e1b7ea5dbc6a22e14c63ef9a6c4f00cfd1993f) Change-Id: I1d769c90bfb82a72a808772906ff54a03a374a1b Reviewed-on: https://chromium-review.googlesource.com/947430 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* host_command: Count suppressed host commands individuallyDaisuke Nojiri2018-02-161-2/+2
| | | | | | | | | | | BUG=chromium:803955 BRANCH=none TEST=Verify counters are printed every hour and before sysjump as follows: [12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0] Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912150
* Nami: Enable hibernate using silegoElthan_Huang2018-02-121-0/+6
| | | | | | | | | | | | | | | | | | | | Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the EC. Thus, we don't use the internal hibernate/wake-up feature in npcx. BUG=b:72641658 BRANCH=none TEST=Test system will shutdown and doesn't auto wake up when type hibernate in ec console. And wake up by AC plugin, LID open, or power button. Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4 Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/890569 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* charge_state_v2: Store battery information in new structuresNicolas Boichat2018-02-071-0/+28
| | | | | | | | | | | | | | | | | | | On dual battery systems, this allows to keep both batteries information in similar structures. This also means that battery information can only be fetched via host commands EC_CMD_BATTERY_GET_STATIC/DYNAMIC (next CL will make it possible to fetch the information via shared memory/ACPI). BRANCH=none BUG=b:65697620 TEST=Boot lux/wand, dual-battery algorithm works, AP can fetch both battery information via host commands. Change-Id: I3c087e8f378c5cef0006f6bfe58335228a880e5b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/888381 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* common: Add support for PWM LEDs.Aseda Aboagye2018-02-051-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for a common framework for PWM controlled LEDs. If there are multiple LEDs, they will all follow the same pattern. The pattern is such that it follows the Chrome OS LED behaviour specification, essentially a similar version of led_policy_std.c but for PWM controlled LEDs. To use this framework, a board must do the following: - First, define the number of logical PWM LEDs which will be controlled by this common policy, CONFIG_LED_PWM_COUNT. - Then declare those logical LEDs and define the PWM channels that comprise those LEDs. (struct pwm_led pwm_leds[]). - Next, define what each color should look like (struct pwm_led led_color_map[]). By default, the colors follow the recommended colors in the LED behaviour spec, which assume an LED with a red and green channel. If a board differs or wishes to change the colors in general, they can redefine the colors (CONFIG_LED_PWM_*_COLOR) as they see fit. The colors must be one in enum ec_led_colors. These colors are the ones that can represent the charging state, SoC state, etc. BUG=b:69138917,chromium:752553 BRANCH=None TEST=make -j buildall TEST=Enable led_pwm for meowth, and verify that LEDs behave as expected. Change-Id: I945b86a7f8ed30df58d7da835d83577192548bea Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888220 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Add support for HW alertsAnatol Pomazau2018-01-311-0/+10
| | | | | | | | | | | | | | | | | | | | | - Add a vendor command that provides alert counter. Userspace can use it e.g. for user metric analysis. - Add 'alerts' debug console command. It provides information about chip alerts: supported alerts, fuse status, interrupt status, alert counter. - Add 'alerts fire [INT]' command to fire a software defined alert (globalsec/fwN where N is 0,1,2,3). Signed-off-by: Anatol Pomazau <anatol@google.com> BUG=b:63523947 TEST=ran the FW at Pyro and checked alerts data sent to host Change-Id: I7cec0c451ed71076b44dad14a151b147ff1337e8 Reviewed-on: https://chromium-review.googlesource.com/817639 Commit-Ready: Anatol Pomazau <anatol@google.com> Tested-by: Anatol Pomazau <anatol@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* usb pd: Adding PPC vbus discharge pathJett Rink2018-01-311-9/+15
| | | | | | | | | | | | | | Boards with a PPC will use the PPC to discharge the VBUS line instead of the TCPC or GPIO discharge path. BRANCH=none BUG=b:72179253 TEST=Fall time after device removal on grunt within spec now Change-Id: I822923a1cedb32a20efc3610cce4437ade3387f0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/886563 Reviewed-by: Edward Hill <ecgh@chromium.org>
* stm32: add usb_isochronousWei-Han Chen2018-01-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Templates for USB isochronous implementation. Current implementation only supports TX transmit. Example of usage can be found in CL:803414. Basically, declare an USB isochronous interface by USB_ISOCHRONOUS_CONFIG_FULL(<NAME>, <INTERFACE_NUM>, <USB_CLASS>, <USB_SUBCLASS>, <SUB_PROTOCOL>, <USB_STR_FOR_INTERFACE_NAME>, <USB_EP_NUM>, <PACKET_SIZE>, <TX_CALLBACK>, <SET_INTERFACE>) where <PACKET_SIZE> is size of each USB packet, <TX_CALLBACK> is called when USB hardware has completed a packet. The buffer that USB is not currently using will be passed to <TX_CALLBACK>, allow applications to write next packet to it. When a SET_INTERFACE packet is received, <SET_INTERFACE> will be called with bAlternateSetting and bInterfaceNumber. We will declare interface descriptor with bAlternateSetting = 0 and 1 for you, if you need more alternate settings, you need to declare by yourself. BUG=b:70482333 TEST=manually on reworked staff board Signed-off-by: Wei-Han Chen <stimim@google.com> Change-Id: Ic6d41da6ddd7945edf0bdfff55ede38a97661783 Reviewed-on: https://chromium-review.googlesource.com/818853 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cleanup: Remove CONFIG_USB_PD_TCPC_BOARD_INITShawn Nematbakhsh2018-01-301-3/+0
| | | | | | | | | | | | | | | | | | It's no longer necessary to call board_tcpc_init() from PD tasks, since HOOK_INIT completion is guaranteed before the task starts. Also, calling board_tcpc_init() for each PD task without a port arg is a bad idea. BUG=b:72229154 BRANCH=none TEST=`make buildall -j` Change-Id: I6fba07771693b8343568041960a263e02775a8fc Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/881538 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* samus_pd: Remove 'adc' console commandShawn Nematbakhsh2018-01-301-3/+6
| | | | | | | | | | | | | | | Remove console command for flash / RAM savings. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ibfccbdf45e5c86260cc55237387994fdf094c19c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/885463 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Nami: Update for ALS and temperture sensorElmo_Lan2018-01-281-0/+1
| | | | | | | | | | | | | | | | | Implement ALS code and add a new thermal sensor (Fintek, F75303) BUG=b:71839392 BRANCH=none TEST=Verify Nami can read ALS and thermal data via I2C by ec console. Change-Id: I0f8fd486f62508bbca30a57f435b9f26621cf34b Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/863350 Commit-Ready: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* driver/led: Add LM3630A driverBenjamin Gordon2018-01-251-0/+1
| | | | | | | | | | | | | | | | | | This chip controls the keyboard backlight. The backlight level is set through PWM, but the chip needs to be enabled and configured before PWM settings are recognized. This will be initially used for grunt and zoombini. BUG=b:69379749 BRANCH=none TEST=In EC console for grunt: kblight 100; kblight 0 Change-Id: I5576d709687d8f61b5757485baa239ffd6b41a74 Signed-off-by: Benjamin Gordon <bmgordon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/879082 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* host_command: Suppress individual host command debug logDaisuke Nojiri2018-01-221-0/+3
| | | | | | | | | | | | | | | | | | Host command handler prints every single host command except when commands are repeated back-to-back. This patch allows each board decide which commands should be ignored. When debug printf is suppressed, a global counter is incremented. Developers know there were commands processed but not reported to the console. BUG=chromium:803955 BRANCH=none TEST=Observe 0x97 and 0x98 were not printed. Global suppress counter is incremented. Change-Id: I05e8cde9039f602e8fc06c20e89b328e797bd733 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/876952 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* backlight: Adding support for active low GPIO signalJett Rink2018-01-181-0/+9
| | | | | | | | | | | | | BUG=b:72007261 BRANCH=none TEST=Verified with grunt board (with is active low) Change-Id: I9a58148b8d92065bec982071ed1d97a466197e9a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/872233 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* CBI: Read board info from EEPROMDaisuke Nojiri2018-01-181-0/+6
| | | | | | | | | | | | | | | This patch adds Cros Board Info APIs. It reads board info from EEPROM. This patch sets CONFIG_CBI for Fizz to make it use CBI. BUG=b:70294260 BRANCH=none TEST=Read data from EEPROM. Change-Id: I7eb4323188817d46b0450f1d65ac34d1b7e4e220 Reviewed-on: https://chromium-review.googlesource.com/707741 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: Add definition/configuration for npcx7m6xb/npcx7m7wCHLin2018-01-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power: introducing pwr_avg console commandRuben Rodriguez Buchillon2018-01-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | pwr_avg provides an average voltage, current, and power over the last 1 minute. It's up to the battery drivers to implement this functionality. This change allows us to have better power tracking while minimizing the power impact on the EC, because - the pwr_avg command only needs to be called once every minute, and is short, thus less expensive to parse on ECs without a UART buffer - the work done to keep the avg is partially done by the batteries already and it's just a question of retrieving it. undefined on wheatley since no power debugging planned on that board. usage: > pwr_avg mv = 7153 ma = -605 mw = -4327 BUG=chromium:752320 BRANCH=None TEST=make buildall -j Change-Id: Id1a3479d277aedf90dfa965afb4ee9136654b1cf Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/823884 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config.h: Define CONFIG_EC_EC_COMM_BATTERY_MASTER/SLAVENicolas Boichat2018-01-111-0/+14
| | | | | | | | | | | | | | | | Instead of defining these options in other header files, set them here. This also prevents pre-submit checks from complaining about these symbols being used without being defined in config.h. BRANCH=none BUG=b:65697962 TEST=make buildall -j, presubmit checks pass for CL that makes use of CONFIG_EC_EC_COMM_BATTERY_MASTER. Change-Id: I8098a8ae6422bf0ffb26523785d7c16a3ee1c6df Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/861365 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver/charger/isl923x: Make sure CONFIG_CHARGER_NARROW_VDC is setNicolas Boichat2018-01-101-1/+10
| | | | | | | | | | | | | | | | | | Without this, the battery will discharge if we disallow battery charging (e.g. calling charge_request with either voltage == 0 or current == 0, either by policy, or when the battery is full). Also update config.h to set the option whenever isl923x is used. BRANCH=none BUG=b:66575472 BUG=b:35585464 TEST=make buildall -j Change-Id: Id5515d5ea82a393a3693a3da44cbdc2778296a95 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856538 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charger/isl923x: Implement charger_get_system_power from PSYSNicolas Boichat2018-01-101-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ISL923x, PSYS output is always enabled when the AP is on (provided CONFIG_CHARGER_PSYS is enabled). We add support for charger_get_system_power function, reading PSYS value, when CONFIG_CHARGER_PSYS_READ is defined. This will be used by the charging algorithm on lux. We also rename CONFIG_CMD_CHARGER_PSYS to CONFIG_CHARGER_PSYS_READ as CONFIG_CHARGER_PSYS_READ provides both "psys" console command and the new function. We also cleanup unneeded undefs in board files. Note that this does not implement the function on bd9995x, but this could be done without too much effort. BRANCH=none BUG=b:71520677 TEST=On lux, without AC connected, check that "psys" output roughly matches the output current from the battery. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: Ie1ce8e0ac103daacc5a08b8ccae604d1d83551b8 Reviewed-on: https://chromium-review.googlesource.com/848487 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charge_state_v2: Add charge_set_output_current_limit functionNicolas Boichat2018-01-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | This function sets up and enables "OTG" mode on the charger chip (i.e. use the charger to provide power from the battery). It also records the output current in curr.output_current, to make sure that the charger loop is aware that current is provided externally. We also add a CONFIG_CHARGER_OTG to remove these functions on boards that do not require it. BRANCH=none BUG=b:65697962 TEST=On wand, when discharging, battery status is updated every 5 seconds (and not every 60 seconds). Change-Id: Ibf93933436f3eb24552a8e1eb9d97522fca2ce79 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/842743 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add SB-TSI temp sensor driverAlec Thilenius2018-01-031-0/+1
| | | | | | | | | | | | | | | | | | This adds the driver for the SB-TSI temp sensor. This is a sensor on the AMD AP SOC (Stoney Ridege FT2) that acts like an 8-pin temp sensor with an I2C interface. BUG=b:69379715 BRANCH=None TEST=Build Change-Id: Iaafe6c7beb3e02e4e341617e8f117c03c0a882a2 Signed-off-by: Alec Thilenius <athilenius@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/833346 Commit-Ready: Alec Thilenius <athilenius@google.com> Tested-by: Alec Thilenius <athilenius@google.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* ec_flash: Add W25Q128 SPI flashScott Worley2017-12-281-0/+1
| | | | | | | | | | | | Add W25Q128 flash device support. BRANCH=none BUG= TEST=Modify a board build for W25Q128 and check SPI code sets flash security bits correctly. Change-Id: I6173f4cf751f3fbf68af75983f44d357a0b954f6 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
* ec_driver: Add ADT7481 and TMP411 I2C sensorsScott Worley2017-12-281-0/+2
| | | | | | | | | | | | | Added I2C sensors ADT7481 and TMP411 with config items and build rules. BRANCH=none BUG= TEST=Define CONFIG_TEMP_SENSOR_ADT7481 or _TMP411 and build board. Change-Id: I4d1eb55ee56ad3f42787538bb839193e683d0a60 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
* ec_gpio: Add GPIO power down supportScott Worley2017-12-281-0/+6
| | | | | | | | | | | | | | | | | | | Experimental and disabled by default feature for powering down GPIO pins on those EC's supporting it. Pins may be powered down by module ID or pin name. Goal is to make use of common GPIO pin table. If enabled, developer must implement power down support in chip level. Developer re-powers module pin(s) by calling the current gpio module enable API in the wake path. BRANCH=none BUG= TEST=Feature is disabled by default. Build all boards with feature disabled. Change-Id: Ifacd08e51def6424baf5c78c84b24f1d9f4bc4aa Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
* ec_chip_mchp: Add MCHP chip folderScott Worley2017-12-281-0/+38
| | | | | | | | | | BRANCH=none BUG= TEST=Review only. Committing small pieces until all code passes review. Change-Id: I9d16f95314a7c97b11c4fe61602c6db2621e6024 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
* printf: add %li format for compatibilityVincent Palatin2017-12-251-0/+7
| | | | | | | | | | | | | | For compatibility/convenience, implement the '%li' printf format as a *32-bit* integer format, as it might be expected by non-EC code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:70320279 TEST=run on Eve EVT with unspecified external binary and see its traces are correctly printed. Change-Id: Iac20e823c74aac4f659176416eebd804c321d47c
* ec_ec_comm_slave: EC-EC communication slave task and functionsNicolas Boichat2017-12-201-0/+14
| | | | | | | | | | | | | | | | | This adds functions required for the slave in EC-EC communication, including the task that processes requests from the master. This also adds required CONFIG_EC_EC_COMM_SLAVE/MASTER/BATTERY config options. BRANCH=none BUG=b:65697962 TEST=Build wand and lux boards, flash it, EC-EC communication works. Change-Id: I772d9023a830f4fbc37316ca31e4da8240de7324 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/828180 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config: Add CONFIG_BUTTON_TRIGGERED_RECOVERY.Aseda Aboagye2017-12-181-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_BUTTON_RECOVERY option was a little confusing especially when we have the CONFIG_DEDICATED_RECOVERY_BUTTON option. This commit renames CONFIG_BUTTON_RECOVERY to CONFIG_BUTTON_TRIGGERED_RECOVERY to help make things a little clearer. Additionally, to avoid copy paste, defining CONFIG_BUTTON_TRIGGERED_RECOVERY will populate the recovery_buttons table with either the volume buttons or a dedicated recovery button depending what the board is configured for. Lastly, if CONFIG_DEDICATED_RECOVERY_BUTTON is defined, CONFIG_BUTTON_TRIGGERED_RECOVERY is defined as well since it's implicit. BUG=chromium:783371 BRANCH=None TEST=make -j buildall Change-Id: Idccaa4d049ace0df3b98b35bdd38ac9dbd843200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/830917 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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