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* Battery: Use host full capacity to compute display percentageDaisuke Nojiri2022-09-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The full capacity known by the host may slightly differ from the full capacity known by the EC because we notify the host of the new capacity only if the difference is larger than 5 mAh. This patch makes the EC use the host's full capacity instead of the local full capacity to compute the display percentage. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:109954565,b:80270446 BRANCH=none TEST=Verify display percentages printed by EC and power_supply_info move up synchronously on charge and the LED and the taskbar icon turn to full at the same time. TEST=buildall Change-Id: Ie695a9937a22fc7a769b82448f4600d4491935b3 Reviewed-on: https://chromium-review.googlesource.com/1330101 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3872564 Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* Battery: Compensate remaining charge to match full capacityDaisuke Nojiri2022-09-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If remaining charge is more than x% of the full capacity, the remaining charge is raised to the full capacity before it's reported to the rest of the system. Some batteries don't update full capacity timely or don't update it at all. On such systems, compensation is required to guarantee the remaining charge will be equal to the full capacity eventually. On some systems, Rohm charger generates audio noise when the battery is fully charged and AC is plugged. A workaround is to do charge- discharge cycles between 93 and 100%. On such systems, compensation was also applied to mask this cycle from users. This used to be done in ACPI, thus, all software components except EC was able to see the compensated charge. This patch is moving the logic to EC. With this and the following changes, EC can see what the rest of the system sees, thus, can control LEDs synchronously (to the display percentage). Another rationale of this move is EC can perform more granular and precise compensation than ACPI since it has more knowledge about the battery and the charger. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> CQ-DEPEND=CL:3880010 BUG=b:109954565,b:80270446 BRANCH=none TEST=Verify charge LED changes to white (full) on Sona synchronously to the display percentage. TEST=Verify charge LED changes to blinking white (low) on Sona within 30 seconds synchronously to the display percentage. Change-Id: I4e3f70efa39e62c91cb8894b603c551cd23511aa Reviewed-on: https://chromium-review.googlesource.com/1312204 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3869317 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver: icm426xx: Use calibration unit to set/get offsetGwendal Grignou2021-01-291-24/+15
| | | | | | | | | | | | | | | | EC interface use constant (not range dependent) units to get/set offsets. Use them in icm426xx driver. BUG=b:177292639 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=compile Change-Id: I6e6b1551464ea389db34646ba5b2bb553d683d7a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657955 Reviewed-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659407
* icm426xx: reset data rate when initDavid Huang2021-01-071-0/+2
| | | | | | | | | | | | | | | | | When icm426xx init, reset data rate to enable sensor. BUG=chromium:1160266 BRANCH=main TEST=Check ectool motionsense get data after shutdown and power on. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I0a1042eaf6dbdb132c4bb50975eae3c6f0cfad00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597131 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600805 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* driver: add ICM-426xx driver supportJean-Baptiste Maneyrol2021-01-075-0/+1570
| | | | | | | | | | | | | | | | | | | | | | | Add ICM-426xx accel/gyro driver code. BUG=chromium:1117541 BRANCH=None TEST=ectool motionsense fifo_read && tast run hardware.SensorRing Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I83fe48abc6aa9cde86576a777ac4272d90fac597 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317888 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2584545 Tested-by: David Huang <david.huang@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Auto-Submit: David Huang <david.huang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600803 Reviewed-by: YH Lin <yueherngl@chromium.org> Commit-Queue: YH Lin <yueherngl@chromium.org>
* driver: bmi160: Fix rounding error in set_offset() and get_offset()Ching-Kang Yen2020-12-241-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | The original set_offset() and get_offset() codes in the driver/accelgyro_bmi160 use simple divisions to write the data. The more times the set_offset() and get_offset() is used, the data will get closer to 0. Fixing it by replacing simple division to round_divide(), division that round to nearest, in the common/math_util.c. BRANCH=octopus BUG=b:146823505 TEST=Testing on octopus:ampton on branch [firmware-octopus-11297.B]. Checking the data did not rounding to 0. Change-Id: Ide9df9e32fc501e63d6f952cb8254df7662afd23 Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002998 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600801 Tested-by: David Huang <david.huang@quanta.corp-partner.google.com> Auto-Submit: David Huang <david.huang@quanta.corp-partner.google.com>
* ps8xxx: support multiple chips in the runtimeMarco Chen2020-09-112-113/+263
| | | | | | | | | | | | | | | | BUG=b:159082424 BRANCH=none TEST=verify the same EC image can work on devices with PS8751 or PS8755 for src / snk roles. Signed-off-by: Marco Chen <marcochen@chromium.org> Change-Id: I3a743666a4ccbcae37ecb6f0d6657122cf9c5a69 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2304237 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393406 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver/tcpm/ps8xxx: Consistent DCI disable methodDevin Lu2020-09-111-46/+19
| | | | | | | | | | | | | | | | This patch make consistent with DCI disable method for PS8705/PS8805/PS8815, they are in the similar chip group. BUG=b:161202452 BRANCH=none TEST=make buildall -j. Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: Ia919dab9fb6afd72e3b693d94fe8abee628e2f40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2313056 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393397 Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver/tcpm: add support for PS8755Devin Lu2020-09-113-9/+20
| | | | | | | | | | | | | | | | | | | The patch adds support for the Parade Tech PS8755 TCPC/SuperSpeed mux. It is similar chip group as PS8705/PS8805/PS8815. BUG=b:159042756, b:159082424 BRANCH=none TEST=make buildall -j. make BOARD=jinlon with this new CONFIG. Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I38fa02704cc352da0e27eae8cd8bbce89a807975 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2279339 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Commit-Queue: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393396 Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8805: Follow the sequence to enable the DCI register accessWai-Hong Tam2020-09-111-4/+23
| | | | | | | | | | | | | | | | | Follow the sequence in the programming guide to enable the DCI register access, even they are always enabled in the firmware. BRANCH=None BUG=b:161202452, b:147772854 TEST=Tested Trogdor negotiate >5V charging and source power to USB devices. Change-Id: Ia121855cf097fe4b517ceefa461568fbec67b63d Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2304264 Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393395 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8xxx: add helper function to access alternate I2C pagesCaveh Jalali2020-09-112-5/+5
| | | | | | | | | | | | | | | | | | this provides a helper function for computing the I2C page address of alternate I2C pages available on the ps8xxx family of chips. BRANCH=none BUG=b:158857815,b:159289062 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I121ec9f2beaadf3e4e3c429d177fe38eb2976be8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2271700 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2392239 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* PS8805: Do not enable and disable DCI registersWai-Hong Tam2020-09-111-17/+3
| | | | | | | | | | | | | | | | | | | | | PS8805 is not like PS8751, which needs to rewrite the TCPC reg A0 bit 0 to enable the DCI registers. The DCI registers are always accessible. Also there is a bug on firmware, like 0x8, 0xC, 0xD, that rewriting the reg A0 bit 0 to 1 will make the TCPC I2C not accessible. BRANCH=None BUG=b:147772854 TEST=Verified on Trogdor, fw 0xC, 0xD, and 0xF, the TCPC I2C is accessible. Change-Id: Ie554d2b4022397801423fb3670305bf536b2cc20 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015641 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2392238 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver/tcpm: Add support for PS8705Aseda Aboagye2020-09-113-2/+47
| | | | | | | | | | | | | | | | | | | | | The commit adds support for the Parade Tech PS8705 TCPC/SuperSpeed mux. It is similar to other Parade TCPCs in its family. BUG=b:158760026 BRANCH=None TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I23288757f2baf56742958357b5ee6bac5cffa02f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2243314 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2392237 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8xxx: add support for the ps8815Caveh Jalali2020-09-113-7/+24
| | | | | | | | | | | | | | | | | | | | | | this adds support for the ps8815 variant of the parade TCPC. this chip is very similar to its predecessors like the ps8751 and ps8805 and can be supported by the same driver. at this point, the TCPM can talk to the chip but we don't properly detect chargers - the CC line states seem wrong and CC status changes do not trigger an ALERT in the ps8815. BRANCH=none BUG=b:144397088,b:147459088 TEST=EC detects the chip on boot. Change-Id: If86abd1fa21cf8f33f28c4ce89050b29e9408532 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1969524 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2392236 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8xxx: disable DCI modeCaveh Jalali2020-09-114-22/+110
| | | | | | | | | | | | | | | | | | | | | | | DCI mode is auto-enabled by default. we don't actually support DCI (intel specific SoC debug path), so we can explicitly disable DCI mode. doing so, saves about 40mW on the 3.3v rail when USB2 devices or USB-C to USB-A dongles are left plugged in. this is particulary relevant in sleep mode as this accounts for a significant portion of the system power consumption. BUG=b:119875949 BRANCH=none TEST=verified power consumption drops using sweetberry, USB devices still functional across suspend/resume. Change-Id: Id13630425c78965d2ac4f2e97715374ae0640d23 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1732231 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2392235 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* syv682x: disable VBUS discharge in sink modeCaveh Jalali2020-07-161-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | The syv682x needs to have FDSG (force discharge mode) disabled in order to allow charging. BRANCH=none BUG=b:148487130,b:148467221 TEST=verified PD charging works with USB3 daughterboard (crrev.com/c/2013656 needed to enable USB3 board). Change-Id: Ifff20576accf88822228b7bd7b9eeb6b6cff6a6b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037097 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org> Tested-by: Eric Herrmann <eherrmann@chromium.org> (cherry picked from commit dd5b97c3e86d71919ec1287e19e740e86081fdde) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2291468 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* syv682x: fix status register readCaveh Jalali2020-07-161-1/+4
| | | | | | | | | | | | | | | | | | | | | We were reading CONTROL_1_REG instead of STATUS_REG to check the VSAFE_0V status. This corrects the register being accessed. BRANCH=none BUG=none TEST=volteer boots without a battery Change-Id: I06d0fbc0b9313b809ed43be13138241beca395a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1999619 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> (cherry picked from commit d9d96d1b01cb66fbfdc50fe705eaa2cc2579b442) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2291467 Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver: lis2dw12: Fix maximal ODRGwendal Grignou2020-03-101-1/+3
| | | | | | | | | | | | | | | | Be sure EC max frequency is taken into account. BUG=chromium:615059,chromium:1059318 BRANCH=hatch, grunt TEST=Check tast run <IP> hardware.SensorRing works on Akemi(hatch) with new firwmare. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I8c4bf1213c876ceec4b20a4dd87094aab79d7b0b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092214 Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org> (cherry picked from commit b13856bc9f193c8c7f4a045b684131b5cf7d0900) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094746
* ppc: Use hard reset to recover from CC overvoltageEdward Hill2019-12-061-66/+27
| | | | | | | | | | | | | | | | When sn5s330 PPC detects CC overvoltage, recover via hard reset and don't enable PP2 sink FET directly. Also clean up the interrupt unmasking in sn5s330_init(). BUG=b:144892533 BRANCH=grunt TEST=Do ESD test to trigger CC1/CC2 OVP, device recovers to sink Change-Id: I662bf164b55508be4d5cc1b3ad639c9613bd1935 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949264 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949267
* helios: Detect PPC sn5s330 CC1/CC2 OVP and release OVP.Michael5 Chen2019-12-062-14/+58
| | | | | | | | | | | | | | | | | | | | If PPC have CC OVP protection, check VBUS_GOOD. If VBUS_GOOD is ok, release CC OVP. BUG=b:141587322 BRANCH=Master TEST=Manual Do ESD test to trigger CC1/CC2 OVP. Using EC console command PPC_DUMP to check ppc regiset is correct. Change-Id: I3b817cc1dcec4c14ed4e2098b7ad7582b938f613 Signed-off-by: Michael5 Chen <michael5_chen@pegatroncorp.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1826098 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1933787 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: lis2dw12/lis2dwl: fix wrong __fls usagePaul Ma2019-10-252-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | __fls(n) is defined as (31 - __builtin_clz(n)) in include/common.h. Because of the definition, n can't be 0. When n is 0, __fls(0) will be -1 and it is a wrong result. Since sensor data rate can be set lower than LIS2DW12_ODR_MIN_VAL, it is possible for __fls() to get a 0 parameter. This CL will fix this condition. Because macros are getting complex, move them to c file and convert to functions. BUG=b:143242489 BRANCH=none TEST=run 'suspend_stress_test --suspend_min=10 --wake_min=10 \ --count=2500' on DUTs, test pass and no EC crash. Change-Id: I46febb602b47624ba5d0106abaedd34a23ebe96f Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1876297 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> (cherry picked from commit 16275bb36d338dd952b9312450c0cee110d5468c) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880349 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: lis2dw12/lis2dwl: add polling mode supportPaul Ma2019-08-231-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add polling (forced mode) support for lis2dw family. 'froced mode' is a common usage model for lid accel sensor. Treeya will support two set (BMI160/KX022 and LSM6DS3/LIS2DWL) of base/lid sensors and both of their lid sensor should work in the same mode (forced mode or interrupt). Since KX022 driver only support polling, so lis2dwl also need polling support. This patch add it. BUG=b:138768226, b:138978278 BRANCH=none TEST=on Akemi board, build both interrupt and polling (by define CONFIG_ACCEL_LIS2DW_AS_BASE or not) mode firmware, boot and confirm sensors init suscess and 'accelinfo on' has correct sensor x/y/z output. Cq-Depend: chromium:1739026 Change-Id: Ib0dcb7b317eec51a38598a644f965d7ecc5928c6 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1741598 Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767533 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: lis2dwl: add driver supportPaul Ma2019-08-233-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | lis2dwl has almost the same register interface as lis2dw12. lis2dwl only has one low power mode and when in low power mode, it has only 12 bit resolution. In order to get 14 bit resolution, we only use its high performance mode. Add MOTIONSENSE_FLAG_INT_ACTIVE_HIGH flag to support both active high and active low interrupt. BUG=b:138768226, b:138978278 BRANCH=none TEST=use Akemi board, add lis2dwl as accel sensor, boot the board and make sure sensor x/y/z get correct value by 'accelinfo on' Cq-Depend: chromium:515302 Change-Id: I37fcc0f43af3c8055079e09db00757b665813ba8 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1739026 Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: mario tesi <mario.tesi@st.com> Commit-Queue: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767532 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: lis2dw12: Add driver supportmario tesi2019-08-233-0/+782
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added ACC LIS2DW12 driver support. Features included in this driver are: - Basic Sensor Read acceleration data - ODR and FS runtime configuration - FIFO support with watermark interrupt events - Shared commons function with ST MEMs devices - Switch Low Power to High perf. mode in case of ODR > 200 Hz - Configure D-TAP event detection in Hardware BUG=b:73546254 BRANCH=master TEST=Tested on discovery_stmems target BOARD with LIS2DW12 connected to EC i2c master bus and motion sense task running. To build firmware for discovery_stmems target with LIS2DW12 sensor connected, simply uncomment CONFIG_ACCEL_LIS2DW12 define in board.h target file and make with target BOARD=discovery_stmems. Commands used to test LIS2DW12 device are: - accelinit 0 (to configure accel. device) All basic features tested, including changing in ODR: - accelrate 0 10000 (set ODR to 10 Hz) - accelrate 0 12500 (set ODR to 12.5 Hz) - accelrate 0 25000 (set ODR to 25 Hz) - accelrate 0 50000 (set ODR to 50 Hz) - accelrate 0 100000 (set ODR to 100 Hz) - accelrate 0 200000 (set ODR to 200 Hz) - accelrate 0 400000 (set ODR to 400 Hz) - accelrate 0 800000 (set ODR to 800 Hz) - accelrate 0 1600000 (set ODR to 1.6 kHz) Full Scale Range: - accelrange 0 2 (set Full Scale Range to 2g) - accelrange 0 4 (set Full Scale Range to 4g) - accelrange 0 8 (set Full Scale Range to 8g) - accelrange 0 16 (set Full Scale Range to 16g) FIFO features and interrupt management: - accelinfo on 1000 (motion info task with refresh rate 1 s) and polling data read: - accelread 0 (to read data from accelerometer) Change-Id: I0b9861a71e81052e7ee8eb235a1a5b2a57d4c6f5 Signed-off-by: mario tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/515302 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Paul Ma <magf@bitland.corp-partner.google.com> Tested-by: Paul Ma <magf@bitland.corp-partner.google.com> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767531 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-08-23120-774/+765
| | | | | | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767528 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* drivers/tcpm/ps8xxx: Return hardcoded vendor and product idKarthikeyan Ramasubramanian2019-08-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | When the requester does not expect the chip information from the live target, return the hardcoded vendor and product id. BUG=b:128820536,b:119046668 BRANCH=None TEST=Boot to ChromeOS Change-Id: I74affb00951411a3483258a8db165038e7eb683f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617894 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767527 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* ec_commands: Rename 'renew' to 'live' in EC_CMD_USB_PD_CHIP_INFOKarthikeyan Ramasubramanian2019-08-236-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as follows: 0 -> Return hard-coded info for Vendor ID/Product ID and cached info for the Firmware Version 1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version Also rename the 'renew' field to 'live' to match the new semantics. BUG=b:128820536,b:119046668 BRANCH=None TEST=make -j buildall; Boot to ChromeOS. Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767526 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-08-23121-825/+4325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767525 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* common: remove CONFIG_SMBUS dead codeDenis Brockus2019-08-231-20/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_SMBUS is not used. Cleaning up the code by removing this. Added a comment to document the removal and why. This will give a way to find the code if we ever needed to bring it back BUG=chromium:982316 BRANCH=none TEST=make buildall Change-Id: I40703a95bc849538e1aee32f6f96beab811285bd Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704279 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767523 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* anx7447: USB Mux is reset when TCPM is resetSam Hurst2019-08-231-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling tcpm_init will reset the Analogix USB Mux on port 0. I'm not sure if this is the proper behavior but I lean towards that it's not because there is a separate function, usb_mux_init, for resetting the usb mux. Also, calling tcpm_init for the Parade does not reset it's mux. BUG=b:134829988 BRANCH=none TEST=manual HATCH (Port 0): The original and new stack was tested as follows: 1) Plug in dock 2) Depending on dock, plug in HDMI or DP 3) Plug TypeC power into dock 4) Verify projection on external monitor isn't lost Change-Id: I88d17479f4d5810be3686cd78545cc99b0c41347 Signed-off-by: Sam Hurst <shurst@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1650728 Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767521 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-08-234-35/+42
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767520 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* USB-PD: Consolidate tcpc_config declarations in usb_pd_tcpm.hDaisuke Nojiri2019-08-231-5/+0
| | | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config is declared in two places. This patch consolidates declarations in usb_pd_tcpm.h. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I4f30d06b1eaeb6a83b664de76116d85d65a9fc97 Reviewed-on: https://chromium-review.googlesource.com/1616007 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767515 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* battery: Consolidate battery_manufacturer_nameDaisuke Nojiri2019-08-235-21/+245
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, the battery_manufacturer_name API is implemented individually by each chip. This patch consolidate the definitions. It also allows a board to return custom manufacturer names. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129599895 BRANCH=none TEST=buildall Change-Id: Ib0f60c9be71fea31658ab284a915d73341b9145e Reviewed-on: https://chromium-review.googlesource.com/1590039 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767513 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-08-231-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767512 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* anx7447.c: change VBUS present detection interfaceXin Ji2019-08-231-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ANX PD has two way to get VBUS present info, 1:ADC, 2:Comparator the ADC has been reset at chip reset stage, the comparator(0x1e:bit2) is analog part, it is not been reset by chip reset. there is a corner case which EC TCPM detect VBUS present info at chip reset stage(at system rebooting stage, EC TCPM issue TEST_R signal, this will trigger chip hardware reset). the original VBUS present function checks the VBUS from ADC, the ADC register value became to 0 while at chip reset stage, so at this moment, EC TCPM need check 0x1e:bit2 to get real VBUS present info. BRANCH=None BUG=b:129092057 TEST=Tested on Phaser, reboot stress test. Change-Id: I1e847c88b22684bc9b17243628179bad534801b2 Signed-off-by: Xin Ji <xji@analogixsemi.com> Reviewed-on: https://chromium-review.googlesource.com/1535085 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767511 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* Battery: add support battery-cutoff SMBus block write functionmatt_wang2019-08-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | Implements battery-cutoff SMBus write block function BUG=b:122944526 BRANCH=None TEST=Verify battery cuff on fleex via SMBus block write. Change-Id: Ib52146cd3042c4a6d2dbafadd430591936230891 Signed-off-by: matt_wang <matt_wang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1470462 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767508 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: anx7447: remove ec_version dependencyGwendal Grignou2019-08-231-1/+0
| | | | | | | | | | | | | | | | | | Prevent anx7447 to be recompiled all the time. BUG=none BRANCH=none TEST=anx7447 is not recompiled all the time. Change-Id: I3d3299c84bc0d60a594f21fe5f937e21fc51af27 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1459820 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767506 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* Ampton: Set the PS8751 to source mode before enter low power modeJames_Chao2019-08-234-1/+18
| | | | | | | | | | | | | | | | | BUG=b:113830171 BRANCH=octopus TEST=check the power consumption is lower Change-Id: I527cdc5d1e4dd5de137ab0927e66c171696758ce Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1426306 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767505 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* rammus: reconfig the PS8751 i2c port according to the board versionZhuohao Lee2019-08-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Shyvana, we found that if we put the Parade PS8751 and Analogix ANX3447 on the same i2c bus, the ANX3447 would be broken because of PS8751 i2c bus error. To avoid this kind of problem, we decided to separate the TCPC i2c bus starting from board version >= 2. The new assignment are ANX3447:i2c_0_0, PS8751:i2c_0_1. This patch also adds a new config CONFIG_USB_PD_TCPC_RUNTIME_CONFIG for enabling runtime switching the TCPC setting. BUG=b:118063849 BRANCH=firmware-rammus-11275 TEST=verified on DUT with board_version <= 1 verified on reworked DUT with board_version >= 2 Change-Id: I0bdc930c1a5e691239f5f5c256d380d0111eed91 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1381600 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767504 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver/anx7447: Modify Vconn SW protection time of inrush current and power ↵xiong.huang2019-08-232-1/+20
| | | | | | | | | | | | | | | | | | | | | | | SW short protect current. The default values of Vconn SW protection time of inrush current is 19us and power SW short protect current is 370mA, it finds that the current of Vconn will up to 656mA during press F3+power button with Huawei dongle plugged in MB, then Vconn will drop when the large current happen. Vendor suggest to adjust Vconn SW protection time of inrush current(modify register 0xAA from 19us to 2.43ms) and power SW short protect current(modify register 0xA8 from 370mA to 440mA). BUG=b:119540455 BRANCH=none TEST=The HDMI display well with Huawei dongle at MB side when pressing F3+ power button to reboot OS. Change-Id: Ibb7e602fc4a4aa9cb69231a7f199f4ea31265148 Reviewed-on: https://chromium-review.googlesource.com/1343643 Commit-Ready: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Tested-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767503 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* anx7447:Configure the MUX correctly at initSanna Parmar2019-08-231-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | ANX initializes its muxes to (MUX_USB_ENABLED | MUX_DP_ENABLED) at init, this is error prone when the display and USB devices are attached before the ANX chip is powered on hence, overriding the default mux state to TYPEC_MUX_NONE at init. BRANCH=none BUG=b:117789358 TEST=Manually tested on yorp 1. EC command "typec 0" shows 'No Superspeed Connection' when nothing is connected. 2. Able to get the HDMI display working on ANX before and after EC reboot. Change-Id: Ic174ff77fbfac7bb7478f4f92abf80018480c406 Signed-off-by: Sanna Parmar <fnu.sanna@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1282017 Tested-by: Sanna Fnu <fnu.sanna@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767502 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* Octopus: add reset logic for C0 TCPCDiana Z2019-08-231-0/+9
| | | | | | | | | | | | | | | | | | | | | This change adds a call to the C0 TCPC reset for standalone TCPC boards which have that pin hooked up in hardware, and adds the GPIO as unimplemented for boards which do not have this yet. BRANCH=None BUG=b:112756630 TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset, then verified that charging on C0 worked. Also imaged yorp proto 2 and rebooted, verifying C0 reset was not attempted. Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257647 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767501 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* driver: set Kionix accel min frequency to 12.5HzEnrico Granata2019-08-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The EC is running at 10Hz itself, so it won't be able to properly handle frequencies below that threshold, and data will end up being sent to the kernel at 10Hz. This is a source of CTS issues on some devices, as Android expects to be able to program the sensor to send data at 1Hz given the sensor's configuration parameters. Fix the issue by picking the closest frequency above 10Hz that the accelerometer supports, i.e. 12.5Hz BUG=b:134422740 BRANCH=oak TEST=run CtsSensorTestCases, observe it pass Change-Id: I56772009817e3cbd452e96637c0a78f54f3854c7 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647363 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719567 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* common: motion_sense: Spread timestamps in motion sense fifoYuval Peress2019-08-024-63/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes moves the specialized logic for timestamp spreading away from the accelgyro_lsm6dsm and into the main motion_sense loop. The motion_sense_fifo_add_data function was replaced by a stage equivalent, and a commit function was added. Similarly, internal static functions for motion_sense.c were renamed to use the stage terminology. The idea is: When a sensor is read, it might provide more than one measurement though the only known timestamp is the one that caused the interrupt. Staging this data allows us to use the same fifo queue space that the entries would consume eventually anyway without making the entries readable. Upon commit, the timestamp entries are spread if needed. Note that if tight timestamps are disabled, the commit becomes a simple tail move. BUG=chromium:966506 BRANCH=None TEST=Ran CTS on arcada. Change-Id: Ib7d0a75c9c56fc4e275aed794058a5eca58ff47f Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1637416 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719566 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* FIXUP: sensor: Adjust max_frequency based on EC performanceGwendal Grignou2019-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | When chaning the macro fro BMA255, the step was set to 125Hz, so it assumes the EC can support MEMS ODR set to 125Hz. This is not the case on poppy and nautilus in the poppy branch. BRANCH=poppy BUG=b:118205424,b:118851581,chromium:615059,b:131705379 TEST=Compile Change-Id: Ib60abb3919dc1ce049211d848fc4e4de2e5e51c0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1621188 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719563 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver: lsm6dsm: sensor event spreadingYuval Peress2019-08-022-12/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:129159505 BRANCH=None TEST=Ran Android CTS Fixes event out of order errors in CTS. This is fixed by doing the spreading on the ec. A new queue is used (data_queue) and in place of the old call to motion_sense_fifo_add_data we now add the event to the queue and increment the sensor's sample count. At the caller (load_fifo) we then figure out the window (time between the last interrupt and the read) and the period by dividing the window by the number of samples (this is done per sensor). If the period is larger than the odr, then the odr is used (this helps with accuracy). Events are now spread between the known time the first entry was added and the read time. Change-Id: I7094a719c76b4b08a758d053e5dfbdba0a30684b Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1620792 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719562 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver: lsm6dsm: Fix missing eventsYuval Peress2019-08-021-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | BUG=b:129159505 BRANCH=None TEST=Ran Android CTS Fixes missing event errors in CTS. This is done by updating the last_fifo_read_ts and checking the interrupt GPIO. If we find that the GPIO is still low at the end of the read, that means that we've gotten new data while reading and never fully empties the FIFO. We know this must have happened some time between the time we read the count and when we were reading the FIFO, for now we'll use the upper bound of this to be safe. Change-Id: I0461f9d2703a3801e57e7769fbfe0e8de750706a Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1620791 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719561 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* motionsense: Convert in_spoof_mode to a more generic flagsYuval Peress2019-08-021-1/+1
| | | | | | | | | | | | | | | | BUG=b:129159505 BRANCH=arcada TEST=I ran `make buildall` since this change isn't used yet it doesn't affect run-time behavior. Change-Id: I01857d679b800f9b53762c659ebd9a018cbf16db Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1612251 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719559 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* FIXUP: driver: Add L3GD20H gyrometer basic driver supportGwendal Grignou2019-08-021-5/+0
| | | | | | | | | | | | | | | | | | | | set_data_rate() was called with wrong argument and is not necessary. set_range is called by motion_sensor_init. BUG=none TEST=compile BRANCH=none Change-Id: Ia21911a0d6361e819a8bf381918740f189496c59 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1620692 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719558 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver: bmi160: Check enable_fifo flags before processing FIFOGwendal Grignou2019-08-021-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | If there is an interrupt pending after we suspend the BMI160, we will try to collect length from the FIFO, but the FIFO is suspended. Bring back enable_fifo flags check before processing the FIFO. It has been move after gathering the length in CL:1128555 BUG=b:127321764,b:131272795 BRANCH=master TEST=Using flip_flop.sh script at b/131272795#comment2 Check the messages "unexpected empty FIFO" disappear. Change-Id: Iaab1a7f3607b902acd92b75c926365d7eb09fd5e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1585420 Reviewed-by: Enrico Granata <egranata@chromium.org> (cherry picked from commit d17cd2add14f1f1e32bd58d51d60a2c93f17f055) Reviewed-on: https://chromium-review.googlesource.com/1585471 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1719554 Reviewed-by: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
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