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this replaces some ROP PMIC register magic numbers with their actual
names. corrected a few comments about the bits we're writing into
these registers along the way.
BUG=b:75070158
BRANCH=none
TEST=boots on atlas
Change-Id: If3be6b4c1d550d7e0770450e9f713282835656b5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1278096
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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this adds definitions for some additional PMIC registers we're using
in our codebase.
BUG=b:112732855
BRANCH=none
TEST=flashed atlas with new EC build
Change-Id: Ibad7b11b3770f00c925c2d8fc3b24109147aa643
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187899
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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this introduces a top-level header file for the bd99992 PMIC.the temp
sensor portion of this chip already has an established header file, so
we can just include it.
at this point, we only need one new register definition - the SDWNCTRL
(shutdown control) register.
BUG=b:110237370
BRANCH=none
TEST=it compiles
Change-Id: I324df08ed37d6d6d85520e1217135657b18a23a0
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096484
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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