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* task: Add task_enable_task() and task_disable_task()Yilun Lin2019-08-225-0/+65
| | | | | | | | | | | | | | | Provide API to disable/enable tasks. All the tasks are marked enabled after hook_task starts. We need a way to control the tasks when it shouldn't run in some states. BUG=b:136240895 TEST=Disable the tasks and see it won't be scheudled when task_wake(). BRANCH=None Change-Id: I2662f3619b22ed28387fe3c783001ba2a745620c Signed-off-by: Yilun Lin <yllin@google.com> Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753562
* log: Preserve Kukui EC reset logs across every EC reboot on SRAM.Shannon Chen2019-08-211-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Kukui, we need to put console logs and reset reasons at fixed addresses on SRAM to save the information across each EC resets. Otherwise, EC will lose console logs and reset reasons after resetting EC. This CL ensures that the contents of reset and console logs will not be clobbered or cleared by putting mandatory symbols at a fixed location on SRAM. The values will only be reset when checksum or sanity check fails. BUG=b:133795403 TEST=1. On Kukui, shutdown AP, reboot AP, or sysjump, and see the previous logs before reboot will be kept on /var/log/croc_ec.log 2. Reset reasons can be viewed with ectool uptimeinfo BRANCH=master Change-Id: I19db49101fda1675dc2fdc047b7f14af77cdb6e6 Signed-off-by: Shannon Chen <shannc@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716671 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Shannon Chen <shannc@chromium.org> Tested-by: Shannon Chen <shannc@chromium.org>
* common/system: refactor some confusing ifdefsJack Rosenthal2019-07-311-2/+2
| | | | | | | | | | | | | | | | | I had a hard time reading this section, so figured I may as well rewrite it to use IS_ENABLED while I was here. Gave CONFIG_{RO,RW}_HEAD_ROOM a default value of zero here, which makes the math work out for boards without it anyway. BUG=none BRANCH=none TEST=buildall Change-Id: I87dc2d73838c350088916b57aa51d5f368c5592f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727570 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* cleanup: remove CONFIG_REPLACE_LOADER_WITH_BSS_SLOWJack Rosenthal2019-07-311-13/+0
| | | | | | | | | | | | | | | | | | This option was only used with kunimitsu, which was removed from the EC codebase a long time ago. The EC code won't even compile with this option enabled anymore. Remove it! BUG=chromium:989301 BRANCH=none TEST=buildall Change-Id: I8ede226ec1e7b300ded6bb1769d82e142db1b0aa Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727569 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cortex-m0: implement __ffssi2Ting Shen2019-07-292-1/+17
| | | | | | | | | | | | | | | | | | | The file is copied from riscv-rv32i/__builtin.c. bc12_update_charge_manager() in pi3usb9201 driver uses this function. BUG=b:135895590 TEST=combined with CL:1673955, build and deploy on jacuzzi BRANCH=master Change-Id: If8b8cc8e4a3acdad7285c23e2f3627c7d05bf3b8 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715951 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* host: make get_time() test_mockableYicheng Li2019-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | Make get_time() test_mockable so that we can: 1) make sure the unit tests are deterministic and not flaky (e.g., do not depend on system timing, context switches, timer precision) 2) don't execute longer than necessary (e.g., if for some reason we wanted to test a several second timeout we don't want to delay the unit tests) 3) verify functionality like timestamp overflow (e.g., things that are hard to test with a real clock) BRANCH=nocturne BUG=chromium:927095 TEST=make -j buildall Change-Id: Icb26617de6382e554bdfae8258a096565c8a7102 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1652627 Tested-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: Use 64-bit hardware timerJack Rosenthal2019-06-241-1/+0
| | | | | | | | | | | | | | | | ISH has native support for storing the hardware ticks in a 64-bit integer. With CONFIG_HWTIMER_64BIT, we can use this instead of relying on the periodic rollover interrupt. BUG=b:133190570,chromium:976804 BRANCH=none TEST=ran arcada_ish for more than 2³² μs, observed timer worked as normal Change-Id: I3b608c49081842f28d2ef8c16279992af1cb4fad Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1668056 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* minute-ia: add 0 error code for exceptions that do not pass oneDenis Brockus2019-06-211-15/+26
| | | | | | | | | | | | | | | | | | The errorcode is pushed to the stack by hardware for vectors 8, 10-14 and 17. The others will be missing that parameter when exception_panic is called. So make sure to push a 0 for these other exceptions to line up parameter values. BUG=b:135671664 BRANCH=none TEST=make buildall -j TEST=verify errorcode 0 on exceptions that hw does not push a value Change-Id: I7aad96278408a5e38cf973c868e05d92b52469dd Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1669884 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* minute-ia: load eip value from top of stackJack Rosenthal2019-06-193-11/+44
| | | | | | | | | | | | | | | | For interrupt vectors (as opposed to exception handlers), the eip value is on top of the stack (referentially the return address by C calling convention). Use separate code for WDT vector. BUG=b:129983997 BRANCH=none TEST='crash watchdog' showing correct EIP, CS values Change-Id: I7efb2c71aba63eefd89fc71af089bc14034b7d08 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663188 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-1958-58/+58
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ish: snowball linker cleanupDenis Brockus2019-06-181-1/+1
| | | | | | | | | | | | | | | | Change AON_ROM references to be AON_PERSISTENT, these are not readonly Use the linker to set a snowball structure in the right place so we do not have to maintain hardcoded addresses in the register file BUG=b:132690500 BRANCH=none TEST=make buildall -j and check map location of snowball to be correct Change-Id: I4983a078fbd067b9c7ec9f0c49f962a4cb1581b7 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m/ec.ld.S: Fix DRAM section layout.Yilun Lin2019-06-171-18/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL fixes DRAM section loaded at the wrong location, and also relayouts the DRAM section to have a smaller flat binary. Current DRAM region layout is as below: .dram.data LMA | LOAD .dram.data VMA | .dram.bss | NOLOAD .dram.rodata | LOAD .dram.text | LOAD This will create a flat binary file as following layout: .dram.data .dram.bss .dram.rodata .dram.text and loader will load .flat.dram to .dram.data LMA's starting section. This leads to .dram.bss, .dram.rodata and .dram.text been loaded at the wrong location, where .dram.data VMA resides. This CL fixes the issue by reorganize the sections into: .dram.text | LOAD .dram.rodata | LOAD .dram.data LMA | LOAD .dram.data VMA | .dram.bss | NOLOAD and thus we have a flat binary as: .dram.text .dram.rodata .dram.data so that: 1. everything will be placed at the correct address. 2. have a smaller flat binary. The CL also removes .dram.keep.* section, which is not used so far. BUG=b:134079593 BRANCH=master TEST=With crrev.com/c/1646691, check the output of object header: 1. SIZEOF(.dram.text + .dram.rodata + .dram.data) = SIZEOF(.image.RW.dram) 0x68 0x18 0x14 0x94 2. ADDR(.dram.data LMA) + SIZEOF(.dram.data) = ADDR(.dram.data VMA) 0x10000080 0x14 0x10000094 arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf Idx Name Size VMA LMA File off Algn 5 .dram.text 00000068 10000000 10000000 00030000 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 6 .dram.rodata 00000018 10000068 10000068 00030068 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .dram.data 00000014 10000094 10000080 00030094 2**0 CONTENTS, ALLOC, LOAD, DATA 8 .dram.bss 00000004 100000a8 100000a8 000300a8 2**0 ALLOC arm-none-eabi-objdump -h build/kukui_scp/ec.obj Idx Name Size VMA LMA File off Algn 2 .image.RW.dram 00000094 50000000 50000000 00020000 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE TEST=With crrev.com/c/1646691, see the console has correct output: dram_bss_val = 0 dram_data_val[0]= 1 dram_data_val[1]= 2 dram_data_val[2]= 3 dram_data_val[3]= 4 dram_data_val[4]= 5 dram_data_val[5]= 6 dram_data_val[6]= 7 dram_data_val[7]= 8 dram_data_val[8]= 9 dram_data_val[9]= 10 dram_data_val[10]= 11 dram_data_val[11]= 12 dram_data_val[12]= 13 dram_data_val[13]= 14 dram_data_val[14]= 15 dram_data_val[15]= 16 dram_data_val[16]= 17 dram_rodata_val[0]= 55 dram_rodata_val[1]= 56 dram_rodata_val[2]= 57 dram_rodata_val[3]= 58 dram_rodata_val[4]= 59 dram_rodata_val[5]= 60 Change-Id: Ic6836c6ad553d0ceae4d55df92caa1896fee905d Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646690 Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* ish: remove conditional compilation where possibleDenis Brockus2019-06-172-80/+78
| | | | | | | | | | | | | | | Removed many of the #if conditions and replaced them with IS_ENABLED BUG=b:132178013 BRANCH=none TEST=make buildall -j TEST=verify basic ish ec functionality Change-Id: I39c1d2dfdb39baa06e53746789d0b6a648275ed9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660021 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/cortex-m: get_interrupt_context is only used inside CONFIG_TASK_PROFILINGTom Hughes2019-06-151-0/+2
| | | | | | | | | | | | | | | | | | | | | get_interrupt_context is only called from code inside #ifdef CONFIG_TASK_PROFILING. clang emits an unused function warning for this: core/cortex-m/task.c:238:19: error: unused function 'get_interrupt_context' [-Werror,-Wunused-function] static inline int get_interrupt_context(void) BRANCH=none BUG=chromium:931797 TEST=make buildall -j Change-Id: I5ba68d1a58a966eeecb5abdb3cb87fa2684f359b Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660017 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* minute-ia: show EC task information during panicJack Rosenthal2019-06-142-4/+16
| | | | | | | | | | | | | | | | | In order to receive better debug info from panic reports, include the current task when the panic was encountered. BUG=b:134071217 BRANCH=none TEST=saw that task was "CONSOLE" when typing "crash divzero" from console Change-Id: I2fa9f931eea0274a762f812b6a7a8281cb8fcc5f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660018 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: remove panic_sw_reasons[] from panic.cDino Li2019-06-141-16/+2
| | | | | | | | | | | | | | | | | | | | | | | Because the CL:1648958 made panic_sw_reasons[] common, so we remove it to fix multiple definition error. BUG=none BRANCH=none TEST=crash console command: > crash stack ... Software panic reason: PANIC_SW_STACK_OVERFLOW Software panic info: 2 > crash assert ... Software panic reason: PANIC_SW_ASSERT Software panic info: 192 Change-Id: Ia34ae92f8b47f14040a78ae8a85bd479757f40ea Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655219 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: remove TODO from build.mkDino Li2019-06-141-4/+0
| | | | | | | | | | | | | We are able to build EC image with coreboot-sdk, so remove the TODO. BUG=b:133639441 BRANCH=none TEST=build board it83xx_evb with RISC-V core. Change-Id: I21d5aa4735f38debb180277ac1acd9f7284298d1 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655218 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m/ec.ld.S: .dram.bss section should not have LOAD attribute.Yilun Lin2019-06-121-1/+5
| | | | | | | | | | | | | | | | | | | | | .dram.bss section is like .bss section that all the contents should be initialized to zero. TEST=build a image with .dram.bss section, and verify it only has ALLOC attribute. $ arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf 7 .dram.bss 00000acb 3009aaa8 3009aaa8 0010aaa8 2**2 ALLOC BUG=b:134079593, b:122058243 BRANCH=master Change-Id: I853b2977465b83458f566c5dd953458147d4e10e Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646689 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* minute-ia: move IRQ definitions to common filesJack Rosenthal2019-06-112-25/+21
| | | | | | | | | | | | | | | | | | | | By moving the __irq_data extern declaration into link_defs.h, the struct can be used in more than just interrupts.c. In addition, this provides a common struct definiton for IRQ definitions consisting of an IRQ number, the assigned routine, and a handler function, which is a fairly common way to store IRQ definitions. BUG=none BRANCH=none TEST=arcada ISH functions as normal Change-Id: Idbb5780ae965faeade74cfe319364f61dd933d9e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1649375 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core:RISC-V / chip:IT83202Dino Li2019-06-1113-0/+1975
| | | | | | | | | | | | | | | | The IT83202 is an embedded controller with RISC-V core. It supports maximum ram size to 256KB and internal flash to 1MB. BUG=none BRANCH=none TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...) on it83202 EVB. Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* minute-ia: ish software panicDenis Brockus2019-06-112-26/+62
| | | | | | | | | | | | | | | | | | | Adding functions for software panic to ISH. This includes panic_set_reason, panic_get_reason and software_panic. Added extra output when a software panic is detected. Had to touch nds32/panic.c in order to make panic_sw_reasons common. BUG=b:134502392 BRANCH=none TEST=Verified with crash assert, with CONFIG_DEBUG_ASSERT defined Change-Id: Iebfe62a7dcd59b4bbed82b450dfd44cc8eaed1da Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1648958 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: use magic number to verify persistent dataJack Rosenthal2019-06-061-0/+4
| | | | | | | | | | | | | | | | | | | Move persistent data definitions to a structure and have linker script define the address of the symbol into the AON ROM (persistent data storage). Use the magic number "ISHd" to verify persistent data storage and copy to static memory when valid. Commit changes from the local copy during reset. BUG=b:133779707,b:133647823,b:132059981 BRANCH=none TEST=power-on is only reset flag under cold reset, panic data persists, watchdog reset produces correct reset flags, UART always printing system info on boot Change-Id: I65a458cc2656f8fe26361ef2117ceb5439edff6c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636293 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
* ish: reload watchdog after lower power exitJett Rink2019-06-052-1/+5
| | | | | | | | | | | | | | | | | | Reload the watchdog timer immediately after exiting from D0ix before re-enabling the reset of the IRQs. Also re-enable all ISRs in a batch while interrupts are disabled to limit the number of context switched if multiple interrupts are pending. BRANCH=none BUG=b:133190570 TEST=let arcada enter and exit D0i[0123] without issue for a couple of minutes. There are not adverse affects of this change. Change-Id: I3ef5878b0618a0c1858664cad061d415329d4302 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1640304 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/host/task: Add OS sleeps instead of busy-loopingNicolas Boichat2019-05-241-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running on a busy builder, fuzzing tests often time out. I suspect this is due to the fact that one of the thread is busy looping, and for some reason, does not give enough time for other threads to run. Fix the issue by using nanosleep OS call (avoiding namespace clash with msleep/usleep that are implemented differently). From the builder stack traces, we know these tests often fail in 2 busy-loops, so fix those. BRANCH=none BUG=chromium:963768 TEST=Emulate busy system with 4 cores only: taskset 0xf yes > /dev/null & (about ten times) Then run tests: while taskset 0xf build/host/usb_pd_fuzz/usb_pd_fuzz.exe \ -runs=1; do :; done => No failures after 30 minutes. Change-Id: I458ff783d166e27fb38dc33853f08e5b3acba980 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1623050 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* ish: fix reading current interrupt vectorHyungwoo Yang2019-05-161-3/+3
| | | | | | | | | | | | | | | | | When we switched to using REG32 macros for registers, we made a mistake in using address of LAPIC's ISR. The original CL that changed this was CL:1586458 BRANCH=none BUG=none TEST=Tested on Arcada platform Change-Id: Ia64806a4cb0fa5d150b41407b0f6c9f34f0168e8 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1611746 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: fix lapic table readJett Rink2019-05-141-4/+8
| | | | | | | | | | | | | | | | | When we switched to using REG32 macros for registers, we also changed the math for the offset of the lapic. Fixing the pointer math. The original CL that changed this was CL:1586458 BRANCH=ish BUG=none TEST=ISH runs normally Change-Id: I1beea99ede496a2eee2adf96adeec21b3f1e1fd4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1600158 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ish: combine watchdog expiration and panic handlerJack Rosenthal2019-05-092-10/+30
| | | | | | | | | | | | | | | | | | watchdog_warning implements similar functionality to exception_panic, but worse, as the value it prints for EIP is wrong, and it does not have the no-double-panic logic of the panic handler. This commit removes watchdog_warning and integrates the relevant functionality into exception_panic. BUG=b:129983997 BRANCH=none TEST=observed watchdog reset with 'waitms 10500' Change-Id: I78375337aa85be5424850e29a8204c409384d019 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1599732 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* USB-PD: Add hook for PD connect eventDaisuke Nojiri2019-05-085-3/+23
| | | | | | | | | | | | | | | | This patch adds a hook for USB PD connect event. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/127228934 BRANCH=none TEST=buildall. Verify a hook is called on BC12 charger connection. Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3 Reviewed-on: https://chromium-review.googlesource.com/1597794 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/ec.lds.S: Workaround for ld not complaining LMA overlapping.Yilun Lin2019-05-071-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ld won't complain .data LMA overlapping if using a computed LMA address. This CL workaround this by assigning a load memory region. Related discussion: https://github.com/rust-embedded/cortex-m-rt/issues/86 TEST=make buildall -j TEST=cherry-pick https://crrev.com/c/1592972 make BOARD=kukui_scp -j and see it ld reports failure for LMA overlapping: build/kukui_scp/RW/ec.RW.elf section `.data' will not fit in region `IROM' region `IROM' overflowed by 3784 bytes TEST=w/o this CL; make buildall -j; cp -r build build.old w/ this CL; comment out EC version rules #.PHONY: $(out)/ec_version.h make buildall -j compares the .flat files by: for f in $(ls build/*/*/ec.*.flat | sed -e 's|build/||'); do echo "###### diff ${f}" diff <(xxd build/${f}) <(xxd build.old/${f}) done and see that all the .flat are the same, except that some boards(aquila, arcadia, cr5*, granite, haven_dev, hg_*, hotelgolf, hslt_*, indus, proto2, red, starcard, tk-x001) using g-chip have different content at addr 0x0~0x360 (related to regen key?), and this change is not likely to touch that address. BUG=b:131641213 BRANCH=None Change-Id: I54c697669ef3836c93027bce90f507c33283c6f3 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1588297 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: preserve panic data across resetJack Rosenthal2019-05-041-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit stores panic data across reset by storing panic data in the last 256 bytes of AON memory (before AON ROM). > crash divzero ========== PANIC ========== Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E Resetting system... =========================== ... ISH reset ... > panicinfo Saved panic data: (NEW) Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E BUG=b:129425206 BRANCH=none TEST=see console output above (on arcada_ish) Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1593418 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/minute-ia: link libgcc for 64bit divisionYangzhong Ge2019-05-021-0/+3
| | | | | | | | | | | | | | | | | | | | | libgcc provides 64bit division operation functions for 32bit arch, such as '__udivdi3', link libgcc for general 64bit division on ish. please note for critical performance required case, do not use these functions from libgcc. examples: scale_us2ticks() in chip/ish/hwtimer.c BRANCH=none BUG=b:131590864 TEST=tested on arcada platform Change-Id: I554e4c79f017e098ab83972928376f82fe7b92d1 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1587396 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-022-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* ish: move REG32 macros for interrupt control into header filesJack Rosenthal2019-05-013-37/+38
| | | | | | | | | | | | | | | This is a good portion of the fixes needed for b:130573158, but we still have the HECI registers to deal with. I have those in a separate CL as they were giving me a significant amount of trouble. BUG=b:130573158 BRANCH=none TEST=arcada_ish is functioning as normal after changes Change-Id: I9c209a329d61f7f55c260006cdffbfc705521195 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1586458 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: fix s/w generated interrupt requestHyungwoo Yang2019-04-266-131/+177
| | | | | | | | | | | | | | | | | Current s/w generated IRQ uses LAPIC's ICR but it causes pending interrupts for other IRQs in IOAPIC and leads LVT error with illegal vector. So instead of using ICR, we use "int" instruction. BRANCH=none BUG=b:129937881,b:124128140 TEST=Tested on Arcada platform Change-Id: I49c4120e7355f9a98d20d5ed259c4fdf6bad5196 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1568786 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* minute-ia: hard reset if we panic while handling a panicJack Rosenthal2019-04-241-3/+19
| | | | | | | | | | | | | | | | | ish_pm_reset is a rather complex procedure, and encountering a panic while it is happening could lead to an infinte loop of handling panics. This will preform a reset of the Minute-IA core if a panic occurs and the system is already resetting from panic. BUG=b:130752748,b:130587334 BRANCH=none TEST=copied some invalid opcodes into switch_to_aontask procedure, observed the hard reset after forcing a panic Change-Id: I43459d78da9b67297f84e3a736d3f92da42a814c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576835 Reviewed-by: Jett Rink <jettrink@chromium.org>
* minute-ia: remove divzero console commandJack Rosenthal2019-04-241-10/+0
| | | | | | | | | | | | | | I had forgotten to remove this from testing the panic handler. This is a duplicate command of "crash divzero" and should be removed. BUG=b:126691187 BRANCH=none TEST=divzero console command is gone on arcada Change-Id: Id37d3f3749bd4228045cca93a38315ee9c94b2e9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576837 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish/ish5: fix high frequent wakeup issue in low power modeHu, Hebo2019-04-201-0/+1
| | | | | | | | | | | | | | | | | | | | on ish, need fw clean fabric agent error status, otherwise will cause ish wakeup immediately after entered low power mode. this operaion has no impact for other functions. BUG=b:130193448 BRANCH=none TEST=verified on arcada platform Change-Id: Iecd85d1ab037aafa988d6c32ad47b51003913198 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1563470 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish: remove scan ISR registers IRQ handlingHyungwoo Yang2019-04-193-14/+13
| | | | | | | | | | | | | | | Currently we can LAPIC's ISR registers to find vector number but it's already know to the IRQ handler. BRANCH=none BUG=none TEST=Tested on Arcada platform Change-Id: If6626eee0b2548eb26d15cf97b220403b6afcfdb Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1573203 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: fix task_start_called()Hyungwoo Yang2019-04-191-2/+2
| | | | | | | | | | | | | | | | Variable "start_called" is never updated due to bug in __task_start. this patch fixes the bug. BRANCH=none BUG=none TEST=Tested on Arcada platform Change-Id: Icdea8adf5a06c891188fc84bc49cb643a7e009ec Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1570150 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: add missing EOI in LAPIC error irq handlerLeifu Zhao2019-04-171-6/+16
| | | | | | | | | | | | | | | | | The LAPIC LVT error irq handler missed EOI to LAPIC at the end of the handler. BUG=b:129937881 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I890271729c5ab1d622016c32e83a8068914f69de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1567105 Tested-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* ish: add temporary workaround for lost interruptJett Rink2019-04-121-7/+12
| | | | | | | | | | | | | | | | | While we figure out how to fix the root cause for missing interrupts, we can at least get ourselves out of the back scenario by proactively checking if there is a pending IOAPIC interrupt that the LAPIC does not know about. BRANCH=none BUG=b:129937881 TEST=ISH communication does not permanently lock up Change-Id: I766b2764748ae85b17992b3c0020ba7fb4e11693 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1566472 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish/ish5: implement reset, reset_prep and D3 flowHu, Hebo2019-04-081-0/+8
| | | | | | | | | | | | | | | | | 1: reset and reset_prep implemented 2: D3 flow implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Ie6bacd89e2363578d85157dfb1dd8b56e2828d05 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1536486 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power mode (D0i1-3)Hu, Hebo2019-04-082-1/+14
| | | | | | | | | | | | | | | | | 1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented 2: D0i3 (TCG + SRAM power off) implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531772 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power management frameworkHu, Hebo2019-04-083-0/+72
| | | | | | | | | | | | | | | | | | | | | AON PM framework including: 1: AON task skeleton 2: task switching between main FW and AON task 3: 'idlestats' console command for D0ix statistic information 4: D0ix entrance in idle task BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1510518 Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* minute-ia: clean up comments about ISR=0 bugJack Rosenthal2019-04-042-10/+8
| | | | | | | | | | | | | | According to Intel, ISR=0 is actually the intended behavior, so these scary comments linking to buganizer can be cleaned up. BUG=b:28444630 BRANCH=none TEST=make buildall -j Change-Id: I877556f1719826cb72eee39e4d14e2c10412c7a9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1550706 Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* arcada_ish: ensure tests target buildsJett Rink2019-04-031-0/+7
| | | | | | | | | | | | | | | | Fix the test target for ish which is run during the test phase of chromeos-ish which is not run under buildall in EC codebase. BRANCH=none BUG=b:12237171 TEST=make BOARD=arcada_ish tests builds successfully. FEATURES=test emerge-sarien chromeos-ish now works Change-Id: I6eeaa7a15a5a026b189b67d54f28d994e6a56bb7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548503 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/minute-ia: add IA32/x86 arch related data structure definitionsHu, Hebo2019-04-024-68/+204
| | | | | | | | | | | | | | | | | includes GDT, LDT, IDT, and TSS tables data structures definitions BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I2e9fea21501a16485fbc4e05163c1f2ffbbc17f4 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531275 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* it83xx/i2cs: add i2c slave functiontim2019-03-301-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | The I2C function of IT8320 is used as the slave. The slave channel A can support 16-byte FIFO for read and write data. The enhanced I2C channel D, E and F can support read and write 256-byte data by DMA mode. When master transmits data to slave, the interrupt signal will generate, and the data will be saved to buffer. BUG=none BRANCH=none TEST=none Change-Id: I167215352119ec11dfd96eb1f33abc1e2111dead Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1488273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* mt_scp: Support ROM section on internal SRAM.Yilun Lin2019-03-271-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, kukui_scp's memory layout interleaves with RO and RW sections. This complicates the MPU region configuration, and it even unconfigurable. This CL propose to simplify the layout and configuration by introducing an IROM region, and re-layout the memory. New layout would be: ---------------------------- 0x0 RO| .stepping_stone | .text .rodata .data LMA ---------------------------- 0x100000 RW| .bss .data stack | ipi shared buffer ---------------------------- 0x7C0000 BRANCH=None BUG=b:123269246 TEST=1. w/o this CL: make buildall -j; mv build build.old 2. w/ this CL: make buildall -j; 3. compare smap by: ls build/*/*/ec.*.smap | \ sed -e 's|build/||' | \ xargs -I{} diff build/{} build.old/{} and sees that only kukui_scp's smap changed. Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530263 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: Add watchdog timerJack Rosenthal2019-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | This adds support for the watchdog timer (WDT) available on Intel Sensor Hub (ISH). The ISH will reset after T1 expires; see the comments at the top of watchdog.c for further information on this design decision. Originally, we had planned to implement a counter that would disable the WDT after N failures. This was abandoned, since the register used to store the counter was not able to maintain a value across reset on a reliable basis (see b:128679825). BUG=b:127980538,b:128679825 BRANCH=none TEST=Used waitms command on arcada to verify WDT triggered a warning IRQ after T1 and reset the system. Change-Id: I4bd16c253110d60c57eb24cda2abc0facee20748 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1526316 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
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