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* cr50: fix annoying LD warningsVadim Bendebury2018-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | The compiler marks data put into the TPM2_common.bss section as PROGBITS, which the linker does not like. Changing the section name prevents the marking and keeps linker happy. BRANCH=cr50 BUG=chromium:799385 TEST=verified that local_state is still in where it belongs: $ egrep '(local_state|__bss_libtpm2)' build/cr50/RW/ec.RW.smap 00010400 B __bss_libtpm2_start 00015d0c b local_state 00015d18 B __bss_libtpm2_end Change-Id: I48f7d2cb08c7ccb2ef3b3159eaf4d66e2b8720b4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/852793 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 57bb4ddf4163dbe3da48ba56464adbabfa596344) Reviewed-on: https://chromium-review.googlesource.com/896753
* tpm2: add nvmem data to the right segmentVadim Bendebury2017-10-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Modules in board/cr50/tpm2 are part of the TPM task, and their .bss segment needs to be wiped out along with other TPM modules' when TPM is reset. The only module from this directory which has static variables is NVMem.c. This patch groups the variables into a structure, and makes sure that the structure is stored in the part of .bss which is zeroed when TPM is reset. BRANCH=none BUG=none TEST=verified that TPM wipeout happening during RMA reset is successful. Change-Id: I5f80dc5e4f5f7cdce2d1a1ed59e0fbac354c5bf6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733814 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> (cherry picked from commit 6b516eda69f92cbc9f06b33cdf2c34cf1114ca16) Reviewed-on: https://chromium-review.googlesource.com/736811
* core/cortex-m0/curve25519: Integrate fast curve25519 implementationNicolas Boichat2017-10-246-0/+3360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move generic implementation to curve25519-generic.o - Always use optimized version on cortex-m0. - Rename .s files to .S, remove unnecessary lines in assembly files. - Rename crypto_scalarmult_curve25519 to x25519_scalar_mult to match the signature provided by the generic implementation. - Replace some handcoded memcpy with function calls - Remove unnecessary "volatile" specifications in the code. Conflicts: common/build.mk core/cortex-m0/curve25519/mpy121666.S core/cortex-m0/curve25519/mul.S core/cortex-m0/curve25519/reduce25519.S core/cortex-m0/curve25519/scalarmult.c core/cortex-m0/curve25519/sqr.S BRANCH=none BUG=b:62813194 TEST=To test old implementation only: - Increase CONFIG_RO_SIZE to 60kb - Increase console stack size to 2048 make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, taskinfo => Used to takes ~4'17" to run (X25519 duration 256347 us). 1496/2048 stack size usage in CONSOLE task => Now takes ~1'25" to run (X25519 duration 84520 us) 732/2048 stack size usage in CONSOLE task TEST=In test/x25519.c, uncomment #define TEST_X25519_1M_ITERATIONS make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, wait ~23 hours, test passes. TEST=- Define CONFIG_CURVE25519_CORTEXM0 (next patch) makes newsizes build/hammer/RW/ec.RW.flat shrank by 1888 bytes: (52208 to 50320) Change-Id: Icce38d3c32f431a85ac0f951cf34456b490dc665 Reviewed-on: https://chromium-review.googlesource.com/540962 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit edc668ea6cca1d4f3e53c211406d6a8bf5fe6364) Reviewed-on: https://chromium-review.googlesource.com/734797 Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. Conflicts: chip/npcx/build.mk BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 0898c7a63a4ccb0f11c1c61bb085d8d062f664ab) Reviewed-on: https://chromium-review.googlesource.com/660892 Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Clean up CONFIG_CASE_CLOSED_DEBUG usageRandall Spangler2017-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1. All boards which use chip/g either use both CONFIG_USB_SERIALNO and CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on CONFIG_USB_SERIALNO. This is in preparation for making common/case_closed_debug refer only to the usb_pd_protocol version (with mode=disabled/partial/enabled), and cr50 will have its own version (with only enabled/disabled, and tied more closely to CCD config). No functionality changes. BUG=none BRANCH=cr50 TEST=make buildall -j; boot cr50 and see change hook called Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648067 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 29d8cc67c35c0e8d17400202fb548707bf448218) Reviewed-on: https://chromium-review.googlesource.com/656420 Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-08-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 4809c70bbea8743cc7c1d382d7510ed937dce914) Reviewed-on: https://chromium-review.googlesource.com/598518 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* Allow core code to request its cross compilerPatrick Georgi2017-08-044-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of having to pass in both the board and the arch used there (which might be complicated in the light of different ECs with different arches), allow passing in the board and a set of cross compilers. The core/*/build.mk then pick the compiler that is responsible for them. The current method works just the same: If you've already set CROSS_COMPILE, no override happens. If you set neither CROSS_COMPILE nor CROSS_COMPILE_$arch, the same default as before this CL is set. BUG=none BRANCH=none TEST=emerge-{samus,kevin} chromeos-ec behave reasonably with adapted ebuild Change-Id: Icf1866f296412dd92ecfe134394224c49f7c3df5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/549344 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 1a67ac2ad6a6c0eedaa672f7856e38fb5abf1ede) Reviewed-on: https://chromium-review.googlesource.com/598516 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* task: Wait for HOOK_INIT completion before scheduling tasksShawn Nematbakhsh2017-06-305-20/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until HOOK_INIT has completed, do not allow any tasks other than HOOKS or IDLE to be scheduled. Programmers often make the assumption that a HOOK_INIT function is guaranteed to be run before task code that depends on it, so let's make it so. BUG=chromium:649398 BRANCH=None TEST=Manual on kevin, compare boot without patch: ... [0.004 power state 0 = G3, in 0x0008] <-- from chipset task RTC: 0x00000000 (0.00 s) [0.004 power state 4 = G3->S5, in 0x0008] RTC: 0x00000000 (0.00 s) [0.005 clear MKBP fifo] [0.006 clear MKBP fifo] [0.006 KB init state: ... <-- from keyscan task [0.012 SW 0x05] [0.155 hash start 0x00020000 0x00019a38] [0.158 HOOK_INIT DONE!] ... to boot with patch: ... RTC: 0x58cc614c (1489789260.00 s) [0.004 clear MKBP fifo] [0.005 clear MKBP fifo] [0.010 SW 0x05] [0.155 hash start 0x00020000 0x000198e0] [0.157 HOOK_INIT DONE!] ... Also, verify kevin boots to OS and is generally functional through sysjump and basic tasks, and verify elm (stm32f0 / cortex-m0) boots. Change-Id: If56fab05ce9b9650feb93c5cfc2d084aa281e622 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/456628 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 8a16e6483ab80a85af44e8ba164e5e91a51ec43a) Reviewed-on: https://chromium-review.googlesource.com/556236 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-06-303-3/+3
| | | | | | | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 629c3964a2bd8a92d61daaef633fc0cc5e65bc10) Reviewed-on: https://chromium-review.googlesource.com/556189 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* system: Use stored size in image_data for determining image_usedShawn Nematbakhsh2017-06-303-27/+2
| | | | | | | | | | | | | | | | | | | | | | | Image used size is now part of the image_data struct present in all images at a fixed offset, so use it rather than scanning from the end of the image. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns the same value as the old implementation, for both RO and RW images. BRANCH=None Change-Id: I35f0aa87f5ab1371dbd8b132f22b9d0044358223 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450859 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit e025e17b3341cd20cebe721ce2d70d2d69d2d5ce) Reviewed-on: https://chromium-review.googlesource.com/556181 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* version: Store image size data in version structShawn Nematbakhsh2017-06-063-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Store our image size (known at build time) in our version struct (now renamed to image_data). This will allow us to more efficiently determine the size of an image in a follow-up CL. Note that compatibility is broken for old ROs that do not include this CL. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that stored image size matches output of system_get_image_used() for both RO and RW images. BRANCH=None Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450858 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 3c4c83b8c3ec35af3a7ba19116e8467e9a09cc80) Reviewed-on: https://chromium-review.googlesource.com/526381 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Remove charge_state_v1Sam Hurst2017-02-065-20/+0
| | | | | | | | | | | | | | | | All boards have been transitioned to charge_state_v2.c So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and CONFIG_CHARGER_TIMEOUT_HOURS can be removed BUG=chrome-os-partner:36272 TEST=make -j buildall BRANCH=none Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a Reviewed-on: https://chromium-review.googlesource.com/435467 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Revert "version: Store image size data in version struct"Vadim Bendebury2017-02-013-11/+3
| | | | | | | | | | | | | This is a dependency of the uderlyaing patch which breaks header composition of g chip based boards. This reverts commit 7cbb815732d7434f5985d3b50a869aa71ba5c507. Change-Id: I4d94647cf5cb09fd338e5a581c956df6b5d83081 Reviewed-on: https://chromium-review.googlesource.com/435551 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* Revert "system: Use stored size in image_data for determining image_used"Vadim Bendebury2017-02-013-1/+27
| | | | | | | | | | | | This breaks header composition of g chip based boards. This reverts commit 93951a491dd00e20addc1ff99c2896bb9752e665. Change-Id: Ia52cf1d9c56fbb588317cec73487b2c9e89b7234 Reviewed-on: https://chromium-review.googlesource.com/435550 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* system: Use stored size in image_data for determining image_usedShawn Nematbakhsh2017-01-303-27/+1
| | | | | | | | | | | | | | | | | | | Image used size is now part of the image_data struct present in all images at a fixed offset, so use it rather than scanning from the end of the image. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns the same value as the old implementation, for both RO and RW images. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic8db5c706d82f7ca2ded2e90129747e7fbefdb38 Reviewed-on: https://chromium-review.googlesource.com/427959 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* version: Store image size data in version structShawn Nematbakhsh2017-01-303-3/+11
| | | | | | | | | | | | | | | | | | | | | Store our image size (known at build time) in our version struct (now renamed to image_data). This will allow us to more efficiently determine the size of an image in a follow-up CL. Note that compatibility is broken for old ROs that do not include this CL. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that stored image size matches output of system_get_image_used() for both RO and RW images. BRANCH=None Change-Id: I49ea5fc27a7f11f66daba485a87d0dfe7d0c770f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/427408 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: Add fabsf and sqrtf functionDino Li2017-01-183-1/+131
| | | | | | | | | | | | | | | | | | | | | | | | The magnetometer online calibration requires these two functions and taken from newlib. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=fabsf(): fabsf(1.23) = 1.23 fabsf(-1.23) = 1.23 sqrtf(): sqrtf(4.56) = 2.135 sqrtf(0.123) = 0.350 sqrtf(-0.123) = an exception is triggered. Change-Id: I808ca7f1bd03c6d6c1b32861ede4ecbfeeaa3da6 Reviewed-on: https://chromium-review.googlesource.com/429730 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ISH: Added UART Rx/Tx interrupt modeKyoung Kim2017-01-111-0/+1
| | | | | | | | | | | | | | | | | Added UART Tx/Rx interrupt mode related code. BUG=None BRANCH=None TEST=On ISH enabled Reef board, check if Tx message is working and tested Rx input from console with console command. Change-Id: I5067304dc74abc29bbbea983b22db3e193e36e6b Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/424322 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* minute-ia: fix floating point inline assemblyKyoung Kim2017-01-091-6/+8
| | | | | | | | | | | | | | | | | | | | change inline assembly for fsqrt and fabs BUG=none BRANCH=None TEST=`make buildall -j` 1. Compare sqareroot(2) from calculator and from sqrtf(2.0f) by multiplying 1.0 x 10E8 for both values to convert int32_t and check the difference. 2. read timestampt before and after 'sqrtf()' and calculate execution time. Change-Id: I62694d8b084a3a74040dc298354b4fd685e77729 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/404927 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* iec: Improve efficiency of host command dispatcherSam Hurst2017-01-065-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use binary search in host command lookup dispatcher BUG=chromium:570895 TEST=manual testing on kevin - Kevin boots - ectool hello make buildall -j Verify *.smap hcmds section is sorted: BOARD with host commands and private host commands 0004d0ec R __hcmds 0004d0ec R __host_cmd_0x00000x0000 0004d0f8 R __host_cmd_0x00000x0001 0004d104 R __host_cmd_0x00000x0002 0004d110 R __host_cmd_0x00000x0003 0004d11c R __host_cmd_0x00000x0004 0004d128 R __host_cmd_0x00000x0005 0004d134 R __host_cmd_0x00000x0007 0004d140 R __host_cmd_0x00000x0008 0004d14c R __host_cmd_0x00000x000a 0004d158 R __host_cmd_0x00000x000d 0004d164 R __host_cmd_0x00000x0010 0004d170 R __host_cmd_0x00000x0011 0004d17c R __host_cmd_0x00000x0012 0004d188 R __host_cmd_0x00000x0013 0004d194 R __host_cmd_0x00000x0015 0004d1a0 R __host_cmd_0x00000x0016 0004d1ac R __host_cmd_0x00000x0017 0004d1b8 R __host_cmd_0x00000x0087 0004d1c4 R __host_cmd_0x00000x008c 0004d1d0 R __host_cmd_0x00000x008f 0004d1dc R __host_cmd_0x00000x0092 0004d1e8 R __host_cmd_0x00000x0093 0004d1f4 R __host_cmd_0x00000x0097 0004d200 R __host_cmd_0x00000x0098 0004d20c R __host_cmd_0x00000x00b6 0004d218 R __host_cmd_0x00000x00d2 0004d224 R __host_cmd_0x00000x00d3 0004d230 R __host_cmd_0x3E000x0000 0004d23c R __host_cmd_0x3E000x0002 0004d248 R __evt_src_EC_MKBP_EVENT_HOST_EVENT 0004d248 R __hcmds_end BOARD with host commands only 100bc888 R __hcmds 100bc888 R __host_cmd_0x00000x0000 100bc894 R __host_cmd_0x00000x0001 100bc8a0 R __host_cmd_0x00000x0002 100bc8ac R __host_cmd_0x00000x0003 100bc8b8 R __host_cmd_0x00000x0004 100bc8c4 R __host_cmd_0x00000x0005 100bc8d0 R __host_cmd_0x00000x0006 100bc8dc R __host_cmd_0x00000x0007 100bc8e8 R __host_cmd_0x00000x0008 100bc8f4 R __host_cmd_0x00000x0009 100bc900 R __host_cmd_0x00000x000a 100bc90c R __host_cmd_0x00000x000b 100bc918 R __host_cmd_0x00000x000d 100bc924 R __host_cmd_0x00000x0010 100bc930 R __host_cmd_0x00000x0011 100bc93c R __host_cmd_0x00000x0012 100bc948 R __host_cmd_0x00000x0013 100bc954 R __host_cmd_0x00000x0015 100bc960 R __host_cmd_0x00000x0016 100bc96c R __host_cmd_0x00000x0017 100bc978 R __host_cmd_0x00000x0025 100bc984 R __host_cmd_0x00000x0026 100bc990 R __host_cmd_0x00000x0029 100bc99c R __host_cmd_0x00000x002a 100bc9a8 R __host_cmd_0x00000x002b 100bc9b4 R __host_cmd_0x00000x002c 100bc9c0 R __host_cmd_0x00000x0044 100bc9cc R __host_cmd_0x00000x0045 100bc9d8 R __host_cmd_0x00000x0046 100bc9e4 R __host_cmd_0x00000x0047 100bc9f0 R __host_cmd_0x00000x0061 100bc9fc R __host_cmd_0x00000x0062 100bca08 R __host_cmd_0x00000x0064 100bca14 R __host_cmd_0x00000x0065 100bca20 R __host_cmd_0x00000x0067 100bca2c R __host_cmd_0x00000x0087 100bca38 R __host_cmd_0x00000x008c 100bca44 R __host_cmd_0x00000x008d 100bca50 R __host_cmd_0x00000x008f 100bca5c R __host_cmd_0x00000x0092 100bca68 R __host_cmd_0x00000x0093 100bca74 R __host_cmd_0x00000x0096 100bca80 R __host_cmd_0x00000x0097 100bca8c R __host_cmd_0x00000x0098 100bca98 R __host_cmd_0x00000x0099 100bcaa4 R __host_cmd_0x00000x009e 100bcab0 R __host_cmd_0x00000x00a0 100bcabc R __host_cmd_0x00000x00a1 100bcac8 R __host_cmd_0x00000x00a8 100bcad4 R __host_cmd_0x00000x00a9 100bcae0 R __host_cmd_0x00000x00b6 100bcaec R __host_cmd_0x00000x00b7 100bcaf8 R __host_cmd_0x00000x00d2 100bcb04 R __host_cmd_0x00000x00d3 100bcb10 R __host_cmd_0x00000x00db 100bcb1c R __host_cmd_0x00000x0101 100bcb28 R __host_cmd_0x00000x0102 100bcb34 R __host_cmd_0x00000x0103 100bcb40 R __host_cmd_0x00000x0104 100bcb4c R __host_cmd_0x00000x0110 100bcb58 R __host_cmd_0x00000x0111 100bcb64 R __host_cmd_0x00000x0112 100bcb70 R __host_cmd_0x00000x0113 100bcb7c R __host_cmd_0x00000x0114 100bcb88 R __host_cmd_0x00000x0115 100bcb94 R __host_cmd_0x00000x0116 100bcba0 R __host_cmd_0x00000x0117 100bcbac R __host_cmd_0x00000x0118 100bcbb8 R __host_cmd_0x00000x011a 100bcbc4 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX 100bcbc4 R __hcmds_end BRANCH=none Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb Reviewed-on: https://chromium-review.googlesource.com/419702 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* nds32: lds: reduce gap of flashDino Li2017-01-052-23/+31
| | | | | | | | | | | | | | | | | | | | | - Before the change was made, the "__ro_end" was at 00013520h. We change to 00012760h. - Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE" this is because we don't support reconfiguration at board-level. - Put some task functions into "__ram_code" section to fill the gap and improving performance of code-fetch. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console commands: flasherase, flashwrite, and flashread. Change-Id: I2f2906a2a0b6971aadd00120c282801161447808 Reviewed-on: https://chromium-review.googlesource.com/424248 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* core: Fix bug will cause tasks sleep forever by mutex_unlock in task.c.Mulin Chao2017-01-052-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there's a task switching occurred between loading waiter and unlocking the lock, the task with higher priority won't wake up since the local variable, waiter, doesn't contain its ID bit before task switching. In this situation, the higher priority task only can be awakened when the other tasks execute mutex_unlock() again. But consider the following conditions: (For example, the driver of charger bd9995x.) 1. There are more than one mutex for the usage path of i2c port. 2. There are more than one task access this usage path of i2c port and one of these tasks, task A, met the situation above. 3. The other tasks have no chance to execute mutex_unlock() of i2c since the task A still occupied the mutex of charger. All the tasks used the same i2c port or the other hardware will sleep forever. This CL makes loading waiter and unlocking the lock as atomic to solve this issue. BRANCH=none BUG=chrome-os-partner:60617 TEST=make BOARD=snappy; make BOARD=oak; Executed charger factory test on 4 units of snappy for 3 days and no symptom occurred. Change-Id: Id976fc47955b33ca83bb2182b197d9f2781c341b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/423285 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nds32: pre-fix for the latest official toolchainDino Li2016-12-202-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the latest nde32 official toolchain to verify the bug of GP-related instruction was fixed (we can remove "-mno-gp-direct" flag to save code space), and code optimization. We got some error on official toolchain, so we fix them as well: - "break" instead of "trap". N8 CPU does not support "trap" instruction to generate an unconditional trap exception, but no error occurred while compiling by using current GCC toolchain (this will trigger a reserved instruction exception, so "ASSERT()" still work). We use "break" to generate a exception in this change. - "li" instead of "la". To fix the error: "Error: la must use with symbol". Also fix: - The "_bss_start" has to be word-aligned because we use "lwi" instruction to load a word from the memory into the general register. BRANCH=none BUG=none TEST=1. console command "crash assert". 2. check registers settings: f02030h, f0203eh, and f02044h. Change-Id: I33404a1d60eeebfa135bf43d3a7d5e73ab35c678 Reviewed-on: https://chromium-review.googlesource.com/422608 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "ec: Improve efficiency of host command dispatcher"Vadim Bendebury2016-11-265-5/+5
| | | | | | | | | | | | | | This reverts commit c459c8278ed2dc84100693eab93389a0df9429bd as the fix is not straightforwad, some host command codes in private repos are expressed using C preprecessor which breaks the assumption of this patch that all host commands are expressed as four digit hex numbers. Change-Id: I922de9ae8dbab6eef048463c5c09b1f338152083 Reviewed-on: https://chromium-review.googlesource.com/414492 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* ec: Improve efficiency of host command dispatcherSam Hurst2016-11-235-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use binary search in host command lookup dispatcher BUG=chrome-os-partner:570895 TEST=manual testing on kevin - Kevin boots - ectool hello make buildall -j Verify *.smap hcmds section is sorted: 100bca94 R __hcmds 100bca94 R __host_cmd_0x0000 100bcaa0 R __host_cmd_0x0001 100bcaac R __host_cmd_0x0002 100bcab8 R __host_cmd_0x0003 100bcac4 R __host_cmd_0x0004 100bcad0 R __host_cmd_0x0005 100bcadc R __host_cmd_0x0006 100bcae8 R __host_cmd_0x0007 100bcaf4 R __host_cmd_0x0008 100bcb00 R __host_cmd_0x0009 100bcb0c R __host_cmd_0x000a 100bcb18 R __host_cmd_0x000b 100bcb24 R __host_cmd_0x000d 100bcb30 R __host_cmd_0x0010 100bcb3c R __host_cmd_0x0011 100bcb48 R __host_cmd_0x0012 100bcb54 R __host_cmd_0x0013 100bcb60 R __host_cmd_0x0015 100bcb6c R __host_cmd_0x0016 100bcb78 R __host_cmd_0x0017 100bcb84 R __host_cmd_0x0025 100bcb90 R __host_cmd_0x0026 100bcb9c R __host_cmd_0x0029 100bcba8 R __host_cmd_0x002a 100bcbb4 R __host_cmd_0x002b 100bcbc0 R __host_cmd_0x002c 100bcbcc R __host_cmd_0x0044 100bcbd8 R __host_cmd_0x0045 100bcbe4 R __host_cmd_0x0046 100bcbf0 R __host_cmd_0x0047 100bcbfc R __host_cmd_0x0061 100bcc08 R __host_cmd_0x0062 100bcc14 R __host_cmd_0x0064 100bcc20 R __host_cmd_0x0065 100bcc2c R __host_cmd_0x0067 100bcc38 R __host_cmd_0x0087 100bcc44 R __host_cmd_0x008c 100bcc50 R __host_cmd_0x008d 100bcc5c R __host_cmd_0x008f 100bcc68 R __host_cmd_0x0092 100bcc74 R __host_cmd_0x0093 100bcc80 R __host_cmd_0x0096 100bcc8c R __host_cmd_0x0097 100bcc98 R __host_cmd_0x0098 100bcca4 R __host_cmd_0x0099 100bccb0 R __host_cmd_0x009e 100bccbc R __host_cmd_0x00a0 100bccc8 R __host_cmd_0x00a1 100bccd4 R __host_cmd_0x00a8 100bcce0 R __host_cmd_0x00a9 100bccec R __host_cmd_0x00b6 100bccf8 R __host_cmd_0x00b7 100bcd04 R __host_cmd_0x00d2 100bcd10 R __host_cmd_0x00d3 100bcd1c R __host_cmd_0x00db 100bcd28 R __host_cmd_0x0101 100bcd34 R __host_cmd_0x0102 100bcd40 R __host_cmd_0x0103 100bcd4c R __host_cmd_0x0104 100bcd58 R __host_cmd_0x0110 100bcd64 R __host_cmd_0x0111 100bcd70 R __host_cmd_0x0112 100bcd7c R __host_cmd_0x0113 100bcd88 R __host_cmd_0x0114 100bcd94 R __host_cmd_0x0115 100bcda0 R __host_cmd_0x0116 100bcdac R __host_cmd_0x0117 100bcdb8 R __host_cmd_0x0118 100bcdc4 R __host_cmd_0x011a 100bcdd0 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX 100bcdd0 R __hcmds_end BRANCH=none Change-Id: Ideb9951b318763f71915e2c4e5052f4b4bfab173 Reviewed-on: https://chromium-review.googlesource.com/405528 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ISH: set toolchain in core/minute-iali feng2016-11-211-3/+3
| | | | | | | | | | | | | | | | | | | When "make buildall" has board which uses core/minute-ia, CROSS_COMPILE?=i686-pc-linux-gnu- doesn't get set unless CROSS_COMPILE is not defined; however, it's defined before this line, and wrong toolchain is used. Remove "?" to set correct CROSS_COMPILE. BUG=none BRANCH=none TEST='make buildall -j' passed Change-Id: Ied4a9f93a4d44714c012d3a3e50e4a34f41a7c1f Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410402 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-154-5/+5
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* minute-ia: Revise macros to be version independentJaiber John2016-11-042-8/+8
| | | | | | | | | | | | | | | | | | | A few macros that were defined for ISH3.0 were renamed to be generic for all ISH generations - e.g, ISH30_I2C0_IRQ -> ISH_I2C0_IRQ. Similarly macros representing base addresses were revised to add ISH_ prefix. BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: Idf6657a112b9bd0f73a77f13d02e327c10a9a272 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Reviewed-on: https://chromium-review.googlesource.com/403550 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Jaiber J John <jaiber.j.john@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Jaiber J John <jaiber.j.john@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fix bugs.Marius Schilder2016-11-021-30/+30
| | | | | | | | | | | | | | | | | | | | L_fallback_32bits: section did not compute remainder correctly. L_sub_loop1: section did not track r6 correctly. Also correctly annotate which instructions need to set the flags. BRANCH=none BUG=none TEST=now passes the tests in http://www.hackersdelight.org/hdcodetxt/divmnu64.c.txt Change-Id: Ib55a3bbbcee35c7f21dc67f51038783ea1d26f6c Reviewed-on: https://chromium-review.googlesource.com/396397 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* task: Don't propagate TASK_EVENT_TIMER between between waitsShawn Nematbakhsh2016-10-264-4/+16
| | | | | | | | | | | | | | | | | | | | In __wait_evt(), if a timer expiration occurs after we read event status, before the timer is canceled, then TASK_EVENT_TIMER will be propagated to the next task wait, likely leading to premature timeout. Prevent this by clearing TASK_EVENT_TIMER after canceling our timer. BUG=chrome-os-partner:58658 BRANCH=gru TEST=Manual on gru, run 'pd # hard' for 12 hours with charger attached, verify no TCPC I2C read errors occur. Change-Id: Iac2f05a768b4ef29f82e7c3eb899f4c7dd5c3744 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400968 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: Add mostly-synchronous tpm_reset() function.Bill Richardson2016-09-241-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reset the TPM task, we send it an event so that it will reset only when it's not busy doing actual TPM stuff that might fiddle with the stack or shared memory. But that means that we can't always know when the task finally gets around to resetting itself. This CL adds a tpm_reset() function that blocks until the reset actually occurs. Obviously it can't do that if it's being called in interrupt context or from the TPM task itself, but otherwise it does. BUG=chrome-os-partner:52366 BRANCH=none CQ-DEPEND=CL:361680 TEST=make buildall, test on Gru, manual tests In addition to the normal rebooting, logging in/out, and so forth. I added a temporary console command to call tpm_reset() and scattered a bunch of ccprintfs around it. When called due to SYS_RST_L, it didn't block. When invoked with the console command, it did. Change-Id: I51e8b1299dbdcd1a12273cf48a890e93ed32a8c8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388125 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: reset only the TPM state on SYS_RST_LRandall Spangler2016-09-241-0/+16
| | | | | | | | | | | | | | | | | | | | | | Rather than doing a full cr50 reset when the system reset SYS_RST_L is asserted, just reset the state of the TPM task and library. Re-clear .bss for those modules, then re-initialize. BRANCH=none BUG=chrome-os-partner:52366 CQ-DEPEND=CL:366792 TEST=make buildall; test on Gru Trigger a SYS_RST_L by using the AP's reboot command, power off/on, log in/out/in. See that the Cr50 does not reboot and the firmware and userspace are still happy about the TPM. Change-Id: I32cd2bb72316f68c74db77a20a8d09112b402d4b Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361680
* npcx: Fixed bug that api utility in ROM doesn't enable burst mode.Mulin Chao2016-09-151-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | We found the api utility in ROM doesn't enable burst mode of GDMA. It influences the performance of FW download a lot. The CL modified GDMA for moving the code of the other region from flash to ram. And move a function that kicks off GMDA transactions to suspend ram in case this utility is erased by itself. This issue will be fixed in our next generation. Modified sources: 1. system.c: Implement GDMA bypass. 2. system_chip.h: Import flash addresses for GDMA bypass code. 3. registers.h: Add GDMA register definitions. 4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script. BRANCH=none BUG=chrome-os-partner:56794 TEST=make BOARD=npcx_evb; test sysjump and measure download time Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/381779 Commit-Ready: Shawn N <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common: Add TABLET_MODE hook.Gwendal Grignou2016-09-075-1/+21
| | | | | | | | | | | | | Add a hook to act when the a device is going in tablet mode and back. BUG=chromium:606718 BRANCH=kevin TEST=Test with evtest that an event is sent to the AP. Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380412 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: Mark several console commands as safeBill Richardson2016-08-311-3/+3
| | | | | | | | | | | | | | | | | | | Even when CONFIG_RESTRICTED_CONSOLE_COMMANDS is enabled, there are many commands that can't do anything dangerous. This marks some of those commands as safe to use, even when restrictions are enforced. I'm only marking commands that are used by the Cr50, since that's the only board that has restrictions. BUG=chrome-os-partner:55322 BRANCH=none TEST=make buildall, test on Cr50 hardware Change-Id: I6289d332830175b6adcb6b20cb4c21d01d27a25e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/376188 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-244-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* minute-ia: Enable x86 core for Intel ISHJaiber John2016-08-1017-0/+1919
| | | | | | | | | | | | | | | | | Add intial minute-IA (x86) core to to enable the FW to boot on Intel Integrated Sensor Hub (ISH). BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I4dcf841766f216cd00fb1d4214fae19ba5de5603 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336443 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* core: Don't discard irqprio table entries due to LTOShawn Nematbakhsh2016-08-074-9/+9
| | | | | | | | | | | | | | | | | Add __keep attribute to irqprio entries to ensure they are not dropped when CONFIG_LTO is enabled. BUG=chrome-os-partner:55920 BRANCH=None TEST=Manual on kevin. Check build/RO/ec.RO.map, verify that .rodata.irqprio section is not empty. Change-Id: I51ae23556d6f46b2cd7ba098f0e7a785292b2853 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366571 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mkbp: Add support for buttons and switches.Aseda Aboagye2016-07-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the matrix keyboard protocol does not have support for handling non-matrixed keys. This commit adds support for buttons which do not appear in the keyboard matrix as well as switches. Additionally, the keyboard FIFO is now just a general MKBP events FIFO which MKBP events are free to use. Now, buttons and switches wil join the key matrix event. BUG=chrome-os-partner:54988 BUG=chrome-os-partner:54976 BUG=chromium:626863 BRANCH=None TEST=Flash kevin, and verify that keyboard is still functional. TEST=make -j buildall CQ-DEPEND=CL:358926 Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/358633 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add cts.tasklistDaisuke Nojiri2016-07-113-0/+11
| | | | | | | | | | | | | | | | | | | | | | cts.tasklist contains tasks run only for CTS. These tasks are added to the tasks registered in ec.tasklist with higher priority. This design allows board directories to be free from CTS stuff. cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist). If a suite does not define its own cts.tasklist, the common list is used (i.e. cts/cts.tasklist). BUG=chromium:624520 BRANCH=none TEST=Ran the followings: make buildall make CTS_MODULE=gpio BOARD=nucleo-f072rb make CTS_MODULE=gpio BOARD=stm32l476g-eval Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359445 Reviewed-by: Chris Chen <twothreecc@google.com>
* it83xx: Support different PLL frequencies setting (24/48/96 MHz)Dino Li2016-06-142-8/+5
| | | | | | | | | | | | | | | | | | | | | | | Default setting is at 48MHz. For PLL frequency at 24MHz: 1. USB module can't work, it requires 48MHz to work. 2. SSPI clock frequency is divide by two. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. uart, i2c, timer, and pd modules are function normally at different PLL frequency settings. 2. use 'flashrom' utility to flash EC binary with different PLL settings. Change-Id: Iabce4726baff493a6136136af18732b58df45d7f Reviewed-on: https://chromium-review.googlesource.com/347551 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove SHIFT_CODE_FOR_TEST handlingShawn Nematbakhsh2016-06-033-12/+0
| | | | | | | | | | | | | | | | | | SHIFT_CODE_FOR_TEST images were used for an old FAFT test but is no longer in use today. BUG=chromium:616806 BRANCH=None TEST=`make buildall -j` CQ-DEPEND=CL:349281 Change-Id: I1b4e8c2560e2a7ff507cf2275dbbbdabf435866b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/349272 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Tom Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* core: cortex-m0: Fix task routine prototypesStefan Reinauer2016-06-031-1/+1
| | | | | | | | | | | | | | | The task routines are void func(void), not int func(void *). BUG=none BRANCH=none TEST=compile tested on chell Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I599ff2433d821bfb446fbb4f84a803c6feffa0b3 Reviewed-on: https://chromium-review.googlesource.com/343213 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip: it83xx: Optimize interrupt usage of LPC accessDino Li2016-05-181-10/+0
| | | | | | | | | | | | | | | | | | LPC access interrupt only enabled when EC entering deep doze mode. This will reduce interrupt of LPC access. Also, this interrupt is always enabled for LPC platform to support "CONFIG_LOW_POWER_S0". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Tested ectool command 'version' x 10000. Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a Reviewed-on: https://chromium-review.googlesource.com/336112 Commit-Ready: Dino Li <dino0303@gmail.com> Tested-by: Dino Li <dino0303@gmail.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-194-16/+44
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core: fix unaligned accessKevin K Wong2016-03-111-0/+2
| | | | | | | | | | | | | | | | without this, there could be unaligned access of __flash_lpfw_start variable in system_hibernate function which causes exception. BUG=none BRANCH=none TEST=make buildall, able to enter/exit EC hibernate Change-Id: I6c0400fd88f3b815a42a70c2983a8f8ecd79b398 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331653 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* core/*/ec.lds.S: quote paths containing OUTDIRPatrick Georgi2016-02-103-8/+17
| | | | | | | | | | | | | | | | | | | If OUTDIR brings in a "@", the build breaks because that delimits the path, leading to invalid file names. This can happen (and happened) when building on a Jenkins CI instance which uses jobname@number as path for parallel checkouts on a single build node. BRANCH=none BUG=none TEST=build with make out=foo@bar ... failed and works now. Change-Id: Id0594f0d7312419110091443755ec11b5f8ee2d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/327110 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* nuc: Add support for CONFIG_LOW_POWER_S0.Mulin Chao2016-02-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get better power consumption in S0, we add FW support for CONFIG_LOW_POWER_S0. Before entering deep idle in S0, we must enable Host interrupt to wake up EC if it needs to service LPC bus. This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal. In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR since preload counter is changed by __hw_clock_source_set all the time. We also found there're no event set if it's deadline is over 32 bits but current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if ITIM32 expires, FW set an event for ITIM32 after process_timers(). Modified sources: 1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition. 2. clock.c: Enable Host interrupt for LPC. 3. clock.c: Disable LP_WK_CTL for better power consumption. 4. gpio.c: Add ISR for Host interrupt. 5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed. 6. register.h: Add uart_clear_pending_wakeup function. 7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow. 8. fan.c: Enable deep sleep if duty cycle is zero. 9. include/system.h: Add SLEEP_MASK_FAN for fan control loop. 10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the instruction pipeline. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324651 Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: fix EC interrupt vector registers issueDino Li2016-01-282-29/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a limitation for EC interrupt vector registers. System may read incorrect interrupt number in ISR so we need to add a workaround to prevent it. The following is a example that got incorrect interrupt number: 1. REG IVCTx = 0x10. (no interrupt pending) 2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR. 3. Read interrupt vector register to determine interrupt number. 4. Higher priority interrupt of same interrupt group occurs (for example: INT134, IVCTx = 0x96) while the system is reading the interrupt vector register for EC INT6, we may end up with an incorrect interrupt number between 0x16 and 0x96. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart, LPC, I2C, and PECI. 2. Console command 'taskinfo'. Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17 Reviewed-on: https://chromium-review.googlesource.com/322097 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-254-0/+16
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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