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* stm32/system: Disable caches before rebootPatryk Duda2021-06-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* cortex-m: provide a function to set IRQ priorityPeter Marheine2020-05-191-0/+14
| | | | | | | | | | | | | | | | On Puff we need to increase some IRQ priorities to meet strict timing requirements. To support that, provide a function encapsulating the bit manipulations to adjust the priority of a single IRQ and update task.c to take advantage of it. BUG=None BRANCH=None TEST=Still builds. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-191-3/+3
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
* core/system: Extract and doc cortex constCraig Hesling2020-01-131-1/+8
| | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=make buildall -j TEST=make BOARD=nucleo-h743zi # Reboot H743 into bootloader using boot0 pin and reset # Flash nucleo over FTDI and STM32 bootloader stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200 # Reset without boot0 # Open console minicom -D/dev/ttyACM0 reboot soft # Verify soft reset was used reboot hard # Verify hard reboot was used Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232 Reviewed-by: Jett Rink <jettrink@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-15/+16
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp: Add functions to clean/invalidated selected ranges of D-cacheNicolas Boichat2019-02-201-4/+4
| | | | | | | | | | | | | | | | | | | | | The previous version could only work on single lines, let's add functions to work on ranges. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content TEST=flush 0x10000000 16 c => clean a single line flush 0x10000020 32 c => clean a single line flush 0x10000040 64 c => clean 2 lines TEST=flush 0x10000080 16 i => invalidate 1 line flush 0x100000a0 32 i => invalidate 1 line flush 0x100000c0 64 i => invalidate 2 lines Change-Id: Ib386eeb4ce5d2f64a23e558c7f562eba234e6b0d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475105 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Add functions to clean/invalidated selected lines of D-cacheNicolas Boichat2019-02-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For performance reasons, we want to be able to flush/invalidate only specific cache lines/addresses. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content: cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 3848c300 3848c301 3848c302 3848c303 3848c304 3848c305 3848c306 3848c307 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => Then clean a cache line > flush 0x10000000 c Clean cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => memory is updated => Then invalidate a cache line > flush 0x10000020 i Inval 10000020 cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => cache content is thrown away, and matches memory Change-Id: I5dbcc366236fef56f7cb048ce313247cf3d51276 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475092 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* cortex-m: add D-cache supportVincent Palatin2018-06-041-2/+7
| | | | | | | | | | | | | | | | | | | | Add support to enable the architectural D-cache on ARMv7-M CPU supporting it. Update the MPU code in order to be able to declare an 'uncached' RAM region (e.g. to store the DMA buffer). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=with the following CL, on ZerbleBarn, boot and capture a finger image. Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285 Reviewed-on: https://chromium-review.googlesource.com/1032776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cortex-m: enable I-cache on ARMv7-MVincent Palatin2018-03-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Change-Id: I6af1021d65048b787630387f7d95797db15d069c Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* mec1322: heavysleep in idle task and console deepsleepKyoung Kim2015-07-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented mec1322's heavysleep in idle task to reduce further EC power down on S3. MEC1322 needs sleep-enabled for all blocks to acheive max power down including UART. Real heavysleep will be effective only when console/uart is not active. To enable this commit, board-specific commit is required. For example, check commit, "Enabling heavysleep idle task at S3". Test: 1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux shell. 2. wait at least 1 min till EC console sleeps 3. measure EC power. Since idle task is continuously scheduled, EC will enters/exits to/from heavy sleep mode frequently in S3 and power consumption will be changed dynamically. For acurate power measurement, high-sampling-rate measurement system might be required and using DMM might not give accurate number. BUG=None TEST=Tested on evt1p0/evt1p7/DVT BRANCH=None Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283603 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cpu: Enable reporting of faultsSimon Glass2012-07-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faults should be enabled, otherwise we just get a hard fault whenever they occur. BUG=chrome-os-partner:10146 TEST=manual: build and boot on snow; cause a fault and see that it is reported correctly in the panic message, rather than just a hard fault. Also tested on link, 'rw 1': > rw 1 === EXCEPTION: 06 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000041 r2 :00000001 r3 :20003720 r4 :00000000 r5 :0000bbb4 r6 :2000371c r7 :00000002 r8 :00000000 r9 :20003721 r10:00000000 r11:00000000 r12:00000000 sp :200019a0 lr :00004ad1 pc :000054f6 Unaligned mmfs = 01000000, shcsr = 00070008, hfsr = 00000000, dfsr = 00000000 Time: 0x00000000006f0938 us Deadline: 0x00000000006ec3d4 -> -0.017764 s from now Active timers: Tsk 1 0x000000000072bc1e -> 0.242406 Tsk 4 0x00000000006ec3d4 -> -0.017764 Tsk 5 0x00000000007a2333 -> 0.727547 Tsk 6 0x00000000007a2193 -> 0.727131 Tsk 7 0x00000000007a1fd9 -> 0.726689 Tsk 9 0x0000000000eeb452 -> 8.366874 Task Ready Name Events Time (s) 0 R << idle >> 00000000 6.854007 1 WATCHDOG 00000000 0.000442 2 VBOOTHASH 00000000 0.286203 3 LIGHTBAR 00000000 0.018957 4 POWERSTATE 00000000 0.020656 5 TEMPSENSOR 00000000 0.000851 6 THERMAL 00000000 0.000643 7 PWM 00000000 0.000243 8 TYPEMATIC 00000000 0.000015 9 X86POWER 00000000 0.010582 10 I8042CMD 00000000 0.000015 11 HOSTCMD 00000000 0.000014 12 R CONSOLE 00000000 0.000336 13 POWERBTN 00000000 0.003883 14 KEYSCAN 00000000 0.000297 Rebooting... Change-Id: I95a4a7fae14359aa4e2b645d2110f91161e7df88 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26170
* Enable checking for divide by 0 and alignment faultsSimon Glass2012-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These likely indicate errors, so we shold trap them. Possibly this should be reconsidered for production. BUG=chrome-os-partner:10148 TEST=manual: build on all boards build and boot on snow with a special rw command containing a division by 0. See that it is trapped: > rw 0 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :08005eba r2 :00000000 r3 :20001048 r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :0800368a Divide by 0, Forced hard fault, Vector catch mmfs = 02000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 Turn off the cpu_init() setup, and see that it is ignored. > rw 0 read 0x0 = 0x00000000 > Similarly, try an unaligned access with the rw command with this enabled: > rw 1 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000041 r2 :00000001 r3 :200012ac r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :08003686 Unaligned, Forced hard fault, Vector catch mmfs = 01000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 but disabled it works: > rw 1 read 0x1 = 0x5d200010 > Change-Id: Id84f737301e467b3b56a7ac22790e55d672df7d8 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/25410 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add an option to report panic fault informationSimon Glass2012-06-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | The fault status registers sometimes have useful information, so provide an option to display these. This adds about 1KB to the code size. BUG=chrome-os-partner:10146 TEST=manual: build for all boards On snow, cause a panic and see that it is reported correctly. === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002 r8 :00000000 r9 :200013de r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000 mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 Change-Id: I1a18c85ee63760502c92b300f5a87e57468469a5 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24505 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Move System Control Block registers to core headerVincent Palatin2012-06-151-0/+2
| | | | | | | | | | | | | | | | | | | The SCB registers are defined in the ARMv7-M architecture, so they are common to all chips. We will need System Control Register (SCR aka SYSCTRL) to implement power management on stm32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=snow Change-Id: I35c283731306541b3d21398c96fdca89954fe20a Reviewed-on: https://gerrit.chromium.org/gerrit/25392 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Support warm reboot from one EC image to another.Randall Spangler2012-03-191-0/+1
| | | | | | | | | | | | | | | | | | | | | This is necessary at init-time for verified boot to jump from RO to one of the RW images. It's also used by factory EC update to update one image and then jump to the updated image to finish the update. In this case, the x86 does NOT reboot. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8449 TEST=manual 1) power on x86 and log in 2) sysjump a --> system is in a; x86 has not rebooted 3) sysjump ro --> system is back in RO; x86 has not rebooted 4) reboot -> system is in RO; x86 HAS rebooted Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
* NVIC registers are not SoC specificVincent Palatin2012-01-251-0/+23
Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
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