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* btle: Add the HCI layerMyles Watson2016-08-082-1/+673
| | | | | | | | | | | | | | | | | | | Add a case statement to handle HCI commands. Add a test commands. Try to match the hcitool syntax, so the same commands can be executed on a Linux host. Added lcmd (long cmd) to pass more parameters in fewer arguments BUG=None BRANCH=None TEST=Use HCI commands to configure an advertiser and listen for it using `hcitool lescan` on the host. Change-Id: Ie28038847c9549eb1c27a605aa0fbad5efd3b2c7 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362145 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* btle: Add common link layer codeMyles Watson2016-08-082-0/+553
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=make BOARD=hadoken Add a task that is responsible for the state of the link layer. Change-Id: Ifc79bf1e4c57f5de448ab05b3a8d3a1aca5a58e2 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362144 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: Decode more reasons for chip resetBill Richardson2016-08-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | There are few reasons why the SoC may reboot which we haven't been reporting (they just show up as "[Reset cause: other]"). This adds a bit of decoding to explain some of those "other" reasons. BUG=none BRANCH=none TEST=make buildall; try on Cr50 I tested one of the new reasons using "crash hang". It shows up correctly as "{Reset cause: security]". I haven't specifically tested all of the new reasons, but since this is basically just a change to console message they should work too. I'll double-check those cases once some blocking bugs are fixed. Change-Id: I46daed29d7e37bda9034a3486127bed0ea25f803 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366400 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add new "hang" option to crash commandBill Richardson2016-08-051-5/+15
| | | | | | | | | | | | | | | | | | | | | The crash command is used to intentionally invoke various failure modes in a running system. This adds one more (and cleans up the command slightly). The "crash hang" command does the same thing as "crash watchdog", except that it disables interrupts first. Some SoCs may require special handling to recover from that case. BUG=none BRANCH=none TEST=make buildall; run on Cr50 hardware Invoked all the options to the crash command, observed that the appropriate response occurred in each case (a stack trace if possible, followed by a reboot). Change-Id: I18897cfc04726e6aeda59f4c6e742d7a0037cf80 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366127 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* common: Add Bluetooth LE supportMyles Watson2016-08-022-0/+193
| | | | | | | | | | | | | | | Add data structures, defines, and helper functions to parse packets and implement frequency hopping. BUG=None BRANCH=None TEST=None Change-Id: I0f7a7d4bee55e00343f6f87f304fb2ba57cb6ec0 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362174 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Levi Oliver <levio@google.com>
* spi_flash: Remove unused write-protect rangesDavid Hendricks2016-08-021-45/+0
| | | | | | | | | | | | | | This removes write-protect ranges that are unnecessary so that we save a bit of space. BUG=chromium:633431 BRANCH=none TEST=compiled only. Change-Id: Ib34c6a125b001fc92a21f795ac3d922e77143342 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365210 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mkbp: Clear host interrupt if no more events.Aseda Aboagye2016-08-021-1/+3
| | | | | | | | | | | | | BUG=chromium:633694 BRANCH=None TEST=Flash kevin; verify that no more console spam is present on the EC. Change-Id: I240fbe330952b82e2a5f97d0be7ebe4b2a8e2b46 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/365470 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm: TPM_FW_VER returns chip ID and board revisionBill Richardson2016-08-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | The chip revision and board version show up on the second line of the returned string, immediately before the build info. BRANCH=none BUG=chrome-os-partner:55558 TEST=Queried version string using tpm_test make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 RO_A:* 0.0.2/d0c9abe3 RO_B: 0.0.2/13eda43f RW_A: cr50_ [...] B2:0 cr50_v1.1.5013-ab0e228+ [...] ^^^^ Change-Id: Iaa1efe5dca441aca24f281f76c1f218e24c844be Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365421 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* gru: Align images sizes to flash block erase sizeShawn Nematbakhsh2016-08-011-0/+7
| | | | | | | | | | | | | | | | | Image sizes must be aligned to block erase size to ensure that the host can erase the entire image and nothing but the image. BUG=chrome-os-partner:55828 BRANCH=None TEST=Manual on kevin, rebuild FW with new EC, rebuild + flash EC once again, verify that SW sync completes and unit boots to OS. Change-Id: If6110f39869d6421038a3fe7afdc7d918323249e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365142 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm: make TPM_FW_VER register return both build and version stringsVadim Bendebury2016-08-011-1/+13
| | | | | | | | | | | | | | | | | | | | | | Both build string (which includes status of all firmware components of the running image) and the firmware version string (which show versions of various objects in the flash) are important to the user. Let's include both of these strings into the TPM_FW_VER register output. Buffer storing the string needs to be increased accordingly. BRANCH=none BUG=chrome-os-partner:55558 TEST=verified the contents of the AP firmware console log: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A: ... cr50_v1.1.5003-af11829+ private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735... Change-Id: I67df3e810bd07053d0b7d8b6fac350253ca06bb0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364830 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tpm: allow TPM_FW_VER register to return arbitrary number of bytesVadim Bendebury2016-08-011-2/+0
| | | | | | | | | | | | | | | | | | | | As the version string grows longer, reading it in 4 byte chunks becomes more and more expensive, the overhead of setting up a separate SPI transaction per very chunk is just too much. There is no reason not to allow the host to read as many bytes at a time as it requires (limiting it by the maximum version string buffer size of course). BRANCH=none BUG=chrome-os-partner:55558 TEST=verified that the version string is still read properly by the TPM driver on Kevin Change-Id: Ib76cd151e8dc32374f87135af36266b4ec725a56 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364831 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: use single buffer for version reportingVadim Bendebury2016-08-011-5/+27
| | | | | | | | | | | | | | | | | | | | | | | The only place where two separate buffers for the RO version strings is required is the tpm_registers.c:set_version_string() function. In preparation of reporting the build string along with the version string, let's rearrange the function not to require separate buffers for the RO versions. BRANCH=none BUG=chrome-os-partner:55558 TEST=verified that version reported by the TPM driver on Kevin is still correct: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:*... Change-Id: I8924ac48bd838851670f0d659e95aa92a8524665 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364587 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* system: split long build linesVadim Bendebury2016-07-311-1/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards now provide very long build version strings including version strings of multiple subcomponents. Let the version command split those long lines printing each subcomponent's version string in a separate line. BRANCH=none BUG=chrome-os-partner:55373 TEST=verified on cr50: > vers Chip: g cr50 B2 Board: 0 RO_A: 0.0.1/84e2dde7 RO_B: * 0.0.2/13eda43f RW_A: * cr50_v1.1.4980-2b9f3e1 RW_B: cr50_v1.1.4979-8cec36d+ Build: cr50_v1.1.4980-2b9f3e1 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-2b12863 cryptoc:v0.0.4-5319e83 2016-07-28 20:40:55 vbendeb@kvasha Change-Id: Ie14af3aa9febd5a3b02b273a7ab6302e74777e43 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364491
* separate dptf logic from existing thermal logic.Ravi Chandra Sadineni2016-07-305-132/+194
| | | | | | | | | | | | | | | | Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> BRANCH=none BUG=chromium:631848 TEST=make buildall -j Change-Id: I718a29b067d37af477306f9bebfcb8e71d84d4ee Reviewed-on: https://chromium-review.googlesource.com/363008 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* HACK tpm: reset fallback counter when readyVadim Bendebury2016-07-291-0/+6
| | | | | | | | | | | | | | | | | | | As a temp measure until a proper solution is implemented, reset the restart counter when the PCR_Read command is issued by the host. This is a good indication that Chrome OS is through the boot process, as PCR value is used to determine the boot mode. BRANCH=none BUG=chrome-os-partner:55667 TEST=installed the new image on a Kevin cr50 and rebooted it in normal and recovery modes, observed on the cr50 console the message like > system_process_retry_counter:retry counter 1 Change-Id: Ib55e161d5edbf8f6e2d387fd756b94aa53c20ed8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364311 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* printf: Add sign ('+') flagDaisuke Nojiri2016-07-291-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | '+' flag can be used with signed integer type (%d) and causes positive integers to be prefixed with '+' (e.g. +1745). This emphasizes output values as a signed value. It can be mixed with left-justification flag '-': %-+8d. It's ignored when used with unsigned integer or non-integer types: %u, %x, %p, %s, %c, etc. BUG=none BRANCH=none TEST=make buildall && int32_t d = 1745; CPRINTS("'%-+8d'", -d); /* '-1745 ' */ CPRINTS("'%-+8d'", d); /* '+1745 ' */ CPRINTS("'%d'", d); /* '1745' */ CPRINTS("'%+08d'", -d); /* '000-1745' */ CPRINTS("'%+08d'", d); /* '000+1745' */ CPRINTS("'%+d'", -d); /* '-1745' */ CPRINTS("'%+d'", d); /* '+1745' */ CPRINTS("'%+s'", "foo"); /* 'foo' */ CPRINTS("'%-+8s'", "foo"); /* 'foo ' */ CPRINTS("'%+08x'", d); /* '000006d1' */ CPRINTS("'%+u'", d); /* '1745' */ Change-Id: I8dcd34b0cf03dbefc500b9c98fea235d85bde8d3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363924
* pd: support CCD provided by an external chipVincent Palatin2016-07-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | | When the case close debug (CCD) feature is provided by an external chip (e.g security chip or TCPC), we still need to be able to detect debug accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without seeing Rp). Add a CONFIG_CASE_CLOSED_DEBUG_EXTERNAL configuration parameter for this case. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:55410 TEST=manual:on Kevin, enable CONFIG_CASE_CLOSED_DEBUG_EXTERNAL, plug a SuzyQ (with Rd/Rd) and verify that the device in debug mode when transitioning to S5. Change-Id: Ie04a000a7b0eb670e3808f7bca1180298dfcd9db Reviewed-on: https://chromium-review.googlesource.com/363400 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: Improve version info for dual RO & RW imagesBill Richardson2016-07-262-57/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC looks for two RO images at reset, and is typically configured for two RW images as well. This CL reports version strings for all those images, as well as identifying the active RO and RW copies. Since the RO image doesn't contain a version string, we create one using the epoch_, major_, minor_, and img_chk_ members of its signed header. BUG=chrome-os-partner:55558 BRANCH=none TEST=make buildall; run on Cr50 hardware The "version" command now includes information like this: RO_A: * 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1.4965-a6c1c73-dirty RW_B: * cr50_v1.1.4959-2f49d5c The '*' indicates the active image. The test/tpm_test/tpmtest.py program has been updated to request the version information at startup, and it also now reports similar information, just all on one line: RO_A:* 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1 ... The active images are marked with a '*' following the ':', so that the same regexp can match either format: ($ro, $rw) = m/RO_[AB]:\s*\*\s+(\S+).*RW_[AB]:\s*\*\s+(\S+)/s; Change-Id: Ic27e295d9122045b2ec5a638933924b65ecc8e43 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362861 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charge_manager: Treat soft-disconnected batteries as not presentShawn Nematbakhsh2016-07-261-3/+8
| | | | | | | | | | | | | | | | | | | | For the purpose of spoofing dual-role capability, treat soft-disconnected batteries as not present, since they are not capable of supplying a current until they are revived. BUG=chrome-os-partner:55617 BRANCH=None TEST=Manual on kevin w/ subsequent CL. Put battery into soft-disconnect state. Attach charger and verify EC doesn't lose power and battery again supplies current. Change-Id: Ie6b83b3d4e1e33c4bbbd1a90450506e7dcd1dfb2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363003 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_state_v2: Add console command to test discharge on ACVijay Hiremath2016-07-251-2/+19
| | | | | | | | | | | | | | | | | Added support to test discharge on AC using console command. BUG=chrome-os-partner:55572 BRANCH=none TEST=Manually tested on Reef. "chgstate discharge on" - Battery is discharging "chgstate discharge off" - Battery is charging Change-Id: I07733fe28d22b0ad6e3bd172a445e43a60650762 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/362678 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_state_v2: BD99955: Do not inhibit charge in battery learn modeVijay Hiremath2016-07-251-20/+24
| | | | | | | | | | | | | | | | | | BD99955 charger auto exits from the battery learn mode if the charge is inhibited. Hence, do not inhibit the charger in battery learn mode. BUG=chrome-os-partner:55491 BRANCH=none TEST=Manually tested on Reef using 'ectool chargecontrol' command. Able to enter/exit battery learn mode safely. Change-Id: If05f9a9451842b77619e0a8c5db5e54fec24f399 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/362123 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tpm: remove int_status variableVincent Palatin2016-07-231-1/+0
| | | | | | | | | | | | | | | | | It doesn't seem to be used anywhere, so let's remove it rather than having to re-initialize it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:52366 TEST=make BOARD=cr50 Change-Id: I08175621fe26a4344ce1716a83ad4233531043a1 Reviewed-on: https://chromium-review.googlesource.com/361940 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add endorsement certificate flownagendra modadugu2016-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This change implements logic for installing endorsement certificates in the RW section. The endorsement certificates are initially provisioned in a fixed RO flash region and are copied in the RW TPM data region (once this region has been initialized). Also add code for reading from the info bank, which is where the endorsement seed is initially stored. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:50115 TEST=TCG tests running Change-Id: Id8c16d399202eee4ac0c4e397bdd29641ff9d2f3 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/362402 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* hostcmd: Flush UART before doing cold rebootShawn Nematbakhsh2016-07-221-0/+1
| | | | | | | | | | | | | | | | | Flush our UART buffer to ensure that we don't miss prints when we reboot the EC. BUG=chrome-os-partner:55539 BRANCH=None TEST=Manual on kevin, issue cold reboot host command, verify that "Executing host reboot command" is seen on console. Change-Id: I96d5687b413ba4f603e3e7845b5cbba1c2d65efa Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tpm: report correct fw versionVadim Bendebury2016-07-221-2/+4
| | | | | | | | | | | | | | | | | | | | | The tpm firmware version register should report the current RW image's version, not the RW_A. BRANCH=none BUG=chrome-os-partner:55145 TEST=verified that tpm firmware version reported by coreboot on the AP console matches the version running on the device, for both RW_A and RW_B. From coreboot console log on two different runs: Firmware version: RO: 84e2dde7 RW: cr50_v1.1.4943-f81a901 Firmware version: RO: 84e2dde7 RW_B: cr50_v1.1.4943-f81a901 Change-Id: I43f5432e44e38dbf9b42750dd2042a0f005bcbfb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362612 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: NvMem: Modified nvmem_init to handle 2 corrupt partitionsScott2016-07-221-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | During initialization the NvMem module looks for either a valid partition or that the NvMem area is fully erased. If neither of these two conditions were found, then it was only returning an error code and logging a message to the console. This CL modifies nvmem_init() so that if the error case as described above is detected, then it will call nvmem_setup() which will create two valid partitions. In addition, the setup function erases all of the existing data in the NvMem space. Enhanced the unit test that deals with both partitions being corrupted so that it verifies the version numbers are correct and that all user buffer data is set to 0xff. BUG=chrome-os-partner:55536 BRANCH=None TEST=Manual Executed make runtests TEST_LIST_HOST=nvmem and verifed that all tests passed. Change-Id: Ib932e02f15bd1aad7811032a12d826c76476e53f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362448 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* timer: fix clock() implementation to match TPM2 library expectationsnagendra modadugu2016-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The clock() function was introduced to provide free running clock for the TPM2 library, which expects this clock to run with a millisecond resolution. This patch fixes the bug where the function in fact was returning the clock running at a microsecond resolution. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:50115 TEST=with the appropriate modification of the user of this function all lockout related TCG tests pass. Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361180 (cherry picked from commit b4e78b309900402499b8742199fb4536570d3000) (cherry picked from commit fefaa02a4f2c807a3ad50137bd7dba7f5f081c31) Change-Id: Ic02fffca610426d22e58609eb8c3693aec96ad5c Reviewed-on: https://chromium-review.googlesource.com/362118
* CR50: do not try searching in uninitialized TPM NV RAM.Vadim Bendebury2016-07-211-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The manufacturing status check verifies if the proper certificates are found in the device NV RAM. This check can not succeed unless NV RAM metadata is initialized by calling _TPM_Init(). If the check shows that the device has not been through manufacturing sequence yet, TPM_Manufacture() needs to be invoked to make sure that all relevant TPM structures are initialized and properly stored in NV RAM. _TPM_Init() needs to be invoked again after that. BRANCH=ToT BUG=chrome-os-partner:43025 TEST=restarting Kevin device with pre-manufactured CR50 takes it through factory initialization on every reboot. Restarting Kevin once TPM is through manufacturing process shows that the previously saved rollback counters are preserved. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361093 Reviewed-by: Nagendra Modadugu <ngm@google.com> (cherry picked from commit 61a0fe734e808d1dbdf56fb6023e04adf66553b3) (cherry picked from commit 3207a57fb2f5957b6e833d9ab1f9ea46021c5e1e) Change-Id: I80b69f2c4b8d0e4cca154db510867df39c707ce2 Reviewed-on: https://chromium-review.googlesource.com/362084
* servo_v4: copypasta usb updater code into commonNick Sanders2016-07-213-0/+523
| | | | | | | | | | | | | | | | | This copies the generic USB update code into common so it can be used on other platforms. There should be no functional change. cr50 folks want no change to their code so vbendeb@chomium.org will refactor this back together at a later date. BUG=chromium:571476 TEST=none BRANCH=none Change-Id: I710afb22940013e7db5d8694898b90c0ae245777 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362131 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tpm: fire watchdog before executing commandsVadim Bendebury2016-07-211-0/+3
| | | | | | | | | | | | | | | | | | | In certain test scenarios the tpm task is hogging all resource and causes watchdog resets. Let's kick the watchdog in every loop, Long calculations already have watchdog kicking in place. BRANCH=ToT BUG=none TEST=tests executed in rapid succession do not cause watchdog resets any more. (cherry picked from commit de8fb11bfd07d3fea2048b6848b8a183c31e2580) Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360229 Reviewed-by: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Change-Id: Ifaad6f9b4af2218f601412a36a075b4b4275d56f Reviewed-on: https://chromium-review.googlesource.com/362170
* mkbp: Extend EC_CMD_MKBP_GET_INFO.Aseda Aboagye2016-07-191-9/+98
| | | | | | | | | | | | | | | | | | | | - Added ability to query the buttons and switches. - Added ability to report the available buttons or switches. BUG=chromium:626863 BRANCH=None TEST=make -j buildall CQ-DEPEND=CL:358633 CQ-DEPEND=CL:358634 CQ-DEPEND=CL:358989 Change-Id: Ie821491269e8d09578eba92127895c0b6b8e91a9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/358926 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mkbp: Add keyboard_update_button().Aseda Aboagye2016-07-192-1/+45
| | | | | | | | | | | | | | | | | | | | | | MKBP can now support buttons, so this commit adds the keyboard_update_button() function which will be used to handle the non-matrixed buttons. BUG=chrome-os-partner:54976 BUG=chromium:626863 BRANCH=None TEST=Flash kevin, press volume and power buttons and verify that keyboard is still functional. TEST=make -j buildall CQ-DEPEND=CL:358633 Change-Id: I1c2d36d2113715cf6bd8c6fa7b26fe9253f6ac9f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/358634 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mkbp: Add support for buttons and switches.Aseda Aboagye2016-07-193-105/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the matrix keyboard protocol does not have support for handling non-matrixed keys. This commit adds support for buttons which do not appear in the keyboard matrix as well as switches. Additionally, the keyboard FIFO is now just a general MKBP events FIFO which MKBP events are free to use. Now, buttons and switches wil join the key matrix event. BUG=chrome-os-partner:54988 BUG=chrome-os-partner:54976 BUG=chromium:626863 BRANCH=None TEST=Flash kevin, and verify that keyboard is still functional. TEST=make -j buildall CQ-DEPEND=CL:358926 Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/358633 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* led_policy_std: Blink LED in S0iXjames_chao2016-07-191-1/+2
| | | | | | | | | | | | | | | | | Blink the LED in S3 as well as S0iX states so there is no user visible difference in their behavior. BUG=chrome-os-partner:55225 BRANCH=glados TEST=Enter S0iX on cave and verify LED blinks. Also verify that the LED still blinks in S3. Change-Id: I883147b1c8e599de077c9f06e567a63d535a01f8 Signed-off-by: james_chao <james_chao@asus.com> Reviewed-on: https://chromium-review.googlesource.com/359985 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/i2c: Remove I2C read/write commandsNicolas Boichat2016-07-191-72/+0
| | | | | | | | | | | | | | | ectool stopped relying on these commands a while back, remove them to save space. BRANCH=none BUG=chrome-os-partner:23570 TEST=ectool i2cread still works Change-Id: I63c7a60cdc5ad5c654c49f165175e1b2fe8c4262 Reviewed-on: https://chromium-review.googlesource.com/361160 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* bd99955: Make changes for new OTP change.Aseda Aboagye2016-07-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a new OTP change for the BD99955 and therefore the following changes needed to be made. - Change VFASTCHG_SET1 to 8.704V before CHG_EN is set to 1. - Change VSYS_REG to 6.144V when starting Fast Charging. - Change VSYS_REG back to 8.906V when Fast Charge is finished. - Wait for 50ms to set CHG_EN to off (0) after Fast Charging has ended. BUG=chrome-os-partner:55220 BUG=chrome-os-partner:55238 BRANCH=None TEST=Flash kevin, plug discharged battery in. Plug AC in. `bd99955 r 0x11 1' and verify that VSYSREG is set to 0x1800 (6144mV). TEST=`bd99955 r 0x1a 1' and verify that VFASTCHARGE is set to 0x2200 (8704mV). TEST=Remove battery. `bd99955 r 0x11 1' and verify that VSYSREG is set to 0x2300 (8960 mV). TEST=Plug in battery and let charge to full. Verify that VSYSREG is set to 0x2300 (8960 mV). Change-Id: I5e5ca2cdcd4ead383416901c904df1e6fe5a9e28 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/360421 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chg_st_v2: NVDC: Request max voltage when battery is full.Aseda Aboagye2016-07-181-0/+3
| | | | | | | | | | | | | | | | When the battery indicates that it's full, request the max voltage for the battery. BUG=chrome-os-partner:54877 BRANCH=None TEST=Verify that EC requests 8688 when battery is full for kevin. Change-Id: I20148591fb231314f1d87bd952a867db02373200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/360027 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* charger: BD99955: Get the VBUS level from the chargerVijay Hiremath2016-07-131-1/+6
| | | | | | | | | | | | | | | | | Added code to get the VBUS level by reading the charger registers. BUG=chrome-os-partner:55117 BRANCH=none TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh) registers are updated with the correct VBUS value on the respective ports. Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/359416 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: disable device monitoring when not in ccdMary Ruthven2016-07-121-0/+76
| | | | | | | | | | | | | | | When cr50 is not trying to do ccd, we dont need to monitor the devices. Disable device state detection interrupts and the AP and EC UARTs. BUG=none BRANCH=none TEST=gru and kevin monitor devices correctly when ccd is enabled, and dont monitor anything when it is disabled. Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356770 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: report rw version properlyVadim Bendebury2016-07-121-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code reporting the RW version is in fact using a fixed location in flash memory. This is fine for a single RW image (i.e. the vast majority of the EC boards), but is wrong for CR50 which can run one of two RW images. The fix is to account for this by providing the currently running image type to the function retrieving the image version. Note that RW and RW_B versions end up at different offsets into the image, it is impossible to retrieve the version of the not currently running RW by just changing the offset into the flash memory. BRANCH=none BUG=chrome-os-partner:55145 TEST=as follows: - build, update and start a cr50 - check the vers. command output, observe that it is running from RW and reports the correct RW version string: > vers Chip: g cr50 B1 0_0 Board: 0 RO: RW: cr50_v1.1.4856-df14f6a Build: cr50_v1.1.4856-df14f6a 2016-07-11 11:52:44 vbendeb@eskimo.mtv.corp.google.com > - build the image again, update and restart the cr50 - check the vers. command output, observe that it is running from RW_B and reports the correct RW version string: > vers Chip: g cr50 B1 0_0 Board: 0 RO: RW_B: cr50_v1.1.4856-df14f6a Build: cr50_v1.1.4856-df14f6a 2016-07-11 11:52:44 vbendeb@eskimo.mtv.corp.google.com > - erase the RW space base flasherase 0x4000 0x20000 - run the vers command again. It was failing before this fix, now it still shows the proper RW_B version. Change-Id: Iab8bc0e61b50dd65a9e18a0369b18bdd9cc05421 Reviewed-on: https://chromium-review.googlesource.com/359580 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Dont switch from PHY 1 to 0 when disabling CCDMary Ruthven2016-07-111-7/+0
| | | | | | | | | | | | | | | | | The AP no longer uses PHY0 to to interact with Cr50. Cr50 only uses PHY1 so dont switch the PHY when disabling CCD just release the usb. BUG=none BRANCH=none TEST=After running 'ccd disable' the command 'usb' still returns PHY B, but 'lsusb | grep 5014' on the host doesn't show any devices. When CCD is enabled 'lsusb | grep 5014' shows a device on the host. Change-Id: Icec0acc7a0d00f7eb56c6feef3ff4cf5a3f99735 Reviewed-on: https://chromium-review.googlesource.com/359931 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add cts.tasklistDaisuke Nojiri2016-07-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | cts.tasklist contains tasks run only for CTS. These tasks are added to the tasks registered in ec.tasklist with higher priority. This design allows board directories to be free from CTS stuff. cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist). If a suite does not define its own cts.tasklist, the common list is used (i.e. cts/cts.tasklist). BUG=chromium:624520 BRANCH=none TEST=Ran the followings: make buildall make CTS_MODULE=gpio BOARD=nucleo-f072rb make CTS_MODULE=gpio BOARD=stm32l476g-eval Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359445 Reviewed-by: Chris Chen <twothreecc@google.com>
* motion: Fix comparison between signed and unsigned integerKoro Chen2016-07-111-0/+3
| | | | | | | | | | | | | | | | | If wait_us < 0, comparison against motion_min_interval actually fails, and this negative wait_us causes task_wait_event() never returns if we are not using any motion task event except the timer. The motion task will then stop running and sensor data stay unchanged. BRANCH=none BUG=chrome-os-partner:54092 TEST=hardcode wait_us to a negative value before motion_min_interval check, and see motion task is still running by EC console cmd timerinfo Change-Id: Ic1e7ffeeb9d2ec1f5c5beb4387294014298123af Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/358332 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: add EC_FEATURE_RTC to features host commandStephen Barber2016-07-091-0/+3
| | | | | | | | | | | | | | | | | | If the EC has CONFIG_HOSTCMD_RTC set to 'y', then export this via the features host command. The kernel can then use this feature to expose an RTC device under /dev/rtc*. Signed-off-by: Stephen Barber <smbarber@chromium.org> BRANCH=none BUG=chrome-os-partner:54639 TEST=`ectool inventory` shows RTC on kevin Change-Id: I644c8e61c4d9f691cc6ca94ef60bee4384c21660 Reviewed-on: https://chromium-review.googlesource.com/359414 Commit-Ready: Stephen Barber <smbarber@chromium.org> Tested-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Add CONFIG_HOSTCMD_DEBUG_MODE to set default hcdebug modeNicolas Boichat2016-07-091-1/+1
| | | | | | | | | | | | | | | | | | elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD is called every 100ms, so we want to set "hcdebug" to "off" as the default (which still includes errors, but no "normal" commands). BRANCH=none BUG=chrome-os-partner:55001 TEST=make buildall -j TEST=Flash elm EC, see that output is fairly quiet. Change-Id: I70d91c291d934b4f032e5c57f3c333e2c10b93bc Reviewed-on: https://chromium-review.googlesource.com/359112 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* HACK: cr50: make sure manufacturing sequence is invoked only onceVadim Bendebury2016-07-071-3/+22
| | | | | | | | | | | | | | | | | | | | | While the proper manufacturing initialization is in the works, we need to be able to initialized the device, but do not want to run manufacturing process on every reboot. Let's store the state in the lowest location of the NVRAM, this patch will be reverted when the proper initialization procedure is in place. BRANCH=none BUG=chrome-os-partner:50115 TEST=used the device in Kevin. Observed that factory initialization sequence was invoked only on the first boot, the following boots had no problems reading rollback counters. Change-Id: I812cbad4d91db47de76ecfa5a14c56ae9c0efdab Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358680 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* motion: Add ability to stop ring interrupts.Gwendal Grignou2016-06-301-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, it is assumed the host will sooner or later retrieve the events from the sensor ring: It is only used by Android and the sensor HAL is enabling the ring buffer at boot. But if nobody processes the ring, and the ring is almost full, the EC will generate interrupt for every new events. This can happen with ARC, where events generated for ChromeOS will be in the ring but nobody will process them until Android is started. Add a command to allow sending ring MKBP events. It will be used when the IIO ring buffer is enabled / disabled. It also can be used for preventing raising interrupt when the device is about to go to sleep. BRANCH=ryu,cyan BUG=b:25425420,b:27849483 TEST=Check with fiforead that no events are queued when IIO ring buffer is disabled. Check with ectool and androsensor that interrupt generation stops. Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356689
* keyboard_scan: Support boot key recognition with stuck KSI2Shawn Nematbakhsh2016-06-301-0/+15
| | | | | | | | | | | | | | | | | For certain board configurations, KSI2 will be stuck asserted for all scan columns if the power button is held. We must be aware of this case in order to correctly handle recovery mode key combinations. BUG=chrome-os-partner:54602 BRANCH=None TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I03d76e1121107484f79520745858388f6cae096c Reviewed-on: https://chromium-review.googlesource.com/357590 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* add support for using flash commands to overwrite rwsigMary Ruthven2016-06-291-0/+5
| | | | | | | | | | | | | | | | | | When verifying RW using rwsig, we need to be able to erase the RW signature to remain in RO. This change excludes the RW signature from the area protected by system_unsafe_to_overwrite, so flash write can be used to overwrite the RW signature while still in the RW system image. BUG=none BRANCH=lucid TEST="ectool flashwrite 0x1ff00 corrupt_sig" runs successfully, and on reboot the EC firmware verification fails. Change-Id: I7e234664ae564eef30a8b021ea0539b6c0ae898e Reviewed-on: https://chromium-review.googlesource.com/356810 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: add RO image hash base to the reported FW versionVadim Bendebury2016-06-281-6/+21
| | | | | | | | | | | | | | | | | | | | The CR50 RO version is identified not just by the git hash, but also by the fuse settings and keys used for signing. The first four bytes of the entire RO image's hash are saved in the image header. Adding these four bytes to the version string reported to the host allows to uniquely identify both RO and RW firmware versions. BRANCH=none BUG=none TEST=verified that the appropriate string is showing up: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO: 97594095 RW: cr50_v1.1.4803-dcac93a-dirty localhost ~ # Change-Id: I30a21fad15d99523b1edfa1baa32d80b44e7d0df Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356735 Reviewed-by: Scott Collyer <scollyer@chromium.org>
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