| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch reduces redundant condition checking in connecting
or disconnecting UART TX.
BUG=none
BRANCH=cr50
TEST=manually checked ccd state with/without servo connection and/or
ccd connection.
[AFTER]
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags:
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX I2C SPI
CCD ports blocked: EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: I2C SPI
CCD ports blocked: AP EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: ignored
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: IGNORE_SERVO
WARNING: enabling UART while servo is connected may damage hardware
Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch extends INT_AP_L pulses to be at least 6.5 micro seconds.
It is a tentative solution to to meet Intel TGL/JSL requirement on
interrupt duration.
BUG=b:130515803
BRANCH=cr50
TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec
with logic analyzer on Hatch.
Checked dmesg and coreboot log has no TPM errors.
Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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There is no need to keep the code supporting chip factory mode in
Chrome OS production branches, this code is never used outside of the
chip factory environment.
BRANCH=cr50, cr50-mp
BUG=none
TEST=built an image, verified that an Atlas device boots up into the
previously created Chrome OS account.
Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The only board which would be built from this branch is Cr50. bds,
fizz and host boards are necessary for proper make infrastructure
operation and tests.
lm4 and npcx are chips used by the bds and fizz boards, so they are
also kept around.
BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST='make buildall -j' succeeds
Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Rolling back to 0.0.22 requires erasing the INFO1 rollback protection
space, as current RW level is at two, and 0.0.22 is at one.
The only way to erase INFO1 is to run a node locked prod signed 0.3.22
image. But 0.3.22 will destroy board ID along with the rollback spaces
AND it is not capable of rollback, so to roll back to a lower than
0.3.22 version one still needs to run the SQA image. 0.3.22 will not
allow to restore the Board ID either.
Another problem is that SQA image would update the rollback INFO1
space, thus again preventing 0.0.22 from running.
This patch alleviates the situation by allowing the SQA images to
write Board ID fields and preventing SQA images from updating rollback
space in INFO1.
BRANCH=cr50
BUG=b:146522336
TEST=with the new image was able to downgrade a device from 0.4.24 to
0.0.22
Change-Id: I8babf15ae32036dc612ae9c808c773a2b3355762
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975092
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Change the OWNERS to cr50 team members and remove OWNERS files from all
subdirectories.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50.
CONFIG_LIBCRYPTOC does similar things for other boards that configures
it, including host. This resulted in cr50_fuzz having concurrent
recipes for libcryptoc, as it has both configs. This change separates
CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc.
Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC.
BRANCH=none
BUG=b:144811298
TEST=make -j buildall > /dev/null
Observed no more "warning: overriding recipe for target
'build/host/cr50_fuzz/cryptoc/libcryptoc.a' "
Change-Id: I2186cbead773629456da254df5f82b96e9646fc2
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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Both RO and RW sections have their respective rollback spaces in
INFO1, but until now Cr50 code did not honor the RO binaries' headers
rollback maps and did not update the appropriate iNFO1 space.
With this patch both RO and RW info maps are updated to the lowest
level of the two images found in the flash when invoked during
board_init() or to match the currently active RO/RW when invoked
through vendor command indicating successful OS startup.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=tried the new image on a chip with freshly erased INFO1 space:
first running a DBG image, which does not touch INFO1 maps:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
..
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Then running an image with debug extensions disabled:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d
...
> sysinfo
...
Rollback: 1/1/1 2/128/2
...
Change-Id: I259a3f46c03199633ca85389872449d667f172fb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
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Cr50 firmware is required to update the rollback prevention map in
INFO1 for both RO and RW images.
This patch adds code to display the state of the RO map and both RO_A
and RO_B headers in addition to previously reported RW information.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=loaded the new image and observed reported rollback state:
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
(cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
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DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing
testing of 192 and 256 bit functionality for AES-GCM.
BUG=b:135623371
BRANCH=cr50
TEST=compile, specific test for issue as described in bug
Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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In npcx7, all I2C modules have separate 32-byte transmit FIFO and
32-byte receive FIFO buffers. In this CL, we add the FIFO mode support
to the I2C driver. This will help to reduce the firmware overhead (i.e.
the occurrence of I2C interrupt) during long I2C transactions by allowing
the EC to write/read more than one byte of data at one time to I2C
module and hence improve the I2C performance.
The FIFO mode is enabled by default on all npcx7 series chips.
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test:
1. iterate ~2000 times of single i2c_xfer_unlocked API call.
i.e.
i2c_xfer_unlocked(.., I2C_XFER_SINGLE)
2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls:
i.e.
i2c_xfer_unlocked(.., I2C_XFER_START)
i2c_xfer_unlocked(.., 0)
.
.
i2c_xfer_unlocked(.., I2C_XFER_STOP)
3. Issue 6 I2C transactions by 6 tasks at the same time.
iterates ~2000 times.
TEST=with this CL; build and upload an image (with/without FIFO mode
enabled.) to yorp; no symptom occurs.
Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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The CONFIG_HOSTCMD_X86 will get automatically defined
if either CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI
are defined. So this definition is redundant in
config_chip.h
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I3cb9b61d4b006becba5eb75e0dabe61bd9e3c999
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868134
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The module ID in alternate function setting for spi
master should be corrected as MODULE_SPI_MASTER.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133
Reviewed-by: Jett Rink <jettrink@chromium.org>
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GPIO, WUC and IRQ changes for chip it83201/it83202.
BRANCH=None
BUG=b:133460224
TEST=test GPIO group O, P, Q, R
1.Input: external input 3.3v, GPDR of corresponding pin is 1.
(GCR31, GCR32 select 1.8v, validate again for O and
P group)
2.Output: GPDR of corresponding pin set 1, measure 3.3v.
3.INT: GPIO_INT input trigger => WU INT (select high, low,
rising, falling, both edge trigger mode) => INT => CPU INT
4.Test power-up and down with this CL on ampton.
Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704
Reviewed-by: Jett Rink <jettrink@chromium.org>
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We have seen cases where after a cold EC reboot the pin is low until the
first CEC message is sent by AP (after which the bus is left in a well
defined state again)
This is a follow up to https://crrev.com/c/1346990 which initializes
the pull up in case not done by the RO FW.
BRANCH=none
BUG=b:144548408
TEST=CEC pin only goes low for ~40ms instead of 30s.
Signed-off-by: Felix Ekblom <felixe@chromium.org>
Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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When we go through the suspend code path, we disabled RX
monitoring, and we have done that for a 4+ years. We have
not had a unit test for that ever. One is come that needs this
BRANCH=none
BUG=b:144369187
TEST=See that disabling RX in set_state no longer causes
assertion failures in tests that it shouldn't.
Change-Id: Iab4b44d3f5fdd1fe8657b23ac59df247a384ee32
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925667
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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The new RO has a new dev key, modify the dev manifest to match the new
RO expectations.
BUG=b:74100307
BRANCH=cr50, cr50-mp
TEST=built a node locked image for ro 0.0.11 and observed it boot and
run
Change-Id: I3ce9ca8d23be6b2d959d4457ea6d08afa05376ac
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866173
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Counter implementation has been moved to the AP, no need to keep space
for it in the flash.
BUG=b:65253310
BRANCH=cr50, cr50-mp
TEST=generated image uses 2048 bytes less than before this patch.
Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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HMAC DRBG is used for U2F key generation, and as such is subject
for ACVP tests. Expose DRBG Init, Generate and Seed commands for
automated testing with externally provided test vectors.
BUG=b:138578319
BRANCH=cr50
TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py
Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
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NIST 800-90B Entropy assesment tests requires 1M of 8-bit samples for
statistical tests. While it's possible to use TPM2_GetRandom command
to get entropy on cr50 (there is no software postprocessing), this
command is not available when compiled with CRYPTO_TEST=1 due to lack
of space in firmware. Adding vendor command which is available with
CRYPTO_TEST=1 to get raw entropy from TRNG. Added support script
to save entropy in file for further analysis. Since downloading
entropy takes a long time, new option'-t' added to tpmtest.py
which only invokes download of TRNG samples
BUG=b:138577834
BRANCH=cr50
TEST=make BOARD=cr50 CRYPTO_TEST=1 && test/tpm_test/tpmtest.py -t
To run NIST tests: nist_entropy.sh
Change-Id: I237a4581332a6e2c0332fe6ecf40731ab0be3355
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919640
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
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With the addition of external i2c keyboard controllers, chips that don't
necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN.
Therefore it's wrong to assume we want the chip/*/keyboard_raw code included.
There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW)
that could get #undefd in strategic places. The place that would always
define it would be in include/config.h but I don't believe that executes
before the build.mk rules.
BUG=b:135895590
TEST=Other boards with keyboards still happy.
TEST=No compile errors (regarding missing keyboard GPIOS) when declaring
TASK_KEYSCAN on a fresh stm32 board.
BRANCH=master
Change-Id: I061812a6941a11784950280648912edd5844bd79
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Let's make sure any change to files used explicitly in Cr50 are
approved by relevant persons.
BRANCH=none
BUG=none
TEST=none
Change-Id: If6affd837063311e3215e7596a3a424dc56c7603
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919649
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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STM32F412xE has 512 KB flash
STM32F412xG has 1 MB flash
https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I260659a1de62f3e79f427dd38ca831b4cabed448
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902463
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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During my bug hunt I had to remove the static attribute. While that
wasn't part of the fix, it slipped through.
Also, Daisuke pointed out that the standard idiom in the EC codebase is
__aligned instead of using the full __attribute__ statement, so switch
over.
BUG=none
TEST=sweetberry gcc8 build still runs
Change-Id: I106a8a2df3d6b56bfaba9819228ea7913029f707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1905767
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
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Some boards have CONFIG_USB_PD_PORT_MAX_COUNT defined as 3. Fix the
concerned build assert.
BUG=None
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and
garg(2A + 1C + 1HDMI config).
Change-Id: I4dc949b69dbb3986acc5aa0444c6056268f815f7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898686
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Certain SKUs of certain boards have less number of USB PD ports than
configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable
board specific helper to return the number of USB PD ports. This helps
to avoid initiating a PD firmware update in SKUs where there are less
number of USB PD ports. Also update charge manager to ensure that absent/
invalid PD ports are skipped during port initialization and management.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and
garg(2A + 1C + 1HDMI config).
Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
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We can reduce the power draw of the MCU by limiting which
GPIO port clocks are enabled.
This CL uses the gpio.inc to determine the minimal set of
GPIO ports that need to be enabled/clocked. Only these
ports have their clocks enabled at boot.
Other stm32 chip variants in EC simply enabled all GPIO
port clocks at boot init.
Thank you to Ravi Chandra Sadineni for identifying this optimization
and validating.
For more context, see crrev.com/c/1888116, which this CL replaces.
BRANCH=nocturne,hatch
BUG=b:130561737
TEST=make buildall -j
TEST=make BOARD=bloonchipper
# Connect dragonclaw dev board over servo micro
sudo servod --board=bloonchipper --config bloonchipper_rev0.1.xml &
./util/flash_ec --board=bloonchipper
minicom -D $(dut-control raw_fpmcu_uart_pty | cut -d: -f2)
> sysinfo
# Check that we are in RW
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: Iad51b11eb5959b5d502320560b9ebda7e614d97e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1890924
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This CL adds support for UNUSED pins to the STM32F4 family
of chips. This places the unused/unconnected pins in the lowest
power state.
In this case, ST recommends that you configure the pin as analog-in to
disable the schmitt trigger logic.
This codified the work done in crrev.com/c/1883127 .
The CL should have no functional change for boards that have not
specified UNUSED pins in their gpio.inc.
BRANCH=nocturne,hatch
BUG=b:130561737
TEST=make buildall -j
Change-Id: I444b868b277b016a896e410dccae84429b68839e
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894242
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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It's ok to set the board id type if it's blank. It doesn't matter if the
flags are set. Use the given flags if the flags are empty or use the
existing flags if they're already set.
BUG=b:143649068
BRANCH=cr50
TEST=manual
eraseflashinfo
gsctool -i ZZAF:0x7f7f - SUCCEEDS.
Board ID: 5a5a4146:a5a5beb9, flags 00007f7f
gsctool -i ZZAF:0x7f7f - FAILS
Board ID: 5a5a4146:a5a5beb9, flags 00007f7f
eraseflashinfo
gsctool -i 0xffffffff:0x3f80 - SUCCEEDS.
Board ID: ffffffff:ffffffff, flags 00003f80
gsctool -i ZZAF:0x7f7f - SUCCEEDS.
Board ID: 5a5a4146:a5a5beb9, flags 00003f80
eraseflashinfo
bid 0xffffffff 0x3f80
Board ID: ffffffff:00000000, flags 00003f80
gsctool -i ZZST:0x3f80 - FAILS.
Board ID: ffffffff:00000000, flags 00003f80
update to image with BID TEST:ffff:10
eraseflashinfo
gsctool -i 0xffffffff:0x3f80 - FAILS
Board ID: ffffffff:ffffffff, flags ffffffff
gsctool -i ZZAF:0x7f7f - FAILS
Board ID: ffffffff:ffffffff, flags ffffffff
gsctool -i ZZST:0x7f7f - SUCCEEDS.
Board ID: 5a5a5354:a5a5acab, flags 00007f7f
update to image with BID TEST:0:100
eraseflashinfo
gsctool -i whitelabel - SUCCEEDS.
Board ID: ffffffff:ffffffff, flags 00003f80
gsctool -i ZZST:0 - SUCCEEDS.
Board ID: 5a5a5354:a5a5acab, flags 00003f80
Change-Id: I07de4721cb9cc9ad6e74a51e1794a49cb70f70fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892122
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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It's ok if type and type_inv are both empty. Only show an error if the
board ID type isn't empty and the inversion is incorrect.
BUG=none
BRANCH=cr50
TEST=set whitelabel rlz and run 'bid' command. Make sure the warning
isn't shown.
Change-Id: I12b1e4b34559bc8b6ad482d9694c9dd143bfcd1c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892121
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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BUG=b:143649068
BRANCH=cr50
TEST=manual
eraseflashinfo
Board ID: ffffffff:ffffffff, flags ffffffff
gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1
succeeds
eraseflashinfo
gsctool -i 0xffffffff:0x3f80
Board ID: ffffffff:ffffffff, flags 0x3f80
gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1
succeeds
eraseflashinfo
gsctool -i ZZAF:0x7f7f
Board ID: 5a5a4146:a5a5beb9, flags 0x3f80
gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1
fails
Change-Id: I5d2a3f35c5c7e4e79cadbb3a6737e5db00f8ca5a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892120
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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If the board id type is 0xffffffff, hold off on erasing any type_inv
bits until we get a type that isn't empty.
BUG=b:143649068
BRANCH=cr50
TEST=Use gsctool -i 0xffffffff:0x3f80 to set flags to 0x3f80. Get the
board id and make sure the rlz and rlz_inv fields are still 0xffffffff.
Change-Id: I8243cb59f2560dc232bb982e1615271136d60f24
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892118
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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We will be able to set the board id flags without setting the type. If
only flags are set, then check the flags. If the type is set, also check
the type.
BUG=b:143649068
BRANCH=cr50
TEST=set flags to 0x3f80. Try to update to a ZZAF:0:0:0 image. Make
sure it isn't rejected with board id type mismatch. Try to update to a
prepvt image. Make sure it's rejected.
Change-Id: Ie0efdd7b1b6d76f385688f75c0765c08cab3755c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892117
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Add type_inv to the bid command output. In the bid output you can't tell
the difference between a board with type 0xffffffff and a empty type.
Change the command output to show type and type_inv, so we can tell the
difference.
Remove unused clear_flag parameter
BUG=b:143649068
BRANCH=cr50
TEST=run 'bid'
Change-Id: I13b6ba472010fdf85f94cb4015a9bbc48531973d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Use the standard board_id_is_blank function to check if the board id is
blank.
BUG=b:143649068
BRANCH=cr50
TEST=set the serialnumber
Change-Id: If4e50a548ec2a4747b7bc291f93f170e28eea949
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892114
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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gcc8 packs uint8 arrays more tightly sometimes, which is bad if a
device expects a certain alignment, so make the 4byte alignment of
gcc 4.9 explicit for the buffers.
BUG=b:132204142
TEST=sweetberry firmware built with coreboot-sdk reaches the console
Change-Id: I24cf151d2df21e106fbb7e8f5b16a3bab81b09ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899437
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Brian Nemec <bnemec@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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Add console print when GPIO line changes for easier unit
test debugging
BRANCH=none
BUG=none
TEST=verified that gpio print occurs in unit tests
Change-Id: I888859c8ef4a1b879146e9c01767ee487f7ce564
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896124
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
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The common EC code expects that if the func parameter passed to
gpio_set_alternate_function() is -1 (GPIO_ALT_FUNC_NONE),
that the pin will be reassigned to a GPIO function.
TEST=make buildall
BUG=b:143710991
BRANCH=kukui
Change-Id: I6ba3d3d323e4fb99617ce4baaec662ceab094ad4
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893026
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Adds support for a second I2C slave address, modeled on the same feature
in the STM32-F4. Also refactored the I2C slave interrupt handler to
streamline host read and writes, reduced I2C slave state variable usage,
and make better use of I2C slave interrupt types.
BRANCH=none
BUG=none
TEST=Slave tested with EC CMDs and board cmds sent from a custom written
EC HOST using another MAX32660 device as an I2C Master. Tested with
Raspberry PI that emulates EC HOST and board commands.
Change-Id: I575a283a9a6735b16f4b6ac0fcb0aa2d1984ee92
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1864791
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Tested-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
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Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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Added code to correct the GPIO alternate function parameter at Chipset
level. Optionally board level functions can cleanup the code in additional
change lists.
BUG=b:139427854
BRANCH=none
TEST=make buildall -j
Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974
Reviewed-by: Keith Short <keithshort@chromium.org>
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Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into
separate options controlling SLP_S3 and SLP_S4. Allow volteer to
configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a
build error if virtual wires are configured, but eSPI is not.
BUG=b:139553375,b:143288478
TEST=make buildall
TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but
CONFIG_HOSTCMD_ESPI undefined; observe build error
BRANCH=none
Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758
Reviewed-by: Keith Short <keithshort@chromium.org>
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Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because
that is the configuration option used to enable to use of the the GPIO
signal name thus defined. Remove the now unused
CONFIG_HOSTCMD_PLTRST_IS_VWIRE option.
BUG=b:139553375,b:143288478
TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite
BRANCH=none
Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Ensure that IOEX and VW signals are not accidentally passed to
NPCX's gpio_get_level or gpio_set_level.
BUG=b:138600691
BRANCH=none
TEST=saw assert when passing IOEX signal to gpio_set_level
Change-Id: Ib3eea074a104820cea4095897f4174a84e8368d6
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1854781
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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There are 3 different IO signal types used by the EC.
Ensure they each use a unique range of values so we can tell them apart.
1) Local GPIO => 0 to 0x0FFF
2) IO expander GPIO => 0x1000 to 0x1FFF
3) eSPI virtual wire signals => 0x2000 to 0x2FFF
BUG=b:138600691
BRANCH=none
TEST=IO expander signals still work on Trembyle
Change-Id: I63fadb4bb4573ed3dd121c24e3bd40a00873e29f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1854778
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Some devices (like the keyboard, CBI) need I2C access pretty early.
Until now I2C would get initialized pretty late in a hook, which was far
too late for some stuff.
As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init()
function will be called at board boot. Some chips (cr50, host tests)
needed a stub i2c_init in order to compile cleanly.
BUG=b/138384267
TEST=EFS doesn't happen significantly later than it used to
TEST=Recovery keys now work with I2C keyboard on jacuzzi
TEST=make buildall
TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety
of ECs:
* ampton (ite EC, x86 AP)
* bobba (npcx EC, x86 AP)
* jacuzzi (stm32f0 EC, ARM AP)
* cheza (npcx EC, ARM AP)
BRANCH=master
Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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During code review for tgl rvp enablement, found some hpet timer
related unused irq defines, so cleanup them.
BUG=b:141519691
BRANCH=none
TEST=successfully compile for arcada
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: Ieb6872d6633be8c5e9f38a4642f874db4201403e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1871247
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
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Since pinhold will hold UART pin, UART won't work correctly. In this
case, we want to delay uart_init() done until pinhold is disengaged.
The messages to UART are still kept in the UART buffer and can be
correctly printed through UART after pinhold is released.
BUG=b:138327854
BRANCH=none
TEST=manual
Testing: verified that after cold or warm reset, messages from RW image
can be correctly printed to UART. Without this change, we might see
incomplete messages or garbage characters.
Change-Id: I00934aa16178b995d996f6ba773abab80f329124
Signed-off-by: Pai Peng <paipeng@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1717547
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Fixed a bug that RELOAD bit not cleared properly when there's two
consecutive chip_i2c_xfer() calls, where the first call only contains
"write" transaction, and the second call contains a "read" transaction.
BUG=b:138095176
TEST=Case 1 - write and read in two separate i2c_xfer call:
`ectool i2cxfer 1 0x55 8 0x64`
On Krane, this should print the string "L16D2P31" in hex.
Case 2 - no write and read 1 byte:
`i2cscan` in ec console.
BRANCH=kukui
Change-Id: I57c1909058606b458801b3b35f54c16c1309c594
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866222
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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