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* mec1322/timer: Unroll udelayDaisuke Nojiri2022-03-281-0/+11
| | | | | | | | | | | | | | | | This patch flattens udelay by unrolling __hw_clock_source_read. This increases the chance that we record LR of the instruction near which an infinite loop happened. BUG=b:218982018,b:200593658 BRANCH= TEST=buildall Change-Id: I8127e9a3308c161fd064e78048d82972bb57e464 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit f0a9a2701fee604ec721b6a23173cec12cd8f4f0) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508423
* npcx/timer: Unroll udelayDaisuke Nojiri2022-03-281-0/+21
| | | | | | | | | | | | | | | | | This patch flattens udelay by unrolling __hw_clock_source_read. This increases the chance that we record LR of the instruction near which an infinite loop happened. BUG=b:218982018,b:200593658 BRANCH= TEST=Sona. Run crash assert. Hack battery command to trigger WD reset. Verify LR points to the root causes. Change-Id: Ibd6cbcf18ab6d58c06ddfd19021058268289bf00 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cc1d30dd2bd3b92d29f5ffb942d016bc207e2ad0) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508422
* Rename Cortex-M MMFS to CFSRPeter Marheine2022-03-281-6/+6
| | | | | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=b:218982018 BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org> (cherry picked from commit 124b2a8654b1bca281277b581fb79daeb1bdadde) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457944
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-171-1/+3
| | | | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit c2c2c083fef813e3e3c70f8c13a1418717ba682d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107292
* npcx: lpc: don't set SHCFG[7:5] in the driver's initializationCHLin2019-08-181-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In older Nuvoton EC chips (prior NPCX5), the Semaphore register is mapped to offset 0 of the Shared RAM Window by default. We usually disable it in the driver by setting SHCFG[7:6] both to 1 if we want to disable the Semaphore mechanism. However, in NPCX5 and later chips, this behavior is deprecated (the Semaphore register is not mapped to offset 0 of the Shared RAM Window by default). These bits (including bit 5) were removed. The driver should keep these bits at their default state. Otherwise, the Semaphore mechanism may not work as expected. BRANCH=none BUG=b:73018524 TEST=pass make buildall. TEST=build and flash reef/grunt/yorp image, stress test the host command and host event, no symptom occurs. Change-Id: I63031f3957d0485f18fb8c4f1b13ad56c2dc5804 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1383675 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692376 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org>
* cr50: Add extern "C" to headers used by future fuzzing target.Allen Webb2018-11-153-0/+23
| | | | | | | | | | | BRANCH=None BUG=None TEST=make -j buildall Change-Id: Icf2cfb6a2657064c10721c0e527d24fbb3be6ab3 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1330102 Reviewed-by: Mike Frysinger <vapier@chromium.org>
* ish gpio: GPIO functionalityli feng2018-11-152-3/+120
| | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=Tested on Atlas board, ISH GPIO is working. Change-Id: I29121dd143a5bf44a7431d12d9e05a3510fb4654 Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/954718 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/npcx: Default output the i2c_recovery() error messageZhuohao Lee2018-11-141-2/+3
| | | | | | | | | | | | | | | | | | | The i2c_recovery() will be called if the i2c bus error is detected. This is an serious error handling and may be caused by the slave which doesn't follow the spec. We should output this error message to let developer catch this error at the beginning like proto stage. BUG=b:118063849 BRANCH=master TEST=error message popped out on Nami and Rammus Change-Id: I4996cd18415d6ee4c5cd48ac374252a2230628b0 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1331249 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish gpio: added GPIO interrupt to IOAPICli feng2018-11-132-1/+11
| | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=none Change-Id: I3d6883554393c1733a902eff8ea3680ec9de33e1 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/884604 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cr50: enable ITE CCD programmingVadim Bendebury2018-11-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support of ITE EC programming by Cr50. ITE EC sync sequence generator implementation is being added to the image, I2C RX and TX queue sizes are increased to be able to accommodate messages sent during programming session. Board level callback function is provided to request ITE SYNC sequence generation on the next boot, and to reset the H1 with a 10 ms delay, necessary for CCD host USB communications to quiesce. Board startup code is modified to when requested invoke function generating ITE SYNC sequence early in the boot before jitter configuration is locked. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263898 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add ITE EC flash programming capabilityVadim Bendebury2018-11-053-0/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a callback function which triggers generation of the ITE EC programming sequence by the H1. It is going to be the board's code responsibility to configure ITE SYNC mode at startup and then reset the H1. The expectation is that when booting after reset the ITE SYNC sequence would be generated before clock jitter is configured and locked. ITE SYNC is a mode when soon after EC reset for duration of at least 20 ms the I2C master generates 200 KHz clock of the SDA line and 100 KHz clock on the SCL line, locked in phase, with 10% frequency variation tolerance. To be able to generate a stable 200 KHz clock jitter has to be disabled, and the actual clock generation function needs to be written in assembler, as this allows for the most accurate clock frequency tuning. The H1 GPIO controller allows to set multiple GPIO pins to requested values in one 32 bit transaction. The C function maps I2C interface directly to the GPIOs, prepares the address of the register to use to control the GPIOs and the values to write to generate all four combinations of the two signals: 00, 01, 10, 11. Then it invokes the assembler function to actually generate the clocks, and then re-enables the clock jitter. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: Iac33c9bab68fc1ab919d960291176195a08f1791 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263901 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: provide API to disable clock jitterVadim Bendebury2018-11-052-32/+61
| | | | | | | | | | | | | | | | | | | | | | | Sometimes it is necessary to disable clock jitter, this patch introduces a new chip API which would allow to do just that. Actual disable is possible only if the chip is not yet running on lowered security level. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable clock jitter during startup to be able to generate ITE SYNC sequence. Also observed expected console output, like: [0.007225 init_jittery_clock_locking_optional: run level high, \ request to enable] Change-Id: I624d781a961cdc17749de4fa80fad0f682537e01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1305117 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: gpio: implement the gpio_get_flags_by_mask functionCHLin2018-11-051-3/+85
| | | | | | | | | | | | | | | | | | | | This CL adds the gpio_get_flags_by_mask function which is used to get the flag information of a GPIO when CONFIG_CMD_GPIO_EXTENDED is enabled. BRANCH=none BUG=b:118390658 TEST=No build error for make buildall. TEST=Enable CONFIG_CMD_GPIO_EXTENDED in npcx7_evb/board.h; modify flags of GPIOs in gpio.inc to cover all the flags required to be shown in print_gpio_info(); check the result of "gpioget" is consistent with what is set in the gpio.inc. Change-Id: Icb17e59f959c0d15e95023f27187972f690d88ce Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1312515 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* NPCX: Fix for alternate GPIOs on the NPCX7Diana Z2018-11-051-2/+4
| | | | | | | | | | | | | | | During a recent naming change to the alternate GPIO tables, a few of the pins for the NPCX7 were missed. This change adds those pins back in. BRANCH=None BUG=b:118856402 TEST=builds, verified bobba USB 2.0 on DB type-c port works now Change-Id: Id3f3fa086b24da37eeeb49c5f4b24ffd4a5cfd6f Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1315628 Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* kukui/emmc: Share EXTI15 interrupt between SPI and eMMCNicolas Boichat2018-10-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | We never need to have interrupts enabled on both SPI1_NSS and EMMC_CMD, so we can actually share the interrupt selection EXTI15 between the 2 pins. This frees up PA14 (and EXTI14) for future interrupt needs. To make sure that we can answer host commands as soon as the AP as booted, we quickly poll for the eMMC bootblock switch to turn away from EC, and switch interrupt from eMMC to SPI. Also, we clear exit_events in chip/stm32/gpio.c, so that we do not report a override warning if we disable then re-enable another interrupt on the same EXTI. BRANCH=none BUG=b:113370127 TEST=Boot kukui rev1, check that EC commands works after boot Change-Id: Ib1f0a56a9f37e1bda01dc4e6b55734196bb3ff50 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1195345 Reviewed-by: Yilun Lin <yllin@chromium.org>
* npcx: gpio: fix bugs of low voltage level selectionCHLin2018-10-302-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL fixed the following bugs of low voltage support of GPIO: 1. fix the mismatch issue of low voltage support GPIOs when the mask passed to gpio_low_voltage_level_sel() has multiple bits set. (see more detail in the bug:118443060.) The idea is to create a new function gpio_low_vol_sel_by_mask() to iterate the match for each bit set in the mask. i.e. while (lv_mask) { bit = get_next_bit(&lv_mask); gpio_low_voltage_level_sel(p, bit, low_vol); }; The second parameter of gpio_match()/gpio_low_voltage_level_sel is also changed from "mask" to "bit" because of above modification. 2. It was observed that there are some errors of the low level mapping table because the older datasheet we used to develop the driver is not correct. After checking the latest datasheets of all EC sku, the low level table should have the following modification: - GPIO65 cannot support low level and should be removed. - GPIO86 can support low level in all EC skus. BRANCH=none BUG=b:118443060 TEST=Add GPIO_SEL_1P8V flag in the ALTERNATE macros which have multiple bits set in the mask field in npcx7_evb board. Flash the image and make sure the warning message doesn't print and the related low level bits are set. Change-Id: I7aa23eb42dda178db34fe44a663df29757910a55 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1301674 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* npcx: add console command to better investigate power consumption of GPIOsCHLin2018-10-301-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the console command to disable the input buffer of non-I2C and non-ISR GPIOs which are configured as either input or open-drain. The GPIOs set as 1.8V are also ignored because they are already disabled in the gpio_pre_init. Usage: 1. type "gpiodisable next" to disable the input buffer of next GPIO wihch is either input or open drain in the gpio list. (if the next one is I2C or 1.8V or ((!input) && (!open-drain)), it will ignore it and check the following next one). Ex: > gpiodisable next current GPIO : 16 LID_ACCEL_INT_L --> Ignore 1v8 pin! current GPIO : 17 PLT_RST_L --> Disable WKINEN! > gpiodisable next current GPIO : 18 SYS_RESET_L --> Disable WKINEN! > gpiodisable next current GPIO : 19 ENTERING_RW --> Not Input or OpenDrain current GPIO : 20 PCH_WAKE_L --> Disable WKINEN! ......... ......... > gpiodisable next current GPIO : 34 I2C0_SCL --> Ignore I2C pin! current GPIO : 35 I2C0_SDA --> Ignore I2C pin! current GPIO : 36 I2C1_SCL --> Ignore I2C pin! current GPIO : 37 I2C1_SDA --> Ignore I2C pin! current GPIO : 38 I2C2_SCL --> Ignore I2C pin! current GPIO : 39 I2C2_SDA --> Ignore I2C pin! current GPIO : 40 I2C3_SCL --> Ignore I2C pin! current GPIO : 41 I2C3_SDA --> Ignore I2C pin! current GPIO : 42 I2C4_SCL --> Ignore I2C pin! current GPIO : 43 I2C4_SDA --> Ignore I2C pin! current GPIO : 44 I2C7_SCL --> Ignore I2C pin! current GPIO : 45 I2C7_SDA --> Ignore I2C pin! current GPIO : 46 EN_USB_A0_5V --> Not Input or OpenDrain current GPIO : 47 EN_USB_A1_5V --> Not Input or OpenDrain current GPIO : 48 USB_A0_CHARGE_EN_L --> Not Input or OpenDrain current GPIO : 49 USB_A1_CHARGE_EN_L --> Not Input or OpenDrain current GPIO : 50 USB_C0_BC12_VBUS_ON --> Not Input or OpenDrain current GPIO : 51 USB_C0_BC12_CHG_DET_L --> Disable WKINEN! 2. Enable/Disable a specific GPIO's input buffer by "gpiodisable ${GPIO_NUM_IN_LIST} on|off" (use "gpiodisable list" can check the GPIO_NUM_IN_LIST of a GPIO) Ex: > gpiodisable list 16: LID_ACCEL_INT_L 17: PLT_RST_L 18: SYS_RESET_L ...... ...... > gpiodisable 17 off --> disable input buffer of GPIO PLT_RST_L > gpiodisable 17 on --> enable input buffer of GPIO PLT_RST_L BRANCH=none BUG=b:117139495 TEST=No build errors for "make buildall". TEST=Manually run the console commands and check the result as expected. Change-Id: I7c750804cf45218a3ab1baacefcda64833861b1f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1275765 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_hid_keyboard: keycode column and row are switchedWei-Han Chen2018-10-301-1/+1
| | | | | | | | | | | | | | | columns and rows of keycodes array are switched in CL:1285291. BRANCH=none BUG=None TEST=test on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I98b28a0765d011a9085202ab3250cd2d9aa85ccd Reviewed-on: https://chromium-review.googlesource.com/1304160 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* system: Remember if reset was due to AP watchdog triggeringNicolas Boichat2018-10-291-0/+32
| | | | | | | | | | | | | | | | | On MT8183, when EC detects a watchdog reset, EC needs to reboot itself in preparation for the next boot. This means that AP loses the reset cause (as AP system reset is toggled), and, therefore, we need to save the reset reason in the EC. BRANCH=none BUG=b:109900671 TEST=apshutdown, powerb, see that reset reason is: reset-pin TEST=Use test-wd from bug. Reset reason: reset-pin ap-watchdog Change-Id: I2e30306db5727a22de930f00dc30de40b9695bef Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1295890 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: gpio: support internal pull-down when enable low voltage modeCHLin2018-10-261-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is the limitation that internal pull-up must be disabled when a GPIO is configured in low voltage level. However, thers is no such limitation of internal pull-down. The current GPIO driver disable no matter pull-up or pull-down when low voltage mode is set. This CL fixes it by: 1. enable internal PD when low voltage mode is set. 2. print warning message in the UART console when both low voltage and internal PU flags are set for any GPIO defined in gpio.inc. BRANCH=none BUG=b:118339468 TEST=No build error for make buildall TEST=define a gpio with internal PD+low-voltage in npcx7_evb/gpio.inc, check the releated bits of PxPULL and PxPUD are set; TEST=define a gpio with internal PU+low-voltage, check the warning message is printed on the console. Change-Id: I8e15125d3a2ccc73f84b8a559d12644b1d1af5f9 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1297872 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: gpio: refactor the composition of pinmux tableCHLin2018-10-252-365/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some GPIOs in npcx chips supprt more than one alternative functions. The current GPIO driver defines a macro for a specific alternative funtion and add it in the alternative function table. If two this kind of alternative macros which are belong to the same GPIO are defined and added to the table, it wiil casue the conflict of pinmux setting. Ex: #define NPCX_ALT_I2S_SYNC ALT(A, 5, NPCX_ALT(E, I2S_SL)) #define NPCX_ALT_SPIP_CS1 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) This CL refactors the macro's definition by using the name of GPIO rather than the alternative fucntion of it. Which altenative fucntion related to the GPIO depends on which module is configured. Ex: #if defined(NPCX_WOV_SUPPORT) && defined(CONFIG_WAKE_ON_VOICE) #define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(E, I2S_SL)) /* I2S_SYNC */ #else #define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1 */ #endif This can prevent from the conflict pinmux setting because there will be the compilier error if the same macro is redefined. BRANCH=none BUG=b:117768182 TEST=No build error for make buildall TEST= Test alternative functions like I2C/keyboard/UART/WoV on yorp/grunt/poppy/npcx7_evb/npcx_evb. Change-Id: I7ca191a2199c4244f373720fb5c3c4e6af428c64 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1282531 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* it83xx/clock: turn off VCC before changing PLLDino Li2018-10-232-0/+15
| | | | | | | | | | | | | | | | | | | | | | | Symptom: On Ampton board, EC's clock frequency is not correct after changing PLL sequence. We have added a workaround to fix changing PLL failure issue while CS# pin's level is low, but it does not fix the issue on the DX version. We need to turn off VCC power to fix this issue on the DX. BUG=b:70537592 BRANCH=none TEST=EC clock frequency is correct on DX version after changing PLL sequence. Change-Id: Id2f507d6b15da40bab178f2754c7b11d64ff5ddf Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1293133 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Keyboard: Allow keyboard size to be set at run timeDaisuke Nojiri2018-10-195-6/+6
| | | | | | | | | | | | | | | | | | | | | | | Currently, the keyboard size (i.e. number of columns) is static. This patch allows it to be configured at run time. It's required to support a keyboard with/without keypad in a single image. KEYBOARD_COLS_MAX has the build time col size. It's used to allocate exact spaces for arrays. Actual keyboard scanning is done using keyboard_cols, which holds a runtime col size. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona and Veyron. Change-Id: I4b3552be0b4b315c3fe5a6884cf25e10aba8be7c Reviewed-on: https://chromium-review.googlesource.com/1285292 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/stm32/usb_hw: include stdint.h and stddef.hPatrick Georgi2018-10-191-0/+3
| | | | | | | | | | | | | | | It uses it, and its includers shouldn't need to know that. BUG=none BRANCH=none TEST=none Change-Id: Icf13d558e4d0772841a06313b352f88d40f1e165 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177709 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* Keyboard: switch column and row of scancode tableDaisuke Nojiri2018-10-191-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches column and row of scancode_set2. That is, scancode_set2[ROWS][COLS] = {0x00, 0x01, 0x02, ..., 0x10, 0x11, ..., 0x20, ..., becomes scancode_set2[COLS][ROWS] = {0x00, 0x10, 0x20, ..., 0x01, 0x11, ..., 0x02, ..., This will allow us to extend the table for a keypad without losing too much readability. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona. Change-Id: I49a7c0796d5c91989f1d3686c80743fb4bcd5ba7 Reviewed-on: https://chromium-review.googlesource.com/1285291 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: gpio: gpio macro addedli feng2018-10-192-3/+7
| | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=Tested on Atlas board with ISH. Change-Id: I6b3913d2374e68e9522927ad5609f2867cc56f34 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/885007 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Li1 Feng <li1.feng@intel.com>
* g: allow i2cm transactions of arbitrary lengthVadim Bendebury2018-10-161-131/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Programming ITE EC over CCD is a very tedious process, with a huge overhead imposed by encapsulating I2C traffic in USB packets. On top of that actual writing into the flash must happen in a single transaction passing a full flash page (256 bytes) worth of data. To accommodate this the I2C master driver needs to be modified to send I2C transactions longer than the I2C controller's FIFO capacity of 64 bytes. This patch makes necessary changes and simplifies the driver, even if making it a little less efficient: the modified driver does not use the FW block of the controller, which allowed to program up to for bytes to transmit before actually getting to transmit from or receive to the FIFO. All transfers now involve FIFO and there is always a full stop/start between a write and the following read, as opposed to a single restart issued before in case the write was 4 bytes or less. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: I589ac33faa33764458d9aee03e74af81be637908 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263900
* chip/g: Convert usb_endpoints to C so gcc's LTO knows about itPatrick Georgi2018-10-162-107/+158
| | | | | | | | | | | | | | | | | | | | | | If we keep it assembly-only, the link time optimizer gets confused and eliminates seemingly unused functions, to then replace references to them with the "no handler" defaults in a later step. Similar approach as with vecttable: Implement the table in C so LTO knows the entire story. BUG=b:65441143 BRANCH=none TEST=usb_ep_{rx,tx,reset} and usb_iface_request look more reasonable in disassembly on cr50. Change-Id: I72103af742164c29aac38e9929d1a83d8c154b53 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177711 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* chip/stm32: Convert usb_endpoints to C so gcc's LTO knows about itPatrick Georgi2018-10-162-108/+169
| | | | | | | | | | | | | | | | | | | | | | If we keep it assembly-only, the link time optimizer gets confused and eliminates seemingly unused functions, to then replace references to them with the "no handler" defaults in a later step. Similar approach as with vecttable: Implement the table in C so LTO knows the entire story. BUG=b:65441143 BRANCH=none TEST=usb_ep_{rx,tx,event} and usb_iface_request look more reasonable in disassembly on whiskers. Change-Id: I35ccfd68cda2d0022aa464ecf622f4eef71c3398 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177710 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* cr50: Only allow SN hash to be written if board ID is not set.Louis Collard2018-10-121-1/+14
| | | | | | | | | | | | | | | This should restrict SN hash such that is can only be written at factory (before board id), with the exception of some edge cases where devices that have left factory do not have a board id set. BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I2ae39e2db4b1a01ec5ec9855634357434f01020b Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1237696 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* chip/stm32/usb_hid_keyboard: Reload keyboard endpoint on resetNicolas Boichat2018-10-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | After the USB device is reset, force sending the keyboard data at least once to make sure the host is aware of the curreny key/switches status. In particular, this is necessary for the host to be aware that we are in tablet mode on host boot (this is not a problem on attach, as other routines in the EC init sequence cause the endpoint to be loaded anyway). BRANCH=nocturne BUG=b:117439202 TEST=Reboot nocturne with whiskers attached in tablet mode, see that nocturne is still in tablet mode after reboot: evtest --query /dev/input/event6 EV_SW SW_TABLET_MODE; echo $? => 10 Change-Id: I4b0e20a9f78c5262d7effd8bd37ace0d033b3f5a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1270297 Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
* g: update test RO to allow self-signed RWs.Marius Schilder2018-10-043-55/+18
| | | | | | | | | | | | | | | | | Instead of hard-coded embedded public keys, use public key from header. Also accommodate padding checks for both 3071 and 2048 signatures. BUG=none BRANCH=none TEST="make board=cr50;vhaven build/cr50/ec.hex --sku 2 --debug_rom" now successfully boots to console. Signed-off-by: mschilder@google.com Change-Id: I493d4832d4b78c734949fe980ef5c9de2d3e4fa1 Reviewed-on: https://chromium-review.googlesource.com/1256058 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Make ADCs on STM32F4 workMoritz Fischer2018-09-284-8/+26
| | | | | | | | | | | | | | | | | | Make ADCs on STM32F4 chips work by reusing most of the STM32F3 code with the addition of SWSTART=1 bit in adc_read_channel. The SWSTART=1 is most likely also required for the F3, but could not be tested on actual hardware. BUG=none BRANCH=master TEST=Build for nucleo-411RE and check measurements Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Change-Id: Iea4f961b22119b5f2c1ee71295ec3ef1b7b7232c Reviewed-on: https://chromium-review.googlesource.com/1217603 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Refactor ADC clock enable for STM32F0/F3Moritz Fischer2018-09-274-2/+14
| | | | | | | | | | | | | | Refactor ADC clock enable code to use clock_module_enable() BUG=none BRANCH=master TEST=Build and run on discovery-stm32f072 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Change-Id: Id3e8852fd5dd2fe47351dd9b9f84b0be9fb82dda Reviewed-on: https://chromium-review.googlesource.com/1217602 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: Check WP_IF for internal flash before writing status registerFurquan Shaikh2018-09-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of internal flash, WP_IF needs to be checked to determine if it is okay to write status register. WP_IF is R/W1S, hence once it is set, it gets cleared only on core domain reset. Thus, it is necessary to reboot EC on WP de-assertion before any attempt to write status register is made. This change checks to ensure that internal flash is not protected based on the state of WP_IF bit in DEV_CTL4 before writing status register. BUG=b:115983409 BRANCH=None TEST=Verified following: 1. Attempt to write status register without rebooting EC: a. Disable WP b. flashrom -p ec --wp-disable ---> Reports failure back to host 2. Attempt to write status register after rebooting EC: a. Disable WP b. Reboot EC c. flashrom -p ec --wp-disable ---> Reports success and SW WP is successfully disabled. Change-Id: I2a89ecfc0bed824d5e75110f00b060980627dd33 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1248481 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Sanna Fnu <fnu.sanna@intel.corp-partner.google.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* stm32h7: Use high performance voltage scaler before clock upDaisuke Nojiri2018-09-272-0/+15
| | | | | | | | | | | | | | | | | | | | This patch switches the voltage scaler to VOS1 before increasing the clock speed (PLL) and switches it back to VOS3 after reducing the clock speed (HSI). BUG=b:114520154 BRANCH=none TEST=Enroll and match fingerprint on Nocturne without exceptions. Change-Id: Ie369a382bab76efb090ca5fecf2cdb5fd05e0575 Reviewed-on: https://chromium-review.googlesource.com/1246832 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit e1f0d3b50bfa30abd2d2aa1a1aee1456bb049662) Reviewed-on: https://chromium-review.googlesource.com/1249721 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: add config for reading observation register of external timer issuetim2018-09-264-22/+20
| | | | | | | | | | | | | | | | | | | | | In IT8320 BX version, there is a chance of failure in reading external timer observation register. We are using the time delay of CPU in order to read register twice that can avoid the bug of reading time failure when CPU and EC are counting at the same time. There will be once successful read. The bug has been fixed in the later version of chip. BUG=none BRANCH=none TEST=Ensure the observation register of external timer will be read successful in IT8320 DX chip. Change-Id: I0ec2d0bb83afd1549118de9383dc16cf5adb6b5a Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1215523 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_hid_touchpad: fix logical max of width & heightWei-Han Chen2018-09-261-1/+1
| | | | | | | | | | | | | | | | Width and Height are 12 bits in USB HID descriptor. But the logical maximum was set to 255. Also scale up width and height reported by ST firmware. BRANCH=nocturne BUG=none TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I899af2b18120d9e877d45e1dc2c14404a412797b Reviewed-on: https://chromium-review.googlesource.com/1232798 Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32h7/nocturne_fp: Enable RDP level 1, tie it to flash protection statusNicolas Boichat2018-09-222-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent flash readout, using RDP field in option byte. When RDP is defined, it makes no sense to be able to unlock RO, as that'd allow flashing arbitrary RO that could read back the rest of the flash, so we just tie EC_FLASH_PROTECT_RO_AT_BOOT and RDP protection. This also means we can't unlock the flash after it has been finalized (without removing WP and using BOOT0/stm32mon to mass erase the chip). Also, in flash_mp_mcu, call stm32mon with -U, to unlock flash for read-back first (which disables RDP and triggers a mass erase if RDP was enabled). Finally, load spidev before putting releasing reset, which makes reflashing more reliable. BRANCH=nocturne BUG=b:111330723 TEST=cp flash_mp_mcu read_mp_mcu, replace stm32mon line with: "stm32mon -u -p -s ${SPIDEV} -r rb.bin" dut-control fw_wp_state:force_off => Check that read_mp_mcu works dut-control fw_wp_state:force_on ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec => RDP is now on dut-control fw_wp_state:force_off => Check that read_mp_mcu does not work anymore TEST=Add -U to stm32mon line above in read_mp_mcu, check that readback only gets blank data. TEST=In EC console, check that RDP bits are indeed not 0xaa: Before: rw 0x5200201c => 0x07d6aaf0 After: rw 0x5200201c => 0x07d600f0 TEST=flash_mp_mcu still works (does a flash erase that removes RDP protection) Change-Id: Ifbe37ecafbf23f48d4a3cc17933130b7b104b728 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1222094 Commit-Ready: Nicolas Norvez <norvez@chromium.org> Tested-by: Nicolas Norvez <norvez@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* npcx: Don't clear IBBR bit via a read-modify-write sequenceCHLin2018-09-212-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx5/npcx7m6g/npcx7m6f, clearing the IBBR bit in the BKUP_STS register is not hazardous because the register only implements the IBBR bit. In npcx7m6fb/npcx7m7wb, the register implements two more bits (VSBY_STS/VCC1_STS). Using read-modify-write operation to clear IBBR bit will also clear these two bits unexpected if they are set. It is fine at this time because the firmware does not rely on these two new bits for any purpose. But it will be better to change it in case these two bits are used in the future. This CL also clears VSBY_STS/VCC1_STS bit (for npcx7m6fb/npcx7m7wb) when power-on reset. BRANCH=none BUG=none TEST=No build error for make buildall; Check IBBR(VSBY_STS/VCC1_STS) are cleared at initial when power-on reset. Check warining messages are printed and IBBR bit is cleared (in function system_check_bbram_on_reset and bbram_valid). Change-Id: I6dc1f5d7f35f9d591db62d1b022ea7b8d92f5b92 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1235733 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* g: fix i2cm NACK processingVadim Bendebury2018-09-201-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When g i2c master controller encounters a NACK it seems to stop processing instruction set included in the INST register and leaves SCL low holding up the bus. Issuing an explicit STOP request in this situation makes sure that the controller completes the NACKed access cycle. BRANCH=cr50, cr50-mp BUG=b:112283593, b:113906660 TEST=verified that when running i2cscan the NACKed cycles complete properly, and the command could be ram multiple times. On dragonegg: > i2csc Scanning 0 master................................................. 0x60................ 0x80. 0x82. 0x84. 0x86............. 0xa0............................................... > i2csc Scanning 0 master................................................. 0x60................ 0x80. 0x82. 0x84. 0x86............. 0xa0............................................... > Change-Id: I7ffff5f32c9f57eb2672318fc8ebd9f74441445d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200078 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* it83xx/fpu: fix floating-point multiplication issue for DX version.Dino Li2018-09-172-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Floating-point multiplication single-precision is failed on DX version, so we use the formula "A/(1/B)" to replace a multiplication operation (A*B = A/(1/B)). BUG=b:112452221 BRANCH=none TEST=add a console command and test different scenarios by changing variable a and b. static int it83xx_fpu_mul(int argc, char **argv) { volatile float a = 1.23f; volatile float b = 4.56f; volatile float c; c = a * b; ccprintf("__mulsf3: (%d)\n", PRINTF_FLOAT(c)); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(mul, it83xx_fpu_mul, "", ""); Change-Id: I9e7d8477cf517b8df2975df9abb02a6387dc659b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1201640 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* flash: Add CONFIG_FLASH_READOUT_PROTECTION config optionNicolas Boichat2018-09-142-2/+2
| | | | | | | | | | | | | | Instead of tying together CONFIG_WP_ALWAYS and RDP protection, separate the options. BRANCH=nocturne BUG=b:111330723 TEST=make buildall -j Change-Id: I905b573a900ef4dd0431666c525c951582143e09 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1222093 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7: Report PSL_CTS on wake from hibernateFurquan Shaikh2018-09-141-0/+14
| | | | | | | | | | | | | | | | This is useful when debugging random wake issues from PSL hibernate to identify the actual cause of wake. BUG=b:115664415 BRANCH=None TEST=make -j buildall Change-Id: Id35be96aef2d73426781d0bf88bf5f6268bc3b6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1225353 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ite: Add support for 3rd Type C port in bbramScott Collyer2018-09-132-2/+5
| | | | | | | | | | | | | | | | | DragonEgg has 3 Type C ports and needs BRAM_IDX_PD2 as only 2 ports were supproted previously. BUG=b:111281797 BRANCH=none TEST=Verfied that error messages from invalid bram_idx went away. Change-Id: I242850a89413f0a573155e5e325f4e0a540d33e6 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178996 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Change sleep in flash_wait_ready to 10usecFurquan Shaikh2018-09-071-15/+14
| | | | | | | | | | | | | | | | | | | | | | | flash_wait_ready had a sleep of 1 msec to check for busy bit status. This is too long of a wait for flash chip operation to complete and hence adds unnecessary delay during flash write. Changing the delay to 10usec helps cut the flash write time by 50%. This change reduces the delay to check busy bit to 10usec and also organizes the code slightly differently to use timestamp_expired() instead of decrementing timeout and checking it against 0. BUG=b:113530328 BRANCH=nocturne,grunt TEST=Verified that EC SW sync time is down to 3.4 seconds with this change. Change-Id: I5796ac3c493031c9623a9e5171ce9c5a7087089e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1213553 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: add TCPC RX circular buffer in ECJett Rink2018-09-071-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The alert line for TCPC will stay asserted as long as there are RX messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear all of the RX messages we know about during a single alert handling session. This CL can stand on its own, but it is a part of a CL stack that will tighten the critical section of time between received messages from the TCPC and sending follow up message out through the TCPC. See go/usb-pd-slow-response-time for more details. BRANCH=none BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761 BUG=b:113057273,b:112825261 TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to adversely affect state machine negotiation. Full CL stack consistently sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the 24 ms threshold we need to be under for USB PD spec compliance. Also testing pd_suspend scenario manually and EC was responsive after port 1 suspend because of "bad behavior" Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185727
* common: flash and nvmem fixes for compatibility with the host board.Allen Webb2018-09-071-1/+3
| | | | | | | | | | | | | | | | | | This CL 1) Forces alignment of __host_flash so it can be used with nvcounter 2) Disables a compile time check for the host board that failes because the host board uses a variable to emulate flash memory. 3) Disables nvmem_vars console commands that are specific to a unit test for fuzzing targets. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests (with cr50_fuzz CL) Change-Id: Id6257132d8f2dd73ae07e796efd0da3df83b30d6 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1183533 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host: Add dcrypto definitions that can be used by fuzzing targets.Allen Webb2018-09-078-0/+161
| | | | | | | | | | | | | | | | These definitions provide the necessary dcrypto functionality for fuzzing pinweaver. They can be built out as needed to support further fuzzing. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests && ./build/host/cr50_fuzz/cr50_fuzz.exe (with the cr50_fuzz CL) Change-Id: I36ce874efab5dbc59825d126f6079b7b6d0da9ef Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180573 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Decide erase size based on ro/rw region sizeFurquan Shaikh2018-09-055-10/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the erase operation in npcx chip to use 64k/32k/4k block erase depending upon the alignment of CONFIG_RO_SIZE. This helps reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7. Ideally, we would want to check the offset and size of region to be erased dynamically and decide which erase operation to use. However, common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure that the area being erased is aligned to that size. Thus, even if we add dynamic erase at chip level, it isn't going to help. This change also updates CONFIG_FLASH_BANK_SIZE to be the same as CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be a safe change. On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the write time as well, thus overall helping with the EC SW Sync time. Please see go/cros-npcx7-ec-sw-sync for more details. BUG=b:113530328 BRANCH=nocturne TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4 seconds. Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1195598 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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