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* cleanup: Update more TODO commentsRandall Spangler2013-11-011-6/+7
| | | | | | | | | | | | | | | Add bug links, reword, or remove as applicable. No code changes, just comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175326 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Fix a bug that GPIO cannot be set as input on stm32lVic Yang2013-09-041-1/+1
| | | | | | | | | | | | | | | | | GPIO_INPUT is defined as 0, and any GPIO flag cannot be examined against GPIO_INPUT. Change GPIO_INPUT to non-zero value to avoid this. BUG=chrome-os-partner:22275 TEST=On Kirby, set a GPIO to output and pull it low, and then set it back to input. Check it can be pull high externally. TEST=Build all boards. TEST=Boot link and spring. BRANCH=None (unless this bug hits some other boards.) Change-Id: I84b9936c24af538ac59c36129fda27ca879bf9d1 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167190 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up configuring GPIO alternate functionsRandall Spangler2013-08-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO alternate functions used to be configured throughout the code, which made it hard to tell which ones you needed to configure yourself in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being configured as alternate functions even if they weren't used on a given board. With this change, every board has a table in board.c which lists ALL GPIOs which have alternate functions. This is now the only place where alternate functions are configured. Each module then calls gpio_init_module() to set up its GPIOs. This also fixes a bug where gpio_set_flags() ignored most of the flags passed to it (only direction and level were actually used). On stm32f, gpio_set_alternate() does not exist, and pins are configured via direct register writes from board.c. Rather than attempt to change that in the same CL, I've stubbed out gpio_set_alternate() for stm32f, and will fix the register writes in a follow-up CL. BUG=chrome-os-partner:21618 BRANCH=peppy (fixes I2C1 being initialized even though those pins are used for other things) TEST=boot link, falco, pit, spring Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64400
* Clean up SPI state machine and add state codesRandall Spangler2013-08-051-40/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | The old low-level SPI protocol provided no useful information to the host about whether it was ready to receive or not. It also could get stuck waiting to receive data without setting up receive DMA, if the host did two transactions back-to-back. Add a real state machine to the SPI module. Add a range of byte codes the EC can return outside of a response frame, to indicate its current state. If the AP receives one of these codes, it can abort the transaction since it now knows the EC is unable to determine when it can send a response frame. This change is backwards-compatible with current AP firmware and kernel drivers, since those only look for the framing byte and don't care what other bytes are received in the meantime. BUG=chrome-os-partner:20257 BRANCH=none TEST=crosec test; passes at 70us. Change-Id: Ia06109ead3fbc421848e01050f7baf753cbeb16c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64254 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Host commands don't set the response pointerRandall Spangler2013-08-021-5/+1
| | | | | | | | | | | | | | | | Remove support for allowing host command handlers to set the response pointer. This is just one more thing that can break (and did, on SPI protocol V2). No commands other than the trivial read-memory-map command in host_command.c and flash read made use of this capability, and the savings in performance was negligible. BUG=chrome-os-partner:21576 BRANCH=none TEST=boot pit; still boots Change-Id: I0a9bcf57dbea7155318fc389d7b47d3742a1a00a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64236
* pit: Align spi protocol buffers on 32-bit boundaryRandall Spangler2013-07-081-7/+11
| | | | | | | | | | | | | | | Flash writes must be done from 32-bit-aligned source buffers. Force the protcol buffer to be aligned like we do for the lpc interface. BUG=chrome-os-partner:20571 BRANCH=none TEST=ectool flashread 0x1f800 0x800 /tmp/foo ectool flasherase 0x1f800 0x800 ectool flashwrite 0x1f800 /tmp/foo Change-Id: Icaa3259bcbc36be49345da5e19ad8a0790b73923 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60892
* Move protocol v2 constants to ec_commands.hRandall Spangler2013-07-031-114/+90
| | | | | | | | | | | | | | | | These constants are scattered around the various interface implementations and should be in one place. This will also clean up the u-boot side when ec_commands.h is copied there. BUG=chrome-os-partner:20257 BRANCH=none TEST=build link, spring, pit; test 'ectool hello' Change-Id: Ib1425db00ec8220538d8c5c65107ac9548009516 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60810 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Add get-protocol-information commandRandall Spangler2013-07-021-12/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary to support larger packet sizes for host protocol ver.3. The host previously didn't have any way to know how big a packet the EC could accept / respond with (except on LPC, where the size is determined by the I/O window). BUG=chrome-os-partner:20257 BRANCH=none TEST='ectool protoinfo' returns good info; on link, Protocol info: protocol versions: 2 3 max request: 256 bytes max response: 256 bytes flags: 0x00000000 and on pit, Protocol info: protocol versions: 2 3 max request: 544 bytes max response: 544 bytes flags: 0x00000001 Change-Id: Ic1e3831d9b4a96ffbf365c0d09b6023472de39a9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60703 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Clean up DMA register usageRandall Spangler2013-06-271-13/+13
| | | | | | | | | | | | Bitfields are now in registers.h where they belong. BUG=chrome-os-partner:20529 BRANCH=none TEST='crosec test' from u-boot still works Change-Id: I726550a32b61111c906c1b10c628c5e47eff74fb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60179
* stm32: Clean up SPI register usageRandall Spangler2013-06-271-20/+7
| | | | | | | | | | | | | Bitfields are now in registers.h where they belong. BUG=chrome-os-partner:20529 BRANCH=none TEST='crosec test' from u-boot still works Change-Id: If0d79a66a90665c8ea336a006d76ccbc00a927ec Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60139 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Clean up DMA module and interface.Randall Spangler2013-06-261-5/+5
| | | | | | | | | | | | | | | | | | | | | | | Explicitly use enum for dma_channel, instead of ints (since channel is 1-based in the docs and 0-based in the enum). Add enum values for other channels like USART. Use volatile structs instead of typecasting through REG32(). Other assorted code cleanup. Remove DMA2 partial support, since neither STM32F100R8 nor STM32L151x has hardware support for it and it cluttered the code. No functional changes. BUG=chrome-os-partner:20485 BRANCH=none TEST=from pit root shell, 'ectool version' still works Change-Id: Ifdd62fb287c608a684ba8fa16934dfcab83ee609 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59949
* pit: Disable SPI output when AP is suspendedRandall Spangler2013-06-201-0/+2
| | | | | | | | | | | | | | | This fixes the problem where the EC consumes too much power during suspend. BUG=chrome-os-partner:20223 BRANCH=none TEST=from root shell, 'powerd_suspend'. 1.8V_MICOM should not go up. after resume, 'ectool hello' should still work. Change-Id: I93b781e96bea633419e923a83f1f6d7300ae8c54 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59474 Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Refactor host command interface to support version 3 packetsRandall Spangler2013-06-201-2/+100
| | | | | | | | | | | | | | | | | | | | | | | | | This will fix EC flash commands on pit, once the host side (u-boot and cros_ec driver) are upgraded to match. This change is backwards-compatible the EC still supports the existing version 2 protocols for talking to existing AP/kernel/ectool. Once the AP-side supports version 3 for SPI (and existing systems are upgraded), we will remove older SPI support since we haven't shipped a product which uses SPI. BUG=chrome-os-partner:20257 BRANCH=none TEST=disable cros_ec driver support in ectool; 'ectool hello' works on link And with an old ectool which predates this CL, 'ectool hello' also works. On pit, from u-boot prompt, 'crosec test' and 'crosec version' work, and keyboard works. Change-Id: I01f193e316e9aa442fe50d632dc8a4681723e282 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58908 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Doug Anderson <dianders@chromium.org>
* Set SPI lines to inputs when AP is offRandall Spangler2013-05-161-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When AP is off, turn off pullup on NSS, and set MISO to an input so the SPI module won't drive it high if the last sent bit was a 1. This reduces leakage when the AP is off. This patch also fixes a bug where gpio_set_alternate_function() set the wrong pins to normal-mode when func=-1; that didn't hit anything else because that functionality wasn't used on STM32 until now. BUG=chrome-os-partner:19304 BRANCH=none TEST=boot pit On EC console, with AP on, 'rw 0x40020000' returns read 0x40020000 = 0x6569aa20 <- must have 0x____aa__ Then 'apshutdown' and 'rw 0x40020000' returns read 0x40020000 = 0x65690020 <- must have 0x____00__ The 'power on' and AP turns back on. At u-boot prompt, 'sspi 2:0 256 9f00000000' returns FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001 (some number of 0xFD's followed by FEEC...) This shows SPI functionality is restored when AP is powered back on, and not just at init time. Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51182 Reviewed-by: Simon Glass <sjg@chromium.org>
* spi: Fix OOBE in bounds-checking the replyDoug Anderson2013-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | There was an off-by-one error in bounds checking the reply. You could trigger it with pydevi2c with: >>> tps = I2CDevice(20, 0x48, force=True) >>> tps.Get(0, 249) The EC would show: ASSERTION FAILURE 'msg_len < sizeof(out_msg)' in reply() at chip/stm32/spi.c:184 BUG=chrome-os-partner:18778 BRANCH=none TEST=Run the above commands and see no error. Change-Id: I9789405a9d70c5dc3fa237504fea8f46a139386c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50254 Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix and enable SPI for pitRandall Spangler2013-05-071-51/+29
| | | | | | | | | | | | | | | | | | | | | | | | | I've simplified the SPI module, since we only ever use SPI1 (and there were already a number of places which assumed this was true). Somewhere along the way I fixed a number of problems keeping the code from compiling and working on STM32L. The code isn't currently used anywhere else, but should still work there (that is, I don't think I broke it working on STM32F if you re-enable it on some STM32F platform). BUG=chrome-os-partner:19073 BRANCH=none TEST=from u-boot console, sspi 2:0 64 9f0000 u-boot prints: FDFDFDFDFDFDFDFD ec prints: [193.740912 HC 0x9f][193.741141 HC err 1] [sjg: gpio optimization back in for now] [dianders: add comment as rspangler requested; update SOBs] Change-Id: Ib9419403e4e44dadc1f17681e48401882cb49175 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49684
* Clean up daisy GPIO and SPI initRandall Spangler2013-04-081-1/+4
| | | | | | | | | | | | | | | Much of the board init duplicated stuff already done in gpio init, so remove it. Powering the SPI module should be done in spi.c, not board.c. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; boot EC on daisy Change-Id: I9a99eeeb971ebbf7de5b9c0548153684fbb7fff6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47469 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Export DMA memory size optionVic Yang2012-09-261-2/+18
| | | | | | | | | | | | | | We need different memory size configuration in different application. Let's export the memory size option to DMA function parameters. BUG=chrome-os-partner:14316 TEST=Boot on snow. Check I2C host command works. BRANCH=none Change-Id: I30481ddf86a1526d517961e009898642ecdd649a Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33981 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spi: Rewrite driver for new protocol, better performanceSimon Glass2012-09-171-124/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old spi driver has atrophied in various ways. It doesn't support the new protocol and does not build either. Rewrite the driver to: - Use dma for reception (rather than just reception) - This makes message reception more robust and allows us to process the new multi-byte commands - Add timeouts for rx and tx so that we don't wait forever - Increase buffer sizes to deal with new larger messages - Always send a preamble byte regardless of SPI clock speed (previously above 10MHz we sometimes miss this) - Use the NSS line to delineate transactions. When it drops, a transaction is starting. When it rises the transaction is immediately terminates regardless of state. This keeps the AP and EC in sync even in the event of timeouts, bus errors and other oddities. - Implement the new protocol which has a checksum, version byte, etc - Set up tx dma in advance and kick it when ready, thus ensuring that a message body is always attached immediately after the preamble - Use the new host_cmd_handle_args structure, which makes things much easier for us, since we don't need globals, and can use the send_response handler to know when a slow command is complete. - Handle the new type of 'slow' commands properly BUG=chrome-os-partner:10533 TEST=manual build and boot to kernel on snow Change-Id: I11767d1a6f045a86f6c9a0b4b1e943b660e4da33 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32076 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host_command: Add send_result() to the arg structureSimon Glass2012-07-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's a bit odd that the drivers package up a command to be processed by host_command, but then host_command calls a global function to pass the response back. This adds ambiguity in the host_send_response() implementations as to whether the command being responded to really is using the same buffers that the driver set up. Add a function pointer to the command, and have host_command call that. Add status to the args structure also, which removes some of the special case logic for error handling. BUG=chrome-os-partner:11317 TEST=manual and a bit ad-hoc: (note, this testing is not completed yet) Check that snow and link still process commands correctly over I2C from U-Boot. At this stage only the old interface is supported. SMDK5250 # mkbp test Old interface: New interface: Version 0: ec_command() returned error Test failed with error -1 SMDK5250 # Change-Id: I816738150bce3f8d78e7cd32abf361621aa12312 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28154 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "host_command: Add send_result() to the arg structure"Randall Spangler2012-07-221-7/+0
| | | | | | | | | | | | This reverts commit 18db93b25b05c871826fd1853a33a560e64ed247 Breaks link checksums. Change-Id: Ieeb278b7d4da0600bdc9ced1476b67f23abce1a1 Reviewed-on: https://gerrit.chromium.org/gerrit/28136 Commit-Ready: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org>
* host_command: Add send_result() to the arg structureSimon Glass2012-07-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's a bit odd that the drivers package up a command to be processed by host_command, but then host_command calls a global function to pass the response back. This adds ambiguity in the host_send_response() implementations as to whether the command being responded to really is using the same buffers that the driver set up. Add a function pointer to the command, and have host_command call that. Add status to the args structure also, which removes some of the special case logic for error handling. BUG=chrome-os-partner:11317 TEST=manual and a bit ad-hoc: (note, this testing is not completed yet) Check that snow and link still process commands correctly over I2C from U-Boot. At this stage only the old interface is supported. SMDK5250 # mkbp test Old interface: New interface: Version 0: ec_command() returned error Test failed with error -1 SMDK5250 # Change-Id: Ic4afdcd7689666cc0f6af228abc6cffe41b0fcbf Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27468
* Pass maximum size of response buffer in via host command handler argsRandall Spangler2012-07-121-0/+1
| | | | | | | | | BUG=chrome-os-partner:11275 TEST=from u-boot prompt, 'mkbp hash' Change-Id: I4cf37acfdd8e4edfe2cb6259b0fc6d0860ef0f79 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27225
* Move host_cmd_handler_args farther up the call chainRandall Spangler2012-07-111-4/+25
| | | | | | | | | | | | | This is necessary for an imminent change which passes version data from the host bus (LPC/I2C/SPI) into the host command handler. BUG=chrome-os-partner:11275 TEST=from u-boot prompt, 'mkbp hash' Change-Id: If34d0d7c6dc320ad5632becf512c30900fd61aca Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27190 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Fix up SPI driver to use host_command interfaceSimon Glass2012-07-021-18/+16
| | | | | | | | | | | | | | | | | | | This driver was not refactored when the host_command changes were made, although i2c was. Tidy this up. SPI requests the command response immediately rather than going through the task queue, since otherwise a response may take long enough that the SPI master misses it altogether. BUG=chrome-os-partner:10533 TEST=manual: build and boot on snow; In U-Boot: > sspi 4:0 240 20 See that it gets key messages back now Change-Id: Ia2c24d4c8876fefedad4c02802f77e50d7159d03 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/25982
* Initial Snow board portDavid Hendricks2012-05-041-1/+1
| | | | | | | | | | | | | | | Mostly stolen from Daisy. Notable differences: - No SYSCFGEN required for external interrupts ? - No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available --> CODEC_INT and ENTERING_RW signals are missing BUG=None TEST=Tested on ADV2/Snow, able to see EC serialconsole Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
* daisy: Re-introduce SPI protocol supportSimon Glass2012-05-031-11/+52
| | | | | | | | | | | | | | The changes in the message protocol break SPI support, so re-introduce these, this time in the driver itself. We add the concept of an option preamble in the message, a length and a trailing byte. BUG=chrome-os-partner:9426 TEST=run U-Boot, see that keyboard works correctly now. Change-Id: I83b4af7e3745b935ffafcd9e2f521fce77e3bc6e Signed-off-by: Simon Glass <sjg@chromium.org>
* remove deprecated stm32-based boardsVincent Palatin2012-05-021-1/+1
| | | | | | | | | | | We no longer support ADV EVT0 board and Discovery reference design. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=daisy && make BOARD=link Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-011-0/+188
just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
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