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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-1437/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* system: fix system_get_scratchpad APIYuval Peress2021-08-201-2/+3
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Fix compilation issues with nocturne SDKPatryk Duda2021-06-171-1/+2
| | | | | | | | | | | | | | | | | | | | | Compiler in nocturne cros SDK doesn't allow for variable declaration inside for loop. This patch removes variable declaration inside for loop in code which is used by nocturne board. This patch doesn't introduce any logical changes. BUG=b:160676144 BRANCH=none TEST=Make sure EC points to commit on cros/main. On nocturne SDK: cros_workon-nocturne start chromeos-ec emerge-nocturne chromeos-ec chromeos-bootimage Make sure that firmware compiles Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* npcx9: fix the workaround for unexpected JTAG selectionJun Lin2021-05-271-10/+29
| | | | | | | | | | | | | | | | | | | | | There is a workaround to disable the JTAG selection when the JTAG is enabled unexpectedly by the strap pin. In npcx9, the register to control the JTAG selection is different. This CL uses the correct register to let the workaround work correctly. BRANCH=none BUG=b:165777478 TEST=pass "make buildall"; check the register is correctly configured; check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not defined and JEN strap pin is pulled down on npcx9_evb. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* power: go to hibernate mode immediately if woken up by rtc overflow.Mulin Chao2021-04-211-0/+31
| | | | | | | | | | | | | | | | | If platform uses PSL (Power Switch Logic) for hibernating and RTC is also supported, this CL determines whether ec is woken up by RTC with overflow event (16 weeks). If so, let it go to hibernate mode immediately for better power consumption. BRANCH=none BUG=b:171919875 TEST= test console command "hibernate" with NPCX_LCT_MAX = 1000 and enable chipset_task on npcx9 EVB. Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Change-Id: I52543ee3cd980d444758c6a0cab32c34bd690b9a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2835259 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* npcx: remove VBNVCNTXT storage in bbramJack Rosenthal2021-02-021-13/+4
| | | | | | | | | | | | | | Nothing uses this anymore, we can free up these indexes for future use. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id7df3091edc3a8d8d07ebdfb0347a26a51389163 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668690 Reviewed-by: Edward Hill <ecgh@chromium.org>
* npcx/system: LCT compensate for MTC in PSL_hibernateWealian Liao2021-01-121-5/+35
| | | | | | | | | | | | | | | | | | | | | NPCX chip uses the MTC module as the RTC counter. However, in PSL hibernate, MTC will stop counting. NPCX9 supports the LCT module which could count continuously when VCC1 power is off. The CL uses LCT to compensate for the MTC counter value after PSL hibernate wake-up. The LCT maximum counting value is 16 weeks. BRANCH=none BUG=b:165777478, b:171919875 TEST=pass "make buildall" TEST=Check the RTC value in the following scenario: 1. "hibernate" and wake up EC by PSL input. 2. "hibernate 30" and wake up EC after timeout. 3. "hibernate 30" and wake up EC by PSL input before timeout. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I39e370a437f40749acbd3a35a8b37ebec70f1bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506864 Reviewed-by: Keith Short <keithshort@chromium.org>
* npcx: Don't delay hibernate wake by 2 seconds (v2)Edward Hill2020-12-161-6/+11
| | | | | | | | | | | | | | | | | | | | | | | Revert CL:2576439 and try again, this time checking for EC_RESET_FLAG_HIBERNATE before setting EC_RESET_FLAG_INITIAL_PWR. The problem with the first attempt was on sysjump to RW after wake from hibernate. Then gpio_pre_init() saw EC_RESET_FLAG_INITIAL_PWR but not EC_RESET_FLAG_HIBERNATE and so added an unwanted 2 second delay because system_common_pre_init() hadn't yet restored the flags from before the jump. Moving the check for EC_RESET_FLAG_HIBERNATE into check_reset_cause() avoids this issue. BUG=b:173180800 BRANCH=zork TEST=no 2 second delay on wake from hibernate, for both RO boot and jump to RW. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ia1bfba5740d77961ccc7e140da80be1070700b1e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592501 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* npcx9: workaround the download_from_flash API of the booterCHLin2020-10-051-1/+7
| | | | | | | | | | | | | | | | | | | | The download_from_flash API in the booter is called to copy the RO/RW image from flash to code RAM when doing the sysjump. There is a bug in the npcx9 A1 chip. We have to workaround it with this CL and remove the bypass when A2 chip is available. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="sysjump RO/RW" succeeds in the npcx9 EVB. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Id2babe9b9dbd36ca8b0450051d22632eb5bd4825 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435165 Tested-by: CH Lin <chlin56@nuvoton.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: support enhanced PSL functions in npcx9CHLin2020-10-051-6/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. In npcx7, the PSL (hibernation) wakeup source only can come from physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer) module is introduced to support wakeup from a configurable timeout. 2. support PSL wakeup from the VCC1_RST pin. This function is disabled by default and enabled (and locked) in the firmware in the npcx9 A1 chip. In the npcx9 A2 chip, this function is enabled (and locked) by booter. 3. Support pulse mode and open drain (if pulse mode is enabled) for PSL_OUT pin. 4. support one PSL general-purpose output pin which is powered by VSBY. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds. make sure the reset cause in the console is "power-on hibernate rtc-alarm" TEST="hibernate"; check EC wakes up from hibernate after pressing VCC1_RST button on the internal test board. Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1 power; check EC can wake up from hibernate with any input event. Test=configure the level of PSL_GPO before hibernation; check the level is kept after entering hibernation. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx/system: Use newly provided functions to access panic dataPatryk Duda2020-10-011-3/+5
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I83dacf1bf680f15a8d5ce3dbb30b03fc3cc54f48 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2379848 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: make required changes in some modules for npcx9CHLin2020-09-251-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Functions are supported in npcx7 but npcx5 are guarded by: "#if defined(CHIP_FAMILY_NPCX7)." In npcx9, most of these functions are inherited. Change the guard to: "#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7" 2. Configure APB4DIV in clock.c 3. In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT register) is updated by booter after VCC1 Power-Up reset according to VHIF voltage. In npcx9, the booter will not do this anymore. Set the HIF_TYP_SEL filed at initialization in lpc.c anyway to cover to all chip family. 4. Configure power down registers appropriately. 5 add symbolic links: i2c-npcx9.c -> i2c_npcx5.c system-npcx9.c -> system-npcx7.c BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx7/9 EVB and yorp, no symptom occurs. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I17a71b7b90435d4a3ff75aac18bf2640b5b15515 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402843 Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* npcx: add features, memory configuration and ID for npcx9CHLin2020-09-231-22/+53
| | | | | | | | | | | | | | | | | | To support npcx9, this CL defines the configurations of RAM/flash and features for npcx9m3f and npcx9m6f. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx9 EVB. Make sure EC can boot up and chip/revision ID are correct. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ie3b343368d13d7f20e3b8970048704c1d94793d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402841 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: change registers and hwtimer to support npcx9CHLin2020-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL makes the following changes to support npcx9. 1. Split the CHIP_FAMILY specific register setting form register.h to register-npcx5.h and register-npcx7.h. 2. Add npcx9's specific register setting in registers-npcx9.h 3. In npcx9, all 16-bit timers are removed from ITIM module. Change the hwtimer driver to use 32-bit timer for npcx9. The table shows the supported and current use of ITIM modules in the system: NPCX5/7 NPCX9 Change-Id: I1d00cbb8d36bff37563cfeaf78e338286e779b00 -------------------|---------------------|--------------------| Supported ITIMs | ITIM16_1-ITIM16_6 | ITIM32_1-ITIM32_6 | | ITIM32 | | -------------------|---------------------|--------------------| System tick timer | ITIM32 | ITIM32_6 | -------------------|---------------------|--------------------| Event timer | ITIM16_1 | ITIM32_1 | -------------------|---------------------|--------------------| Watchdog timer | ITIM16_5 | ITIM32_5 | BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=boot up EC on the npcx7/npcx9 EVB. Check HOOT_SECOND function is working; EC watchdog resets after console command "waitms 4000" TEST=build and flash image for yorp, no symptom occurred. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ibf0fa5fa44590de6bb3e1bff677f40aafd70b556 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402840 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx7: introduce new chip variant npcx7m7fcCHLin2020-08-191-2/+5
| | | | | | | | | | | | | | | | | | | | | | | Add the following changes: 1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to define what (RAM, flash, features...) are supported in npcx7m7fc. 2. add the chip id and chip revision id of npcx7m7fc BRANCH=none BUG=b:163910671 TEST=pass "make buildall" TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in board/npcx7_evb/build.mk; flash image and run on the internal testing board of npcx7m7fc; make sure the EC can boot up; check the chip ID and chip revision ID are correct by console command "version". Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: Add a new flag to check for initial power-onAndrew McRae2020-06-231-7/+56
| | | | | | | | | | | | | | | | | | | | | The CR50 will reset the EC on some platforms after power-on. Add a reset flag to detect this and treat the second restart as a power-on restart rather than reset. Subsume the CONFIG_GPIO_INIT_POWER_ON_DELAY_MS config to make it clear what the behaviour will be. BUG=b:151329011 TEST=Confirm on dalboz, puff & variants that second reset is treated correctly. BRANCH=none Change-Id: Ib66de920403f08099b87d1eff797270606b44f8f Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2255830 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* PB: Make CONFIG_POWER_BUTTON_INIT_IDLE commonDaisuke Nojiri2020-06-131-32/+0
| | | | | | | | | | | | | | | | | Currently CONFIG_POWER_BUTTON_INIT_IDLE is available only for NPCX chips. This patch moves the code to common/power_button.c. There is no functionality change. BUG=b:37536389 BRANCH=none TEST=Verify no functionality change on Puff. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ib4b1182900acea21e5210a2f9a699da18fe55611 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2242661 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Use AP_IDLE instead of AP_OFF to restore AP powerDaisuke Nojiri2020-05-231-8/+11
| | | | | | | | | | | | | | | | | | | | | When CONFIG_POWER_BUTTON_INIT_IDLE is defined, the AP power state is restored after power loss (e.g. black out for chromebox). This feature is implemented by EC_RESET_FLAG_AP_OFF. When AP_OFF is set, EC forces the AP to stay off even if the AP is sequencing up. This patch will prevent RW from shutting off the AP unintentionally after sysjump. BUG=b:154778457 BRANCH=none TEST=Verify test_that suite:faft_bios passes. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8f64023bd58d5679194dfa389851edf2234c58be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213730 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx/system: Clean up bbram_data_readDaisuke Nojiri2020-05-231-3/+3
| | | | | | | | | | | | | | This patch replaces calls to bbram_data_read for BBRM_DATA_INDEX_SAVED_RESET_FLAGS with chip_read_reset_flags. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I008ff594c1d754eb4cc814d4020e587c36f24cda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213358 Reviewed-by: Yicheng Li <yichengli@chromium.org>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-191-6/+6
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-281-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* dedede: Add z-state supportAseda Aboagye2020-01-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | Dedede has support for the new low power "Z-state". In this state. the EC and H1 are unpowered, but power will be restored to the EC once one of the wakeup events occurs. These events are ACOK, lid open, and a power button press. This commit simply enables the Z-state when the EC hibernates. BUG=b:147819424 BRANCH=None TEST=build and flash waddledoo, enter `hibernate`, verify that EC power is turned off and can be restored by pressing the power button or plugging in a charger. Change-Id: I4f93efd0632f457354f4bf6bf0274b19a9cd799c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006215 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* npcx: Disable ITIM after watchdog_stop_and_unlock()Tim Wawrzynczak2019-12-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | watchdog_stop_and_unlock() depends upon the ITIM32 module to ensure that it has been at least 3 watchdog ticks since the last time the watchdog has been touched. If it has been > 100ms since then, there will be no problem, but if it has been less than 100ms, then because the ITIM32 module was disabled, then the system will get stuck in the while (time_since32() ...) loop. This will eventually cause the watchdog to kick in and reboot the EC, which will also cause the AP to reboot. BUG=b:145371494, b:140207603 BRANCH=firmware-hatch-12672.B TEST=sanity testing (alt+volup+h still works) and buildall (this bug was nearly impossible to reproduce) Change-Id: I5e32f4940f03fee90b3aa809b185c13ed66ce7f1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1946773 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: Ensure the watchdog isn't stopped while it is invalid to do soJett Rink2019-10-091-6/+2
| | | | | | | | | | | | | | | | | | | We cannot unlock the watchdog timer within 3 watch dog ticks of touching it per the datasheet. This is actually around 100ms so we should protect against this. Note: To avoid bringing in other dependencies into the npcx_monitor_fw, the "old" method of stopping the watchdog is used (no waiting first). BRANCH=none BUG=b:140207603 TEST=eliminates cold reset issue. Change-Id: I440d36fb9aecdd6d78bae6fc4002208198a3357f Signed-off-by: Jett Rink <jettrink@chromium.org> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1842592 Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cleanup: fix byte access and ifdefs for BBRAM_PD2Jett Rink2019-09-301-8/+1
| | | | | | | | | | | | | | Ensure that PD2 is accessed as a single byte instead of 4 bytes and remove unnecessary ifdef guards in all chip implementations. BRANCH=none BUG=none TEST=builds Change-Id: I319d8d6a8456662235ab4d8dcda6bda7e8ed7c15 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1809938 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "npcx: ensure we don't unlock watchdog too soon"Caveh Jalali2019-09-121-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 031c5d2d62dd891622ded885756c03021e934ef2. Reason for revert: introduced compilation errors: chip/npcx/spiflashfw/npcx_monitor.c: In function 'sspi_flash_upload': chip/npcx/spiflashfw/npcx_monitor.c:290:2: error: implicit declaration of function 'watchdog_stop_and_unlock' [-Werror=implicit-function-declaration] watchdog_stop_and_unlock(); ^~~~~~~~~~~~~~~~~~~~~~~~ Original change's description: > npcx: ensure we don't unlock watchdog too soon > > We cannot unlock the watchdog timer with 3 watch dog ticks of touching > it per the datasheet. This is actually around 100ms so we should protect > against this. > > BRANCH=none > BUG=b:140207603 > TEST=eliminates cold reset issue. > > Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 > Reviewed-by: Scott Collyer <scollyer@chromium.org> > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> > Reviewed-by: Furquan Shaikh <furquan@chromium.org> > Tested-by: Furquan Shaikh <furquan@chromium.org> > Commit-Queue: Furquan Shaikh <furquan@chromium.org> Bug: b:140207603 Change-Id: I540fa53c2c568cb789400d55b807a672b182302a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799293 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* npcx: ensure we don't unlock watchdog too soonJett Rink2019-09-121-6/+2
| | | | | | | | | | | | | | | | | | | | We cannot unlock the watchdog timer with 3 watch dog ticks of touching it per the datasheet. This is actually around 100ms so we should protect against this. BRANCH=none BUG=b:140207603 TEST=eliminates cold reset issue. Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-23/+23
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: chip_save_reset_flags takes uint32_tJack Rosenthal2019-05-171-1/+1
| | | | | | | | | | | | | | | The getters and setters for the reset flags should take and return the same type. `uint32_t' seems the more appropraiate type than `int', so change the setter to take `uint32_t'. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I50928a114858dd51034a048520efa849f5182bd0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615648 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-271-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: introduce npcx7m7wc chip and refine memory layout of npcx7m7wbCHLin2019-04-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL includes the following changes: 1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to define what (RAM, features...) is supported in npcx7m7wc. 2. add the chip id and chip revision id of npcx7m7wc. 3. re-organize the memory of npcx7m7wb from: current: 320 KB code RAM + 64 KB data RAM. to : 256 KB code RAM + 128 KB data RAM. The reason is that the extra 64 KB RAM is excepted to store the WoV voice data when it operates under RAM mode. Under the limitation of current memory layout, the 64 KB voice buffer is declared as const to force it allocated in the code section, which is strange. This can be fixed after changing the layout. BRANCH=none BUG=none TEST=pass "make buildall" TEST=with related CLs, change CHIP_VARIANT to npcx7m7wc in board/npcx7_evb/build.mk; flash image in the internal testing board of npcx7m7wc; make sure the EC can boot up; check the chip ID and chip revision ID are correct by console command "version". TEST=build npcx7m7wb image and test it on npcx7_evb, no symptom found. Change-Id: I7533c1f5490e151571696ac615da2d0430827a78 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1543062 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: cleanup: Add CONFIG_RTCJack Rosenthal2019-03-011-1/+1
| | | | | | | | | | | | | | | | | | This allows the chipset task to print RTC information, without requiring CONFIG_CMD_RTC to be enabled. BUG=chromium:649851 BRANCH=none TEST=Built and flashed on grunt (careena), confirmed RTC state printed when the power state was changed, but without RTC command present Change-Id: I6b11c4d2822117c57febdacf299a865710ed1edd Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1490672 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: introduce npcx7m6fc chip definitions and configurationsCHLin2018-11-281-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. add CHIP_VARIANT_NPCX7M6FC in the npcx chip configuration files to define what (RAM, features...) is supported in npcx7m6fc. 2. add the chip id and chip revision id of npcx7m6fc. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk; flash image in the internal testing board of npcx7m6fc; make sure the EC can boot up. Check the chip ID and chip revision ID are correct by console command "version". TEST=build and flash the yorp image to the platform; make sure no issues are found. Change-Id: Ibcb25fc09b21ec3e5738418af16826035ec81e69 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1343639 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Don't clear IBBR bit via a read-modify-write sequenceCHLin2018-09-211-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx5/npcx7m6g/npcx7m6f, clearing the IBBR bit in the BKUP_STS register is not hazardous because the register only implements the IBBR bit. In npcx7m6fb/npcx7m7wb, the register implements two more bits (VSBY_STS/VCC1_STS). Using read-modify-write operation to clear IBBR bit will also clear these two bits unexpected if they are set. It is fine at this time because the firmware does not rely on these two new bits for any purpose. But it will be better to change it in case these two bits are used in the future. This CL also clears VSBY_STS/VCC1_STS bit (for npcx7m6fb/npcx7m7wb) when power-on reset. BRANCH=none BUG=none TEST=No build error for make buildall; Check IBBR(VSBY_STS/VCC1_STS) are cleared at initial when power-on reset. Check warining messages are printed and IBBR bit is cleared (in function system_check_bbram_on_reset and bbram_valid). Change-Id: I6dc1f5d7f35f9d591db62d1b022ea7b8d92f5b92 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1235733 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* chip/npcx: Make check_reset_cause() staticSimon Glass2018-08-241-3/+2
| | | | | | | | | | | | | | | This function is not called from outside this file so make it static. Also drop a pointless comment, and rename the function since the 'system' prefix suggests it is defined in system.h (which it is not). BUG=chromium:876737 BRANCH=none TEST=make -j50 BOARD=grunt Change-Id: Ic429fb1da2e56e1888e008f4739c90e8ed2c1947 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1184975 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: system: change the default value of FMUL_WIN_DLYMulin Chao2018-07-151-0/+8
| | | | | | | | | | | | | | | | | This CL changes the default value of Nuvoton internal register, FMUL_WIN_DLY, from 0x8A to 0x81 on npcx7 ec series. It increases the tuning rate of the FMULs to improve audio quality. For consistency, this is done across all NPCX7 devices. BRANCH=none BUG=b:74600211 TEST=make buildall; Run cold-reset stress test over 3 days on grunt. No symptoms occurred. Change-Id: I5ad0c115da4254413d43269140eb71092c11b3b2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1134815 Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: system: Add chip generation info in system_get_chip_revision().Mulin Chao2018-05-091-6/+29
| | | | | | | | | | | | | | | | | | | | | In npcx5 series, there is no other chip generation and npcx's system driver fixed the first character of revision array as 'A'. But in npcx7 series, there are two chip generations and it's better to show chip generation information by 'version' console command. In this CL, we used SRID_CR to distinguish the generation of npcx7 series. It also adds the support for NPCX787G in system_get_chip_name() since it is used on the version 1 of npcx7 evb. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Verified npcx5m5g, npcx7m6g and npcx7m7wb on evbs by 'version' console command. Change-Id: I7572b5688b4430c6febd21c25f36c3903fb97e27 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1046689 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: change chip variants of npcx7 series for better clarification.Mulin Chao2018-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w to npcx7m7wb for better clafiication since it introduced new parameter "b" for chip generation in the same family series. In new npcx7 series naming rule, it follows: Format: NPCX7(M)(N)(G/K/F)(B/C) param M: 8: 128-pins package, 9: 144-pins package param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size param G/K/F/W: Google EC depends on specific features. param B/C: Chip generation in npcx7. (Generation A is ignored. It follows nameing rule in npcx5.) The all chip variants of npcx7 used in boards are also listed below: npcx7m6g - for npcx7 ec without internal flash on npcx_evb. npcx7m6f - for npcx7 ec with internal flash. npcx7m6fb - for npcx7 ec with internal flash, enhanced features. npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV. BRANCH=none BUG=none TEST=No build errors for npcx7 series. Change-Id: I896ee33209efa5d7157c90515005db5f36318c76 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1025471 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: Add BBRM idx for a 3rd PD port.Aseda Aboagye2018-04-251-1/+5
| | | | | | | | | | | | | | | | | | | Currently, there's only one board with 3 PD ports and it uses NPCX. Therefore, this commit just adds the index to NPCX which will be used to save the fact that there was an explicit contract in place. BUG=b:72838807 BRANCH=None TEST=make -j buildall CQ-DEPEND=CL:905390 Change-Id: Ic960f14a52f2a740adbe08bc340c45edfefbbf26 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/905922 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-261-4/+2
| | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=b:76232539 BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx: do not power down eSPI when enabledCaveh Jalali2018-02-121-1/+11
| | | | | | | | | | | | | | | | | | | | if we're using eSPI for connectivity to the AP, we should never power it down... powering it down just causes transient errors on eSPI. BUG=b:72838699 BRANCH=none TEST=booted on meowth, no more eSPI bus errors. Change-Id: I737a03bb745868c7e8e02ffd5607db4d2da74c30 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910320 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Nami: Enable hibernate using silegoElthan_Huang2018-02-121-2/+4
| | | | | | | | | | | | | | | | | | | | Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the EC. Thus, we don't use the internal hibernate/wake-up feature in npcx. BUG=b:72641658 BRANCH=none TEST=Test system will shutdown and doesn't auto wake up when type hibernate in ec console. And wake up by AC plugin, LID open, or power button. Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4 Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/890569 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Nami: force to set RESET_FLAG_RESET_PINElmo_Lan2018-01-301-1/+1
| | | | | | | | | | | | | | | | | Like other KBL designs (eve, poppy and followers). EC is not able to distinguish between power up and reset. BUG=b:71839731 BRANCH=none TEST=Verify Nami power on flag by EC console. Change-Id: Ice8b80259b8405f28b508918d5b3cfe37a8b1eb9 Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/891042 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* system: Allow hibernate to clear AP_OFF flagDaisuke Nojiri2017-12-051-1/+9
| | | | | | | | | | | | | | | | | | | After firmware update, cr50 toggles the EC's reset line, expecting the system will boot. This isn't the case for Chromebox because it sets AP_OFF flag on a clean shutdown (to restore the previous power state after power loss & restore). This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot command. It makes EC first clear AP_OFF then hibernate. BUG=b:69721737 BRANCH=none TEST=Verify Fizz reboot after cr50 update. Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/802632 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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