| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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The npcx monitor LFW (little firmware) can be used in two scenarios:
1. For npcx5 which supports the external flash and doesn't support UUT,
it is used by the openocd via servo JTAG to flash the EC image.
2. For npcx7 (and newer chips) which support the internal flash and UUT,
it is used by the UUT via UART to flash the EC image.
For case 1, the DEVALT0.bit7 (NO_F_SPI) should be cleared in order to
program the external flash. In case 2, this bit should be set because
the internal flash is used. Otherwise, the GPIOA0 (F_CS0) will also
toggles while programming the internal flash.
Before this CL, the monitor unconditionally clears this bit when
programming the flash.
In this CL, the monitor decides to set/clear this bit according to
the value of the tag filed in the monitor header.
(Assuming that when UUT is used, the target is always the internal
flash.)
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Programming the internal flash via UUT, make sure the GPIOA0 doesn't
toggle with scope.
Change-Id: I9f1695351b201767cc5ed32877fb395c1e459bc8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2272419
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
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This reverts commit 031c5d2d62dd891622ded885756c03021e934ef2.
Reason for revert: introduced compilation errors:
chip/npcx/spiflashfw/npcx_monitor.c: In function 'sspi_flash_upload':
chip/npcx/spiflashfw/npcx_monitor.c:290:2: error: implicit declaration of function 'watchdog_stop_and_unlock' [-Werror=implicit-function-declaration]
watchdog_stop_and_unlock();
^~~~~~~~~~~~~~~~~~~~~~~~
Original change's description:
> npcx: ensure we don't unlock watchdog too soon
>
> We cannot unlock the watchdog timer with 3 watch dog ticks of touching
> it per the datasheet. This is actually around 100ms so we should protect
> against this.
>
> BRANCH=none
> BUG=b:140207603
> TEST=eliminates cold reset issue.
>
> Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d
> Signed-off-by: Jett Rink <jettrink@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302
> Reviewed-by: Scott Collyer <scollyer@chromium.org>
> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
> Tested-by: Furquan Shaikh <furquan@chromium.org>
> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Bug: b:140207603
Change-Id: I540fa53c2c568cb789400d55b807a672b182302a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799293
Reviewed-by: Caveh Jalali <caveh@google.com>
Commit-Queue: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
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We cannot unlock the watchdog timer with 3 watch dog ticks of touching
it per the datasheet. This is actually around 100ms so we should protect
against this.
BRANCH=none
BUG=b:140207603
TEST=eliminates cold reset issue.
Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This change updates the erase operation in npcx chip to use 64k/32k/4k
block erase depending upon the alignment of CONFIG_RO_SIZE. This helps
reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7.
Ideally, we would want to check the offset and size of region to be
erased dynamically and decide which erase operation to use. However,
common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure
that the area being erased is aligned to that size. Thus, even if we
add dynamic erase at chip level, it isn't going to help.
This change also updates CONFIG_FLASH_BANK_SIZE to be the same as
CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am
honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled
with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be
a safe change.
On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the
write time as well, thus overall helping with the EC SW Sync time.
Please see go/cros-npcx7-ec-sw-sync for more details.
BUG=b:113530328
BRANCH=nocturne
TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4
seconds.
Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1195598
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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In order to reduce the time of programming EC image, the UUT in this CL
checks each segment before it is written. If the content of the segment
is empty (ie. all 0xFF), the UUT will not write the empty data to flash
but only erase it.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=
------------------------------------------------------------------------
1. Connect the servo connector (J24) on npcx7 EVB to servo board v2 via
flex cable.
2. Manually turn the switch SW1.6 to "ON" on npcx7 EVB.
3. Reset ec by issuing Power-Up or VCC1_RST reset.
4. Manually turn the switch SW1.6 to "OFF" on npcx7 EVB.
5. Move npcx7_evb from array BOARDS_NPCX_7M7X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. "./util/flash_ec --board=npcx7_evb", make sure ec boots up.
(Note: "ec_reset" must be removed in line 1051 of flash_ec)
5."time ./util/flash_ec --board=cheza"
flash time before this CL: 1m26.489s
flash time after this CL : 0m36.760s
6. Dump the flash content via JTAG, make sure it is the same as cheza's
ec.bin.
Change-Id: Id5ee2bd3a03d13e9b693267b03613c9f2847e0c8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1095057
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.
The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341
Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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