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* npcx/timer: Unroll udelayDaisuke Nojiri2022-03-281-0/+21
| | | | | | | | | | | | | | | | | This patch flattens udelay by unrolling __hw_clock_source_read. This increases the chance that we record LR of the instruction near which an infinite loop happened. BUG=b:218982018,b:200593658 BRANCH= TEST=Sona. Run crash assert. Hack battery command to trigger WD reset. Verify LR points to the root causes. Change-Id: Ibd6cbcf18ab6d58c06ddfd19021058268289bf00 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cc1d30dd2bd3b92d29f5ffb942d016bc207e2ad0) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508422
* chip/npcx: Tidy up comments for init_hw_timer()Simon Glass2018-09-041-1/+1
| | | | | | | | | | | | | | The comments suggest that this function only operates with ITIM16 timers but it seems to support ITIM32 as well. Also it allows selecting the clock source. Update the comments, hopefully making them correct. BUG=chromium:876737 BRANCH=none TEST= make buildall -j50 Change-Id: Ic4ec2457cde2de55d51371f781d49bae80365989 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185225
* Add CONFIG_GPIO_INIT_POWER_ON_DELAY_MSEdward Hill2018-09-041-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | On power on, H1 releases the EC from reset but then quickly asserts and releases the reset a second time (so that the EC comes out of reset the second time after the SPI buffers have been configured by H1). Add a delay so the EC can wait for this second reset before configuring GPIO outputs, to avoid extra output toggles. Unfortunate the timer is not set up by the time gpio_pre_init() is called, so we add a new __hw_early_init_hwtimer() function to set it up so that mdelay() worked. Without that, mdelay() hangs. BUG=b:72132384 BRANCH=none TEST=GPIO_OUT_HIGH has a single rising edge after power on (before it would rise-fall-rise) Check that mdelay(10) delays for about 10ms (actually perhaps a little more using a scope line on KB_BL_EN Change-Id: Iadc96fceb190e43ac0758f291f22e03aef81c379 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/879353 Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* chip/npcx: Ensure software watchdog has highest priorityNicolas Boichat2018-04-051-2/+2
| | | | | | | | | | | | | | | | | | | | | Before this change uart_ec_interrupt and software watchdog interrupt handler both had priority 0. Since UART IRQ number is 33, and software watchdog is 44, the UART interrupt handler would have higher prority. Fix this by increasing all interrupt handler priorities, leaving the software watchdog handler alone on priority 0. BRANCH=eve,poppy,fizz BUG=b:76391320 TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt handler), check that panicinfo contains a sensible PC in r5 after reset. Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/979738 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: lpc: fixed bug that ec gets stuck in lpc_sib_wait_hostxx routines.Mulin Chao2018-04-011-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done() and lpc_sib_wait_host_write_done() routines, in rare case, ec might have a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD bits are high forever. (Normally, CSWR/CSRD bits won't be always high. These bits are high forever also means something wrong on LPC/eSPI bus.) In order to prevent this situation, the CL checks TO_STS bit of ITCTS in these routines. If this bit is set, restoring ITIM32 preload counter value to maximum value and processing overflow will be done by force_time(). BRANCH=eve,fizz,poppy BUG=b:76182199 TEST=No build errors for npcx series. Passed test command of CL 979389 on npcx_evb. No symptom occurred during warm reset stress test on soraka. Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/979874 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: hwtimer: Fix deadlock close to hwtimer wrapShawn Nematbakhsh2016-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | __hw_clock_event_set() is not reentrant and may be called from both our event timer ISR and our hwtimer ISR when hwtimer is close to wrapping. Modify the interrupt priority of our hwtimer int to match our event timer int so that one cannot preempt the other. Originally the priority was changed to allow the hwtimer ISR to run first in case both are pending, but this condition can be handled cleanly and isn't a big concern. BUG=chrome-os-partner:60470 BRANCH=gru TEST=Pass 500 S/R cycles on kevin with hwtimer wrap rate sped up 300x (roughly equivalent to 150,000 real S/R cycles). Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ied466f14661f04c8662b5db709c0e3770a5bb200 Reviewed-on: https://chromium-review.googlesource.com/417060 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit ac28ec53b63a02c4d25e8a222d13595bc857fef0) Reviewed-on: https://chromium-review.googlesource.com/417112 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: hwtimer: Add consecutive reading for ITCNT32Mulin Chao2016-11-221-5/+15
| | | | | | | | | | | | | | | | | | | | The mux for selecting source clock of ITIM will introduce a delay and have a chance to make ITIM's source clock and core clock are asynchronous. We need consecutive reading for ITCNT32 no matter source clock is APB2 or 32k. Modified sources: 1. hwtimer.c: Add consecutive reading for ITCNT32 BRANCH=none BUG=chrome-os-partner:34346,chrome-os-partner:59240 TEST=No time stamp symptoms occur on wheatley for 30 hours. Change-Id: I8b54e93b320e3ea74fc3d6ea13f0d178f9c449cd Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/412505 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* npcx: hwtimer: Fix 'slow' timer count just before overflowShawn Nematbakhsh2016-11-091-5/+0
| | | | | | | | | | | | | | | | | | | | If our 32-bit usec timer is close to overflow, we may deep sleep several times in succession without making any adjustment to our count, causing deadlines on the other side (eg. HOOK_TICK expiration) to be reached much slower than expected. Avoid this by not entering deep sleep if our timer is about to overflow. This will result in a <= HOOK_TICK_INTERVAL (200ms interval) period of not entering deep sleep, every ~4300 seconds. BUG=chrome-os-partner:59240 BRANCH=gru TEST=Verify 3x kevin units survive 16 hours in S3 without EC watchdog. Change-Id: I2126458be8820f78212e19c2bb79242ff1194f6f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409673 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Fix hwtimersShawn Nematbakhsh2016-11-091-2/+12
| | | | | | | | | | | | | | | | | | | | | | - Wait for ITEN bit to be set / cleared, since writing this bit just sets a 'request'. - Ensure ITIM_EVENT_NO reg is set with minimum value 1, per the datasheet. - Don't dsleep if our wake event is in the past (eg. wake event will occur any time now) BUG=chrome-os-partner:59240 BRANCH=gru TEST=Manual on kevin, verify that dsleep period never exceeds expected wait period. Also verify that EC watchdog doesn't occur after 5 hours in S3. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iedb2723c3f12b74dea66082b1d8b8ce1b6e7d945 Reviewed-on: https://chromium-review.googlesource.com/409672 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Adjust relative IRQ priorities for high-priority UARTShawn Nematbakhsh2016-08-071-1/+1
| | | | | | | | | | | | | | | | | | | Our UART interrupt must be able to preempt our SHI_CS interrupt, otherwise console input may be lost. Adjust our relative IRQ priorities to accommodate this. BUG=chrome-os-partner:55920 BRANCH=None TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from the recovery screen, verify that all input is received by the EC. Change-Id: I36203511f5883272287ac22d0704098fbd933758 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366622 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Fixed bug that unexpected value of timer which source clock is 32KMulin Chao2016-05-111-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rare case, FW read the unexpected counter value of timer which source clock is 32K (Watchdog timer and ITIM16/32 which use 32K source clock). The root cause is the clocks between reading registers and timer's are asynchronous. It has a chance to get invalid counter value when timer is under transaction edge. The solution is using two consecutive equal readings to make sure the counter value is valid. Beside different source clocks of timer, we also found there's chip's bug which causes unexpected value of timer. If an interrupt that occurs very shortly before entering deep idle with instant wakeup, it might result in disruptive execution (such as skipping some instructions or hard fault) after "wfi". The workaround is adding the same bypass for idle in deep idle section. Modified sources: 1. clock.c: Add bypass for instant wakeup from deep sleep. 2. hwtimer.c: Add consecutive reading function for event timer. 3. watchdog.c: Add consecutive reading function for watchdog timer. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I7c9f1fb9618a3c29826d8f4599864a8dac4203bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/327356 Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Add support for CONFIG_LOW_POWER_S0.Mulin Chao2016-02-061-24/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get better power consumption in S0, we add FW support for CONFIG_LOW_POWER_S0. Before entering deep idle in S0, we must enable Host interrupt to wake up EC if it needs to service LPC bus. This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal. In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR since preload counter is changed by __hw_clock_source_set all the time. We also found there're no event set if it's deadline is over 32 bits but current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if ITIM32 expires, FW set an event for ITIM32 after process_timers(). Modified sources: 1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition. 2. clock.c: Enable Host interrupt for LPC. 3. clock.c: Disable LP_WK_CTL for better power consumption. 4. gpio.c: Add ISR for Host interrupt. 5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed. 6. register.h: Add uart_clear_pending_wakeup function. 7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow. 8. fan.c: Enable deep sleep if duty cycle is zero. 9. include/system.h: Add SLEEP_MASK_FAN for fan control loop. 10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the instruction pipeline. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324651 Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Support hibernate_wake_pins on wheatley, npcx_evb and npcx_evb_arm.Mulin Chao2016-01-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb and npcx_evb_arm. For better power consumption, we disable ADC, tri-state spi pins, all inputs of wake-ups to prevent leakage current caused by input floating and set necessary GPIOs' states in hibernate function. Modified drivers: 1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate. 2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate. 3. wheatley/board.c: Add hibernate_wake_pins array for hibernate. 4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting GPIOs' status related to board for better power consumption. 5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt will disable before it is called. 6. register.h: Add WKINEN definition and declarations used for hibernate. 7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs' state and wake-up inputs before entering hibernate. 8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field. 9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/321466 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Get more accurate value of deep idle time.Mulin Chao2016-01-051-3/+9
| | | | | | | | | | | | | | | | | | | | | We should consider the interval between the calling __hw_clock_event_set and entering deep idle. In order to get more accurate value of deep idle time, FW should record the time-stamp before entering deep idle and calculate the deep idle time based on it. Modified drivers: 1. hwtimer_chip.h: Add new function declarations for deep idle time caculation. 2. hwtimer.c: Add new functionsfor deep idle time caculation. 3. clock.c: Modified for calculating more accurate deep idle time. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Id037c4dc3564659e4ad493f2fc3ffc5d06c18b06 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320071 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: use fix point math for timer calculationGwendal Grignou2015-09-181-5/+7
| | | | | | | | | | | | | | Remove needs for FPU unit for calculating timer. BRANCH=none BUG=none TEST=compile Change-Id: Ice12c2d2f914974f7b4db5dadfca77257557e5a5 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299519 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc:Ian Chao2015-07-251-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-60/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-141-0/+255
Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
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