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* npcx: Decide erase size based on ro/rw region sizeFurquan Shaikh2018-09-051-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the erase operation in npcx chip to use 64k/32k/4k block erase depending upon the alignment of CONFIG_RO_SIZE. This helps reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7. Ideally, we would want to check the offset and size of region to be erased dynamically and decide which erase operation to use. However, common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure that the area being erased is aligned to that size. Thus, even if we add dynamic erase at chip level, it isn't going to help. This change also updates CONFIG_FLASH_BANK_SIZE to be the same as CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be a safe change. On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the write time as well, thus overall helping with the EC SW Sync time. Please see go/cros-npcx7-ec-sw-sync for more details. BUG=b:113530328 BRANCH=nocturne TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4 seconds. Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1195598 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: uart: Add driver support for the second UARTCHLin2018-07-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nuvoton NPCX79nxB serie chips include two UART ports. In this CL, we add the driver support for these two UART modules. Develoers can select one of the UART ports as EC console by configuring "CONFIG_CONSOLE_UART" in board.h BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB; check EC console working via J21. TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB; check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3 must be connected together.) TEST=build images of board npcx_evb, poppy, and grunt, make sure EC console is functional on these boards. TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write function still works by using the console command like: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1113269 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gpio: extend flags size to accommodate GPIO_ flagsJett Rink2018-06-111-1/+1
| | | | | | | | | | | | | | | | | | | Widen the flags field from 16-bit to 32-bit to fit all of the current GPIO_flags. Also reorder fields within struct to allow arm compiler to use 16-bit instructions instead of 32-bit instructions when accessing fields (which is important for kevin board, otherwise it runs out of space) Lastly, re-tool macros to all reordering of gpio_alt_func struct fields. BRANCH=none BUG=b:109884927 TEST=builds on all boards Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096018 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* chip/npcx: Increase default stack size for tasksNicolas Boichat2018-05-161-7/+7
| | | | | | | | | | | | | | | | | | | | Usually, we enable CONFIG_FPU on NPCX, which requires larger stack size. Also, NPCX has very deep call patch in I2C transactions (in particular, I2C recovery path), so it generally requires larger stack. To make the code fit, however, we need to reduce the accelerometer fifo depth from 1024 to 512, on a few boards. BRANCH=none BUG=b:75234824 TEST=make buildall -j, stackanalyzer result on poppy looks a little better. Change-Id: I37b5a2a97a760dc4fd225253c23962d74e25605a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967963 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-071-0/+3
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Introduce npcx7 series ec chip definitions and configurations.Mulin Chao2017-04-251-36/+9
| | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin / gru: Increase size of code RAMShawn Nematbakhsh2016-07-261-1/+1
| | | | | | | | | | | | | | | | Reduce size of UART Tx buffer to 1024 bytes on all npcx platforms and increase size of code memory by 6K bytes on Kevin. BUG=chrome-os-partner:52876 BRANCH=None TEST=`make buildall -j` with subsequent commit. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib9e52a4406f84cfc434984f8819d7ef02b70beb4 Reviewed-on: https://chromium-review.googlesource.com/363591 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin: Move RAM from data section to codeShawn Nematbakhsh2016-05-101-2/+2
| | | | | | | | | | | | | | | | | | Kevin is code space constrained, so use RAM normally used for data instead for code. BUG=chrome-os-partner:52876 BRANCH=None TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes to add sensor task). Also, verify kevin continues to boot + power sequence. Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343191 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: Reduce system stack sizeShawn Nematbakhsh2016-05-021-1/+1
| | | | | | | | | | | | | | | | Reduce system stack size to 1K to match other recent chips. BUG=None TEST=Build + boot on kevin. BRANCH=None Change-Id: I0be6e865ca03f4eef2ee7a99856df8257d7269d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341850 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* amenia: enable BMM150 compassKevin K Wong2016-04-151-0/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo return data from compass Change-Id: Ib64ca8a06071744294c0bc88bbb18f1445d71780 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331656 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Add CHIP_VARIANT variant for different versions of npcx ec.Mulin Chao2016-03-051-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT variant to distinguish which verson ec is. In config_chip.h, we use CHIP_VARIANT to specify the size and start address of program memory. Ecst tool also needs a chip parameter to make sure the address range checking of entry pointer won't fail. Modified sources: 1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec of npcx ec. 2. config_flash_layout.h: Replace constant value with CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE. 3. build.mk: Add -chip parameter for ecst tool to check entry address. 4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g). BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330072 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-031-1/+0
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* chip: Set CONFIG_FPU on a board basis.Gwendal Grignou2015-09-181-1/+0
| | | | | | | | | | | | | | Only few boards need FPU. Not enabling FPU saves on stack memory. BRANCH=none BUG=chrome-os-partner:36126 TEST=compile all boards. Change-Id: I1fed9920f9d64664be303e9e2a74673416c05365 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299517 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Fix npcx buildShawn Nematbakhsh2015-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | The previous commits left npcx in a bad state. Change CONFIG_PROGRAM_MEMORY_BASE to point to the actual start of code memory and correct the linker file. This still results in a non-working npcx image (more changes forthcoming) but it does build. BUG=chrome-os-partner:23796 TEST=make clean; make buildall -j BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia300c5d18695dccd8d9fd9a6122cd7d30353adfa Reviewed-on: https://chromium-review.googlesource.com/300295 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-2/+0
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cleanup: Remove COMPILE_FOR_RAM option from linker scriptsBill Richardson2015-09-081-3/+0
| | | | | | | | | | | | | | | This option was added way back in January 2012 for early EC bringup, and never used since. We can probably remove it. BUG=none BRANCH=none TEST=make buildall Change-Id: Idc8c3099388f2e28d620848a0e78b555b02fba9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297334 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Clarify use of flash layout CONFIGsShawn Nematbakhsh2015-09-021-37/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Based on feedback from programmers, it's not clear when config_std_internal_flash should be used, and when non-standard chip-specific layouts need to be defined. Add clarity here with the following changes: - Explain in-depth the one config that config_std_internal_flash should be used for. - Move non-standard chip-level flash layout CONFIGs to their own new chip-level file, config_flash_layout. All chips should either include config_std_internal_flash.h OR define their own layout in their own config_flash_layout. Functionally, this change is a NOP. BUG=chrome-os-partner:23796 TEST=`make buildall -j` BRANCH=None Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296527 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc:Mulin Chao2015-08-191-1/+9
| | | | | | | | | | | | | | | | | | | | | Modified i2c driver into controllers and ports to support I2C0 port 0/1 at the same time. Modified drivers: 1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions used by i2c_wedge and i2c_unwedge. 2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func. 3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should replace GLUE_SDP0/1 with DP80BUF. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/294015 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc:Ian Chao2015-07-251-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* mec1322: Simplify GPIO listsSteven Jian2015-05-271-0/+3
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-151-2/+3
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* npcx: Use SPI status register instead of pstateRandall Spangler2015-02-261-34/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npcx chip and evb use a SPI flash chip to hold the EC image. They don't need pstate, and should use the SPI flash status register directly. 1. Remove CONFIG_FLASH_PSTATE from npcx_evb. 2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect line to the SPI flash chip). 3. Change the npcx flash driver so that it directly reads/writes the SPI status register instead of mucking with pstate. BUG=chrome-os-partner:34346 BRANCH=none TEST=manual Add a switch or jumper to the EVB so R1 can be closed. Toggle the switch and see that WP_L state changes. Leave enabled. flashinfo -> nothing is protected, WP_L is enabled (=0) (also do this after each flashwp command to check the protection status) flashwp enable -> RO is protected now and at boot. reboot flashwp enable -> RO is still protected. flashwp disable -> RO is still protected. (because WP switch is enabled). Toggle the switch so WP_L is disabled (=1) flashwp disable -> Succeeds, flash is not protected Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253633 Reviewed-by: Shawn N <shawnn@chromium.org>
* WIP - Nuvoton 30-Jan patchRandall Spangler2015-02-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues fixed on 0216: 1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c 2.Modified warm_reset checking in gpio.c 3.Modified system_get_chip_name in system.c for package info. 4.Modified fan.c and pwm.c for: ● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low. ● Fan stall condition event: If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called. 5. Change cycle_pluses to 480 in board.c Issues fixed: 1. Jump data at top of RAM is getting corrupted. Changed the flag to RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST issue. 2. Hibernate wake need to report whether wake reason was GPIO or RTC 3. Hibernate wake must be distinguishable from watchdog reset. The booter will log reset reason in Code RAM. I copy the log data to battery-backup RAM in little FW. And system driver will refer this data to distinguish if it's watchdog reset or not. 4. Watchdog reset flag is not set. Same fix as 3. 5. Should return error if unable to clear SPI flash status register. 6. Remove chip_temp_sensor.c 7. Remove use of pstate from flash driver 8. Remove support for watchdog warm reset 9. Keyboard raw driver must support COL2 inverted 10. LPC memory mapped data must be read-only from host 11. LPC should support PLTRST# signal 12. Problems reading chip type/version. Use core registers and ROM data to read IDs. 13. When chip type/version is unknown, report hex value. 14. Watchdog does not consistently print panic information. 15. Remove console force enable logic. 16. Enable only the peripheral clocks that are needed. Please notice user should add bit mask in CGC_XXX_MASK if they want to enable additional module. For example, if user wants to enable PWM3, he must add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK. Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions. If I turn off all I2C modules in system_pre_init and turn on the modules I need in i2c_init, I found its freq is not correct. The root cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in clock_init) before i2c_init. At this time, i2c modules are power-down and writing to freq register is useless. I re-execute freq-changed hook function after turning on modules again. 17. MPU properly configured to prevent code execution from data RAM 18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM. Additional items we also modified: 1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func array to support it) 2. ec_npcxflash.c: Use definition to replace constant value. Stop watchdog during flash programing. 3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock MPU commands for Data RAM. BUG=chrome-os-partner:34346 BRANCH=none TEST=manually verify changes Change-Id: I722a77d29e7543b054819480c7b7477af4263119 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248670
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-141-0/+140
Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
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