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* chip: add support for npcx trngDavid Cross2023-05-151-0/+1
| | | | | | | | | BUG=b:280889889 TEST=add CONFIG_RNG to NPCX based board.h file (e.g. npcx9_evb) Change-Id: I93b3a7742c3b7d614cc1218104cd642b3339f8b3 Signed-off-by: David Cross <davidmcross@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4507895 Reviewed-by: Bobby Casey <bobbycasey@google.com>
* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip: Remove -march, since -mcpu itself is sufficientTom Hughes2022-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the GCC documentation: -mcpu specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance (as if specified by -mtune). https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html This means that unless we're overriding some setting with -march or -mtune, there's no need to specify them. In our case, we aren't overriding the default for -mtune that -mcpu sets, so make things simpler by only specifying -mcpu. Additional details in https://community.arm.com/arm-community-blogs/b/tools-software-ides-blog/posts/compiler-flags-across-architectures-march-mtune-and-mcpu BRANCH=none BUG=b:145677491 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1999ef25642ed9e32b2e8eeb76d4ba7a23dc2b8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3699792 Reviewed-by: Andrea Grandi <agrandi@google.com>
* cleanup: it8801: Rename discrete Keyboard configsVijay Hiremath2022-04-251-1/+1
| | | | | | | | | | | | | | | | Renamed IT8801 discrete keyboard related names like NOT_RAW, I2C_PORT, I2C_ADDRESS and Interrupt GPIO to support discrete keyboard in Zephyr Shim. BUG=b:230008245 BRANCH=none TEST=make buildall Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Change-Id: I9be3ff570681f88e1fc3ac0650f9919ad272b847 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3600627 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHIKeith Short2021-11-191-1/+1
| | | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I35959149554f58c8911459dcd025720b6d66eb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095843 Tested-by: Michał Barnaś <mb@semihalf.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPIKeith Short2021-11-191-1/+1
| | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842 Tested-by: Michał Barnaś <mb@semihalf.com>
* chip/npcx: Disable linker section check warningTom Hughes2021-11-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | When linking with clang (lld), it complains that the .header and .text virtual memory address (VMA) overlaps: ld.lld: error: section .header virtual address range overlaps with .text >>> .header range is [0x10070000, 0x1007003F] >>> .text range is [0x10070000, 0x10095DDB] However, in this case it appears that it's ok that the header overlaps with the text section, since the bootloader uses the header to copy the firmware from flash to RAM (the header itself is not copied). BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=elemi TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ic2a7058c85bbcb90c69d2b372f6d33930ac4d212 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3207346 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* core: Fix flash size calculation when linking with lld (clang)Tom Hughes2021-10-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The map file generated by lld has a different format than the gnu linker (ld). (We save this map file into build/<board>/<image>/ec.<image>.map during the build.) Instead of trying to parse the different formats in the .map file, use the .smap file (the output of "nm"), which has the values of the symbols and has the same format whether using lld or ld. We need to add a new "__flash_size" symbol so that we can use that symbol to get the size from the .smap. This add flash sizes to a few boards that previously didn't have it: asurada_scp, cherry_scp, and kukui_scp, since the previous logic was always looking for FLASH and these use IROM. BRANCH=none BUG=b:172020503 TEST=make buildall -j TEST=make CC=arm-none-eabi-clang BOARD=elemi TEST=bcompare build_before_change build_after_change => only difference between space_free_flash.txt and space_free_ram.txt files in the two builds is that this change adds the space_free_flash.txt files for asurada_scp, cherry_scp, and kukui_scp. Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I7c64b6ba9bceeeb4044559188c1c1bebbf60471d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179314 Reviewed-by: Keith Short <keithshort@chromium.org>
* COIL: Change host interface option to CONFIG_HOSTCMD_SHIKeith Short2021-08-031-1/+1
| | | | | | | | | | | | | | Update SPI host interface config option for inclusive language. BUG=b:163885307 BRANCH=none TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* npcx9: support SHA256 hardware acceleratorCHLin2020-10-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | There is the hardware accelerator for SHA computation inside npcx9. This CL wraps the Nuvoton SHA library APIs (which are in the ROM) to Chromium EC's SHA256_* APIs to speed up the SHA256 computation. With the help of the hardware accelerator, the hash computation runs several times faster than the software method (see b:155771688 for more detailed evaluation data.) Also, we can gain ~840 bytes of code size. BRANCH=none BUG=b:165777478 BUG=b:155771688 TEST=pass "make buildall" TEST=flash the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE ; verify the RW hash value is the same in the console message. TEST=with the following test CL, move test patterns in test/sha256.c to board/npcx9_evb/test_sha256.c; pass all test patterns. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I45ca609889bd73573d67d15f3e561614201e60f6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2455021 Tested-by: CH Lin <chlin56@nuvoton.com> Auto-Submit: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* npcx: support enhanced PSL functions in npcx9CHLin2020-10-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. In npcx7, the PSL (hibernation) wakeup source only can come from physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer) module is introduced to support wakeup from a configurable timeout. 2. support PSL wakeup from the VCC1_RST pin. This function is disabled by default and enabled (and locked) in the firmware in the npcx9 A1 chip. In the npcx9 A2 chip, this function is enabled (and locked) by booter. 3. Support pulse mode and open drain (if pulse mode is enabled) for PSL_OUT pin. 4. support one PSL general-purpose output pin which is powered by VSBY. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds. make sure the reset cause in the console is "power-on hibernate rtc-alarm" TEST="hibernate"; check EC wakes up from hibernate after pressing VCC1_RST button on the internal test board. Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1 power; check EC can wake up from hibernate with any input event. Test=configure the level of PSL_GPO before hibernation; check the level is kept after entering hibernation. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: add GPIO support for npcx9 and refactor GPIO driverCHLin2020-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | 1. Add GPIO driver support for npcx9. 2. move the GPIO interrupt handler (MIWU) from gpio.h to gpio-npcx5.h, gpio-npcx7.h, and gpio-npcx9.h separately. Note: gpio-npcx7.h is a link to gpio-npcx5.h because almost all of the source codes are the same. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx5/7/9 EVB and yorp; verify GPIO functionality. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I665507f804ca3772f81f0ff8bd917a633bda2d11 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402842 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: add support for rom resident sectionsKeith Short2020-08-131-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC images are copied in full from flash to RAM. When the code RAM size is smaller than 1/2 the flash size, the EC image size is limited to the code RAM size, leaving unused flash space. Create a new linker section .init_rom used to store data objects that are single use in the previously unused flash area. Data objects can be used at runtime by copying into RAM using the flash_read() function. This change is tied to the NPCX flash layout, with asserts to ensure builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by the chip. CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until the predecessor CL:2325764 is available in CPFE images. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=With debug code, use the _init_rom macro and validate the data can be read using flash_read(). TEST=Using hex editor, verify .init_rom section located at 192K boundary and unused bytes are filled with 0xFF. TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* npcx: Add driver support for PS/2 interfaceCHLin2020-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | Morphius connects the trackpoint device to EC via the PS/2 interface. To support it, we implemented the chip level PS/2 driver in this CL. The PS/2 driver can be used on all series of NPCX EC chips (NPCX5/7). BUG=b:145575366 BRANCH=none TEST=No error for "make buildall" TEST=Apply this and related CLs, connect npcx5/npcx7 EVBs to standard PS/2 keyboards and PS/2 device emulator with different channels. Verify that the PS/2 write/read transaction can keep working for several hours without issue. Change-Id: I5bae313db2d697999c2da5cf33478be2da754b8c Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982302 Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Edward Hill <ecgh@chromium.org> Auto-Submit: CH Lin <chlin56@nuvoton.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* audio_codec: npcx: deprecate legacy option CONFIG_WAKE_ON_VOICETzung-Bi Shih2020-01-141-2/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_WAKE_ON_VOICE consists 3 features in NPCX: - DMIC - I2S_RX - WOV These features has broken down into smaller CONFIG options. Deprecates CONFIG_WAKE_ON_VOICE and prepares to separate smaller features in NPCX. BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ieaa123299ea687644f19066cf95ef150a18bf252 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986687 Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* audio_codec: npcx: migrate DMIC and I2S_RX featuresTzung-Bi Shih2020-01-141-1/+2
| | | | | | | | | | | | | | | Migrates DMIC and I2S_RX to new audio codec framework. BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ifbc6d939110311578c4aa0655ede92b1df714774 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986686 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
* keyscan: decouple keyboard_raw functionality from the presence of TASK_KEYSCANAlexandru M Stan2019-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | With the addition of external i2c keyboard controllers, chips that don't necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN. Therefore it's wrong to assume we want the chip/*/keyboard_raw code included. There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW) that could get #undefd in strategic places. The place that would always define it would be in include/config.h but I don't believe that executes before the build.mk rules. BUG=b:135895590 TEST=Other boards with keyboards still happy. TEST=No compile errors (regarding missing keyboard GPIOS) when declaring TASK_KEYSCAN on a fresh stm32 board. BRANCH=master Change-Id: I061812a6941a11784950280648912edd5844bd79 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* audio_codec: Implement NPCX version of audio host command functionsCheng-Yi Chiang2019-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | This CL implements the host sub command functions for the audio codec by adding calls to the appropriate wov driver API functions. BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: Ifda8f94ce6bbe35a715b04b1fb8cbec8d9c3922c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1356185 Commit-Ready: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* npcx: uart: Add driver support for the second UARTCHLin2018-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nuvoton NPCX79nxB serie chips include two UART ports. In this CL, we add the driver support for these two UART modules. Develoers can select one of the UART ports as EC console by configuring "CONFIG_CONSOLE_UART" in board.h BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB; check EC console working via J21. TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB; check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3 must be connected together.) TEST=build images of board npcx_evb, poppy, and grunt, make sure EC console is functional on these boards. TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write function still works by using the console command like: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1113269 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-221-2/+2
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: CEC: Add stub implementation of CECStefan Adolfsson2018-05-111-0/+1
| | | | | | | | | | | | | | | | | | | Add CEC stub implementation and enable it for Fizz. All it does is print a message when the driver is initialized. Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:76467407 BRANCH=none TEST=Check that "CEC initialized" is printed on the console when the EC boots. CQ-DEPEND=CL:1030219 Change-Id: I1cf674e664e091354e344e0c08a69bd09f415904 Reviewed-on: https://chromium-review.googlesource.com/1030220 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx7: Add definition/configuration for npcx7m6xb/npcx7m7wCHLin2018-01-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: modify the npcxspiflash little firmware to support UUTCHLin2018-01-031-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original ec_npcxspiflash lfw is used by the openocd to program SPI flash via Servo JTAG. In order to support UUT mode to program SPI flash, this CL modified the lfw with the following changes: 1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming. 2. The npcx_monitor will read the first 4 bytes from the area of monitor header. If the monitor identifies the first 4 bytes is a UUT tag, it will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of monitor header. Otherwise, it will read parameter from the general register r0/r1 which will be restored by openocd script in advance. 3. Add monitor_hdr.c to generate the monitor header binary files (monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled. The memory layout to restore the reuqired binaries are listed below: ec firmware(RO/RW) - the start address of Code RAM area. monitor header - 0x200C3000 npcx_monitor - 0x200C3020 BRANCH=none BUG=none TEST=No build errors for "make buildall". TEST=Follow instructions in CL:826763; make sure the ec firmware is updated and ec can boot up. CQ-DEPEND=CL:828341 Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/826909 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-071-1/+1
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: system: Add support for npcx7 series ecMulin Chao2017-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL implements two methods for hibernating on npcx7 ec. One is using PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The other is turning off the power of all ram blocks except the last code ram block. In order to make sure hibernate utilities are located in the last code ram block and work properly, we introduce a new section called 'after_init' in ec.lds.S. We also moved the hibernate utilities, workarounds for sysjump and so on which are related to chip family into system-npcx5/7.c. It should be easier to maintain. It also includes: 1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for hibernating. 2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of wake-up inputs during hibernating. 3. Add DEVICE_ID for npcx796f. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Make sure AC_PRESENT and POWER_BUTTON_L can wake up system from hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is enabled or not on npcx796f evb. Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/493006 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: i2c: Add support for npcx7 series ecMulin Chao2017-05-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL added support for 8 i2c controllers and 11 i2c ports in npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions related to chip family to them. (Such as i2c_port_to_controller(), i2c_select_port() and so on.) Note the layout and bit position of i2c registers which are accessed in these functions are irregular between npcx5 and npcx7. We think abstracting them from i2c.c is easier to maintain. In this CL, we also modified the checking rule for I2C_PORT_COUNT in task.h in order to prevent compiler error. So far, the ECs besides stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule for all ECs seems not suitable. It also includes 1. Remove useless NPCX_I2C_PUBIT macro function. 2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h. 3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c controllers of npcx7 ec. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed i2c stress tests on npcx796f evb. Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/487541 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Introduce npcx7 series ec chip definitions and configurations.Mulin Chao2017-04-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: CONFIG_FLASH should be optionalBill Richardson2016-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The application may need to read/write/erase the flash memory, but we not want console users to do so. This CL adds CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH to be undefined while still providing the chip-specific flash_physical_* accessor functions. There aren't many board.h files that needed changes, since CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; try on Gru with and without CR50_DEV=1 See that it still boots, updates, wipes, restores, etc. without linking common/flash.o in the production image; and that the flash commands are still there in the dev build. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93 Reviewed-on: https://chromium-review.googlesource.com/391188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: Add espi driver of npcx5mng for x86-based platform.Mulin Chao2016-08-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Add espi driver for x86-based platform which support espi interface such as skylake and so on. Added source: 1. espi.c: Add drivers which supports the utilities of peripheral and virtual-wire channels so far. 2. espi.h: Add espi virtual-wire declaration for power sequence FW. Modified sources: 1. lpc.c: Add interrupts and initialization steps for espi. 2. gpio.c: Add interrupt handler of espi reset. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366181 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Rename CONFIG_SHI to CONFIG_HOSTCMD_SPSShawn Nematbakhsh2016-03-081-1/+1
| | | | | | | | | | | | | | | | | CONFIG_SHI ("SPI host interface") has identical meaning to CONFIG_HOSTCMD_SPS ("Accept EC host commands over the SPI slave"). Use CONFIG_HOSTCMD_SPS, since it came first and is already defined in config.h. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I665c405ad72caa3b84e583a80c0893e4c625632a Reviewed-on: https://chromium-review.googlesource.com/331342 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Add CHIP_VARIANT variant for different versions of npcx ec.Mulin Chao2016-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT variant to distinguish which verson ec is. In config_chip.h, we use CHIP_VARIANT to specify the size and start address of program memory. Ecst tool also needs a chip parameter to make sure the address range checking of entry pointer won't fail. Modified sources: 1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec of npcx ec. 2. config_flash_layout.h: Replace constant value with CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE. 3. build.mk: Add -chip parameter for ecst tool to check entry address. 4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g). BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330072 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Simplify adc/pwm/fan drivers and related structures in boardsMulin Chao2015-09-291-1/+1
| | | | | | | | | | | | | | | | | | | Modified drivers: 1. register.h: Add marco field operation funcs for muti-bits field of register. 2. adc.c/fan.c/pwm.c: Simplify field operations by marco funcs. 3. adc.c: Add support for ADC_CH3/4 4. pwm.c: Add PWM_CONFIG_DSLEEP_CLK flag 6. fan.c: Support multi-fans mechanism BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Iaaeb6c4ae8d55b4245a1cefb9c20feae4c0fdec2 Reviewed-on: https://chromium-review.googlesource.com/300673 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc:Ian Chao2015-07-251-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* WIP - Nuvoton 30-Jan patchRandall Spangler2015-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues fixed on 0216: 1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c 2.Modified warm_reset checking in gpio.c 3.Modified system_get_chip_name in system.c for package info. 4.Modified fan.c and pwm.c for: ● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low. ● Fan stall condition event: If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called. 5. Change cycle_pluses to 480 in board.c Issues fixed: 1. Jump data at top of RAM is getting corrupted. Changed the flag to RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST issue. 2. Hibernate wake need to report whether wake reason was GPIO or RTC 3. Hibernate wake must be distinguishable from watchdog reset. The booter will log reset reason in Code RAM. I copy the log data to battery-backup RAM in little FW. And system driver will refer this data to distinguish if it's watchdog reset or not. 4. Watchdog reset flag is not set. Same fix as 3. 5. Should return error if unable to clear SPI flash status register. 6. Remove chip_temp_sensor.c 7. Remove use of pstate from flash driver 8. Remove support for watchdog warm reset 9. Keyboard raw driver must support COL2 inverted 10. LPC memory mapped data must be read-only from host 11. LPC should support PLTRST# signal 12. Problems reading chip type/version. Use core registers and ROM data to read IDs. 13. When chip type/version is unknown, report hex value. 14. Watchdog does not consistently print panic information. 15. Remove console force enable logic. 16. Enable only the peripheral clocks that are needed. Please notice user should add bit mask in CGC_XXX_MASK if they want to enable additional module. For example, if user wants to enable PWM3, he must add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK. Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions. If I turn off all I2C modules in system_pre_init and turn on the modules I need in i2c_init, I found its freq is not correct. The root cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in clock_init) before i2c_init. At this time, i2c modules are power-down and writing to freq register is useless. I re-execute freq-changed hook function after turning on modules again. 17. MPU properly configured to prevent code execution from data RAM 18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM. Additional items we also modified: 1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func array to support it) 2. ec_npcxflash.c: Use definition to replace constant value. Stop watchdog during flash programing. 3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock MPU commands for Data RAM. BUG=chrome-os-partner:34346 BRANCH=none TEST=manually verify changes Change-Id: I722a77d29e7543b054819480c7b7477af4263119 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248670
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-141-0/+38
Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
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