summaryrefslogtreecommitdiff
path: root/chip/lm4
Commit message (Collapse)AuthorAgeFilesLines
* Drop DPWROK when system is off for more than 10 secrelease-R20-2268.BRandall Spangler2012-05-091-18/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | This saves ~70mw of power. To make this work, I also had to stretch the power button signal to give the system a chance to come back up when the user taps the power button. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9574 TEST=manual For each of the following tests, wait ~15 sec after the system is powered off to give it a chance to drop DPWROK. 1) tap power button -> system turns on 2) hold power button 1 sec -> system turns on 3) open lid -> system turns on 4) silego reset (power+refresh, or power+esc on proto1) -> system stays off 5) silego recovery (power+esc+refresh) -> system turns on 6) hold down power button and type 'reboot' on EC console -> system turns on 7) type 'powerbtn' on EC console -> system turns on Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
* Add hooks for chipset power transitionsRandall Spangler2012-05-092-0/+27
| | | | | | | | | | | | This is cleaner than having x86_power explicitly know about everything else in the system that cares about power transitions. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=boot and shutdown system; still works. Mouse powered to system is off in S5. Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
* Change recovery key to ESC on EVT systemsRandall Spangler2012-05-081-2/+13
| | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9554 TEST=manual 1) Boot system. No recovery. 2) Boot system holding down Refresh+Esc. No recovery. 3) Hold down Power+Esc. System reboots and stays shut down. 4) Hold down Power+Esc+Refresh. System reboots into recovery mode. Change-Id: I53db224b6d2a03406244e79fb64fb67851919857
* Add gpio_set_flags() and system_get_board_version()Randall Spangler2012-05-082-29/+55
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=version; board version should be 0 on proto1 and 1 on EVT Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
* Merge "Move gpio list into gpio.h header file"Gerrit2012-05-081-4/+0
|\
| * Move gpio list into gpio.h header fileSimon Glass2012-05-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is referenced by various files, so should be in the gpio.h header. BUG=none TEST=manual: build and boot on daisy, see that USB download still works build on all platforms Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4 Signed-off-by: Simon Glass <sjg@chromium.org>
* | Clean up sysjump struct parsing and add memmove()Randall Spangler2012-05-071-0/+2
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9447 TEST=update from old EC 517 to this one Change-Id: I275b5bf6c4ae1ab6e0c0a05cf9260314d644c79b
* Update EC config and FMAP to reserve room for vboot signaturesBill Richardson2012-05-041-8/+18
| | | | | | | | | | | | | This just reserves room. It doesn't actually perform any verification yet. BUG=chrome-os-partner:7459 TEST=manual make BOARD=link dump_fmap build/link/ec.bin Change-Id: I424db1d601a614be3dfe5abb200e24e8bc62e47e Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Merge "Add link helper procedure"Gerrit2012-05-041-0/+6
|\
| * Add link helper procedureVadim Bendebury2012-05-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Jim procedure to program the Link EC image from the default location as generated by 'emerge-link chromeos-ec'. BUG=none TEST=manual . emerge-link chromeos-ec . start openocd as described in the Link care and feeding document . in the port 4444 terminal session type flash_emerged_link . observe it succeed Change-Id: Ibfbc38060d7e82ec8c83a73e2ccadff81d633ae4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
* | Add gpio_get_name() to return the name of a signalSimon Glass2012-05-031-0/+6
|/ | | | | | | | | | | | Add this to the GPIO API. It seems that the implementation is copied in LM4 and STM32 so I have reluctantly done the same with this new function. BUG=chrome-os-partner:9424 TEST=build and boot on Daisy Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge "Enhance LPC EC REBOOT reset command to allow to request recovery"Gerrit2012-05-021-0/+4
|\
| * Enhance LPC EC REBOOT reset command to allow to request recoveryVadim Bendebury2012-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the host reboots the EC it should be able to request the EC to force recovery mode after reset. This is achieved by extending the REBOOT EC command with a bitmask byte, with bit 0 dedicated to recovery request. So, when BIOS on the way up determines that recovery is requested, but the EC is not running from the RO space, the BIOS would reset the EC forcing it to run from RO and to request recovery mode through the LPC bitmask. Then BIOS will restart itself ensuring that the system comes up in consistent state. Some refactoring was also done to make the code a bit more compact. BUG=chrome-os-partner:9040 TEST=manual . tested along with coreboot changes (test described in the coerboot CL). Change-Id: I29801b6aec80da0901ba0e8db8e92e615cc778bd Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
* | make verified boot feature optionalVincent Palatin2012-05-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this fixes the build breakage on stm32-based platforms. In the linker script, remove the ASSERT since this macro is not designed to work in that context and this size condition is already verified by the linker by setting the "length" of the "FLASH" memory region. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=daisy boot on Link and Daisy Change-Id: I08964749d44f47caa0a359bc93c303a9611e5d73
* | Add basic FMAP to EC firmware image.Bill Richardson2012-05-011-0/+9
|/ | | | | | | | | | | | | | | | | | | | | | | This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff. Still, you should be able to do things like this: flashrom -p internal:bus=lpc -r ec.bin flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat BUG=chrome-os-partner:8198 TEST=manual Build the image, look for the FMAP in it. cd src/platform/ec make BOARD=link dump_fmap ./build/link/ec.bin Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Prevent issuing warning when fan is offVic Yang2012-04-301-1/+2
| | | | | | | | | | | | LM4 reports fan stalled when fan speed is set to 0. Need to check this before issuing warning. Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=chrome-os-partner:7497 TEST=Did not see fan stall warning when fan speed is 0. Change-Id: I8eecca8516b5442d4943d9195d04acc5b4041085
* Merge "Issue warning on fan stall."Gerrit2012-04-261-0/+16
|\
| * Issue warning on fan stall.Vic Yang2012-04-261-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | When PWM module detects fan stall, issue SMI warning and print warning message to console. Signed-off-by: Vic Yang <victoryang@google.com> BUG=chrome-os-partner:7497 TEST=Disconnect fan and power up. See warning message. Change-Id: I4d96595f7f3cdfab5df333afc35206304bacab9d
* | Merge "Remove unused uart.h includes"Gerrit2012-04-252-2/+0
|\ \
| * | Remove unused uart.h includesRandall Spangler2012-04-252-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: I8f9c6e67427a5c7f2c42754b421db44504f9c10d
* | | Merge "Watchdog fixes"Gerrit2012-04-251-22/+22
|\ \ \ | |/ /
| * | Watchdog fixesRandall Spangler2012-04-251-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) When frequency changes, reload the watchdog timer right away, or it may expire before the next reload. (Only matters when re-enabling the PLL.) 2) Split out the timer/task debug output used by the watchdog into their own routines, instead of assuming it's safe to call the command handlers. Also make the flushes in those print routines safe to call from interrupt level. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=waitms 1500; should print task dump again Change-Id: I07e0ed24a526ae499566dab0bbeb0f5755cd5be6
* | | Merge "Add more info to pll debug command"Gerrit2012-04-251-2/+14
|\ \ \ | |/ / |/| |
| * | Add more info to pll debug commandRandall Spangler2012-04-251-2/+14
| |/ | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=pll, then pll on, then pll off Change-Id: I9e220a20e234f5eb30009d0a2a4fc080a167c971
* | Fix watchdog handler stack alignmentRandall Spangler2012-04-251-5/+8
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9306 TEST=waitms 1600; see that timer info isn't all upscrewed Change-Id: I7945f5114bbe0e9525cac76ce7376d4c32c4e654
* Use console output instead of uart output for console commandsRandall Spangler2012-04-247-81/+70
| | | | | | | | | | | | This completes console output cleanup. The remaining calls to uart_puts() and uart_printf() actually need to be that way. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual Change-Id: Ib1d6d370d30429017b3d11994894fece75fab6ea
* Refactor async console outputRandall Spangler2012-04-244-39/+42
| | | | | | | | | | | | | | | | | | This adds a 'ch' command which prints/sets which channels are active This handles all the async output; the remaining debug commands will be refactored to use ccprintf() / ccputs() in a followup CL. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual ch --> all channels active ch 0x100 -> just port80 active powerbtn -> system boots; only port 80 codes shown on console Change-Id: I9efc43acec919b62b78c2c82c61946d32380adfe
* Implement task profilingRandall Spangler2012-04-241-1/+1
| | | | | | | | | | | | | | Also tracks the distribution of IRQs, so we can see what's triggering interrupts. Task profiling is optional, enabled via CONFIG_TASK_PROFILING. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=taskinfo Change-Id: I266f2b49bff9648cda446210d5a302b460fec244
* Merge "Disable PLL at end of init"Gerrit2012-04-241-9/+24
|\
| * Disable PLL at end of initRandall Spangler2012-04-241-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This saves power. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual Get a proto1 system modified with INA current sensor 1) From chroot: dut-control i2c_mux_en:on i2c_mux:rem dut-control pp3300_alw_mv pp3300_alw_ma 2) From EC console: pll (this should turn the PLL back on; it'll report clock frequency ~66MHz) 3) From chroot: dut-control i2c_mux_en:on i2c_mux:rem dut-control pp3300_alw_mv pp3300_alw_ma Current (ma) should be bigger than in step 1 Change-Id: I806953684c57fd60bf481acb01dddffe2f2ad0ed
* | Set BOOTCFG register to test valueRandall Spangler2012-04-242-1/+14
|/ | | | | | | | | | | | | | Needed for testing preprogramming chips Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8769 TEST=manual hibernate 1; should reboot rw 0x400fe1d0; should print: read word 0x400fe1d0 = 0xfffffdfe Change-Id: I95b419d7285a0bf5204f95d1f68f64dc212bb39e
* Merge "Remove clock calibration for PIOSC"Gerrit2012-04-202-10/+16
|\
| * Remove clock calibration for PIOSCRandall Spangler2012-04-202-10/+16
| | | | | | | | | | | | | | | | | | | | | | Proto1 has A3 silicon which is factory-trimmed. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7693 TEST=boot and look for glitchy EC console. If it's not glitchy, it worked. Change-Id: I56cb2458e600e76e458bce0f24832ef4f456ac14
* | Add openocd macros to write image A or BRandall Spangler2012-04-201-6/+15
|/ | | | | | | | | | | | | | | | | | | These are faster than writing the entire EC, and safer if you're mucking with things like the clock config. Of course, if you're changing verified boot or something else that happens before vboot_init(), these new commands won't help, and you should keep using the existing flash_link command. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual from openocd - Compile a new image - From openocd, flash_link_b - From ec console, note build compile date in image A: shouldn't have changed - From ec consle, sysjump b; compile date should be for your new image Change-Id: Ifd6aabe963948d3c5da5bdeb78c5f962a0f9f857
* Implement HOOK_SYSJUMP and use it to preserve LPC host event maskRandall Spangler2012-04-191-99/+131
| | | | | | | | | | | | | | | | | | | | This also changes shared_mem to use all the remaining RAM, instead of reserving a fixed-size buffer. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9161 TEST=manual hostevent --> all masks should be 0 hostevent smi 0x12300000 hostevent --> should confirm SMI mask was set sysjump b hostevent --> should confirm SMI mask is still set reboot hostevent --> should confirm SMI mask is back to 0 Change-Id: Iccb6da6ccc93ee5036a3f478d24b717a462d9150
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-198-9/+28
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* Clean up initsRandall Spangler2012-04-193-17/+6
| | | | | | | | | | | | We can clear the reset cause in system pre-init now because of a previous change which preserves it across a sysjump. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I1d8b99df5a0be0de9545d22ad1a6b7fb3140f813
* Add hooks module so modules can be notified of system-level events.Randall Spangler2012-04-195-37/+36
| | | | | | | | | | | | This will be used for sleep/wake/sysjump/etc. For now it's just wired up to clock frequency changing. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual: use nopll command, should still work Change-Id: Iedcea5830bc18eacfd955c29b8f793aba8905dd8
* EC: Use interrupt for ADCVic Yang2012-04-161-3/+49
| | | | | | | | | | | | We used to wait in a loop for ADC conversion completion. This CL modify this to use real interrupt. Signed-off-by: Vic Yang <victoryang@google.com> BUG=chrome-os-partner:7492 TEST=See 'temps' still reporting EC internal temperature Change-Id: Iffd3cc3c021d82d3284bed198589be5b63d72d4d
* Disable screen and keyboard backlights when lid is closed.Randall Spangler2012-04-132-5/+38
| | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7832 TEST=manual 1. Power on system 2. From ec console: kblight 100 3. Use a magnet next to the left shift key to trigger the lid switch. Screen and keyboard should go dark. 4. Remove the magnet and they should light up again. Change-Id: I298ea94930976153d8dcd102316b010ee28cd747
* Fix power button turning system back on after 4 secRandall Spangler2012-04-121-3/+16
| | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8981 TEST=manual Turn system on Hold power button for 5 sec Let go System should stay off Change-Id: I4660108972795d631b7c33926df58513ee09e1c7
* Add timeout for flash operations.Randall Spangler2012-04-121-5/+19
| | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7479 TEST=manual. From the linux console, ectool reboot_ec RO ectool flashread 81920 163840 /tmp/ec.bin ectool flasherase 163840 81920 ectool flashwrite 81920 /tmp/ec.bin ectool reboot_ec A Change-Id: I850f4cea5dfdb76cfe3957988b10cf8841de55c1
* Re-enable watchdog in watchdog_reload()Randall Spangler2012-04-121-14/+21
| | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8971 TEST=manual waitms 1500 (see watchdog trace) waitms 1500 (should see watchdog trace again) waitms 3000 (should see trace, then system should reboot) Change-Id: Ieb5009d7a7bc9e1ed795e58efb0cb44a1eeb2706
* Reload watchdog timer during flash operations.Randall Spangler2012-04-121-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8967 TEST=manual While ssh'd into the device: 1) Create a test image: Extracting to: /tmp/ecup 132+1 records in 132+1 records out 136132 bytes (136 kB) copied, 0.000550122 s, 247 MB/s 2) Force the EC into its RO image: done. 3) Erase the A and B images, then reprogram them: Erasing 163840 bytes at offset 81920... done. Reading 136132 bytes from /home/chronos/user/ecb.bin... Writing to offset 81920... done. 4) Repeat step 3 about 10 times while monitoring the EC debug console. Commands should complete successfully all the time. (Note that during the flashwrite, there's a ton of debug output; what you should NOT see is something like this: WATCHDOG PC=00002104 / LR=0000597f / pSP=200013a0 Change-Id: I2f1f05eb19abcd6e19c6364f6d4ac785cca6a4c6
* Merge "Update keyboard scanning for stm32 to use messages"Gerrit2012-04-111-0/+6
|\
| * Update keyboard scanning for stm32 to use messagesSimon Glass2012-04-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide the required plumbing for the stm32 keyboard scan code so that the message layer will pick up keyboard scans. The design is as follows: - When a change in keyboard state is detected, the keyboard matrix scanning code will call the board-specific board_keyboard_scan_ready() function to interrupt the AP. - The AP will initiate a CMDC_KEY_STATE transaction over SPI or I2C - The SPI or I2C driver will call message_process_cmd() to process the command - This in turn will call keyboard_get_scan() to get the latest scan data For SPI: - The AP will initiate an 20-byte (or longer) SPI transaction - The EC will see the command, and provide the keyboard state in response, with the response being part of the same transaction For I2C: - The AP will initiate a 1-byte write to set the EC mode. - The AP will then initiate an 18-byte read, and the EC will send the message including keyboard state BUG=chromium-os:28925 TEST=build on daisy and discovery; run on daisy Change-Id: I905ef9d567e43d85fb851052f67586eff58e1167 Signed-off-by: Simon Glass <sjg@chromium.org>
* | Add USER_REG3 and indicate it's reserved for preprogramming process data.Randall Spangler2012-04-111-0/+3
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8889 TEST=code still builds Change-Id: Ifdd31189fb5de779f090aa089173407e381c62b7
* Add fake developer switchRandall Spangler2012-04-102-23/+52
| | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8884 TEST=manual optget fake_dev_switch --> 0 optset fake_dev_switch 1 optget fake_dev_switch --> 1 optset fake_dev_switch 0 optget fake_dev_switch --> 0 Reboot by holding ESC+D and tapping power optget fake_dev_switch --> 1 Reboot by holding ESC+F and tapping power optget fake_dev_switch --> 0 Change-Id: Iccb3bc8b3d571e551e204892769efc4161858055
* use the full 256kB for partitionsVincent Palatin2012-04-102-8/+3
| | | | | | | | | | | | Now Link has 256kB parts, we can restore the third partition and use 80kB partitions. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Link proto-1, try to use RO/A/B images (sysjump B, then boot). Change-Id: I9b7e4cae1504e86a62643db4d035cc9f3de0af52 (cherry picked from commit cefaf59328e4b91308d0347cc1f55861e93db480)
* Support dynamically changing the system clockRandall Spangler2012-04-096-104/+193
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
View Lorry Controller Status