summaryrefslogtreecommitdiff
path: root/chip/g
Commit message (Collapse)AuthorAgeFilesLines
...
* g: avoid CERT_28Marius Schilder2019-06-271-19/+1
| | | | | | | | | | | | | | | | | | | | | | | chip/g has a hardware KI with executing CERT_28 more than 512 times after reset. Current use of CERT_28 makes little sense so we address the issue with deletion. While at it, delete a bunch of other useless code in this function. Ultimately we're left with just pulling bits from TRNG and mixing them with entropy from the keyladder as mild hedge. Signed-off-by: mschilder@google.com BUG=b:127343845 BRANCH=none TEST=b:127343845 Change-Id: I84218f644aa2508c45101464512019754647f229 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646533 Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org> Auto-Submit: Marius Schilder <mschilder@chromium.org>
* g: try batching USB stream data under heavy loadVadim Bendebury2019-06-272-55/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX data rate is much higher than UART RX, this results in USB driver streaming data received from UART in smaller than max size chunks, which in turn means that per byte overhead of shipping USB packets to the host is not as low as it could have been. This patch detects attempt to ship less than full chunk over USB stream and instead of processing data immediately posts a deferred function, which is supposed to triggers another send attempt in a few milliseconds. If there is a high traffic on the stream, the queue would have much more data after deferred interval ends. The problem with the posted deferred function is the fact that it is not guaranteed to run soon enough in case there are other deferred functions waiting. To address this issue an additional check is being introduced to make sure that the USB buffer does not overflow: if the deferred function is posted, and the buffer is half full or more, let's cancel the deferred function and process the stream right away. If the deferred function gets to execute - there is a chance that a UART and or USB interrupt comes while the deferred function is running, which is likely to mess up USB controller settings by tx_stream_handler(). To avoid these issues, interrupts are disabled before the kicker function calls the handler. Note that this optimization applies only to AP and EC console streams. BRANCH=cr50, cr50-mp BUG=b:38448364 TEST=two full chargen streams on an octopus device run indefinitely and don't seem to be interrupting even when some CLI command is ran on the Cr50 console or when an update is uploaded over USB or TPM Change-Id: Id151c494967d1eb15d2af42acf8f2282966b5147 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672209 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: set up USB TX in USB endpoint interrupt handlerNamyoon Woo2019-06-272-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX used to be set up in a deferred function. This patch makes USB endpoint interrupt handler to setup USB TX to speed up sending data to host USB. It reduces Flash usage by 100 bytes, and RAM usage by 40 bytes. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=(1) Flashed EC FW on fleex (uut), atlas (npcx_int_spi), ampton (it83xx), bob (npcx_spi), coral (npcx_spi), and scarlet(stm32). (2) Flashed AP FW on fleex. (3) Ran firmware_Cr50DeviceState on Coral. (4) Uart Stress Tester on fleex. [ before applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... ERROR : /dev/ttyUSB2: 1953 lost / 330330 : .5 % ERROR : /dev/ttyUSB1: 451 lost / 200655 : .2 % [ after applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... INFO : /dev/ttyUSB2: 0 lost / 334425 : 0 % INFO : /dev/ttyUSB1: 0 lost / 200655 : 0 % Change-Id: Ic966486f034a199b601ca002f6ed76a73b2b9dd8 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1574661 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: make uart run fasterVadim Bendebury2019-06-241-14/+17
| | | | | | | | | | | | | | | | | | The EC queue library wrappers are very heavy, let's bypass them and use direct queue access where performance matters the most, in the UART RX driver used by USB streams. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=with the rest of the patches in place observed a much more reliable streaming of two consoles (ec and ap), both pumping chargen streams into their respective UARTs on an Octopus device. Change-Id: I45dc8f1c0841b43e17ef67e96820669053fba831 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672208 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Revert "g: minor fix in putting a character into usb_console tx queue"Namyoon Woo2019-06-191-19/+21
| | | | | | | | | | | | | | | The patch cases slow-down in CR50 uart when RDD is not connected. BUG=None BRANCH=None TEST=manually ran on bob This reverts commit 2d62dee3a8f32499bab8f4b95b84a9eaeea919dc. Change-Id: I92c4b8e7d065a01dc2c398778351db207ab28ca5 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666318 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-1917-17/+17
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "g: consolidate USB console transfer codes to usb-stream"Namyoon Woo2019-06-183-90/+12
| | | | | | | | | | | | | | | | | | | | | This reverts commit 79e88d81f3e090d959669b4de6215cef96c2a3ed. Reason for revert: It slows down CR50 UART console response. The original plan was to consolidate CR50 console USB configuration into USB stream configuration, then optimize USB stream implementation. However, I am changing the plan: will commit this patch after USB stream is optimized. BUG=None BRANCH=None TEST=Downloaded the cr50 bin, and checked the cr50 console responding stable. Change-Id: I21ae8c4e043e10c4325bbf91123f2ee185faa413 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1662849 Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: system: move print statements to CC_SYSTEMMary Ruthven2019-06-181-19/+18
| | | | | | | | | | | | | | | Move the system prints to CC_SYSTEM, so we can disable them when we just want to print console output. BUG=none BRANCH=cr50 TEST=chan 0 disables these prints and they're still printed normally Change-Id: Id728729c8472a033d6a9702991c32c3b809588b1 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1656519 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: minor fix in putting a character into usb_console tx queueNamyoon Woo2019-06-141-21/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When __tx_char attempts to push a character into tx_queue, it doesn't return an error if it fails. Eventually usb_puts() doesn't recognize tx queue getting full if it happens, and processes all characters, and always return EC_SUCCESS. BUG=None BRANCH=None TEST=ran uart_usb_tester on bob. uart_stress_tester.sh --pty="/dev/ttyUSB0 /dev/ttyUSB2 /dev/ttyUSB1" --min_char 400000 INFO : ChromeOS UART stress test starts. INFO : UART devices: /dev/ttyUSB0 /dev/ttyUSB2 /dev/ttyUSB1 ...................................................... INFO : /dev/ttyUSB0: 0 lost / 483415 : 0 % ERROR : /dev/ttyUSB2: 277497 lost / 415835 : 66.7 % ERROR : /dev/ttyUSB1: 244459 lost / 400575 : 61.0 % INFO : Test files are in /tmp/uart_stress_tester.sh_latest INFO : and also in /tmp/tmp.X7jwZfxNe2.uart_stress_tester.sh. ERROR : FAIL CR50 console (/dev/ttyUSB0) error rate got improved from 4~7% to 0 %. Change-Id: I5ae0b7bd494fbc29978ce3e87531e246a9be51f8 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1650622 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: consolidate USB console transfer codes to usb-streamNamyoon Woo2019-06-143-13/+91
| | | | | | | | | | | | | | | | | | | usb-console.c and usb_stream.c include some amount of copied/pasted code. This patch converts USB console implementation to USB stream to reduce the redundancy. Flash usage decreases by 260 bytes. BUG=None BRANCH=None TEST=Ran uart_stress_tester.sh (http://crrev.com/c/1586581/23) on bob. This CL slightly increases CR50 console char loss rate: 5.5% -> 6.5% in average. Change-Id: Ibdc16867618d67ae33574e802c1949aa6b5cf1a6 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1648921 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: use GLOBALSEC_REGION5 for flash log access controlVadim Bendebury2019-06-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flash log space access needs to be explicitly enabled. The previously chosen for this purpose global security region 7 is also used by the TPM endorsement procedure, and this may cause race condition resulting in flash log space not accessible. Let's use previously unused region 5 instead. This is how the regions are configured after this patch on a system where RO_A and RW_B are active (bit 0 enables region in general, bit 1 enables reads, bit 2 enables writes): Reg Base Size Enable bits 0 00040000 000027ff 3 # RO_A 1 00084000 00037fff 3 # RW_B 2 00044000 000387ff 7 # RW_A 3 0007c800 000037ff 7 # NVMEM 4 000bc800 000037ff 7 # NVMEM 5 00083800 000007ff 3 # Flash log 6 00028400 0000000f 3 # Info 1 board ID 7 00028000 000007ff 3 # Info 1 endorsement seed BRANCH=cr50. cr50-mp BUG=b:132287488 TEST=verified that there is no flash log lockups when the device boots with an unendorsed TPM. Change-Id: I4fc65989b3930d91ed8e076310ecb58bac5f085e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1656158 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: reduce a mem copy in usb upstream transferNamyoon Woo2019-06-122-17/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream data path from uart to usb for cr50/ec/ap console is as below: UART RX FIFO -> (usart) rx buffer -> usb config consumer queue -> usb tx buffer -> USB HOST This CL reduces a memory copy from consumer queue to usb tx buffer by giving the memory address of head in consumer queue in USB endpoint descriptor. This CL can set up to two endpoint descriptors since the queue is implemented as linear queue, and target data could be separated in two continuous area. This reduces RAM usage by 312 bytes, but increases Flash usage by 208 bytes. BUG=b:38448364 BRANCH=cr50 TEST=ran uart_stress_tester.sh on bob, and checked the character loss improves from 41% to 33%. Also checked flash_ec on coral, scarlet, bob, and ampton. Change-Id: I42dc07e0f4bf327f3e8bfed825f8fdc4063572b4 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1570148 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: enforce order of enabling RO/RW sectionsVadim Bendebury2019-06-071-8/+14
| | | | | | | | | | | | | | | | | | | | | When a post update reset happens and the host sends the vendor command to enable the update, in case both RO and RW have been updated, the Cr50 should enable the RW section first, and then the RO. This would cover the case when the new RO has the new key and would not be able to start the old RW, so the matching RW must be available first. Enabling RW without enabling RO is not a problem, worst thing which could happen is that the old RO would not start the new RW and the update process will have to be repeated. BRANCH=cr50, cr50-mp BUG=b:74100307 TEST=none yet. Will verify when a new RO is available. Change-Id: I00175a5a957166d4423fb270bbe9f92d4e408d5c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644479 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add rx_handled into USB_STREAM_CONFIGNamyoon Woo2019-06-062-10/+15
| | | | | | | | | | | | | | | | | | | | | The variable rx_handled tracks how many of the bytes in the HW FIFO was moved into the incoming queue. It used to be defined as local static variable for multiple USB_STREAM_CONFIGs, and could cause a problem if multiple USB downstream traffic get heavier. It should be defined for each USB_STREAM_CONFIG. This patch add rx_handled into USB_STREAM_CONFIG, which tracks how many of the bytes in the HW FIFO was moved into the incoming queue. BUG=None BRANCH=None TEST=manually ran uart_stress_tester.sh and flash_ec on Bob. Change-Id: I561a54b0594a71b557693007a181bde48155d403 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644958 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: keep track of frequent update attacks separately for RO and RWVadim Bendebury2019-06-041-9/+61
| | | | | | | | | | | | | | | | | | | | | | | Cr50 image update handler guarantees that malicious attempts to write into the same block will be prevented. In fact writes into the same address or below the most recently written block not accepted sooner than in 60s. This scheme causes rejection of the RO image if it is located below the RW, as the RW image needs to be updated first. To address the problem this patch adds code to keep track of the previously written block offsets in RO and RW images separately. BRANCH=cr50, cr50-mp BUG=b:74100307 TEST=tried updates from all four permutations of running images (ro[ab], rw[ab]), verified that all updates succeed. Change-Id: Iebc016d85fc0c9343feb18998d5c2e4e60d38b14 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1626317 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: improve trng error handlingVadim Bendebury2019-05-241-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to track TRNG stalls happening in the field. This patch adds a log message to report detected TRNG stalls. The code detecting the stall is being modified to monitor a different status bit as per chip designer recommendation. A console command allowing to test TRNG is being added, compiled in only if TEST_TRNG is defined. BRANCH=cr50, cr50-mp BUG=b:27646393 TEST=compiled the test command in, ran the command rand 10000000 several times, observed reasonable stats and no stall reports. Change-Id: Idcf83ff2c41e23f601b8da8c46fa4d4d1cde0270 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1601470 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: do not run when crypto is disabledVadim Bendebury2019-05-241-0/+5
| | | | | | | | | | | | | | | | | | There is no point in trying any nvmem operations when encryption/decryption services are not available. Test changes necessary to make sure test app compiles and runs successfully. BRANCH=cr50, cr50-mp BUG=b:132800220 TEST=The device does not crash any more after tpm is disabled. Change-Id: I97f9afc6e4d5377162500fc757084e4d5a57d37d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615424 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Change G2F cert CN to "CrOS"Louis Collard2019-05-212-8/+19
| | | | | | | | | | | | | | BUG=b:132310780 TEST=flash to soraka, retrieve G2F cert, check CN retrieve anonymous U2F cert, check CN unchanged BRANCH=none Change-Id: Id409ac5d534f2ee9e16376d690f58b184f5ac1a6 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1614581 Reviewed-by: Andrey Pronin <apronin@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* g: do not destroy manufacturing space by flasheraseVadim Bendebury2019-05-172-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | When modifying flasherase behavior last time around, it was mistakenly presumed that the manufacture_space field was set during Chrome OS device manufacturing. In fact it is set during chip manufacture and should be preserved. BRANCH=none BUG=b:132720245 TEST=using a device with H1 with cert seeds present: - install CR50_DEV=1 image containing this patch - install a recent prod image (it is not yet running, as its version is lower than the ToT) - on Cr50 console run . flasherase . rollback - observe the released image start and successfully complete TPM manufacture process. Change-Id: Id028ffc51bb69810a0564c915b1be944ff5f1d89 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615422 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: prevent USB read queue overflowNamyoon Woo2019-04-263-2/+8
| | | | | | | | | | | | | | | | | | | | CR50 should check whether USB RX queue has enough space for host data. If not, it schedules to retry it in another deferred call. BUG=b:130908211 BRANCH=cr50 TEST=manually ran "echo 'help' > /dev/ttyUSB0" more than 30 times. Without this CL, it used to break cr50 console input, and it worked as if it is 'read-only'. After applying this CL, cr50 console input works normal even after excessive input stream. Change-Id: Ieace84b51c31800b52d2c4a9334e6ffe7888e592 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576326 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* tasks: convert TASK_EVENT_CUSTOM macro to bitJett Rink2019-04-243-9/+9
| | | | | | | | | | | | | | | | | | | | | We should ensure that all custom task definition are non-zero and fit with the globally defined events. Add compile time check and change semantics to specify bit number (instead of making all callers use the BIT macro). This also fixes an error with TASK_EVENT_PHY_TX_DONE for ITE being 0. The bug that made that happen hasn't landed on any firmware branches that use it though. BRANCH=none BUG=none TEST=builds Cq-Depend:chrome-internal:1178968,chrome-internal:1178952 Change-Id: I5e1d1312382d200280c548e9128e53f4eddd3e61 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570607 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* cr50: sqa: don't modify flags if board id is erasedMary Ruthven2019-04-151-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 can only set a board id if the board id is blank. 0xffffffff:0xffffffff:0xffffffff is a blank board id. As SQA images are now if you run eraseflashinfo while the board id isn't set, eraseflashinfo will set the flags to 0 without changing the RLZ information. The BID will be 0xffffffff:0xffffffff:0. This board id isn't considered blank, so you won't be able to set the RLZ in the future. Also the second field is not the inverse of the first, so it will be considered invalid. This is a very bad state to get the board id into because you can't change it, but it's also invalid. This change checks that the board id is set before modifying the flags. Cr50 wont modify the flags of an erased board id. It will only change the flags if the board id is set. BUG=none BRANCH=none TEST=erase the board id. make sure flags aren't set to 0 after running eraseflashinfo. Set the board id. Make sure flags are set to 0 after running eraseflashinfo. Change-Id: Idc184e58c0dc398bc93c1119d822a13889c59963 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1565452 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: upgrade_fw: check board id if CR50_RELAXED isn't definedMary Ruthven2019-04-151-1/+1
| | | | | | | | | | | | | | | | | | | | | CL:1529834 mistakenly changed an ifndef to a ifdef. If CR50_RELAXED is defined, contents_allowed should always return True. In a normal image contents_allowed should check the board id before an update. This change changes the ifdef back to ifndef which is what it should be. BUG=none BRANCH=cr50 TEST=create dbg image and try to flash an image with a mismatched board id. Make sure it runs ok. Build a non dbg image and make sure mismatched board id images are rejected. Change-Id: I1dcef5a6af4edbb431fe894ca37df5dc4e1b852e Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1561972 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: clean up UART channel namesVadim Bendebury2019-04-111-6/+5
| | | | | | | | | | | | | | | For some reasons functions dealing with the Cr50 console are using the 'uart_ec' prefx. This patch renames them to match the actual use. BRANCH=cr50, cr50mp BUG=none TEST=make buildall -j still succeeds. Change-Id: Ifc216fdfa1adf42e96e491b65250d1cfa73f8cd4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1551690 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* cr50: add INFO1 RW MAP erasing to CR50_SQA modeVadim Bendebury2019-04-104-57/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building with CR50_SQA defined, the resulting image is supposed to allow transitioning the H1 chip it is running on from pre-pvt to MP track. This should include preserving the Board ID value, but setting the board id flags to zero, and erasing the INFO1 RW map, because older MP image could have a less restrictive mask. The rest of the INFO1 space should be preserved. Sometimes there is a need to set flags to a non-zero value and migrate from MP to pre-pvt. This would be possible if image is compiled with CR50_SQA set 2 or a larger numeric value. This patch creates a structure describing the layout of the INFO1 space and modifies the 'eraseflashinfo' command to behave differently depending on the build time configuration. In addition to erasing the INFO1 RW map: - when CR50_DEV is set - everything but INFO1 RO map is erased - when CR50_SQA is set to 1, the board ID flags are set to zero, and INFO1 RW map is erased. - when CR50_SQA is set to 1, the board ID flags can be set to a value which would not lock out the currently running image and INFO1 RW map is erased. With these modifications the 'eraseflashinfo' command can be used instead of 'bid force_pvt', and previously erased INFO1 RO map is preserved. BRANCH=none BUG=none TEST=tried running 'eraseflashinfo' in three kinds of images (CR50_DEV=1, CR50_SQA=1, and CR50_SQA=2) and with various board ID flags set in the image header, and observed the desired behavior. Change-Id: Icf26dc3a4a4bb6fac2fcec630749c81aa46e16ae Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1549981 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: convert functions into staticNamyoon Woo2019-04-051-2/+2
| | | | | | | | | | | BUG=b:112778363 BRANCH=cr50 TEST=ran test_that suite:faft_cr50_prepvt on coral. Change-Id: I1b3c573ee5fcb40290541f231c78bf31650c13c4 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1410482 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: make ccd_mode_l pseudo open drainMary Ruthven2019-04-041-3/+3
| | | | | | | | | | | | | | | | | | gpio.c has support for making pins open drain. This implementation will prevent the signals from being driven high. Use the gpio.c support instead of the hack we were using before. BUG=none BRANCH=cr50 TEST=the EC can assert CCD_MODE_L when cr50 has it deasserted. Verify this on a ARM and x86 device in the lab. Change-Id: I7f2a465782f2c60a850c25153fb65eb96fff0712 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1282019 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: move to use flash event logVadim Bendebury2019-03-281-3/+3
| | | | | | | | | | | | | | | | | | | | | With upcoming Cr50 changes which might trigger occasional reboots, it is better to keep the Cr50 log in the newly introduced flash log space as opposed to the circular log in SRAM. There is no need to log TPM resent events, as this is not something worth tracking in a flash log. Enabling flash log facility adds 624 bytes to the prod Cr50 image and 1420 bytes to the DBG Cr50 image. BRANCH=cr50, cr50-mp BUG=b:63760920 TEST=with modified code observed saving of FE_TPM_I2C_ERROR event. Change-Id: Id6779de887dac20ce6c1091c8b1571ae900623fd Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1525145 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: add flash elog support functionVadim Bendebury2019-03-282-1/+29
| | | | | | | | | | | | | | | | | Cr50 flash layout does not use space in the top of RO_B section, this is a good location for the flash log, as it can not be easily used for the code or RO data of the main Cr50 application. BRANCH=cr50, cr50-mp BUG=b:63760920 TEST=with the rest of the stack of patches applied was able to add and retrieve flash log messages on Cr50. Change-Id: I8639ad437c5b90eb2d182453bd8bbdda610bdb15 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1525144 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* common: add flash event log facilityVadim Bendebury2019-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds implementation and test for a generic logger saving log entries in the flash. The entries payload are limited to 64 bytes in size, each entry starts with a header, which includes - 8 bit type type to allow to interpret the payload - 6 bit size field (two top bits of the byte are left for user flags, not yet used) - 32 bit timestamp to allow to identify newer log entries (presently this is just a monotonically increasing number) - 8 bit crc field protecting the entire entry The entries are padded to make sure that they are ending on the flash write boundary. The location of the log is defined by the platform using it. There is a provision for allowing the platform to register a callback which is needed to be called to allow write access to the log (as is the case on H1). While the device is running, the log is growing until the allotted flash space is 90% full. If there is an attempt save another entry after that the log is compacted, namely the last 25% worth of flash space is preserved, the log space is erased and the saved contents written back. On restarts the log is compacted if its size exceeds 75% of the allotted flash space. An API is provided to add entries to the log and to retrieve an entry newer than a certain timestamp value. Thus starting with timestamp zero will result in reading the very first log entry. To read the next entry, the read function needs to be called with the timestamp value of the current entry. This allows to browse the entire log, one entry at a time. A CLI command compiled in when CONFIG_CMD_FLASH_LOG is defined, allows to add log and retrieve log entries. BUG=b:63760920 BRANCH=cr50, cr50-mp TEST=the included test case can be invoked by make run-flash_log and it passes. More tests are done when the rest of the patch stack is added. Change-Id: I3dcdf2704a1e08fd3101183e434ac4a4e4cf1b9a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1525143 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: check that the tx fifo is ready before writing itNamyoon Woo2019-03-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | USB TX FIFO should be checked for readiyness before trying to moving data from uart consumer queue to usb producer queue. BUG=b:126909037 BRANCH=cr50 TEST=manually ran the script below. i=0 while true; do dut-control power_state:off && dut-control power_state:rec && \ dut-control lid_open i=$((i+1)) echo $i done Change-Id: I56316165c2ce420029fdc9d594bf1c5274a002d1 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1515816 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-269-88/+88
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-2610-35/+35
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add support for building CR50_SQA imagesMary Ruthven2019-03-203-11/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices in the lab need to be switched from prepvt to pvt flags. This change adds a build flag for CR50_SQA. Images built with CR50_SQA have more capabilities than normal cr50 images, but less than CR50_DEV images. SQA images can access the rollback command, updates including downgrading to images with lower version numbers and mismatched board id will not be rejected, and the 'bid force_pvt' console command can be used to set the bid flags to 0. bid force_pvt does not erase flashinfo. After the board id has been set, we can still change 1 bits to 0, so we don't need to eraseflashinfo to change the board id flags to 0. This makes the command a bit safer, because the board id RLZ can't be changed just the flags. Changing the flags to 0 works for the test team, because it prevents cr50 from updating to prepvt. This change also marks rollback as a safe command. CR50_SQA images aren't automatically open, so if rollback isn't safe, they will have to go through the open process to change to pvt. Rollback is only included in DEV and SQA images, so it's ok if it's marked safe. It's understood these images aren't supposed to be used on regular devices. They're just for special development and test environments. NEW PROCESS FOR SQA: - update to sqa image - run 'bid force_pvt' - flash pvt image - run rollback BRANCH=cr50 BUG=b:126618143 TEST=run sqa process Change-Id: Ia713274830c9e19cdb3ccafa87849c160d667683 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1529834 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* g: add board_id_is_blankMary Ruthven2019-03-202-3/+16
| | | | | | | | | | | | | | | | Add board_id_is_blank for checking that all fields of a board id are 0xffffffff. BUG=none BRANCH=cr50 TEST=none Change-Id: I591a3529a7f5a2aa4fcd4a7e0ec43356d0e97237 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1531321 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: use closed loop reset based on board propertyMary Ruthven2019-03-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the closed loop reset when cr50 needs to reset the device. Cr50 expects the board to reset in three places: board_reboot_ap, board_reboot_ec, or during init after any cr50 reset other than deep sleep. This change modifies these to use the closed loop reset if the board property is set. In board_reboot_ap and board_reboot_ec it calls board_closed_loop_reset instead of doing the normal reset steps if the board property is set. In init_ap_detect call board_closed_loop_reset if cr50 just resumed from any reset other than hibernate. Don't trigger the tpm_rst_isr manually. BUG=b:123544145 BRANCH=cr50 TEST=manual Flash firmware that supports resetting the AP when EC_RST_L is asserted. Reboot cr50 and verify deferred_tpm_rst_isr is only called after tpm_rst_asserted. Open Cr50. Verify the AP is reset Flash old Mistral firmware which seems to take around 12 seconds for the warm reset to happen. Boot the AP. Reboot cr50 while the AP is up. The AP wont reset for a while. While the AP is still up, verify Cr50 keeps EC_RST_L asserted, the AP state is Unknown, and tpm commands fail while the AP is in this state. Eventually the AP resets. Make sure the TPM becomes usable again and the AP state is on. Change-Id: I6f0e8728717f1ed35c96b2669f1796078ebf93f7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1447001 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: decorate _i2cs_write_complete_int() so that LTO does not loose itVadim Bendebury2019-02-101-1/+1
| | | | | | | | | | | | | | | Otherwise LTO optimizes this function away before finding out that it, in fact, needs this it. BRANCH=cr50, cr50-mp BUG=b:65253310 TEST=after the entire stack was applied Cr50 builds successfully with CONFIG_LTO enabled, and passes TCG test suite. Change-Id: I1bd8292b7228efc982118e23455503fefd52c689 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1460087 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: use list of object files instead of the libraries for cryptocVadim Bendebury2019-02-101-6/+8
| | | | | | | | | | | | | | | | In preparation to enabling link time optimizations for Cr50, modify build system to link cryptoc tree's modules directly instead of linking the archive. CQ-DEPEND=CL:1457210 BRANCH=cr50, cr50-mp BUG=b:65253310 TEST=make buildall -j succeeds, TCG tests succeed. Change-Id: I3ffc27e8ef56a45dad8dd96aa90acace710474a1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1457600 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/g: mark symbols used that are used from assembly codePatrick Georgi2019-02-072-2/+2
| | | | | | | | | | | | | | | Otherwise LTO optimizes them away before finding out it, in fact, needs them - then complains. BRANCH=cr50, cr50-mp BUG=b:65253310 TEST=after the entire stack was applied Cr50 builds successfully with CONFIG_LTO enabled, and passes TCG test suite. Change-Id: I244e5bd3da18dddec636bbe1e99c229bc3af44ec Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1411542
* cr50: Add NIST SP 800-90A HMAC DRBG.Louis Collard2019-01-296-176/+386
| | | | | | | | | | | | | | | | | | | This adds a new DRBG, and refactors the existing RFC6979 DRBG to make use of it. The new DRBG will initially be used to incorporate user-specific secrets into U2F key generation. CQ-DEPEND=CL:*729958,CL:*729959 BRANCH=none BUG=b:112603199 TEST=cr50 console rfc6979 test, hmac_drbg test, hmac_drbg_rand test Generate U2F key, patch CL, use U2F key Change-Id: I9af5da65cbd6fbfbd3570f40fb9e11ecef57532d Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1371584 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g/i2cs: Sample SDA multiple times before considering the bus wedgedRaul E Rangel2019-01-281-45/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cr50 tpm i2c protocol works as follows: 1. Master wants to read a register from the tpm. It writes the 1 byte register address to the tpm. 2. Master completes the transaction then waits for AP_INT to fire. 3. i2c write complete isr fires on the tpm. 1. register data is pushed into the tx fifo 2. AP_INT is pulsed to notify the master that the write has been processed, and the data is ready to be read. 3. tpm increments i2cs_read_irq_count 4. Master reads n bytes from the tpm. 5. Times passes 6a. Master decides to update a register on the TPM 1. Master writes n bytes to the tpm. 2. Master completes transaction then waits for AP_INT to fire. 3. i2c write complete isr fires on the tpm 1. tpm processes the write command 2. AP_INT is pulsed to notify the master that the read is ready. 4. Master receives AP_INT and continues issuing commands. 6b. Master decides to read a register from the TPM 1. goto 1 poll_read_state will currently poll SDA every 500 ms. If it sees that there have been no write completions since the last polling period and SDA is currently low, it assumes the bus is wedged and it resets the i2cs controller. This logic has the potential to terminate in flight transactions. For example: The poller runs at step 4 and notices that a write interrupt has occurred and it updates last_i2cs_read_irq_count. The master waits 499.99 ms and then initiates a new transaction (6a or 6b). This causes the master to start a new i2c write transaction. The poller then runs again at 500ms and notices that the write complete interrupt counter has not incremented and SDA is low because a 0 is currently being written by the master. The poller then resets the i2cs controller. This causes the master to receive a NAK. This cl changes the logic so that the poller requires SDA to be low for 3 consecutive periods between write completes before it resets the controller. See the comments in the code for the specifics. BUG=b:113880780 BRANCH=none TEST=Ran a reboot stress test for over 16 hours and did not see any transaction failures. Also manually grounded SDA to see if read_recovery_count incremented: [585.024822 I2CS bus is stuck] [585.475883 I2CS bus is stuck] [585.926944 I2CS bus is stuck] [586.378009 I2CS bus is stuck] [586.829067 I2CS bus is stuck] > i2cstpm rd fifo adjust cnt = 0 wr mismatch cnt = 0 read recovered cnt = 5 Change-Id: I7b6f446ee75b43e9d66a6a5e51dd077c60108f90 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1387346 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* link_defs.h: Renames __ro_end to __data_lma_start.Yilun Lin2019-01-281-1/+1
| | | | | | | | | | | | | | | | | | The name of __ro_end is confusing. The variable is actually used as a label tagging that it is the starting address of .data LMA. Renames to __data_lma_start to be more decriptive. BRANCH=None TEST=make buildall -j BUG=b:122084384 Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1433160 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Extend CR50 Bitbang Receive buffer.Namyoon Woo2019-01-161-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bitbang receive buffer in CR50 gets bigger so that 257 byte chunk transfer can be done without any data loss. BUG=b:112163028 BRANCH=cr50 TEST=manually tested by writing/reading EC binary in bitbang mode. (a) Flash EC binary $ flash_ec --board=${BOARD} --bitbang_rate 57600 \ --image ${EC_BIN_PATH} (b) Read EC binary $ dut-control --port=9999 ec_ec3po_interp_connect:off $ dut-control --port=9999 ccd_ec_boot_mode_bitbang:on $ dut-control --port=9999 cold_reset:on $ dut-control --port=9999 cold_reset:off $ dut-control --port=9999 ec_uart_parity:even $ dut-control --port=9999 ec_uart_baudrate:57600 $ dut-control --port=9999 ec_uart_bitbang_en:on $ time stm32mon -d ${RAW_EC_UART_PTY} -c -r ${EC_BIN_READ_PATH} \ -b 57600 ... Reading 262144 bytes at 0x08000000 262144 bytes read. real 1m0.739s user 0m0.024s sys 0m0.125s $ diff ${EC_BIN_PATH} ${EC_BIN_READ_PATH} $ Change-Id: I0ee76085eedf44b1cba2c686003335b109c0272c Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1394284 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Deferred RDD check in deasserting EC_RST_L.Namyoon Woo2019-01-091-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RDD connection can be detected after the debug cables comparator values are stable, which takes RDD_MAX_WAIT_TIME_COUNTER. This CL changes to check RDD connection in a deferred way only when it is a power-on reset and the power button is held. This CL increases Flash memory usage by 40 bytes. BRANCH=cr50 BUG=b:37351386 TEST=manually on bob, coral and scarlet. 1. (EC) cutoff 2. unplug all cables. 3. hold the power button. 4. plug USB-C cable of Servo V4 (or SuzyQ cable) in. 5. check EC console. Should be off. To verify, run the cr50 console command, 'ecrst' and check if 'EC_RST_L' is asserted. 6. release the power button. EC should run. Change-Id: I4c7b0653bf49fbe57c8ad8395c72e006fa3a0ff0 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1398921 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: VENDOR_CC_IMMEDIATE_RESET may have a delay argument.Namyoon Woo2018-12-131-6/+39
| | | | | | | | | | | | | | | | | VENDOR_CC_IMMEDIATE_RESET has either uint16_t argument or none. The argument is a time delay in millisecond unit. If it has no argument, then Cr50 resets H1 immediately without any delay. BUG=b:120485010 BRANCH=cr50 TEST=none Change-Id: I33aaacbb0a0532aa84f39a8cd51d0d54fa2d281a Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361998 Commit-Ready: Joel Kitching <kitching@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Fix return value for VENDOR_CC_SN_SET_HASH.Louis Collard2018-12-061-2/+2
| | | | | | | | | | | | | | | | | I made a careless mistake when incorporating comments during review of CL:1237696 and broke the return value for this vendor command. The command still sets SN bits correctly, but in most cases (success and failure), returns VENDOR_RC_NOT_ALLOWED. BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I6d3bc1c9df7737f7469c6f432da2e65c79f324a6 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1364490 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: provide DCRYPTO_ladder_is_enabled() for test and fuzz buildsVadim Bendebury2018-12-061-10/+14
| | | | | | | | | | | | | | | This function is called from common/nvmem.c, it should be available when compiling for tests, the stub could be filled up later when new tests are added. BRANCH=cr50, cr50-mp BUG=b:119221935 TEST=make buildall -j still succeeds. Change-Id: I082292818c7f2b10336c9a7c49e0a9195e25a12b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363816 Reviewed-by: Allen Webb <allenwebb@google.com>
* cr50: revoke key ladder on disabling TPMNamyoon Woo2018-12-052-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabling TPM will do revoke H1 key laddder. Querying TPM_MODE or enabling TPM_MODE will fail if H1 Key Ladder is already revoked. BUG=b:118504817 BRANCH=cr50 TEST=Manually tested with TPM disabling and Resume or Warm Reboot. (1) Resume $ trunks_send --raw 80 01 00 00 00 0c 00 00 01 45 00 01 80010000000A00000000 $ gsctool -a -m disable TPM Mode: disabled (2) $ echo mem > /sys/power/state (press key on chromebook either after three seconds or in a second.) (2) Warm Reboot $ gsctool -a -m disable (press refresh + power button or run kernel command 'reboot') Check Chrome os boot ok. No TPM command failures were observed (in CR50 console). (3) Windows Warm Reboot or Resume are checked. Change-Id: I32fffc432a9a6068ea324a97225974c581cb9359 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1312197 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add extern "C" to headers used by future fuzzing target.Allen Webb2018-11-152-0/+15
| | | | | | | | | | | BRANCH=None BUG=None TEST=make -j buildall Change-Id: Icf2cfb6a2657064c10721c0e527d24fbb3be6ab3 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1330102 Reviewed-by: Mike Frysinger <vapier@chromium.org>
* cr50: enable ITE CCD programmingVadim Bendebury2018-11-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support of ITE EC programming by Cr50. ITE EC sync sequence generator implementation is being added to the image, I2C RX and TX queue sizes are increased to be able to accommodate messages sent during programming session. Board level callback function is provided to request ITE SYNC sequence generation on the next boot, and to reset the H1 with a 10 ms delay, necessary for CCD host USB communications to quiesce. Board startup code is modified to when requested invoke function generating ITE SYNC sequence early in the boot before jitter configuration is locked. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263898 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
View Lorry Controller Status