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* board/reef: enable CONFIG_CHIPSET_RESET_HOOKAaron Durbin2016-07-211-0/+1
| | | | | | | | | | | | | | | | In order for the vstore to be unlocked one needs to enable the CHIPSET_RESET_HOOK. Do that for reef. BUG=chrome-os-partner:55471 BRANCH=None TEST=Able to boot and reboot without getting vboot hash saving errors. Also am able to see the assertion/deassertion messages on the console. Change-Id: I94a41a08ad8649423988372607835da01ec12b8b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362001 Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpm: anx74xx: Add alert polarity member to tcpc_config_tDavid Hendricks2016-07-213-5/+6
| | | | | | | | | | | | | | | This allows us to specify the polarity of the alert signal for each TCPC chip onboard, even if we have multiple instances of the same chip. BUG=none BRANCH=none TEST=built and booted on reef Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360948 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_micro: support servo micro v2, console gpioNick Sanders2016-07-203-67/+34
| | | | | | | | | | | | | | | * Remove GPIO USB endpoint to make room for update endpoint. * Change GPIO mapping slightly to support servo micro v2. BUG=chromium:571477 BRANCH=None TEST=run servod, see new controls. Change-Id: Id3b85b4c77b8f21afd9636b2ee459ace6f42f68e Reviewed-on: https://chromium-review.googlesource.com/361383 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* kevin / gru: Enable low-power idleShawn Nematbakhsh2016-07-201-1/+1
| | | | | | | | | | | | | BUG=chrome-os-partner:54343 BRANCH=None TEST=Verify system continues to function as normal in S0 and S5. Change-Id: I1b46c47a074a308f2e316e93813559d170bfe5ee Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355161 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add an option to disable uart0 rx no matter whatMary Ruthven2016-07-201-0/+1
| | | | | | | | | | | | | | | | Having uart0 RX enabled can cause serious issues. This change adds a config option to disable uart0 rx no matter what. BUG=none BRANCH=none TEST=On B2 check that the ultradebug console is now read only Change-Id: Icaec6954ffd3cbf0fda3f53581f6e4020d555267 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361976 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin: Add CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEADShawn Nematbakhsh2016-07-201-0/+4
| | | | | | | | | | | | | | | | | The battery on kevin apparently requests 0A / 0V when extremely low, so ignore this request and apply the pre-charge current. BUG=chrome-os-partner:55416 BRANCH=None TEST=Verify Kevin powers on with dead battery and battery charges as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef Reviewed-on: https://chromium-review.googlesource.com/361994 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hadoken: Add Bluetooth defines to board.hMyles Watson2016-07-201-0/+4
| | | | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=make BOARD=hadoken CONFIG_BLUETOOTH_LE CONFIG_BLUETOOTH_LE_STACK CONFIG_BLUETOOTH_LE_RADIO_TEST Change-Id: I0a4bbc20e512c2a2ca02f3690e92e9cec92d3a0e Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361535 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Levi Oliver <levio@google.com>
* cr50: add INA 3V3 load switch GPIOVincent Palatin2016-07-201-0/+4
| | | | | | | | | | | | | | | Add a GPIO to control the INA 3.3V power rail load switch on Reef. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I2be33ebff376b50f9cc2962db5fc3fa11f4bb107 Reviewed-on: https://chromium-review.googlesource.com/361692 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org>
* reef: reject charge port on init till battery is initializedDivya Sasidharan2016-07-194-27/+70
| | | | | | | | | | | | | | | | | | | | | Ported from patch below: Change-Id: If8fd84f82f5a7fb7ca3736031a161d90e5e77c12 Reviewed-on: https://chromium-review.googlesource.com/349853 Also added CUSTOM_BATTERY_PRESENT check for battery not initialized BUG=chrome-os-partner:55255 BRANCH=master TEST="batterycutoff" command successful and boots fine after plugging in AC to exit ship mode;make buildall -j Change-Id: I928e17b7ae186d9be695f45540fd79b844f8e3ac Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/360217 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: disable usb wakeup when debug accessory is disconnectedMary Ruthven2016-07-191-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | USB is only used for CCD. USB should not be enabled as a wakeup source unless a debug accessory is detected, because that is the only USB traffic we care about. The rest may be from other sources like the HID interface or something else using those signals. This change disables the utmi wake source when the debug accessory is attached and enables it when it is connected. BUG=chrome-os-partner:54796 BRANCH=none TEST=manual The SPI_CS_L pin still gets triggered and will wake up cr50 before usb so disable wake up pins as a wakeup source. Verify Cr50 goes to sleep and plugging in a SuzyQ will wake it up and after removing it Cr50 will go back to sleep. Change-Id: Ib97244016b0af244c340259915def9f4d8f97569 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360693 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* hadoken: Remove I2C and add ADCMyles Watson2016-07-193-52/+18
| | | | | | | | | | | | | | | As of EVT2, remove I2C (TWI). Use the pins for analog sensing of the battery level. BUG=None BRANCH=None TEST=Sense the battery level and use the serial port. Change-Id: I3d5d2401e61e6e7d203e933d2566f6f3cd65c054 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361546 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Levi Oliver <levio@google.com>
* big: Enable link-time optimizations.Aseda Aboagye2016-07-191-0/+1
| | | | | | | | | | | | | | | big is running out of space in ToT. Grab some space by enabling LTO. BUG=None BRANCH=None TEST=make -j buildall tests Change-Id: I54bc4b368e863f65c76c2b77fa06e3123cff766f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/361549 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* servo v4: Add new GPIO mappings for rev2Nick Sanders2016-07-192-13/+27
| | | | | | | | | | | | | | | | | | Servo V4 rev2 has slightly different gpio mappings. Note that this change will cause rev1 to not work. Allow uservo routing before servod init. Further work is needed on uservo port preinit as servod will reset the port on startup, disconnecting uservo. BRANCH=none BUG=chromium:571476 TEST=Boot, use dut-control, see uservo. Change-Id: I6436eed030cfdd329c5bd0cbca49038b268c2b71 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359620 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* BD99955: System VR in battery LEARN, Cut-off & No-battery conditionVijay Hiremath2016-07-182-18/+2
| | | | | | | | | | | | | | | | | | | Regulate the system voltage by setting the charging voltage to battery maximum in case of battery LEARN, Cut-off & No-battery conditions. BUG=chrome-os-partner:55292, chrome-os-partner:55255 BRANCH=none TEST=Manually tested on Amenia using console command charger. Charging voltage is set to battery max in LEARN, Cut-off & No-battery conditions. Change-Id: I74bbab8174fd63b5f8439b8b35098db4a506d72d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/360681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* rk3399: kevin: Inhibit booting w/ insufficient pwrAseda Aboagye2016-07-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Before, as soon as the EC started booting, it would unconditionally boot the AP (unless explicitly told not to. ie: "reboot ap-off"). However, we weren't waiting for our power to settle which was causing some brownouts. This would happen when trying to boot without the battery. This commit causes the EC to inhibit powering on the AP until we have sufficient power. BUG=chrome-os-partner:55289 BRANCH=None TEST=Flash EVT2; verify can boot normally. TEST=Remove battery and insert charger. Verify that DUT can boot up. TEST=Insert drained battery. Verify power on is inhbited. Plug in charger and verify that DUT can power on. Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/361005 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Elm: Allow rejected 'Dont charge' request on initRyan Zhang2016-07-171-0/+14
| | | | | | | | | | | | | | | | | | If our battery isn't able to provide enough power to the EC on boot, we should not cut off our input power, regardless of dual role determination or other charging policy. BUG=chrome-os-partner:54944 BRANCH=master TEST=Manual on Elm. Drain battery completely, attach USB-C charger, verify that "Battery critical, don't disable charging" is seen on the console and the EC doesn't brown out. Change-Id: I7782d333da89b872e33ea31304f878ca490329cf Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/360781 Reviewed-by: YH Huang <yh.huang@mediatek.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* cts: Added GPIO test suiteChris Chen2016-07-152-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Contains code for all the gpio tests so far. Code in cts_task for th and dut is for testing purposes and test result reporting will be updated in the next patch. BRANCH=None BUG=None TEST=Manual - Connect handshake and gpio test lines between th and dut - Build tests - run 'cat /dev/ttyACM0' in one terminal - run 'cat /def/ttyACM1' in another - Flash boards - All test results should print either passed or unknown Change-Id: I7142fb87a6ce0a20c571cde608fbbe60e35898ea Reviewed-on: https://chromium-review.googlesource.com/359935 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kevin: change coordinates axis for sensorsInno Park2016-07-151-2/+23
| | | | | | | | | | | | | | BUG=chrome-os-partner:52844 BRANCH=none TEST=check x-y-z value from base/lid accelerometer with ec console command 'accelread' Change-Id: I38a83f13e415504600cc6c566cf8586e1309a270 Signed-off-by: Inno Park <ih.yoo.park@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/354321 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* g: tristate spi master pinsMary Ruthven2016-07-142-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having DIO A4, A8, and A14 connected to the spi master output pads prevents reef from booting. We need to tristate those pins when spi ccd is not in use. This change disconnects those pins from the spi peripheral when spi is disabled and reconnects them when spi is enabled. BUG=chrome-os-partner:53582 BRANCH=none TEST=manual use 'pinmux' to verify DIOA4, DIOA8, and DIOA14 are set have GPIO 7, 8, and 9 as their output sources when not using the usb spi interface. Check the usb spi interface still works. Enable usb spi then disable ccd and check that the pins are connected back to the non-peripheral gpios. Verify the AP on kevin and reef can be flashed using servo. Verify the AP boots successfully on both. Change-Id: I85d70422a30da445076432d2bfc81960aeba8578 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357883 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charger: BD99955: Get the VBUS level from the chargerVijay Hiremath2016-07-132-3/+0
| | | | | | | | | | | | | | | | | Added code to get the VBUS level by reading the charger registers. BUG=chrome-os-partner:55117 BRANCH=none TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh) registers are updated with the correct VBUS value on the respective ports. Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/359416 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: enable virtual batteryMary Ruthven2016-07-131-0/+2
| | | | | | | | | | | | | | Enable using the virtual battery on Kevin. BUG=chrome-os-partner:53322 BRANCH=none TEST=Verify 'power_supply_info' still works. Change-Id: I5a732d4cdd0f764d8bae086ef23b2690522a038e Reviewed-on: https://chromium-review.googlesource.com/360186 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* elm: Add sensor power controlKoro Chen2016-07-131-0/+3
| | | | | | | | | | | | | PD11 is added in PVT to control power of sensors BRANCH=none BUG=chrome-os-partner:54129 TEST=verify sensor power can be controlled on a reworked elm Change-Id: Ib7457c9c21a26ec853b00f3709922aab70c9d514 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/359153 Reviewed-by: Rong Chang <rongchang@chromium.org>
* kevin: change pwm frequency to reduce EE noiseWonjoon Lee2016-07-131-1/+1
| | | | | | | | | | | | | | | | Currently we have EEnoise(Decap Switching Noise) from LCD PWM Kevin use LCD Backlight Driver IC and PWM Frequency from EC Current 10kHz frequency can make switching Noise easily. BUG=chrome-os-partner:55169 BRANCH=None TEST=measuring noise reduced, verifying there was no influence to LCD/digitizer/tsp Change-Id: I1e65e56a19177dadba0110de5678669288a8555a Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/360003 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: add more waking up signal from hibernatingWonjoon Lee2016-07-131-1/+1
| | | | | | | | | | | | BUG=None BRANCH=None TEST=type "hibernate" in console, and wake up using power button, lid open, insert power supplier Change-Id: Ide28974145602db550079c21e76169fbb358c847 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/360041 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: disable device monitoring when not in ccdMary Ruthven2016-07-123-33/+37
| | | | | | | | | | | | | | | When cr50 is not trying to do ccd, we dont need to monitor the devices. Disable device state detection interrupts and the AP and EC UARTs. BUG=none BRANCH=none TEST=gru and kevin monitor devices correctly when ccd is enabled, and dont monitor anything when it is disabled. Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356770 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* big: Remove battfake command.Aseda Aboagye2016-07-121-0/+1
| | | | | | | | | | | | | | | | big is running out of space due to some incoming changes. Remove the battfake command. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ib8ee7d52a2a9dd3a473508648583b303079e67b8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/359616 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cts: Added sync() functionChris Chen2016-07-122-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | sync() involves 2 gpios on each board, each labeled GPIO_HANDSHAKE_OUTPUT and GPIO_HANDSHAKE_INPUT on their respective boards. They both start low, then the th wiggles his line up and down, waiting for the dut to mimic it. BRANCH=None BUG=None TEST=manual - Connect handshake lines to appropriate pins on each board (pins found in board's gpio.inc) - Build tests - Flash boards - run 'cat /dev/ttyACM0' in one terminal - run 'cat /dev/ttyACM1' in another - They should each have printed 'successful sync' Change-Id: I61233bca9605ba89c3628c2a65ca9013c56365ea Reviewed-on: https://chromium-review.googlesource.com/359355 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: do a soft reset instead of hard when responding to sys_rst_lMary Ruthven2016-07-111-30/+1
| | | | | | | | | | | | | | | | | | | | | Soft reset will not power down Cr50, so it wont assert EC_RST_L when it reboots. This is a short term solution that fixes the cold vs warm reset issue, but it does not fix the problem with all of all of the other Cr50 functions disappearing during warm reset. We will need to just reset the TPM functionality on Cr50 to fix those issues. BUG=chrome-os-partner:52366 BRANCH=none TEST=Check asserting SYS_RST_L resets Cr50 and the AP and doesn't reset the EC. Disable the Cr50 reset when SYS_RST_L is asserted, and verify that the AP doesn't boot after the first reboot. Enable soft reset when SYS_RST_L is asserted and verify the AP can successfully reboot many times. Change-Id: I7c0d0712ee6df59cfadd3975caf3503d44f3eff2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359342 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Dont switch from PHY 1 to 0 when disabling CCDMary Ruthven2016-07-111-8/+2
| | | | | | | | | | | | | | | | | The AP no longer uses PHY0 to to interact with Cr50. Cr50 only uses PHY1 so dont switch the PHY when disabling CCD just release the usb. BUG=none BRANCH=none TEST=After running 'ccd disable' the command 'usb' still returns PHY B, but 'lsusb | grep 5014' on the host doesn't show any devices. When CCD is enabled 'lsusb | grep 5014' shows a device on the host. Change-Id: Icec0acc7a0d00f7eb56c6feef3ff4cf5a3f99735 Reviewed-on: https://chromium-review.googlesource.com/359931 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add cts.tasklistDaisuke Nojiri2016-07-112-4/+2
| | | | | | | | | | | | | | | | | | | | | | cts.tasklist contains tasks run only for CTS. These tasks are added to the tasks registered in ec.tasklist with higher priority. This design allows board directories to be free from CTS stuff. cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist). If a suite does not define its own cts.tasklist, the common list is used (i.e. cts/cts.tasklist). BUG=chromium:624520 BRANCH=none TEST=Ran the followings: make buildall make CTS_MODULE=gpio BOARD=nucleo-f072rb make CTS_MODULE=gpio BOARD=stm32l476g-eval Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359445 Reviewed-by: Chris Chen <twothreecc@google.com>
* cr50: disable UART0 RXMary Ruthven2016-07-111-2/+8
| | | | | | | | | | | | | | | | | | | | | | | If the UART0 RX pad is not pulled up, cr50 will get held up on all of the interrupts triggered by the low signal. This causes cr50 to reboot continuously. UART0 RX was moved to DIOA13, which does not have an internal pull up. This means we have to rely on an external pull up. Because not having an external pull up on DIOA13 could prevent the system from booting and UART0 RX is only used as an alternate debugging mechanism from suzyq, we decided it is best for UART0 RX to be disabled by default. BUG=none BRANCH=none TEST=Connect UART1_RX to DIOA1 and test that it still accepts input. Disconnect it from any pads. Verify the system boots normally and console input from DIOA1 no longer works but the suzyq shell still does. Change-Id: I68988c59cfce610cc6c360bf8dd9685e98ab12ff Reviewed-on: https://chromium-review.googlesource.com/357881 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Elm: Update max input current for safetyRyan Zhang2016-07-101-0/+2
| | | | | | | | | | | | | | | | tested Constant Current from 2248mA (100%:2.25A) become 2136mA (95%:2137.5) BUG=chrome-os-partner:54890 BRANCH=master TEST=`make -j BOARD=elm` Change-Id: I1c64eb98e044262f9dd54c21cfeb4339e411d4b3 Reviewed-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/356354 Commit-Ready: Ryan Zhang <Ryan.Zhang@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cts: First patch flashes blank testsChris Chen2016-07-092-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The first time you use this with a particular th, connect only th and run ./cts.py --th Then connect both boards and you can run ./cts.py to build/flash both boards. BRANCH=None BUG=None TEST=manual - Enter chroot - Navigate to ec/cts - Connect only th - 'sudo ./cts.py --th' - './cts.py -b' - Exit chroot - Connect both boards - './cts.py -f' Each board should flash successfully Change-Id: Ib14fccabcd9fdad04f9b92817da597bc0dcb3d89 Reviewed-on: https://chromium-review.googlesource.com/358100 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Remove Makefile symlinks under board directoryDaisuke Nojiri2016-07-0939-39/+0
| | | | | | | | | | | | | | | | | | | | | | | | This feature is inconsistent. Not all boards have such a symlink (for a obvious reason). This feature is fragile. It's most likely not tested and going to be broken if not already. Developers won't like it if they have to test two different ways to build boards before submitting patches. This feature is not necessary. If you build EC in the standard way (e.g. make BOARD=samus), these symlinks are not needed. This feature is wasteful. Extra disk spaces are used and extra lines are added to Makefile (increasing code complexity slightly). BUG=chromium:626776 BRANCH=none TEST=make buildall Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359321 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* elm: Increase UART TX buffer size to 8kbNicolas Boichat2016-07-091-0/+4
| | | | | | | | | | | | | | | | | We have more than enough memory for that, and it makes it possible to poll the logs from AP much more unfrequently. BRANCH=oak BUG=chromium:527904 TEST=make buildall -j TEST=Boot elm, cat /sys/kernel/debug/cros_ec/console_log does not miss any data. Change-Id: I8cce88e39d00a94397b6fc852a371b4595870b24 Reviewed-on: https://chromium-review.googlesource.com/358181 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* elm: Disable hostcommand debuggingNicolas Boichat2016-07-091-0/+3
| | | | | | | | | | | | | | | | | elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD is called every 100ms. Even when hcdebug is set to off, we still get command errors. BRANCH=oak BUG=chrome-os-partner:55001 TEST=make buildall -j TEST=Flash elm EC, see that output is fairly quiet. Change-Id: I0a5ab2950911648e2e34f4ab1b6886e3e4bff774 Reviewed-on: https://chromium-review.googlesource.com/358438 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cr50: Disable reset triggered by sys_reset until after bootMary Ruthven2016-07-081-1/+29
| | | | | | | | | | | | | | | | | | | | | | | The EC asserts system reset on init, and Cr50 asserts ec_rst when it is rebooted. Having the EC and Cr50 keep resetting each other prevents the system from booting. We only care that Cr50 is restarted when the system is restarted, so if it gets a system reset call when it is still initializing everything it is okay to ignore it. This change expects the EC to do a system reset on init, so it ignores the first system reset. It will automatically enable the hard resets two seconds after the board is initialized if it doesn't detect the initial system reset. BUG=none BRANCH=none TEST=reef and kevin can boot normally. Verify asserting sys_rst_l after boot resets Cr50 and the rest of the system. Change-Id: I198208950c526efd3ee0171812de3052785555f2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358943 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chell: Remove command_battfake commandGwendal Grignou2016-07-071-0/+1
| | | | | | | | | | | | | To save space, remove command_battfake console command. BRANCH=chell TEST=compile BUG=none Change-Id: Ife8704df974d0c24f3c8477ae4590a62b529d819 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358887 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reef: Add a print to indicate board version.David Hendricks2016-07-071-0/+1
| | | | | | | | | | | | | | This just adds a print statement to display board version at the EC console the first time board_get_version() is called. BUG=none BRANCH=none TEST=print shows up as expected with follow-up patches applied. Change-Id: Ib7eae79a90bdaa58165aa5b102bc446f21a98963 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358910 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: Rejigger PROCHOT pinsDavid Hendricks2016-07-071-2/+6
| | | | | | | | | | | | | | Proto had two pins for PROCHOT# - One to monitor and one to override. Newer boards have only one pin that serves both purposes. BUG=chrome-os-partner:54953 BRANCH=none TEST=built and booted on reef Change-Id: Ida4bc2766caf15562c26e7a4b792a07604361da2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358940 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: Update board ID values and add positive error marginDavid Hendricks2016-07-071-8/+9
| | | | | | | | | | | | | | | | | | | This makes corrections to the board ID values and also adds a small multiplier to allow for higher-than-ideal voltages to match. Currently we see values that are below the ideal value by about 2.5%, so it seems like a good idea to also allow slightly above ideal voltage to account for variations in Vref or PP3300_EC that could cause the calculated value to become higher than expected. BUG=none BRANCH=none TEST=none Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia091fbbad7ffce2da9a04c48c7676ad9b4a08dea Reviewed-on: https://chromium-review.googlesource.com/358614 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* reef: Fix board ID ADC scaling factorsDavid Hendricks2016-07-071-1/+3
| | | | | | | | | | | | | | | | | | | The ADC multiplier and divider factors were lazily set to 1 when the board support was first added, so the value was not scaled properly. The conversion formula is: Vi = CHNnDAT * (Vfs / 1024) where Vfs = Vref = 2.816V for Reef. BUG=none BRANCH=none TEST=added debug print and reading now approximately matches what the voltmeter reads. Change-Id: Ic60a8bc1d84c4f9a7b5664e9daddfa331b6a890c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358613 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* amenia: enable 1 slot of secure temporary storageKevin K Wong2016-07-071-0/+7
| | | | | | | | | | | BUG=none BRANCH=none Test=amenia is able to resume from S3 Change-Id: Idd89c791b65b67051a433d02ffb0fb1df1b834ef Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/358630 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: correct GPIO name for PMIC_EN signal pinKevin K Wong2016-07-063-7/+7
| | | | | | | | | | | | | | | | | | | Rename from V5A_EN to PMIC_EN. The name V5A_EN came from Amenia where it controls both 5V_A-Rail and PMIC_EN. Reef has a separate 5V_A-Rail control (EN_PP5000) and an another GPIO pin for PMIC_EN. BUG=chrome-os-partner:53666 BRANCH=none TEST=buildall pass Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354767 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* elm: Set PD_MAX_POWER_MW to 45WKoro Chen2016-07-051-1/+1
| | | | | | | | | | | | | Since we are targeting a 45W solution, set max power to 45W. BRANCH=none BUG=chrome-os-partner:54519 TEST=Plug in Zinger and make sure 20V/2.25A is used instead of 20V/3A Change-Id: Ie57a1df39f0cc642fe3644535aa1b5aa92f1ff35 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/358320 Reviewed-by: Rong Chang <rongchang@chromium.org>
* cr50: generate HARD RESET when sys_reset is assertedVadim Bendebury2016-07-012-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch replaces a long standing stub. When the EC asserts this signal, the CR50 must reset. But this signal could be driven by CR50 itself as well, and in that case the signal's assertion should not be causing the CR50 reset. Ideally it should be possible to tell if the pin is configured as output and ignore its assertion in that case. But there is no API for checking the pin configuration settings at this time. An API function is added to check if the AP Flash is being programmed, the GPIO configuration access API is left for future enhancements. BRANCH=none BUG=chrome-os-partner:52366, chrome-os-partner:54982 TEST=issue 'reboot' command from the bash command line. - verify on the cr50 console that it reboots along with the rest of the device - observe that reading of the NVRam spaces is still fully functional, and Kevin can boot all the way up to the login screen. - try flashing AP firmware through CR50, verify that it succeed. Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357967 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Wait to allow ADC 'version' cap to sufficiently chargeShawn Nematbakhsh2016-06-301-1/+1
| | | | | | | | | | | | | | | | | Allow at least 10ms for the 'version' cap to charge in order to have a voltage on the ADC pin that reflects our voltage divider circuit. BUG=chrome-os-partner:54768 BRANCH=None TEST=Manual on kevin. Run 'ver', verify that rev3 board is recognized as version 3. Change-Id: I1f3326f4c99a165d77363834d5671aa357a89007 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357970 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* kevin: re-define for changed GPIOWonjoon Lee2016-06-303-9/+8
| | | | | | | | | | | | | | | - swap M10/J6 to avoid SHI interrupt priority contention - USB-C power enable signal to active high BUG=none BRANCH=none TEST=get proper working on kevin-rev3 Change-Id: I52b71636779cad8975cef5921e9c9a1b7da8645e Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/351151 Commit-Ready: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* keyboard_scan: Support boot key recognition with stuck KSI2Shawn Nematbakhsh2016-06-301-0/+1
| | | | | | | | | | | | | | | | | For certain board configurations, KSI2 will be stuck asserted for all scan columns if the power button is held. We must be aware of this case in order to correctly handle recovery mode key combinations. BUG=chrome-os-partner:54602 BRANCH=None TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I03d76e1121107484f79520745858388f6cae096c Reviewed-on: https://chromium-review.googlesource.com/357590 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* reef: Add I2C_PORT_ACCELDavid Hendricks2016-06-291-0/+7
| | | | | | | | | | | | | | | | | | | The motion sensor drivers used to rely on #defines indicating I2C or SPI port to tell which to use. However, these days the drivers get that info passed in via the motion_sensor_t struct. Now this #define simply decides whether to compile in SPI or I2C wrapper code. We should eventually make it less confusing, but that's beyond the scope for now. BUG=none BRANCH=none TEST=reef motion sensor init works now Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356822 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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