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* Fix minor typo.Marius Schilder2016-08-081-1/+1
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025 TEST=no typo observed. Change-Id: I698fd6de3656bcf6a048c1cadba21c8278603697 Reviewed-on: https://chromium-review.googlesource.com/366891 Commit-Ready: Dan Shi <dshi@google.com> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* btle: Add the HCI layerMyles Watson2016-08-081-0/+1
| | | | | | | | | | | | | | | | | | | Add a case statement to handle HCI commands. Add a test commands. Try to match the hcitool syntax, so the same commands can be executed on a Linux host. Added lcmd (long cmd) to pass more parameters in fewer arguments BUG=None BRANCH=None TEST=Use HCI commands to configure an advertiser and listen for it using `hcitool lescan` on the host. Change-Id: Ie28038847c9549eb1c27a605aa0fbad5efd3b2c7 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362145 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* btle: Add common link layer codeMyles Watson2016-08-082-0/+2
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=make BOARD=hadoken Add a task that is responsible for the state of the link layer. Change-Id: Ifc79bf1e4c57f5de448ab05b3a8d3a1aca5a58e2 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362144 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Rename EXTENSION_EC to EXTENSION_ECCBill Richardson2016-08-071-1/+1
| | | | | | | | | | | | | | | | | | | I keep thinking this refers to "Embedded Controller" instead of "Elliptic Curve Cryptography". Make it clearer. There's no functional change, I'm just renaming a constant. BUG=none BRANCH=none TEST=make buildall; run tests on Cr50 dev board make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py Change-Id: Iaf2e2839e88fdbbcb1a712934be56a0dd47e4a70 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366752 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* reef: enable CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2Kevin K Wong2016-08-051-0/+1
| | | | | | | | | | | | | | | | KSI2 get stuck when Refresh+Pwrbtn is used to reset EC, so it was not able to detect the Esc key if it is also pressed to enter recovery mode. BUG=chrome-os-partner:55548 BRANCH=none TEST=Reef EVT is able to enter recovery mode with Esc+Refresh+Pwrbtn Change-Id: I0539e8fad9980cb563de94417079fe763c311887 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/366411 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Read slave config pins always if board properties are not setScott2016-08-051-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the strapping configuration pins were only being read following a POR reset event. In all other cases, the strapping configuration was presumed to be stored in a long life register. An issue with this method is that when Cr50 FW is upgraded (via Suzyq), there is no POR reset event until either the battery becomes fully discharged, or the battery is manually disconnected. Without a POR, following a FW upgrade, the long life register will contain 0 and so neither the SPI interface (on Kevin/Gru) or I2C interface (on Reef) will be properly initialized. Come to think of it, the contents of the scratch register should never be zero unless this is a power on event, or a restart after migration from the version not setting the scratch register. Let's read the scratch register always if its contents are zero. BRANCH=none BUG=chrome-os-partner:50728 TEST=manual Via the Cr50 console, cleared the long life register with temp console command. Then executed a FW upgrade with Suzyq and verified that the strapping pins are read and the correct value is stored in the long life register. Note that 'reboot' commands from either the Cr50 or EC console do not cause a hard reboot. Change-Id: I1b3aa92552b14bde9bda848aa3dc4c8221ce73a9 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366390 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: The battery-present gpio is active lowBill Richardson2016-08-051-3/+3
| | | | | | | | | | | | | | | | The input should be active low, not active high. BUG=chrome-os-partner:49959 BRANCH=none TEST=manual Remove and reattach the battery. "gpioget BATT_PRES_L" shows the GPIO value changing appropriately. Change-Id: I7d513471f6ab5e7e8cd0e601148915697fa9162a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366134 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* kevin: Turn on CONFIG_HOST_COMMAND_STATUSDouglas Anderson2016-08-051-0/+1
| | | | | | | | | | | | | | | The AP expects this to be enabled and it's not so happy when it's not there. Let's turn it on. BRANCH=None BUG=chrome-os-partner:55942 TEST=See bug Change-Id: If7edb0c9533125d9974a43d024c4c4ae6ba5b1cf Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366460 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: add pull-up for TCPC1 INT# when daughter board is not connected.Kevin K Wong2016-08-032-13/+30
| | | | | | | | | | | | | | | | | | when the daughter board is not connected, TCPC1 INT# (USB_C1_PD_INT_ODL) will be floating since the external pull-up is located on the daughter board as well, and this floating signal will cause an interrupt storm and eventually cause a watchdog. BUG=chrome-os-partner:55488 BRANCH=none TEST=verify board no longer has watchdog reset when daughter baord is not connected. Change-Id: If1d73fa7d90f6ac52fd1ab0ac563a6bf5fd10dc0 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/365499 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: Add code to read battery temperatureVijay Hiremath2016-08-031-10/+1
| | | | | | | | | | | | | | | | | | Reef doesn't have the battery temperature sense pin connected to the charger, hence reading the battery temperature from the battery registers. BUG=chrome-os-partner:55834 BRANCH=none TEST=Using 'battery' & 'temps' console command verified, temperature readings are same from both the commands. Change-Id: I897e453296151f31344f3e0434202baa67c7025d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/365970 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Cr50: Sample slave configuration pins at PORScott2016-08-032-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is just one version of Cr50 firmware for all boards that it's used on. However, on some boards the AP communicates to the TPM via a SPI interface (i.e. Kevin) and on others, the AP communicates via an I2C interface (i.e. Reef). In order to dynamically discover which interface to configure, there are strapping resistors added to the board which enables the Cr50 to detect which configuration to implement. This CL is a first pass and is only looking at DIOA1 which is pulled high for SPI and pulled low for I2C configurations. The strapping resistor should be read when the AP is in reset prior to it attempting to drive any of the lines used for strapping. To ensure this condition is met, Cr50 will only check the strapping options following a POR (power on reset). Once the configuration type is discovered, a 'long_life' register is used to hold the result so that the result can always be available. The long_life register contents remain unchanged until a subsequent power down event. BRANCH=none BUG=chrome-os-partner:50728 TEST=manual Tested on Kevin and Reef. Verfifed by reading the stored value that the SPI configuraiton is detected for Kevin and the I2C interface is detected on Reef. In addition, verified on Kevin that the Cr50 FW version is correctly reported to the AP which means that TPM register reads via the slave SPI are functioning. Change-Id: Ibd7624ad8e3b4126f6346dce0bc72f62a3cc6d18 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363014 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: Complain (loudly) if FW is built for wrong boardDavid Hendricks2016-08-031-0/+22
| | | | | | | | | | | | | | This adds a hook that will run every second and complain if the EC firmware was built for the wrong board. BUG=chrome-os-partner:54947 BRANCH=none TEST=tested on proto and EVT units Change-Id: I9799249f74f3cea9a3f6b66b2441af8f16be7e01 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365505 Reviewed-by: Martin Roth <martinroth@chromium.org>
* reef: battery: Revive batteries in soft-disconnect stateRachel Nancollas2016-08-022-5/+61
| | | | | | | | | | | | | | | | | | | ESC+F3+Power+AC removal puts the battery into a soft-disconnect state where is stops supplying current. Revive batteries in this state by supplying a precharge current. BUG=chrome-os-partner:55858 BRANCH=None TEST=Manual on reef. Put battery into soft-disconnect state. Attach charger and verify EC doesn't lose power and battery again supplies current. Change-Id: I9a772bf02a8bd40edc1db51de66de135f7299212 Signed-off-by: Rachel Nancollas <rachelsn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365495 Commit-Ready: Rachel Nancollas <rachelsn@google.com> Tested-by: Rachel Nancollas <rachelsn@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* servo_v4: add usb-c gpio configsNick Sanders2016-08-023-3/+9
| | | | | | | | | | | | | | Default to set DUT_CC1 to RD to enable USB and indicate USB SS orientation. Add ADC entries for SBU detect. BUG=chromium:571476 TEST=check that ADC maps to the right pins, check that usb3 initializes. BRANCH=None Change-Id: Ic9f7c6d1506b9ef83ed3b93a98516ab10b1a471c Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364301 Reviewed-by: Todd Broch <tbroch@chromium.org>
* reef: Check PD reset level in tcpc_get_alert_statusDavid Hendricks2016-08-021-5/+12
| | | | | | | | | | | | | | | Only report alert status if the PD chip is not being held in reset. (idea borrowed from Amenia's implementation) BUG=none BRANCH=none TEST=built and booted on reef Change-Id: Ic637b1ab4e20527c806311a45c149b9ea5f64362 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360020 Reviewed-by: Martin Roth <martinroth@chromium.org>
* reef: Rail and PMIC init changes for newer boardsDavid Hendricks2016-08-021-28/+39
| | | | | | | | | | | | | | | | | | | | | Proto brought up 5V, 3.3V, and PMIC very early in the EC boot process due to dependencies in the power topology. This had some other side- effects, for example, a lot of the power rails would already be up by the time the EC got around to processing the power state machine thus leaving it waiting for signal changes that were supposed to come later but had already occurred instead. This patch updates the nominal codepath for rail and PMIC init on EVT while using IS_PROTO to retain the Proto sequence if desired. BUG=chrome-os-partner:54962 BRANCH=none TEST=built and booted on proto and evt boards with subsequent patches Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: If9ddd41044f132e719b0b7f0ab80ed908ddb1d9b Reviewed-on: https://chromium-review.googlesource.com/358913 Reviewed-by: Martin Roth <martinroth@chromium.org>
* Kevin: support DP hot-plugChris Zhong2016-08-021-7/+16
| | | | | | | | | | | | | | | | | | | | | | The kernel DP driver do not support hpd gpio detect, it use EXTCON_DISP_DP cable state to decide power on/off DP PHY. Hence, do not change GPIO_USB_DP_HPD level, but set or clear the TYPEC_MUX_DP when hpd level changing in attention. BUG=chrome-os-partner:52872 BRANCH=none TEST=keep Type-C Dock inserted 1. plug HDMI cable, check with "ectool usbpdmuxinfo" Port 0: USB DP 2. unplug HDMI cable, check with "ectool usbpdmuxinfo" Port 0: USB Change-Id: I369a92135bf0ca177e81eab6385980d51d863172 Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/364401 Commit-Ready: Guenter Roeck <groeck@chromium.org> Tested-by: Guenter Roeck <groeck@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Remove task profiling to improve SHI interrupt latencyShawn Nematbakhsh2016-08-011-0/+6
| | | | | | | | | | | | | | | BUG=chrome-os-partner:55710 BRANCH=None TEST=Manual on gru with subsequent commit. Verify `flashrom -p ec -r file.bin` passes 100x with no errors or warnings. Change-Id: Id208ebc5d402518012f9adc10f86d8b4de5a35ce Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364235 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Align images sizes to flash block erase sizeShawn Nematbakhsh2016-08-011-2/+2
| | | | | | | | | | | | | | | | | Image sizes must be aligned to block erase size to ensure that the host can erase the entire image and nothing but the image. BUG=chrome-os-partner:55828 BRANCH=None TEST=Manual on kevin, rebuild FW with new EC, rebuild + flash EC once again, verify that SW sync completes and unit boots to OS. Change-Id: If6110f39869d6421038a3fe7afdc7d918323249e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365142 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* reef: Enable thermal sensorsDavid Hendricks2016-08-012-31/+69
| | | | | | | | | | | | BUG=chrome-os-partner:54818 BRANCH=none TEST=field CQ-DEPEND=CL:363008 Change-Id: I236e7e39f4d60e9bd758c387c93ac57e64868bf8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360722 Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: support lid accelerometerBrian Norris2016-08-012-8/+60
| | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:55758 TEST=gru tablet mode Change-Id: I4396f39da74f8ef409d4d335cdef92d2697f7421 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364842 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Use CONFIG_DPTF flag instead of THROTTLE_AP.Ravi Chandra Sadineni2016-07-3017-122/+8
| | | | | | | | | | | | | | | | | Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> BRANCH=none BUG=chromium:631848 TEST=make buildall -j CQ-DEPEND=CL:363008 Change-Id: I3c35f5ab2e3a1537ac6e8c750171d5c2b3a6570f Reviewed-on: https://chromium-review.googlesource.com/363583 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* reef led: add battery led supportli feng2016-07-294-9/+164
| | | | | | | | | | | | | | | BUG=chrome-os-partner:55492 BRANCH=none TEST=on Reef proto, verified led behavior on battery charing, discharging cases Change-Id: Ibc134b741e5c433697b752f73bd3e29ba5910124 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/364025 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cts: Add timer testDaisuke Nojiri2016-07-292-0/+20
| | | | | | | | | | | | | | | | | | | | | The timer test checks the accuracy of the internal timer. After sync, DUT and TH start counting down one second. After one second, DUT raises GPIO level. TH determines whether the test passes or not based on how much more or less time elapsed than one second, assuming its clock is calibrated. This test takes advantage of TH running on a bare chip. If the host were measuring (instead of TH), the timing would be affected by many software and hardware layers (e.g. UART drivers on DUT and host, python interpreter, etc.). BUG=chromium:624520 BRANCH=none TEST=cts.py --module timer && cts.py --module gpio && make buildall Change-Id: I535e7772b4d93f1f5d248506f7ea167429a50174 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361384
* reef: Update pins for EVTDavid Hendricks2016-07-292-15/+58
| | | | | | | | | | | | | | | | | | Updates for EVT: - TCPC0 interrupt polarity is now low, define GPIO_INT and set ANX74xx internal polarity control based on IS_PROTO. - Swapped pin assignments for USB_C1_PD_INT_ODL and EN_USB_C1_5V_OUT. - Rename USB_PD_RST_ODL to USB_C0_PD_RST_L and make it push-pull. - Add USB_C1_PD_RST_ODL BUG=chrome-os-partner:54958,chrome-os-partner:54952,chrome-os-partner:55165 BRANCH=none TEST=needs testing Change-Id: I075934cced532d656f942841c30e3640a6f42568 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358944 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* reef: Check if interrupt is active in tcpc_alert_eventDavid Hendricks2016-07-291-1/+2
| | | | | | | | | | | | | | | | | This ensures that we're only checking the reset signal for the corresponding interrupt. Otherwise we can hit a race condition when both TCPC chips are taken out of reset. (This is also how it's done on Amenia) BUG=none BRANCH=none TEST=needs testing Change-Id: I47513b3b47e947c8b4644f4d837ddc3fb1ee7a30 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361061 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Initialize TCPC chips in their own functionDavid Hendricks2016-07-291-8/+20
| | | | | | | | | | | | | | | | | | This makes board_set_tcpc_power_mode() a noop since that's controlled by anx74xx code and we have another TCPC chip onboard. Instead, we'll reset the TCPC chips in a hook that will run after board and I2C init. This is more like what Amenia code does. BUG=chrome-os-partner:54952 BRANCH=none TEST=needs testing. Change-Id: Id3af4af1014432235b699a9568ee19df63601b2c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361060 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: fix usb spi to disable resets while doing updatesMary Ruthven2016-07-282-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ignore sys_rst_l right now when we use the usb spi endpoint to update the AP or EC. We hold the EC and AP in reset and this causes sys_rst_l to be asserted at the start of updating the AP and when the EC comes out of reset. Using the USB SPI endpoint may require doing a bunch of transactions back to back. Cr50 should not reset itself between each one. This change postpones the reset until we're done using the usb spi endpoint. Once sys_rst_l just resets the TPM we can remove all of this. BUG=chrome-os-partner:52366 BUG=chrome-os-partner:54982 BRANCH=none TEST=manual verify 'util/flash_ec --board=kevin --raiden' updates the EC 'sudo flashrom -p raiden_debug_spi:target=AP -w $IMG' updates the AP The AP and cr50 reset after usb_spi is disabled. Change-Id: I68a76012bc7bf6d3abd073a70f0b90e440d72c49 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364051 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kevin: invert accelerometer matrixBrian Norris2016-07-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have the lid and base sensors correct in relation to each other. e.g., when at 90 degree lid angle, this reports correctly: # ectool motionsense lid_angle Lid angle: 90 But it appears that our axes are opposite from (e.g.) what Chrome expects. With the lid angle at 180 degrees flat on a desk, I see: # ectool motionsense Motion sensing inactive Sensor 0: -571 1018 -16302 Sensor 1: 0 0 0 Sensor 2: 896 -3424 -16208 but the Z-axis should be positive. After this patch, I see: # ectool motionsense Motion sensing inactive Sensor 0: 580 -1000 16289 Sensor 1: 0 0 0 Sensor 2: -832 16368 1008 Which looks more accurate, and actually gets Chrome to rotate properly. All tested on kevin rev3. BRANCH=none BUG=chrome-os-partner:55717 TEST=`ectool motionsense`, `ectool motionsense lid_angle`; also test rotation in Chrome Change-Id: Ie1bffe27989c893d6037e251499f235ef10d4578 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364161 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: fix wake pin handling when resuming from sleepMary Ruthven2016-07-282-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 was not waking up long enough after SPS_CS_L was asserted for the spi slave transactions to start and disable sleep. It also was not handling SYS_RST_L properly when it was asleep. This change sets SPS_CS_L to be an edge triggered wake up source instead of level triggered, because cr50 should just wake up on the edge and disable sleep until the spi transaction is done. It also adds sys_rst_l as a wakeup source. The sys_rst_asserted interrupt cannot be triggered while cr50 is asleep, so the pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at resume. This change relies on the EC extending the delay in chipset_reset to be long enough for SYS_RST_L to still be asserted when cr50 resumes. BUG=chrome-os-partner:54331 BRANCH=none TEST=manual make sure suzyq is disconnected. verify ap boots up to the kernel after running 'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec console. Check that cr50 goes to sleep when the AP is not trying to use the TPM. When cr50 is asleep pwrbtn + refresh still resets the system. Disable SYS_RST_L_IN as a wake source and verify the system verification fails and requests a recovery image. Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363606 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kevin: reef: enable CCD provided by an external chipstabilize-8647.BVincent Palatin2016-07-272-0/+2
| | | | | | | | | | | | | | | | | | | | | The case close debug (CCD) feature is provided by the external security chip. We add CONFIG_CASE_CLOSED_DEBUG_EXTERNAL to be able to detect debug accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without seeing Rp). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:55410 TEST=manual:on Kevin, plug a SuzyQ (with Rd/Rd) either in S5 or transition the device to S5 afterwards and see the debug USB endpoint works. Change-Id: Icef4209470463be77d43f4a46e32769ebf58f558 Reviewed-on: https://chromium-review.googlesource.com/363401 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: battery: Revive batteries in soft-disconnect stateShawn Nematbakhsh2016-07-262-0/+54
| | | | | | | | | | | | | | | | | | | | ESC+F3+Power+AC removal puts the battery into a soft-disconnect state where is stops supplying current. Revive batteries in this state by supplying a precharge current. BUG=chrome-os-partner:55617 BRANCH=None TEST=Manual on kevin. Put battery into soft-disconnect state. Attach charger and verify EC doesn't lose power and battery again supplies current. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I8dfcfa90c723d627636d9bebca48429b9f1106f7 Reviewed-on: https://chromium-review.googlesource.com/363004 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin / gru: Increase size of code RAMShawn Nematbakhsh2016-07-261-3/+3
| | | | | | | | | | | | | | | | Reduce size of UART Tx buffer to 1024 bytes on all npcx platforms and increase size of code memory by 6K bytes on Kevin. BUG=chrome-os-partner:52876 BRANCH=None TEST=`make buildall -j` with subsequent commit. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib9e52a4406f84cfc434984f8819d7ef02b70beb4 Reviewed-on: https://chromium-review.googlesource.com/363591 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin / gru: Add psys console commandShawn Nematbakhsh2016-07-261-0/+5
| | | | | | | | | | | | | | | | | Add `psys` console command for system power monitoring. Note that pmon resistor / cap are not stuffed by default. BUG=chrome-os-partner:55616 BRANCH=None TEST=Verify `psys` command on kevin prints a result. Change-Id: I9ac7b55ad30d0709624f94c27e173eb80f80a1ac Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363061 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Stephen Barber <smbarber@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* CR50: add endorsement certificate flownagendra modadugu2016-07-232-0/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | This change implements logic for installing endorsement certificates in the RW section. The endorsement certificates are initially provisioned in a fixed RO flash region and are copied in the RW TPM data region (once this region has been initialized). Also add code for reading from the info bank, which is where the endorsement seed is initially stored. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:50115 TEST=TCG tests running Change-Id: Id8c16d399202eee4ac0c4e397bdd29641ff9d2f3 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/362402 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin / gru: Warn users when incompatible GPIO config is usedShawn Nematbakhsh2016-07-221-0/+52
| | | | | | | | | | | | | | | | | | | | Old kevin / gru boards are no longer supported by our current GPIO configuration and must revert a CL to boot properly. Detect if old boards are used with an incompatible config and warn users of this fact by spamming the EC console and blinking the LED red. BUG=chrome-os-partner:55561 BRANCH=None TEST=Boot new kevin, verify no console spam or LED blinkage is seen. Verify old kevin + old gru spam the console and blink LED. Change-Id: I6d49720f760a6bef2bb3db6872857a5f61259e06 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362653 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Rearrange flash to allow dual RO imagesBill Richardson2016-07-222-27/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We had been putting the NVMEM flash where the boot rom would expect to find RO_B, preventing us from ever being able to update the bootloader. With this CL, we're rearranging the flash to support both RO_A and RO_B. The current flash layout now looks like this: 0x40000 RO_A 0x44000 RW_A 0x7c000 TOP_A 0x80000 RO_B 0x84000 RW_B 0xbc000 NVMEM 0xbffff <end of flash> BUG=chrome-os-partner:44803 BRANCH=none TEST=make buildall, also manual tests on Cr50 boards First, check that our current process still works: make BOARD=cr50 CR50_RO_KEY=cr50_rom0-dev-blsign.pem.pub spiflash -i -v build/cr50/ec.hex Yep, it does, but that only produces RO_A, not RO_B. To test the dual RO behavior, I used prebuilt RO_A and RO_B blobs for the bootloaders, signed using Marius' new scheme. Build the unsigned image, then sign it using Vadim's scripts: make BOARD=cr50 -j30 ~/bin/bs hex We'll garble various bits of the full image to invalidate each of the four RO/RW/A/B parts. Find lines common to both ROs and common to both RWs: sort B1*.hex | uniq -c | grep ' 2 ' | \ awk '{print $2}' | sort > tmp.ro2 sort build/cr50/RW/ec.RW*.signed.hex | uniq -c | grep ' 2 ' | \ awk '{print $2}' | sort > tmp.rw2 ro=$(diff tmp.ro2 tmp.rw2 | grep '<' | head -1 | awk '{print $2}') rw=$(diff tmp.ro2 tmp.rw2 | grep '>' | head -1 | awk '{print $2}') Double-check to be sure we don't have any false matches: grep -l $ro build/cr50/RW/ec.RW*.signed.hex B1_*.hex grep -l $rw build/cr50/RW/ec.RW*.signed.hex B1_*.hex The pre-signed RO_A image is older than RO_B, but both have the same epoch/major/minor, which is all that the bootrom checks for. It doesn't look at the timestamp. The RW_A is older than RW_B because of the sequential signing process. The RO bootloaders will check their timestamp, so RW_B should be preferred. RO_A RO_B RW_A RW_B good good good good cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex spiflash -v -i foo.hex jump @00040400 jump @00084000 => boots RO_A -> RW_B RO_A RO_B RW_A RW_B good good good bad cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}') sed -i "${ln}d" foo.hex spiflash -v -i foo.hex jump @00040400 jump @00044000 => boots RO_A -> RW_A RO_A RO_B RW_A RW_B bad good good good cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}') sed -i "${ln}d" foo.hex spiflash -v -i foo.hex jump @00080400 jump @00084000 => boots RO_B -> RW_B RO_A RO_B RW_A RW_B bad good good bad cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}') sed -i "${ln}d" foo.hex ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}') sed -i "${ln}d" foo.hex spiflash -v -i foo.hex jump @00080400 jump @00044000 => boots RO_B -> RW_A Yay. Now make sure RW_A and RW_B can be updated using usb_updater. \rm -rf build make BOARD=cr50 -j30 ~/bin/bs ./extra/usb_updater/usb_updater build/cr50/ec.bin I'm running RW_A, it updates and reboots into RW_B. Good. reboot 5 times, and it reverts to RW_A. Power cycle and it goes to RW_B again. Update to RW_A. \rm -rf build make BOARD=cr50 -j30 ~/bin/bs ./extra/usb_updater/usb_updater build/cr50/ec.bin I'm running RW_B, it updates and reboots into RW_A. Good. reboot 5 times, and it reverts to RW_B. Power cycle and it goes to RW_A again. Cool. Change-Id: I6c1689920de06c72c69f58ad2ef1059d9ee0d75f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362521 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* reef: Introduce IS_PROTO hackDavid Hendricks2016-07-221-0/+3
| | | | | | | | | | | | | | | | | | This will be used to hack around code that only works on proto. The earlier method of attempting to use board ID to determine codepath worked to a limited extent, but fell short due to pin swappings. So the dream of having a single binary that would work on multiple board revisions died, and now if someone wants to build for an old proto board they need to set this #define to 1. BUG=chrome-os-partner:54947 BRANCH=none TEST=tested with upcoming patches in this series Change-Id: I5468c252e5401d69b108c75fa00b3dfbbcf77c22 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360949 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_v4: add USB updaterNick Sanders2016-07-213-14/+41
| | | | | | | | | | | | | | This adds a Google FW update endpoint to servo v4. BUG=chromium:571476 TEST=successfully update servo v4 via usb BRANCH=None Change-Id: I79cb46364d416300e430708db25814f861a6d7c9 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361833 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* servo_micro: add USB updaterNick Sanders2016-07-213-21/+45
| | | | | | | | | | | | | | | | | This adds a Google FW update endpoint to servo micro in place of a GPIO enpoint. BUG=chromium:571477 TEST=successfully update servo micro via usb BRANCH=None Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I3d6c501d515b3f1db6e8259fbb829abe18f72e00 Reviewed-on: https://chromium-review.googlesource.com/361834 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tpm: add manufacturing status checkVadim Bendebury2016-07-212-0/+44
| | | | | | | | | | | | | | | For now the presence of both RSA and EC certificates at fixed NVRAM indices is considered evidence of TPM being through manufacturing. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied TPM manufacturing status is properly detected at startup. Change-Id: Iff3861603272cdfb58ebc523458c114685b2429f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362351 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: match private key against certs on endorsementnagendra modadugu2016-07-212-13/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the ecc and rsa key generation templates. Due to crosbug.com/p/55260 in which the TPMT_PUBLIC template is truncated during personalization, ecc generation requires a workaround. For RSA, allow the standard template to be used even on development builds. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:50115,chrome-os-partner:55260 TEST=test full personalize + cros_ack verify cert flow Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/360441 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit db5a1ca8a40be9bf7e741637cd8d7f15f520ab11) Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit b6620239bb7c4f5900051677f40f161c0a853a94) Change-Id: I1af83f1ec86e7ee4d325a4b7aabe03ce08c4108b Reviewed-on: https://chromium-review.googlesource.com/362142 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: fix uninitialized buffer size in _cpri__SignRSAnagendra modadugu2016-07-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The TPM2 wrapper library does not initialize the size of an output buffer length prior to calling into cr50/tpm2. This results in arbitrary failures depending on memory layout. Force the buffer length unseen, though this should be fixed in the TPM2 library. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:50115,chrome-os-partner:55260 TEST=test full personalize + cros_ack verify cert flow TEST=CPCTPM_TC2_2_20_02_03 passes, which was consistently failing Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/360908 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 635cb7ada25e76e504087916364e2db08a2133ab) Change-Id: I90e9b4d76986ffa27acc944e48afc2efaadad7cd Reviewed-on: https://chromium-review.googlesource.com/362116 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: rename struct BIGNUM -> struct LITE_BIGNUMnagendra modadugu2016-07-211-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | The name BIGNUM collides with a namesake struct in openssl. It would be convenient to write test code that compares results between openssl and dcrypto, hence this rename. Also rename some #defines that conflict with openssl names. CQ-DEPEND=CL:*270476 BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115 TEST=build succeeds Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/360346 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit a15b495497728a6b212bd87e92f6ba5ba463f985) Change-Id: Ic53ce805cfcc591c68fbc1ef90ff2f92cec973a6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362112 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* board/reef: enable CONFIG_CHIPSET_RESET_HOOKAaron Durbin2016-07-211-0/+1
| | | | | | | | | | | | | | | | In order for the vstore to be unlocked one needs to enable the CHIPSET_RESET_HOOK. Do that for reef. BUG=chrome-os-partner:55471 BRANCH=None TEST=Able to boot and reboot without getting vboot hash saving errors. Also am able to see the assertion/deassertion messages on the console. Change-Id: I94a41a08ad8649423988372607835da01ec12b8b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362001 Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpm: anx74xx: Add alert polarity member to tcpc_config_tDavid Hendricks2016-07-213-5/+6
| | | | | | | | | | | | | | | This allows us to specify the polarity of the alert signal for each TCPC chip onboard, even if we have multiple instances of the same chip. BUG=none BRANCH=none TEST=built and booted on reef Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360948 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_micro: support servo micro v2, console gpioNick Sanders2016-07-203-67/+34
| | | | | | | | | | | | | | | * Remove GPIO USB endpoint to make room for update endpoint. * Change GPIO mapping slightly to support servo micro v2. BUG=chromium:571477 BRANCH=None TEST=run servod, see new controls. Change-Id: Id3b85b4c77b8f21afd9636b2ee459ace6f42f68e Reviewed-on: https://chromium-review.googlesource.com/361383 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* kevin / gru: Enable low-power idleShawn Nematbakhsh2016-07-201-1/+1
| | | | | | | | | | | | | BUG=chrome-os-partner:54343 BRANCH=None TEST=Verify system continues to function as normal in S0 and S5. Change-Id: I1b46c47a074a308f2e316e93813559d170bfe5ee Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355161 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add an option to disable uart0 rx no matter whatMary Ruthven2016-07-201-0/+1
| | | | | | | | | | | | | | | | Having uart0 RX enabled can cause serious issues. This change adds a config option to disable uart0 rx no matter what. BUG=none BRANCH=none TEST=On B2 check that the ultradebug console is now read only Change-Id: Icaec6954ffd3cbf0fda3f53581f6e4020d555267 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361976 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin: Add CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEADShawn Nematbakhsh2016-07-201-0/+4
| | | | | | | | | | | | | | | | | The battery on kevin apparently requests 0A / 0V when extremely low, so ignore this request and apply the pre-charge current. BUG=chrome-os-partner:55416 BRANCH=None TEST=Verify Kevin powers on with dead battery and battery charges as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef Reviewed-on: https://chromium-review.googlesource.com/361994 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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